| blob | e0b1238d31df6906a4cbea897d584a2d173ddd22 |
1 /*
2 * Copyright(c) 2015 - 2018 Intel Corporation.
3 *
4 * This file is provided under a dual BSD/GPLv2 license. When using or
5 * redistributing this file, you may do so under either license.
6 *
7 * GPL LICENSE SUMMARY
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * BSD LICENSE
19 *
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions
22 * are met:
23 *
24 * - Redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer.
26 * - Redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in
28 * the documentation and/or other materials provided with the
29 * distribution.
30 * - Neither the name of Intel Corporation nor the names of its
31 * contributors may be used to endorse or promote products derived
32 * from this software without specific prior written permission.
33 *
34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
37 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
38 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
39 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
40 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
41 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
42 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
43 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45 *
46 */
48 /*
49 * This file contains all of the code that is specific to the HFI chip
50 */
52 #include <linux/pci.h>
53 #include <linux/delay.h>
54 #include <linux/interrupt.h>
55 #include <linux/module.h>
70 uint kdeth_qp;
78 /*
79 * Default time to aggregate two 10K packets from the idle state
80 * (timer not running). The timer starts at the end of the first packet,
81 * so only the time for one 10K packet and header plus a bit extra is needed.
82 * 10 * 1024 + 64 header byte = 10304 byte
83 * 10304 byte / 12.5 GB/s = 824.32ns
84 */
97 uint loopback;
101 /* Other driver tunables */
111 u16 unused0;
112 u32 unused1;
113 };
115 /* str must be a string constant */
116 #define FLAG_ENTRY(str, extra, flag) {flag, str, extra}
117 #define FLAG_ENTRY0(str, flag) {flag, str, 0}
119 /* Send Error Consequences */
120 #define SEC_WRITE_DROPPED 0x1
121 #define SEC_PACKET_DROPPED 0x2
125 #define DEFAULT_KRCVQS 2
126 #define MIN_KERNEL_KCTXTS 2
127 #define FIRST_KERNEL_KCTXT 1
129 /*
130 * RSM instance allocation
131 * 0 - Verbs
132 * 1 - User Fecn Handling
133 * 2 - Vnic
134 */
135 #define RSM_INS_VERBS 0
136 #define RSM_INS_FECN 1
137 #define RSM_INS_VNIC 2
139 /* Bit offset into the GUID which carries HFI id information */
140 #define GUID_HFI_INDEX_SHIFT 39
142 /* extract the emulation revision */
143 #define emulator_rev(dd) ((dd)->irev >> 8)
144 /* parallel and serial emulation versions are 3 and 4 respectively */
145 #define is_emulator_p(dd) ((((dd)->irev) & 0xf) == 3)
146 #define is_emulator_s(dd) ((((dd)->irev) & 0xf) == 4)
148 /* RSM fields for Verbs */
149 /* packet type */
150 #define IB_PACKET_TYPE 2ull
151 #define QW_SHIFT 6ull
152 /* QPN[7..1] */
153 #define QPN_WIDTH 7ull
155 /* LRH.BTH: QW 0, OFFSET 48 - for match */
156 #define LRH_BTH_QW 0ull
157 #define LRH_BTH_BIT_OFFSET 48ull
158 #define LRH_BTH_OFFSET(off) ((LRH_BTH_QW << QW_SHIFT) | (off))
159 #define LRH_BTH_MATCH_OFFSET LRH_BTH_OFFSET(LRH_BTH_BIT_OFFSET)
160 #define LRH_BTH_SELECT
161 #define LRH_BTH_MASK 3ull
162 #define LRH_BTH_VALUE 2ull
164 /* LRH.SC[3..0] QW 0, OFFSET 56 - for match */
165 #define LRH_SC_QW 0ull
166 #define LRH_SC_BIT_OFFSET 56ull
167 #define LRH_SC_OFFSET(off) ((LRH_SC_QW << QW_SHIFT) | (off))
168 #define LRH_SC_MATCH_OFFSET LRH_SC_OFFSET(LRH_SC_BIT_OFFSET)
169 #define LRH_SC_MASK 128ull
170 #define LRH_SC_VALUE 0ull
172 /* SC[n..0] QW 0, OFFSET 60 - for select */
173 #define LRH_SC_SELECT_OFFSET ((LRH_SC_QW << QW_SHIFT) | (60ull))
175 /* QPN[m+n:1] QW 1, OFFSET 1 */
176 #define QPN_SELECT_OFFSET ((1ull << QW_SHIFT) | (1ull))
178 /* RSM fields for Vnic */
179 /* L2_TYPE: QW 0, OFFSET 61 - for match */
180 #define L2_TYPE_QW 0ull
181 #define L2_TYPE_BIT_OFFSET 61ull
182 #define L2_TYPE_OFFSET(off) ((L2_TYPE_QW << QW_SHIFT) | (off))
183 #define L2_TYPE_MATCH_OFFSET L2_TYPE_OFFSET(L2_TYPE_BIT_OFFSET)
184 #define L2_TYPE_MASK 3ull
185 #define L2_16B_VALUE 2ull
187 /* L4_TYPE QW 1, OFFSET 0 - for match */
188 #define L4_TYPE_QW 1ull
189 #define L4_TYPE_BIT_OFFSET 0ull
190 #define L4_TYPE_OFFSET(off) ((L4_TYPE_QW << QW_SHIFT) | (off))
191 #define L4_TYPE_MATCH_OFFSET L4_TYPE_OFFSET(L4_TYPE_BIT_OFFSET)
192 #define L4_16B_TYPE_MASK 0xFFull
193 #define L4_16B_ETH_VALUE 0x78ull
195 /* 16B VESWID - for select */
196 #define L4_16B_HDR_VESWID_OFFSET ((2 << QW_SHIFT) | (16ull))
197 /* 16B ENTROPY - for select */
198 #define L2_16B_ENTROPY_OFFSET ((1 << QW_SHIFT) | (32ull))
200 /* defines to build power on SC2VL table */
201 #define SC2VL_VAL( \
202 num, \
203 sc0, sc0val, \
204 sc1, sc1val, \
205 sc2, sc2val, \
206 sc3, sc3val, \
207 sc4, sc4val, \
208 sc5, sc5val, \
209 sc6, sc6val, \
210 sc7, sc7val) \
211 ( \
212 ((u64)(sc0val) << SEND_SC2VLT##num##_SC##sc0##_SHIFT) | \
213 ((u64)(sc1val) << SEND_SC2VLT##num##_SC##sc1##_SHIFT) | \
214 ((u64)(sc2val) << SEND_SC2VLT##num##_SC##sc2##_SHIFT) | \
215 ((u64)(sc3val) << SEND_SC2VLT##num##_SC##sc3##_SHIFT) | \
216 ((u64)(sc4val) << SEND_SC2VLT##num##_SC##sc4##_SHIFT) | \
217 ((u64)(sc5val) << SEND_SC2VLT##num##_SC##sc5##_SHIFT) | \
218 ((u64)(sc6val) << SEND_SC2VLT##num##_SC##sc6##_SHIFT) | \
219 ((u64)(sc7val) << SEND_SC2VLT##num##_SC##sc7##_SHIFT) \
220 )
222 #define DC_SC_VL_VAL( \
223 range, \
224 e0, e0val, \
225 e1, e1val, \
226 e2, e2val, \
227 e3, e3val, \
228 e4, e4val, \
229 e5, e5val, \
230 e6, e6val, \
231 e7, e7val, \
232 e8, e8val, \
233 e9, e9val, \
234 e10, e10val, \
235 e11, e11val, \
236 e12, e12val, \
237 e13, e13val, \
238 e14, e14val, \
239 e15, e15val) \
240 ( \
241 ((u64)(e0val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e0##_SHIFT) | \
242 ((u64)(e1val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e1##_SHIFT) | \
243 ((u64)(e2val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e2##_SHIFT) | \
244 ((u64)(e3val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e3##_SHIFT) | \
245 ((u64)(e4val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e4##_SHIFT) | \
246 ((u64)(e5val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e5##_SHIFT) | \
247 ((u64)(e6val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e6##_SHIFT) | \
248 ((u64)(e7val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e7##_SHIFT) | \
249 ((u64)(e8val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e8##_SHIFT) | \
250 ((u64)(e9val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e9##_SHIFT) | \
251 ((u64)(e10val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e10##_SHIFT) | \
252 ((u64)(e11val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e11##_SHIFT) | \
253 ((u64)(e12val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e12##_SHIFT) | \
254 ((u64)(e13val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e13##_SHIFT) | \
255 ((u64)(e14val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e14##_SHIFT) | \
256 ((u64)(e15val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e15##_SHIFT) \
257 )
259 /* all CceStatus sub-block freeze bits */
260 #define ALL_FROZE (CCE_STATUS_SDMA_FROZE_SMASK \
261 | CCE_STATUS_RXE_FROZE_SMASK \
262 | CCE_STATUS_TXE_FROZE_SMASK \
263 | CCE_STATUS_TXE_PIO_FROZE_SMASK)
264 /* all CceStatus sub-block TXE pause bits */
265 #define ALL_TXE_PAUSE (CCE_STATUS_TXE_PIO_PAUSED_SMASK \
266 | CCE_STATUS_TXE_PAUSED_SMASK \
267 | CCE_STATUS_SDMA_PAUSED_SMASK)
268 /* all CceStatus sub-block RXE pause bits */
269 #define ALL_RXE_PAUSE CCE_STATUS_RXE_PAUSED_SMASK
271 #define CNTR_MAX 0xFFFFFFFFFFFFFFFFULL
272 #define CNTR_32BIT_MAX 0x00000000FFFFFFFF
274 /*
275 * CCE Error flags.
276 */
279 CCE_ERR_STATUS_CCE_CSR_PARITY_ERR_SMASK),
281 CCE_ERR_STATUS_CCE_CSR_READ_BAD_ADDR_ERR_SMASK),
283 CCE_ERR_STATUS_CCE_CSR_WRITE_BAD_ADDR_ERR_SMASK),
285 CCE_ERR_STATUS_CCE_TRGT_ASYNC_FIFO_PARITY_ERR_SMASK),
287 CCE_ERR_STATUS_CCE_TRGT_ACCESS_ERR_SMASK),
289 CCE_ERR_STATUS_CCE_RSPD_DATA_PARITY_ERR_SMASK),
291 CCE_ERR_STATUS_CCE_CLI0_ASYNC_FIFO_PARITY_ERR_SMASK),
293 CCE_ERR_STATUS_CCE_CSR_CFG_BUS_PARITY_ERR_SMASK),
295 CCE_ERR_STATUS_CCE_CLI2_ASYNC_FIFO_PARITY_ERR_SMASK),
297 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_PIO_CRDT_PARITY_ERR_SMASK),
299 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_SDMA_HD_PARITY_ERR_SMASK),
301 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_RXDMA_PARITY_ERROR_SMASK),
303 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_DBG_PARITY_ERROR_SMASK),
305 CCE_ERR_STATUS_PCIC_RETRY_MEM_COR_ERR_SMASK),
307 CCE_ERR_STATUS_PCIC_RETRY_SOT_MEM_COR_ERR_SMASK),
309 CCE_ERR_STATUS_PCIC_POST_HD_QCOR_ERR_SMASK),
311 CCE_ERR_STATUS_PCIC_POST_DAT_QCOR_ERR_SMASK),
313 CCE_ERR_STATUS_PCIC_CPL_HD_QCOR_ERR_SMASK),
315 CCE_ERR_STATUS_PCIC_CPL_DAT_QCOR_ERR_SMASK),
317 CCE_ERR_STATUS_PCIC_NPOST_HQ_PARITY_ERR_SMASK),
319 CCE_ERR_STATUS_PCIC_NPOST_DAT_QPARITY_ERR_SMASK),
321 CCE_ERR_STATUS_PCIC_RETRY_MEM_UNC_ERR_SMASK),
323 CCE_ERR_STATUS_PCIC_RETRY_SOT_MEM_UNC_ERR_SMASK),
325 CCE_ERR_STATUS_PCIC_POST_HD_QUNC_ERR_SMASK),
327 CCE_ERR_STATUS_PCIC_POST_DAT_QUNC_ERR_SMASK),
329 CCE_ERR_STATUS_PCIC_CPL_HD_QUNC_ERR_SMASK),
331 CCE_ERR_STATUS_PCIC_CPL_DAT_QUNC_ERR_SMASK),
333 CCE_ERR_STATUS_PCIC_TRANSMIT_FRONT_PARITY_ERR_SMASK),
335 CCE_ERR_STATUS_PCIC_TRANSMIT_BACK_PARITY_ERR_SMASK),
337 CCE_ERR_STATUS_PCIC_RECEIVE_PARITY_ERR_SMASK),
339 CCE_ERR_STATUS_CCE_TRGT_CPL_TIMEOUT_ERR_SMASK),
341 CCE_ERR_STATUS_LA_TRIGGERED_SMASK),
343 CCE_ERR_STATUS_CCE_SEG_READ_BAD_ADDR_ERR_SMASK),
345 CCE_ERR_STATUS_CCE_SEG_WRITE_BAD_ADDR_ERR_SMASK),
347 CCE_ERR_STATUS_CCE_RCPL_ASYNC_FIFO_PARITY_ERR_SMASK),
349 CCE_ERR_STATUS_CCE_RXDMA_CONV_FIFO_PARITY_ERR_SMASK),
351 CCE_ERR_STATUS_CCE_MSIX_TABLE_COR_ERR_SMASK),
353 CCE_ERR_STATUS_CCE_MSIX_TABLE_UNC_ERR_SMASK),
355 CCE_ERR_STATUS_CCE_INT_MAP_COR_ERR_SMASK),
357 CCE_ERR_STATUS_CCE_INT_MAP_UNC_ERR_SMASK),
359 CCE_ERR_STATUS_CCE_MSIX_CSR_PARITY_ERR_SMASK),
360 /*41-63 reserved*/
361 };
363 /*
364 * Misc Error flags
365 */
366 #define MES(text) MISC_ERR_STATUS_MISC_##text##_ERR_SMASK
381 };
383 /*
384 * TXE PIO Error flags and consequences
385 */
388 SEC_WRITE_DROPPED,
389 SEND_PIO_ERR_STATUS_PIO_WRITE_BAD_CTXT_ERR_SMASK),
391 SEC_SPC_FREEZE,
392 SEND_PIO_ERR_STATUS_PIO_WRITE_ADDR_PARITY_ERR_SMASK),
394 SEC_SPC_FREEZE,
395 SEND_PIO_ERR_STATUS_PIO_CSR_PARITY_ERR_SMASK),
397 SEC_SPC_FREEZE,
398 SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO0_ERR_SMASK),
400 SEC_SPC_FREEZE,
401 SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO1_ERR_SMASK),
403 SEC_SPC_FREEZE,
404 SEND_PIO_ERR_STATUS_PIO_PCC_FIFO_PARITY_ERR_SMASK),
406 SEC_SPC_FREEZE,
407 SEND_PIO_ERR_STATUS_PIO_PEC_FIFO_PARITY_ERR_SMASK),
409 SEC_SPC_FREEZE,
410 SEND_PIO_ERR_STATUS_PIO_SBRDCTL_CRREL_PARITY_ERR_SMASK),
412 SEC_SPC_FREEZE,
413 SEND_PIO_ERR_STATUS_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR_SMASK),
415 SEC_SPC_FREEZE,
416 SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_FIFO_PARITY_ERR_SMASK),
418 SEC_SPC_FREEZE,
419 SEND_PIO_ERR_STATUS_PIO_SM_PKT_RESET_PARITY_ERR_SMASK),
421 SEC_SPC_FREEZE,
422 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_UNC_ERR_SMASK),
424 SEC_SPC_FREEZE,
425 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_UNC_ERR_SMASK),
428 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_COR_ERR_SMASK),
431 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_COR_ERR_SMASK),
433 SEC_SPC_FREEZE,
434 SEND_PIO_ERR_STATUS_PIO_CREDIT_RET_FIFO_PARITY_ERR_SMASK),
436 SEC_SPC_FREEZE,
437 SEND_PIO_ERR_STATUS_PIO_PPMC_PBL_FIFO_ERR_SMASK),
440 SEND_PIO_ERR_STATUS_PIO_INIT_SM_IN_ERR_SMASK),
442 SEC_SPC_FREEZE,
443 SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_SM_OR_ARB_SM_ERR_SMASK),
445 SEC_SPC_FREEZE,
446 SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_UNC_ERR_SMASK),
449 SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_COR_ERR_SMASK),
451 SEC_SPC_FREEZE,
452 SEND_PIO_ERR_STATUS_PIO_WRITE_DATA_PARITY_ERR_SMASK),
454 SEC_SPC_FREEZE,
455 SEND_PIO_ERR_STATUS_PIO_STATE_MACHINE_ERR_SMASK),
458 SEND_PIO_ERR_STATUS_PIO_WRITE_QW_VALID_PARITY_ERR_SMASK),
461 SEND_PIO_ERR_STATUS_PIO_BLOCK_QW_COUNT_PARITY_ERR_SMASK),
463 SEC_SPC_FREEZE,
464 SEND_PIO_ERR_STATUS_PIO_VLF_VL_LEN_PARITY_ERR_SMASK),
466 SEC_SPC_FREEZE,
467 SEND_PIO_ERR_STATUS_PIO_VLF_SOP_PARITY_ERR_SMASK),
469 SEC_SPC_FREEZE,
470 SEND_PIO_ERR_STATUS_PIO_VL_FIFO_PARITY_ERR_SMASK),
472 SEC_SPC_FREEZE,
473 SEND_PIO_ERR_STATUS_PIO_PPMC_BQC_MEM_PARITY_ERR_SMASK),
475 SEC_SPC_FREEZE,
476 SEND_PIO_ERR_STATUS_PIO_PPMC_SOP_LEN_ERR_SMASK),
477 /*30-31 reserved*/
479 SEC_SPC_FREEZE,
480 SEND_PIO_ERR_STATUS_PIO_CURRENT_FREE_CNT_PARITY_ERR_SMASK),
482 SEC_SPC_FREEZE,
483 SEND_PIO_ERR_STATUS_PIO_LAST_RETURNED_CNT_PARITY_ERR_SMASK),
485 SEC_SPC_FREEZE,
486 SEND_PIO_ERR_STATUS_PIO_PCC_SOP_HEAD_PARITY_ERR_SMASK),
488 SEC_SPC_FREEZE,
489 SEND_PIO_ERR_STATUS_PIO_PEC_SOP_HEAD_PARITY_ERR_SMASK),
490 /*36-63 reserved*/
491 };
493 /* TXE PIO errors that cause an SPC freeze */
494 #define ALL_PIO_FREEZE_ERR \
495 (SEND_PIO_ERR_STATUS_PIO_WRITE_ADDR_PARITY_ERR_SMASK \
496 | SEND_PIO_ERR_STATUS_PIO_CSR_PARITY_ERR_SMASK \
497 | SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO0_ERR_SMASK \
498 | SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO1_ERR_SMASK \
499 | SEND_PIO_ERR_STATUS_PIO_PCC_FIFO_PARITY_ERR_SMASK \
500 | SEND_PIO_ERR_STATUS_PIO_PEC_FIFO_PARITY_ERR_SMASK \
501 | SEND_PIO_ERR_STATUS_PIO_SBRDCTL_CRREL_PARITY_ERR_SMASK \
502 | SEND_PIO_ERR_STATUS_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR_SMASK \
503 | SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_FIFO_PARITY_ERR_SMASK \
504 | SEND_PIO_ERR_STATUS_PIO_SM_PKT_RESET_PARITY_ERR_SMASK \
505 | SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_UNC_ERR_SMASK \
506 | SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_UNC_ERR_SMASK \
507 | SEND_PIO_ERR_STATUS_PIO_CREDIT_RET_FIFO_PARITY_ERR_SMASK \
508 | SEND_PIO_ERR_STATUS_PIO_PPMC_PBL_FIFO_ERR_SMASK \
509 | SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_SM_OR_ARB_SM_ERR_SMASK \
510 | SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_UNC_ERR_SMASK \
511 | SEND_PIO_ERR_STATUS_PIO_WRITE_DATA_PARITY_ERR_SMASK \
512 | SEND_PIO_ERR_STATUS_PIO_STATE_MACHINE_ERR_SMASK \
513 | SEND_PIO_ERR_STATUS_PIO_WRITE_QW_VALID_PARITY_ERR_SMASK \
514 | SEND_PIO_ERR_STATUS_PIO_BLOCK_QW_COUNT_PARITY_ERR_SMASK \
515 | SEND_PIO_ERR_STATUS_PIO_VLF_VL_LEN_PARITY_ERR_SMASK \
516 | SEND_PIO_ERR_STATUS_PIO_VLF_SOP_PARITY_ERR_SMASK \
517 | SEND_PIO_ERR_STATUS_PIO_VL_FIFO_PARITY_ERR_SMASK \
518 | SEND_PIO_ERR_STATUS_PIO_PPMC_BQC_MEM_PARITY_ERR_SMASK \
519 | SEND_PIO_ERR_STATUS_PIO_PPMC_SOP_LEN_ERR_SMASK \
520 | SEND_PIO_ERR_STATUS_PIO_CURRENT_FREE_CNT_PARITY_ERR_SMASK \
521 | SEND_PIO_ERR_STATUS_PIO_LAST_RETURNED_CNT_PARITY_ERR_SMASK \
522 | SEND_PIO_ERR_STATUS_PIO_PCC_SOP_HEAD_PARITY_ERR_SMASK \
523 | SEND_PIO_ERR_STATUS_PIO_PEC_SOP_HEAD_PARITY_ERR_SMASK)
525 /*
526 * TXE SDMA Error flags
527 */
530 SEND_DMA_ERR_STATUS_SDMA_RPY_TAG_ERR_SMASK),
532 SEND_DMA_ERR_STATUS_SDMA_CSR_PARITY_ERR_SMASK),
534 SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_UNC_ERR_SMASK),
536 SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_COR_ERR_SMASK),
537 /*04-63 reserved*/
538 };
540 /* TXE SDMA errors that cause an SPC freeze */
541 #define ALL_SDMA_FREEZE_ERR \
542 (SEND_DMA_ERR_STATUS_SDMA_RPY_TAG_ERR_SMASK \
543 | SEND_DMA_ERR_STATUS_SDMA_CSR_PARITY_ERR_SMASK \
544 | SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_UNC_ERR_SMASK)
546 /* SendEgressErrInfo bits that correspond to a PortXmitDiscard counter */
547 #define PORT_DISCARD_EGRESS_ERRS \
548 (SEND_EGRESS_ERR_INFO_TOO_LONG_IB_PACKET_ERR_SMASK \
549 | SEND_EGRESS_ERR_INFO_VL_MAPPING_ERR_SMASK \
550 | SEND_EGRESS_ERR_INFO_VL_ERR_SMASK)
552 /*
553 * TXE Egress Error flags
554 */
555 #define SEES(text) SEND_EGRESS_ERR_STATUS_##text##_ERR_SMASK
559 /* 2 reserved */
564 /* 6 reserved */
569 /* 9-10 reserved */
651 };
653 /*
654 * TXE Egress Error Info flags
655 */
656 #define SEEI(text) SEND_EGRESS_ERR_INFO_##text##_ERR_SMASK
680 };
682 /* TXE Egress errors that cause an SPC freeze */
683 #define ALL_TXE_EGRESS_FREEZE_ERR \
684 (SEES(TX_EGRESS_FIFO_UNDERRUN_OR_PARITY) \
685 | SEES(TX_PIO_LAUNCH_INTF_PARITY) \
686 | SEES(TX_SDMA_LAUNCH_INTF_PARITY) \
687 | SEES(TX_SBRD_CTL_STATE_MACHINE_PARITY) \
688 | SEES(TX_LAUNCH_CSR_PARITY) \
689 | SEES(TX_SBRD_CTL_CSR_PARITY) \
690 | SEES(TX_CONFIG_PARITY) \
691 | SEES(TX_LAUNCH_FIFO0_UNC_OR_PARITY) \
692 | SEES(TX_LAUNCH_FIFO1_UNC_OR_PARITY) \
693 | SEES(TX_LAUNCH_FIFO2_UNC_OR_PARITY) \
694 | SEES(TX_LAUNCH_FIFO3_UNC_OR_PARITY) \
695 | SEES(TX_LAUNCH_FIFO4_UNC_OR_PARITY) \
696 | SEES(TX_LAUNCH_FIFO5_UNC_OR_PARITY) \
697 | SEES(TX_LAUNCH_FIFO6_UNC_OR_PARITY) \
698 | SEES(TX_LAUNCH_FIFO7_UNC_OR_PARITY) \
699 | SEES(TX_LAUNCH_FIFO8_UNC_OR_PARITY) \
700 | SEES(TX_CREDIT_RETURN_PARITY))
702 /*
703 * TXE Send error flags
704 */
705 #define SES(name) SEND_ERR_STATUS_SEND_##name##_ERR_SMASK
710 };
712 /*
713 * TXE Send Context Error flags and consequences
714 */
718 SEND_CTXT_ERR_STATUS_PIO_INCONSISTENT_SOP_ERR_SMASK),
721 SEND_CTXT_ERR_STATUS_PIO_DISALLOWED_PACKET_ERR_SMASK),
724 SEND_CTXT_ERR_STATUS_PIO_WRITE_CROSSES_BOUNDARY_ERR_SMASK),
727 SEND_CTXT_ERR_STATUS_PIO_WRITE_OVERFLOW_ERR_SMASK),
730 SEND_CTXT_ERR_STATUS_PIO_WRITE_OUT_OF_BOUNDS_ERR_SMASK),
731 /* 5-63 reserved*/
732 };
734 /*
735 * RXE Receive Error flags
736 */
737 #define RXES(name) RCV_ERR_STATUS_RX_##name##_ERR_SMASK
815 };
817 /* RXE errors that will trigger an SPC freeze */
818 #define ALL_RXE_FREEZE_ERR \
819 (RCV_ERR_STATUS_RX_RCV_QP_MAP_TABLE_UNC_ERR_SMASK \
820 | RCV_ERR_STATUS_RX_RCV_CSR_PARITY_ERR_SMASK \
821 | RCV_ERR_STATUS_RX_DMA_FLAG_UNC_ERR_SMASK \
822 | RCV_ERR_STATUS_RX_RCV_FSM_ENCODING_ERR_SMASK \
823 | RCV_ERR_STATUS_RX_RBUF_FREE_LIST_UNC_ERR_SMASK \
824 | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_REG_UNC_ERR_SMASK \
825 | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_REG_UNC_COR_ERR_SMASK \
826 | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_UNC_ERR_SMASK \
827 | RCV_ERR_STATUS_RX_RBUF_BLOCK_LIST_READ_UNC_ERR_SMASK \
828 | RCV_ERR_STATUS_RX_RBUF_CSR_QHEAD_BUF_NUM_PARITY_ERR_SMASK \
829 | RCV_ERR_STATUS_RX_RBUF_CSR_QENT_CNT_PARITY_ERR_SMASK \
830 | RCV_ERR_STATUS_RX_RBUF_CSR_QNEXT_BUF_PARITY_ERR_SMASK \
831 | RCV_ERR_STATUS_RX_RBUF_CSR_QVLD_BIT_PARITY_ERR_SMASK \
832 | RCV_ERR_STATUS_RX_RBUF_CSR_QHD_PTR_PARITY_ERR_SMASK \
833 | RCV_ERR_STATUS_RX_RBUF_CSR_QTL_PTR_PARITY_ERR_SMASK \
834 | RCV_ERR_STATUS_RX_RBUF_CSR_QNUM_OF_PKT_PARITY_ERR_SMASK \
835 | RCV_ERR_STATUS_RX_RBUF_CSR_QEOPDW_PARITY_ERR_SMASK \
836 | RCV_ERR_STATUS_RX_RBUF_CTX_ID_PARITY_ERR_SMASK \
837 | RCV_ERR_STATUS_RX_RBUF_BAD_LOOKUP_ERR_SMASK \
838 | RCV_ERR_STATUS_RX_RBUF_FULL_ERR_SMASK \
839 | RCV_ERR_STATUS_RX_RBUF_EMPTY_ERR_SMASK \
840 | RCV_ERR_STATUS_RX_RBUF_FL_RD_ADDR_PARITY_ERR_SMASK \
841 | RCV_ERR_STATUS_RX_RBUF_FL_WR_ADDR_PARITY_ERR_SMASK \
842 | RCV_ERR_STATUS_RX_RBUF_FL_INITDONE_PARITY_ERR_SMASK \
843 | RCV_ERR_STATUS_RX_RBUF_FL_INIT_WR_ADDR_PARITY_ERR_SMASK \
844 | RCV_ERR_STATUS_RX_RBUF_NEXT_FREE_BUF_UNC_ERR_SMASK \
845 | RCV_ERR_STATUS_RX_LOOKUP_DES_PART1_UNC_ERR_SMASK \
846 | RCV_ERR_STATUS_RX_LOOKUP_DES_PART1_UNC_COR_ERR_SMASK \
847 | RCV_ERR_STATUS_RX_LOOKUP_DES_PART2_PARITY_ERR_SMASK \
848 | RCV_ERR_STATUS_RX_LOOKUP_RCV_ARRAY_UNC_ERR_SMASK \
849 | RCV_ERR_STATUS_RX_LOOKUP_CSR_PARITY_ERR_SMASK \
850 | RCV_ERR_STATUS_RX_HQ_INTR_CSR_PARITY_ERR_SMASK \
851 | RCV_ERR_STATUS_RX_HQ_INTR_FSM_ERR_SMASK \
852 | RCV_ERR_STATUS_RX_RBUF_DESC_PART1_UNC_ERR_SMASK \
853 | RCV_ERR_STATUS_RX_RBUF_DESC_PART1_COR_ERR_SMASK \
854 | RCV_ERR_STATUS_RX_RBUF_DESC_PART2_UNC_ERR_SMASK \
855 | RCV_ERR_STATUS_RX_DMA_HDR_FIFO_RD_UNC_ERR_SMASK \
856 | RCV_ERR_STATUS_RX_DMA_DATA_FIFO_RD_UNC_ERR_SMASK \
857 | RCV_ERR_STATUS_RX_RBUF_DATA_UNC_ERR_SMASK \
858 | RCV_ERR_STATUS_RX_DMA_CSR_PARITY_ERR_SMASK \
859 | RCV_ERR_STATUS_RX_DMA_EQ_FSM_ENCODING_ERR_SMASK \
860 | RCV_ERR_STATUS_RX_DMA_DQ_FSM_ENCODING_ERR_SMASK \
861 | RCV_ERR_STATUS_RX_DMA_CSR_UNC_ERR_SMASK \
862 | RCV_ERR_STATUS_RX_CSR_PARITY_ERR_SMASK)
864 #define RXE_FREEZE_ABORT_MASK \
865 (RCV_ERR_STATUS_RX_DMA_CSR_UNC_ERR_SMASK | \
866 RCV_ERR_STATUS_RX_DMA_HDR_FIFO_RD_UNC_ERR_SMASK | \
867 RCV_ERR_STATUS_RX_DMA_DATA_FIFO_RD_UNC_ERR_SMASK)
869 /*
870 * DCC Error Flags
871 */
872 #define DCCE(name) DCC_ERR_FLG_##name##_SMASK
920 };
922 /*
923 * LCB error flags
924 */
925 #define LCBE(name) DC_LCB_ERR_FLG_##name##_SMASK
963 };
965 /*
966 * DC8051 Error Flags
967 */
968 #define D8E(name) DC_DC8051_ERR_FLG_##name##_SMASK
981 };
983 /*
984 * DC8051 Information Error flags
985 *
986 * Flags in DC8051_DBG_ERR_INFO_SET_BY_8051.ERROR field.
987 */
993 FAILED_SERDES_INTERNAL_LOOPBACK),
1004 EXTERNAL_DEVICE_REQ_TIMEOUT),
1005 };
1007 /*
1008 * DC8051 Information Host Information flags
1009 *
1010 * Flags in DC8051_DBG_ERR_INFO_SET_BY_8051.HOST_MSG field.
1011 */
1023 };
1060 u32 state);
1089 /*
1090 * Error interrupt table entry. This is used as input to the interrupt
1091 * "clear down" routine used for all second tier error interrupt register.
1092 * Second tier interrupt registers have a single bit representing them
1093 * in the top-level CceIntStatus.
1094 */
1101 };
1103 #define NUM_MISC_ERRS (IS_GENERAL_ERR_END + 1 - IS_GENERAL_ERR_START)
1104 #define NUM_DC_ERRS (IS_DC_END + 1 - IS_DC_START)
1105 #define NUM_VARIOUS (IS_VARIOUS_END + 1 - IS_VARIOUS_START)
1107 /*
1108 * Helpers for building HFI and DC error interrupt table entries. Different
1109 * helpers are needed because of inconsistent register names.
1110 */
1111 #define EE(reg, handler, desc) \
1112 { reg##_STATUS, reg##_CLEAR, reg##_MASK, \
1113 handler, desc }
1114 #define DC_EE1(reg, handler, desc) \
1115 { reg##_FLG, reg##_FLG_CLR, reg##_FLG_EN, handler, desc }
1116 #define DC_EE2(reg, handler, desc) \
1117 { reg##_FLG, reg##_CLR, reg##_EN, handler, desc }
1119 /*
1120 * Table of the "misc" grouping of error interrupts. Each entry refers to
1121 * another register containing more information.
1122 */
1132 /* the rest are reserved */
1133 };
1135 /*
1136 * Index into the Various section of the interrupt sources
1137 * corresponding to the Critical Temperature interrupt.
1138 */
1139 #define TCRIT_INT_SOURCE 4
1141 /*
1142 * SDMA error interrupt entry - refers to another register containing more
1143 * information.
1144 */
1154 /* rest are reserved */
1155 };
1157 /*
1158 * The DC encoding of mtu_cap for 10K MTU in the DCC_CFG_PORT_CONFIG
1159 * register can not be derived from the MTU value because 10K is not
1160 * a power of 2. Therefore, we need a constant. Everything else can
1161 * be calculated.
1162 */
1163 #define DCC_CFG_PORT_MTU_CAP_10240 7
1165 /*
1166 * Table of the DC grouping of error interrupts. Each entry refers to
1167 * another register containing more information.
1168 */
1174 /* the rest are reserved */
1175 };
1178 /*
1179 * counter name
1180 */
1183 /*
1184 * csr to read for name (if applicable)
1185 */
1186 u64 csr;
1188 /*
1189 * offset into dd or ppd to store the counter's value
1190 */
1193 /*
1194 * flags
1195 */
1196 u8 flags;
1198 /*
1199 * accessor for stat element, context either dd or ppd
1200 */
1203 };
1205 #define C_RCV_HDR_OVF_FIRST C_RCV_HDR_OVF_0
1206 #define C_RCV_HDR_OVF_LAST C_RCV_HDR_OVF_159
1208 #define CNTR_ELEM(name, csr, offset, flags, accessor) \
1209 { \
1210 name, \
1211 csr, \
1212 offset, \
1213 flags, \
1214 accessor \
1215 }
1217 /* 32bit RXE */
1218 #define RXE32_PORT_CNTR_ELEM(name, counter, flags) \
1219 CNTR_ELEM(#name, \
1220 (counter * 8 + RCV_COUNTER_ARRAY32), \
1221 0, flags | CNTR_32BIT, \
1222 port_access_u32_csr)
1224 #define RXE32_DEV_CNTR_ELEM(name, counter, flags) \
1225 CNTR_ELEM(#name, \
1226 (counter * 8 + RCV_COUNTER_ARRAY32), \
1227 0, flags | CNTR_32BIT, \
1228 dev_access_u32_csr)
1230 /* 64bit RXE */
1231 #define RXE64_PORT_CNTR_ELEM(name, counter, flags) \
1232 CNTR_ELEM(#name, \
1233 (counter * 8 + RCV_COUNTER_ARRAY64), \
1234 0, flags, \
1235 port_access_u64_csr)
1237 #define RXE64_DEV_CNTR_ELEM(name, counter, flags) \
1238 CNTR_ELEM(#name, \
1239 (counter * 8 + RCV_COUNTER_ARRAY64), \
1240 0, flags, \
1241 dev_access_u64_csr)
1243 #define OVR_LBL(ctx) C_RCV_HDR_OVF_ ## ctx
1244 #define OVR_ELM(ctx) \
1246 (RCV_HDR_OVFL_CNT + ctx * 0x100), \
1247 0, CNTR_NORMAL, port_access_u64_csr)
1249 /* 32bit TXE */
1250 #define TXE32_PORT_CNTR_ELEM(name, counter, flags) \
1251 CNTR_ELEM(#name, \
1252 (counter * 8 + SEND_COUNTER_ARRAY32), \
1253 0, flags | CNTR_32BIT, \
1254 port_access_u32_csr)
1256 /* 64bit TXE */
1257 #define TXE64_PORT_CNTR_ELEM(name, counter, flags) \
1258 CNTR_ELEM(#name, \
1259 (counter * 8 + SEND_COUNTER_ARRAY64), \
1260 0, flags, \
1261 port_access_u64_csr)
1263 # define TX64_DEV_CNTR_ELEM(name, counter, flags) \
1264 CNTR_ELEM(#name,\
1265 counter * 8 + SEND_COUNTER_ARRAY64, \
1266 0, \
1267 flags, \
1268 dev_access_u64_csr)
1270 /* CCE */
1271 #define CCE_PERF_DEV_CNTR_ELEM(name, counter, flags) \
1272 CNTR_ELEM(#name, \
1273 (counter * 8 + CCE_COUNTER_ARRAY32), \
1274 0, flags | CNTR_32BIT, \
1275 dev_access_u32_csr)
1277 #define CCE_INT_DEV_CNTR_ELEM(name, counter, flags) \
1278 CNTR_ELEM(#name, \
1279 (counter * 8 + CCE_INT_COUNTER_ARRAY32), \
1280 0, flags | CNTR_32BIT, \
1281 dev_access_u32_csr)
1283 /* DC */
1284 #define DC_PERF_CNTR(name, counter, flags) \
1285 CNTR_ELEM(#name, \
1286 counter, \
1287 0, \
1288 flags, \
1289 dev_access_u64_csr)
1291 #define DC_PERF_CNTR_LCB(name, counter, flags) \
1292 CNTR_ELEM(#name, \
1293 counter, \
1294 0, \
1295 flags, \
1296 dc_access_lcb_cntr)
1298 /* ibp counters */
1299 #define SW_IBP_CNTR(name, cntr) \
1300 CNTR_ELEM(#name, \
1301 0, \
1302 0, \
1303 CNTR_SYNTH, \
1304 access_ibp_##cntr)
1306 /**
1307 * hfi_addr_from_offset - return addr for readq/writeq
1308 * @dd - the dd device
1309 * @offset - the offset of the CSR within bar0
1310 *
1311 * This routine selects the appropriate base address
1312 * based on the indicated offset.
1313 */
1316 u32 offset)
1317 {
1321 }
1323 /**
1324 * read_csr - read CSR at the indicated offset
1325 * @dd - the dd device
1326 * @offset - the offset of the CSR within bar0
1327 *
1328 * Return: the value read or all FF's if there
1329 * is no mapping
1330 */
1332 {
1336 }
1338 /**
1339 * write_csr - write CSR at the indicated offset
1340 * @dd - the dd device
1341 * @offset - the offset of the CSR within bar0
1342 * @value - value to write
1343 */
1345 {
1349 /* avoid write to RcvArray */
1353 }
1354 }
1356 /**
1357 * get_csr_addr - return te iomem address for offset
1358 * @dd - the dd device
1359 * @offset - the offset of the CSR within bar0
1360 *
1361 * Return: The iomem address to use in subsequent
1362 * writeq/readq operations.
1363 */
1366 u32 offset)
1367 {
1371 }
1375 {
1376 u64 ret;
1386 }
1390 }
1392 /* Dev Access */
1395 {
1406 }
1408 }
1412 {
1418 }
1422 {
1428 }
1432 {
1438 }
1442 u64 data)
1443 {
1449 }
1453 {
1466 }
1470 }
1474 {
1489 }
1493 }
1495 /* Port Access */
1498 {
1504 }
1508 {
1510 u64 val;
1520 }
1523 }
1525 /* Software defined */
1527 u64 data)
1528 {
1529 u64 ret;
1539 }
1544 }
1548 {
1554 }
1558 {
1564 }
1568 u64 data)
1569 {
1575 }
1579 {
1588 else
1592 }
1596 u64 data)
1597 {
1605 }
1609 {
1617 }
1620 {
1627 }
1632 {
1641 /* A write can only zero the counter */
1644 else
1649 }
1652 }
1656 {
1661 }
1665 {
1670 }
1674 {
1678 }
1682 {
1686 }
1690 {
1694 }
1698 {
1702 }
1706 {
1710 }
1714 {
1719 }
1721 /* Software counters for the error status bits within MISC_ERR_STATUS */
1724 u64 data)
1725 {
1729 }
1733 u64 data)
1734 {
1738 }
1742 u64 data)
1743 {
1747 }
1752 {
1756 }
1760 u64 data)
1761 {
1765 }
1770 {
1774 }
1779 {
1783 }
1787 u64 data)
1788 {
1792 }
1796 u64 data)
1797 {
1801 }
1806 {
1810 }
1815 {
1819 }
1824 {
1828 }
1832 u64 data)
1833 {
1837 }
1839 /*
1840 * Software counter for the aggregate of
1841 * individual CceErrStatus counters
1842 */
1846 {
1850 }
1852 /*
1853 * Software counters corresponding to each of the
1854 * error status bits within CceErrStatus
1855 */
1858 u64 data)
1859 {
1863 }
1867 u64 data)
1868 {
1872 }
1876 u64 data)
1877 {
1881 }
1885 u64 data)
1886 {
1890 }
1894 u64 data)
1895 {
1899 }
1904 {
1908 }
1913 {
1917 }
1922 {
1926 }
1930 u64 data)
1931 {
1935 }
1939 {
1943 }
1947 u64 data)
1948 {
1952 }
1956 u64 data)
1957 {
1961 }
1966 {
1970 }
1975 {
1979 }
1983 u64 data)
1984 {
1988 }
1992 u64 data)
1993 {
1997 }
2001 u64 data)
2002 {
2006 }
2010 u64 data)
2011 {
2015 }
2020 {
2024 }
2028 u64 data)
2029 {
2033 }
2038 {
2042 }
2047 {
2051 }
2055 u64 data)
2056 {
2060 }
2064 u64 data)
2065 {
2069 }
2073 u64 data)
2074 {
2078 }
2082 u64 data)
2083 {
2087 }
2092 {
2096 }
2100 u64 data)
2101 {
2105 }
2110 {
2114 }
2119 {
2123 }
2128 {
2132 }
2137 {
2141 }
2146 {
2150 }
2155 {
2159 }
2164 {
2168 }
2172 u64 data)
2173 {
2177 }
2181 u64 data)
2182 {
2186 }
2191 {
2195 }
2200 {
2204 }
2209 {
2213 }
2217 u64 data)
2218 {
2222 }
2224 /*
2225 * Software counters corresponding to each of the
2226 * error status bits within RcvErrStatus
2227 */
2230 u64 data)
2231 {
2235 }
2240 {
2244 }
2248 u64 data)
2249 {
2253 }
2257 u64 data)
2258 {
2262 }
2267 {
2271 }
2276 {
2280 }
2284 u64 data)
2285 {
2289 }
2293 u64 data)
2294 {
2298 }
2302 u64 data)
2303 {
2307 }
2312 {
2316 }
2321 {
2325 }
2330 {
2334 }
2339 {
2343 }
2348 {
2352 }
2357 {
2361 }
2366 {
2370 }
2375 {
2379 }
2383 u64 data)
2384 {
2388 }
2393 {
2397 }
2402 {
2406 }
2411 {
2415 }
2420 {
2424 }
2429 {
2433 }
2438 {
2442 }
2447 {
2451 }
2456 {
2460 }
2465 {
2469 }
2474 {
2478 }
2483 {
2487 }
2492 {
2496 }
2501 {
2505 }
2509 u64 data)
2510 {
2514 }
2518 u64 data)
2519 {
2523 }
2527 u64 data)
2528 {
2532 }
2536 u64 data)
2537 {
2541 }
2546 {
2550 }
2555 {
2559 }
2564 {
2568 }
2573 {
2577 }
2582 {
2586 }
2591 {
2595 }
2600 {
2604 }
2609 {
2613 }
2618 {
2622 }
2627 {
2631 }
2636 {
2640 }
2645 {
2649 }
2654 {
2658 }
2663 {
2667 }
2672 {
2676 }
2681 {
2685 }
2689 u64 data)
2690 {
2694 }
2698 u64 data)
2699 {
2703 }
2707 u64 data)
2708 {
2712 }
2716 u64 data)
2717 {
2721 }
2725 u64 data)
2726 {
2730 }
2735 {
2739 }
2744 {
2748 }
2752 u64 data)
2753 {
2757 }
2761 u64 data)
2762 {
2766 }
2770 u64 data)
2771 {
2775 }
2779 u64 data)
2780 {
2784 }
2788 u64 data)
2789 {
2793 }
2797 u64 data)
2798 {
2802 }
2804 /*
2805 * Software counters corresponding to each of the
2806 * error status bits within SendPioErrStatus
2807 */
2811 {
2815 }
2820 {
2824 }
2829 {
2833 }
2838 {
2842 }
2846 u64 data)
2847 {
2851 }
2855 u64 data)
2856 {
2860 }
2864 u64 data)
2865 {
2869 }
2874 {
2878 }
2882 u64 data)
2883 {
2887 }
2891 u64 data)
2892 {
2896 }
2901 {
2905 }
2910 {
2914 }
2919 {
2923 }
2927 u64 data)
2928 {
2932 }
2937 {
2941 }
2946 {
2950 }
2955 {
2959 }
2964 {
2968 }
2972 u64 data)
2973 {
2977 }
2981 u64 data)
2982 {
2986 }
2991 {
2995 }
3000 {
3004 }
3009 {
3013 }
3018 {
3022 }
3027 {
3031 }
3036 {
3040 }
3045 {
3049 }
3054 {
3058 }
3063 {
3067 }
3071 u64 data)
3072 {
3076 }
3080 u64 data)
3081 {
3085 }
3089 u64 data)
3090 {
3094 }
3098 u64 data)
3099 {
3103 }
3107 u64 data)
3108 {
3112 }
3117 {
3121 }
3125 u64 data)
3126 {
3130 }
3132 /*
3133 * Software counters corresponding to each of the
3134 * error status bits within SendDmaErrStatus
3135 */
3139 {
3143 }
3148 {
3152 }
3156 u64 data)
3157 {
3161 }
3165 u64 data)
3166 {
3170 }
3172 /*
3173 * Software counters corresponding to each of the
3174 * error status bits within SendEgressErrStatus
3175 */
3179 {
3183 }
3188 {
3192 }
3196 u64 data)
3197 {
3201 }
3206 {
3210 }
3215 {
3219 }
3223 u64 data)
3224 {
3228 }
3232 u64 data)
3233 {
3237 }
3241 u64 data)
3242 {
3246 }
3250 u64 data)
3251 {
3255 }
3259 u64 data)
3260 {
3264 }
3268 u64 data)
3269 {
3273 }
3277 u64 data)
3278 {
3282 }
3286 u64 data)
3287 {
3291 }
3295 u64 data)
3296 {
3300 }
3304 u64 data)
3305 {
3309 }
3313 u64 data)
3314 {
3318 }
3322 u64 data)
3323 {
3327 }
3331 u64 data)
3332 {
3336 }
3340 u64 data)
3341 {
3345 }
3350 {
3354 }
3359 {
3363 }
3367 u64 data)
3368 {
3372 }
3377 {
3381 }
3386 {
3390 }
3395 {
3399 }
3404 {
3408 }
3413 {
3417 }
3422 {
3426 }
3431 {
3435 }
3440 {
3444 }
3449 {
3453 }
3458 {
3462 }
3467 {
3471 }
3476 {
3480 }
3485 {
3489 }
3494 {
3498 }
3503 {
3507 }
3512 {
3516 }
3521 {
3525 }
3530 {
3534 }
3539 {
3543 }
3548 {
3552 }
3557 {
3561 }
3566 {
3570 }
3575 {
3579 }
3584 {
3588 }
3593 {
3597 }
3602 {
3606 }
3610 u64 data)
3611 {
3615 }
3620 {
3624 }
3628 u64 data)
3629 {
3633 }
3637 u64 data)
3638 {
3642 }
3647 {
3651 }
3655 u64 data)
3656 {
3660 }
3664 u64 data)
3665 {
3669 }
3674 {
3678 }
3683 {
3687 }
3691 u64 data)
3692 {
3696 }
3701 {
3705 }
3709 u64 data)
3710 {
3714 }
3719 {
3723 }
3727 u64 data)
3728 {
3732 }
3737 {
3741 }
3746 {
3750 }
3752 /*
3753 * Software counters corresponding to each of the
3754 * error status bits within SendErrStatus
3755 */
3759 {
3763 }
3768 {
3772 }
3776 u64 data)
3777 {
3781 }
3783 /*
3784 * Software counters corresponding to each of the
3785 * error status bits within SendCtxtErrStatus
3786 */
3790 {
3794 }
3798 u64 data)
3799 {
3803 }
3808 {
3812 }
3817 {
3821 }
3825 u64 data)
3826 {
3830 }
3832 /*
3833 * Software counters corresponding to each of the
3834 * error status bits within SendDmaEngErrStatus
3835 */
3839 {
3843 }
3848 {
3852 }
3857 {
3861 }
3865 u64 data)
3866 {
3870 }
3874 u64 data)
3875 {
3879 }
3884 {
3888 }
3893 {
3897 }
3902 {
3906 }
3910 u64 data)
3911 {
3915 }
3919 u64 data)
3920 {
3924 }
3928 u64 data)
3929 {
3933 }
3937 u64 data)
3938 {
3942 }
3946 u64 data)
3947 {
3951 }
3955 u64 data)
3956 {
3960 }
3964 u64 data)
3965 {
3969 }
3974 {
3978 }
3983 {
3987 }
3991 {
3995 }
3999 u64 data)
4000 {
4004 }
4008 u64 data)
4009 {
4013 }
4018 {
4022 }
4026 u64 data)
4027 {
4031 }
4035 u64 data)
4036 {
4040 }
4044 u64 data)
4045 {
4049 }
4053 u64 data)
4054 {
4069 }
4071 }
4073 #define def_access_sw_cpu(cntr) \
4074 static u64 access_sw_cpu_##cntr(const struct cntr_entry *entry, \
4075 void *context, int vl, int mode, u64 data) \
4076 { \
4077 struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context; \
4078 return read_write_cpu(ppd->dd, &ppd->ibport_data.rvp.z_ ##cntr, \
4079 ppd->ibport_data.rvp.cntr, vl, \
4080 mode, data); \
4081 }
4087 #define def_access_ibp_counter(cntr) \
4088 static u64 access_ibp_##cntr(const struct cntr_entry *entry, \
4089 void *context, int vl, int mode, u64 data) \
4090 { \
4091 struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context; \
4092 \
4093 if (vl != CNTR_INVALID_VL) \
4094 return 0; \
4095 \
4096 return read_write_sw(ppd->dd, &ppd->ibport_data.rvp.n_ ##cntr, \
4097 mode, data); \
4098 }
4121 CNTR_NORMAL),
4123 CNTR_NORMAL),
4125 RCV_TID_FLOW_GEN_MISMATCH_CNT,
4126 CNTR_NORMAL),
4128 CNTR_NORMAL),
4134 CNTR_NORMAL),
4136 CNTR_NORMAL),
4138 CNTR_NORMAL),
4140 CNTR_NORMAL),
4142 CNTR_NORMAL),
4144 CNTR_NORMAL),
4150 CNTR_SYNTH),
4152 access_dc_rcv_err_cnt),
4154 CNTR_SYNTH),
4156 CNTR_SYNTH),
4158 CNTR_SYNTH),
4162 DCC_PRF_PORT_RCV_MULTICAST_PKT_CNT,
4163 CNTR_SYNTH),
4167 CNTR_SYNTH),
4169 CNTR_SYNTH),
4171 CNTR_SYNTH),
4173 CNTR_SYNTH),
4175 CNTR_SYNTH),
4177 CNTR_SYNTH),
4179 CNTR_SYNTH),
4191 CNTR_SYNTH),
4195 CNTR_SYNTH),
4200 CNTR_SYNTH),
4202 CNTR_SYNTH),
4204 CNTR_SYNTH),
4206 CNTR_SYNTH),
4208 CNTR_SYNTH),
4211 CNTR_SYNTH),
4213 CNTR_SYNTH),
4215 CNTR_SYNTH),
4218 CNTR_SYNTH),
4221 CNTR_SYNTH),
4224 CNTR_SYNTH),
4227 CNTR_SYNTH),
4230 CNTR_SYNTH),
4232 CNTR_SYNTH),
4235 CNTR_SYNTH),
4240 CNTR_SYNTH),
4251 CNTR_SYNTH),
4256 CNTR_SYNTH),
4258 access_sw_cpu_intr),
4260 access_sw_cpu_rcv_limit),
4262 access_sw_ctx0_seq_drop),
4264 access_sw_vtx_wait),
4266 access_sw_pio_wait),
4268 access_sw_pio_drain),
4270 access_sw_kmem_wait),
4272 hfi1_access_sw_tid_wait),
4274 access_sw_send_schedule),
4278 dev_access_u32_csr),
4281 access_sde_int_cnt),
4284 access_sde_err_cnt),
4287 access_sde_idle_int_cnt),
4290 access_sde_progress_int_cnt),
4291 /* MISC_ERR_STATUS */
4293 CNTR_NORMAL,
4294 access_misc_pll_lock_fail_err_cnt),
4296 CNTR_NORMAL,
4297 access_misc_mbist_fail_err_cnt),
4299 CNTR_NORMAL,
4300 access_misc_invalid_eep_cmd_err_cnt),
4302 CNTR_NORMAL,
4303 access_misc_efuse_done_parity_err_cnt),
4305 CNTR_NORMAL,
4306 access_misc_efuse_write_err_cnt),
4309 access_misc_efuse_read_bad_addr_err_cnt),
4311 CNTR_NORMAL,
4312 access_misc_efuse_csr_parity_err_cnt),
4314 CNTR_NORMAL,
4315 access_misc_fw_auth_failed_err_cnt),
4317 CNTR_NORMAL,
4318 access_misc_key_mismatch_err_cnt),
4320 CNTR_NORMAL,
4321 access_misc_sbus_write_failed_err_cnt),
4323 CNTR_NORMAL,
4324 access_misc_csr_write_bad_addr_err_cnt),
4326 CNTR_NORMAL,
4327 access_misc_csr_read_bad_addr_err_cnt),
4329 CNTR_NORMAL,
4330 access_misc_csr_parity_err_cnt),
4331 /* CceErrStatus */
4333 CNTR_NORMAL,
4334 access_sw_cce_err_status_aggregated_cnt),
4336 CNTR_NORMAL,
4337 access_cce_msix_csr_parity_err_cnt),
4339 CNTR_NORMAL,
4340 access_cce_int_map_unc_err_cnt),
4342 CNTR_NORMAL,
4343 access_cce_int_map_cor_err_cnt),
4345 CNTR_NORMAL,
4346 access_cce_msix_table_unc_err_cnt),
4348 CNTR_NORMAL,
4349 access_cce_msix_table_cor_err_cnt),
4352 access_cce_rxdma_conv_fifo_parity_err_cnt),
4355 access_cce_rcpl_async_fifo_parity_err_cnt),
4357 CNTR_NORMAL,
4358 access_cce_seg_write_bad_addr_err_cnt),
4360 CNTR_NORMAL,
4361 access_cce_seg_read_bad_addr_err_cnt),
4363 CNTR_NORMAL,
4364 access_la_triggered_cnt),
4366 CNTR_NORMAL,
4367 access_cce_trgt_cpl_timeout_err_cnt),
4369 CNTR_NORMAL,
4370 access_pcic_receive_parity_err_cnt),
4372 CNTR_NORMAL,
4373 access_pcic_transmit_back_parity_err_cnt),
4376 access_pcic_transmit_front_parity_err_cnt),
4378 CNTR_NORMAL,
4379 access_pcic_cpl_dat_q_unc_err_cnt),
4381 CNTR_NORMAL,
4382 access_pcic_cpl_hd_q_unc_err_cnt),
4384 CNTR_NORMAL,
4385 access_pcic_post_dat_q_unc_err_cnt),
4387 CNTR_NORMAL,
4388 access_pcic_post_hd_q_unc_err_cnt),
4390 CNTR_NORMAL,
4391 access_pcic_retry_sot_mem_unc_err_cnt),
4393 CNTR_NORMAL,
4394 access_pcic_retry_mem_unc_err),
4396 CNTR_NORMAL,
4397 access_pcic_n_post_dat_q_parity_err_cnt),
4399 CNTR_NORMAL,
4400 access_pcic_n_post_h_q_parity_err_cnt),
4402 CNTR_NORMAL,
4403 access_pcic_cpl_dat_q_cor_err_cnt),
4405 CNTR_NORMAL,
4406 access_pcic_cpl_hd_q_cor_err_cnt),
4408 CNTR_NORMAL,
4409 access_pcic_post_dat_q_cor_err_cnt),
4411 CNTR_NORMAL,
4412 access_pcic_post_hd_q_cor_err_cnt),
4414 CNTR_NORMAL,
4415 access_pcic_retry_sot_mem_cor_err_cnt),
4417 CNTR_NORMAL,
4418 access_pcic_retry_mem_cor_err_cnt),
4421 CNTR_NORMAL,
4422 access_cce_cli1_async_fifo_dbg_parity_err_cnt),
4425 CNTR_NORMAL,
4426 access_cce_cli1_async_fifo_rxdma_parity_err_cnt
4427 ),
4430 CNTR_NORMAL,
4431 access_cce_cli1_async_fifo_sdma_hd_parity_err_cnt),
4434 CNTR_NORMAL,
4435 access_cce_cl1_async_fifo_pio_crdt_parity_err_cnt),
4438 access_cce_cli2_async_fifo_parity_err_cnt),
4440 CNTR_NORMAL,
4441 access_cce_csr_cfg_bus_parity_err_cnt),
4444 access_cce_cli0_async_fifo_parity_err_cnt),
4446 CNTR_NORMAL,
4447 access_cce_rspd_data_parity_err_cnt),
4449 CNTR_NORMAL,
4450 access_cce_trgt_access_err_cnt),
4453 access_cce_trgt_async_fifo_parity_err_cnt),
4455 CNTR_NORMAL,
4456 access_cce_csr_write_bad_addr_err_cnt),
4458 CNTR_NORMAL,
4459 access_cce_csr_read_bad_addr_err_cnt),
4461 CNTR_NORMAL,
4462 access_ccs_csr_parity_err_cnt),
4464 /* RcvErrStatus */
4466 CNTR_NORMAL,
4467 access_rx_csr_parity_err_cnt),
4469 CNTR_NORMAL,
4470 access_rx_csr_write_bad_addr_err_cnt),
4472 CNTR_NORMAL,
4473 access_rx_csr_read_bad_addr_err_cnt),
4475 CNTR_NORMAL,
4476 access_rx_dma_csr_unc_err_cnt),
4478 CNTR_NORMAL,
4479 access_rx_dma_dq_fsm_encoding_err_cnt),
4481 CNTR_NORMAL,
4482 access_rx_dma_eq_fsm_encoding_err_cnt),
4484 CNTR_NORMAL,
4485 access_rx_dma_csr_parity_err_cnt),
4487 CNTR_NORMAL,
4488 access_rx_rbuf_data_cor_err_cnt),
4490 CNTR_NORMAL,
4491 access_rx_rbuf_data_unc_err_cnt),
4493 CNTR_NORMAL,
4494 access_rx_dma_data_fifo_rd_cor_err_cnt),
4496 CNTR_NORMAL,
4497 access_rx_dma_data_fifo_rd_unc_err_cnt),
4499 CNTR_NORMAL,
4500 access_rx_dma_hdr_fifo_rd_cor_err_cnt),
4502 CNTR_NORMAL,
4503 access_rx_dma_hdr_fifo_rd_unc_err_cnt),
4505 CNTR_NORMAL,
4506 access_rx_rbuf_desc_part2_cor_err_cnt),
4508 CNTR_NORMAL,
4509 access_rx_rbuf_desc_part2_unc_err_cnt),
4511 CNTR_NORMAL,
4512 access_rx_rbuf_desc_part1_cor_err_cnt),
4514 CNTR_NORMAL,
4515 access_rx_rbuf_desc_part1_unc_err_cnt),
4517 CNTR_NORMAL,
4518 access_rx_hq_intr_fsm_err_cnt),
4520 CNTR_NORMAL,
4521 access_rx_hq_intr_csr_parity_err_cnt),
4523 CNTR_NORMAL,
4524 access_rx_lookup_csr_parity_err_cnt),
4526 CNTR_NORMAL,
4527 access_rx_lookup_rcv_array_cor_err_cnt),
4529 CNTR_NORMAL,
4530 access_rx_lookup_rcv_array_unc_err_cnt),
4533 access_rx_lookup_des_part2_parity_err_cnt),
4536 access_rx_lookup_des_part1_unc_cor_err_cnt),
4538 CNTR_NORMAL,
4539 access_rx_lookup_des_part1_unc_err_cnt),
4541 CNTR_NORMAL,
4542 access_rx_rbuf_next_free_buf_cor_err_cnt),
4544 CNTR_NORMAL,
4545 access_rx_rbuf_next_free_buf_unc_err_cnt),
4548 CNTR_NORMAL,
4549 access_rbuf_fl_init_wr_addr_parity_err_cnt),
4552 access_rx_rbuf_fl_initdone_parity_err_cnt),
4555 access_rx_rbuf_fl_write_addr_parity_err_cnt),
4557 CNTR_NORMAL,
4558 access_rx_rbuf_fl_rd_addr_parity_err_cnt),
4560 CNTR_NORMAL,
4561 access_rx_rbuf_empty_err_cnt),
4563 CNTR_NORMAL,
4564 access_rx_rbuf_full_err_cnt),
4566 CNTR_NORMAL,
4567 access_rbuf_bad_lookup_err_cnt),
4569 CNTR_NORMAL,
4570 access_rbuf_ctx_id_parity_err_cnt),
4572 CNTR_NORMAL,
4573 access_rbuf_csr_qeopdw_parity_err_cnt),
4576 CNTR_NORMAL,
4577 access_rx_rbuf_csr_q_num_of_pkt_parity_err_cnt),
4580 CNTR_NORMAL,
4581 access_rx_rbuf_csr_q_t1_ptr_parity_err_cnt),
4584 access_rx_rbuf_csr_q_hd_ptr_parity_err_cnt),
4587 access_rx_rbuf_csr_q_vld_bit_parity_err_cnt),
4590 access_rx_rbuf_csr_q_next_buf_parity_err_cnt),
4593 access_rx_rbuf_csr_q_ent_cnt_parity_err_cnt),
4596 CNTR_NORMAL,
4597 access_rx_rbuf_csr_q_head_buf_num_parity_err_cnt),
4600 access_rx_rbuf_block_list_read_cor_err_cnt),
4603 access_rx_rbuf_block_list_read_unc_err_cnt),
4605 CNTR_NORMAL,
4606 access_rx_rbuf_lookup_des_cor_err_cnt),
4608 CNTR_NORMAL,
4609 access_rx_rbuf_lookup_des_unc_err_cnt),
4612 CNTR_NORMAL,
4613 access_rx_rbuf_lookup_des_reg_unc_cor_err_cnt),
4615 CNTR_NORMAL,
4616 access_rx_rbuf_lookup_des_reg_unc_err_cnt),
4618 CNTR_NORMAL,
4619 access_rx_rbuf_free_list_cor_err_cnt),
4621 CNTR_NORMAL,
4622 access_rx_rbuf_free_list_unc_err_cnt),
4624 CNTR_NORMAL,
4625 access_rx_rcv_fsm_encoding_err_cnt),
4627 CNTR_NORMAL,
4628 access_rx_dma_flag_cor_err_cnt),
4630 CNTR_NORMAL,
4631 access_rx_dma_flag_unc_err_cnt),
4633 CNTR_NORMAL,
4634 access_rx_dc_sop_eop_parity_err_cnt),
4636 CNTR_NORMAL,
4637 access_rx_rcv_csr_parity_err_cnt),
4639 CNTR_NORMAL,
4640 access_rx_rcv_qp_map_table_cor_err_cnt),
4642 CNTR_NORMAL,
4643 access_rx_rcv_qp_map_table_unc_err_cnt),
4645 CNTR_NORMAL,
4646 access_rx_rcv_data_cor_err_cnt),
4648 CNTR_NORMAL,
4649 access_rx_rcv_data_unc_err_cnt),
4651 CNTR_NORMAL,
4652 access_rx_rcv_hdr_cor_err_cnt),
4654 CNTR_NORMAL,
4655 access_rx_rcv_hdr_unc_err_cnt),
4657 CNTR_NORMAL,
4658 access_rx_dc_intf_parity_err_cnt),
4660 CNTR_NORMAL,
4661 access_rx_dma_csr_cor_err_cnt),
4662 /* SendPioErrStatus */
4664 CNTR_NORMAL,
4665 access_pio_pec_sop_head_parity_err_cnt),
4667 CNTR_NORMAL,
4668 access_pio_pcc_sop_head_parity_err_cnt),
4671 access_pio_last_returned_cnt_parity_err_cnt),
4674 access_pio_current_free_cnt_parity_err_cnt),
4676 CNTR_NORMAL,
4677 access_pio_reserved_31_err_cnt),
4679 CNTR_NORMAL,
4680 access_pio_reserved_30_err_cnt),
4682 CNTR_NORMAL,
4683 access_pio_ppmc_sop_len_err_cnt),
4685 CNTR_NORMAL,
4686 access_pio_ppmc_bqc_mem_parity_err_cnt),
4688 CNTR_NORMAL,
4689 access_pio_vl_fifo_parity_err_cnt),
4691 CNTR_NORMAL,
4692 access_pio_vlf_sop_parity_err_cnt),
4694 CNTR_NORMAL,
4695 access_pio_vlf_v1_len_parity_err_cnt),
4697 CNTR_NORMAL,
4698 access_pio_block_qw_count_parity_err_cnt),
4700 CNTR_NORMAL,
4701 access_pio_write_qw_valid_parity_err_cnt),
4703 CNTR_NORMAL,
4704 access_pio_state_machine_err_cnt),
4706 CNTR_NORMAL,
4707 access_pio_write_data_parity_err_cnt),
4709 CNTR_NORMAL,
4710 access_pio_host_addr_mem_cor_err_cnt),
4712 CNTR_NORMAL,
4713 access_pio_host_addr_mem_unc_err_cnt),
4715 CNTR_NORMAL,
4716 access_pio_pkt_evict_sm_or_arb_sm_err_cnt),
4718 CNTR_NORMAL,
4719 access_pio_init_sm_in_err_cnt),
4721 CNTR_NORMAL,
4722 access_pio_ppmc_pbl_fifo_err_cnt),
4725 access_pio_credit_ret_fifo_parity_err_cnt),
4727 CNTR_NORMAL,
4728 access_pio_v1_len_mem_bank1_cor_err_cnt),
4730 CNTR_NORMAL,
4731 access_pio_v1_len_mem_bank0_cor_err_cnt),
4733 CNTR_NORMAL,
4734 access_pio_v1_len_mem_bank1_unc_err_cnt),
4736 CNTR_NORMAL,
4737 access_pio_v1_len_mem_bank0_unc_err_cnt),
4739 CNTR_NORMAL,
4740 access_pio_sm_pkt_reset_parity_err_cnt),
4742 CNTR_NORMAL,
4743 access_pio_pkt_evict_fifo_parity_err_cnt),
4746 CNTR_NORMAL,
4747 access_pio_sbrdctrl_crrel_fifo_parity_err_cnt),
4749 CNTR_NORMAL,
4750 access_pio_sbrdctl_crrel_parity_err_cnt),
4752 CNTR_NORMAL,
4753 access_pio_pec_fifo_parity_err_cnt),
4755 CNTR_NORMAL,
4756 access_pio_pcc_fifo_parity_err_cnt),
4758 CNTR_NORMAL,
4759 access_pio_sb_mem_fifo1_err_cnt),
4761 CNTR_NORMAL,
4762 access_pio_sb_mem_fifo0_err_cnt),
4764 CNTR_NORMAL,
4765 access_pio_csr_parity_err_cnt),
4767 CNTR_NORMAL,
4768 access_pio_write_addr_parity_err_cnt),
4770 CNTR_NORMAL,
4771 access_pio_write_bad_ctxt_err_cnt),
4772 /* SendDmaErrStatus */
4775 access_sdma_pcie_req_tracking_cor_err_cnt),
4778 access_sdma_pcie_req_tracking_unc_err_cnt),
4780 CNTR_NORMAL,
4781 access_sdma_csr_parity_err_cnt),
4783 CNTR_NORMAL,
4784 access_sdma_rpy_tag_err_cnt),
4785 /* SendEgressErrStatus */
4787 CNTR_NORMAL,
4788 access_tx_read_pio_memory_csr_unc_err_cnt),
4791 access_tx_read_sdma_memory_csr_err_cnt),
4793 CNTR_NORMAL,
4794 access_tx_egress_fifo_cor_err_cnt),
4796 CNTR_NORMAL,
4797 access_tx_read_pio_memory_cor_err_cnt),
4799 CNTR_NORMAL,
4800 access_tx_read_sdma_memory_cor_err_cnt),
4802 CNTR_NORMAL,
4803 access_tx_sb_hdr_cor_err_cnt),
4805 CNTR_NORMAL,
4806 access_tx_credit_overrun_err_cnt),
4808 CNTR_NORMAL,
4809 access_tx_launch_fifo8_cor_err_cnt),
4811 CNTR_NORMAL,
4812 access_tx_launch_fifo7_cor_err_cnt),
4814 CNTR_NORMAL,
4815 access_tx_launch_fifo6_cor_err_cnt),
4817 CNTR_NORMAL,
4818 access_tx_launch_fifo5_cor_err_cnt),
4820 CNTR_NORMAL,
4821 access_tx_launch_fifo4_cor_err_cnt),
4823 CNTR_NORMAL,
4824 access_tx_launch_fifo3_cor_err_cnt),
4826 CNTR_NORMAL,
4827 access_tx_launch_fifo2_cor_err_cnt),
4829 CNTR_NORMAL,
4830 access_tx_launch_fifo1_cor_err_cnt),
4832 CNTR_NORMAL,
4833 access_tx_launch_fifo0_cor_err_cnt),
4835 CNTR_NORMAL,
4836 access_tx_credit_return_vl_err_cnt),
4838 CNTR_NORMAL,
4839 access_tx_hcrc_insertion_err_cnt),
4841 CNTR_NORMAL,
4842 access_tx_egress_fifo_unc_err_cnt),
4844 CNTR_NORMAL,
4845 access_tx_read_pio_memory_unc_err_cnt),
4847 CNTR_NORMAL,
4848 access_tx_read_sdma_memory_unc_err_cnt),
4850 CNTR_NORMAL,
4851 access_tx_sb_hdr_unc_err_cnt),
4853 CNTR_NORMAL,
4854 access_tx_credit_return_partiy_err_cnt),
4857 access_tx_launch_fifo8_unc_or_parity_err_cnt),
4860 access_tx_launch_fifo7_unc_or_parity_err_cnt),
4863 access_tx_launch_fifo6_unc_or_parity_err_cnt),
4866 access_tx_launch_fifo5_unc_or_parity_err_cnt),
4869 access_tx_launch_fifo4_unc_or_parity_err_cnt),
4872 access_tx_launch_fifo3_unc_or_parity_err_cnt),
4875 access_tx_launch_fifo2_unc_or_parity_err_cnt),
4878 access_tx_launch_fifo1_unc_or_parity_err_cnt),
4881 access_tx_launch_fifo0_unc_or_parity_err_cnt),
4884 access_tx_sdma15_disallowed_packet_err_cnt),
4887 access_tx_sdma14_disallowed_packet_err_cnt),
4890 access_tx_sdma13_disallowed_packet_err_cnt),
4893 access_tx_sdma12_disallowed_packet_err_cnt),
4896 access_tx_sdma11_disallowed_packet_err_cnt),
4899 access_tx_sdma10_disallowed_packet_err_cnt),
4902 access_tx_sdma9_disallowed_packet_err_cnt),
4905 access_tx_sdma8_disallowed_packet_err_cnt),
4908 access_tx_sdma7_disallowed_packet_err_cnt),
4911 access_tx_sdma6_disallowed_packet_err_cnt),
4914 access_tx_sdma5_disallowed_packet_err_cnt),
4917 access_tx_sdma4_disallowed_packet_err_cnt),
4920 access_tx_sdma3_disallowed_packet_err_cnt),
4923 access_tx_sdma2_disallowed_packet_err_cnt),
4926 access_tx_sdma1_disallowed_packet_err_cnt),
4929 access_tx_sdma0_disallowed_packet_err_cnt),
4931 CNTR_NORMAL,
4932 access_tx_config_parity_err_cnt),
4934 CNTR_NORMAL,
4935 access_tx_sbrd_ctl_csr_parity_err_cnt),
4937 CNTR_NORMAL,
4938 access_tx_launch_csr_parity_err_cnt),
4940 CNTR_NORMAL,
4941 access_tx_illegal_vl_err_cnt),
4944 CNTR_NORMAL,
4945 access_tx_sbrd_ctl_state_machine_parity_err_cnt),
4947 CNTR_NORMAL,
4948 access_egress_reserved_10_err_cnt),
4950 CNTR_NORMAL,
4951 access_egress_reserved_9_err_cnt),
4954 access_tx_sdma_launch_intf_parity_err_cnt),
4956 CNTR_NORMAL,
4957 access_tx_pio_launch_intf_parity_err_cnt),
4959 CNTR_NORMAL,
4960 access_egress_reserved_6_err_cnt),
4962 CNTR_NORMAL,
4963 access_tx_incorrect_link_state_err_cnt),
4965 CNTR_NORMAL,
4966 access_tx_linkdown_err_cnt),
4969 CNTR_NORMAL,
4970 access_tx_egress_fifi_underrun_or_parity_err_cnt),
4972 CNTR_NORMAL,
4973 access_egress_reserved_2_err_cnt),
4975 CNTR_NORMAL,
4976 access_tx_pkt_integrity_mem_unc_err_cnt),
4978 CNTR_NORMAL,
4979 access_tx_pkt_integrity_mem_cor_err_cnt),
4980 /* SendErrStatus */
4982 CNTR_NORMAL,
4983 access_send_csr_write_bad_addr_err_cnt),
4985 CNTR_NORMAL,
4986 access_send_csr_read_bad_addr_err_cnt),
4988 CNTR_NORMAL,
4989 access_send_csr_parity_cnt),
4990 /* SendCtxtErrStatus */
4992 CNTR_NORMAL,
4993 access_pio_write_out_of_bounds_err_cnt),
4995 CNTR_NORMAL,
4996 access_pio_write_overflow_err_cnt),
4999 access_pio_write_crosses_boundary_err_cnt),
5001 CNTR_NORMAL,
5002 access_pio_disallowed_packet_err_cnt),
5004 CNTR_NORMAL,
5005 access_pio_inconsistent_sop_err_cnt),
5006 /* SendDmaEngErrStatus */
5009 access_sdma_header_request_fifo_cor_err_cnt),
5011 CNTR_NORMAL,
5012 access_sdma_header_storage_cor_err_cnt),
5014 CNTR_NORMAL,
5015 access_sdma_packet_tracking_cor_err_cnt),
5017 CNTR_NORMAL,
5018 access_sdma_assembly_cor_err_cnt),
5020 CNTR_NORMAL,
5021 access_sdma_desc_table_cor_err_cnt),
5024 access_sdma_header_request_fifo_unc_err_cnt),
5026 CNTR_NORMAL,
5027 access_sdma_header_storage_unc_err_cnt),
5029 CNTR_NORMAL,
5030 access_sdma_packet_tracking_unc_err_cnt),
5032 CNTR_NORMAL,
5033 access_sdma_assembly_unc_err_cnt),
5035 CNTR_NORMAL,
5036 access_sdma_desc_table_unc_err_cnt),
5038 CNTR_NORMAL,
5039 access_sdma_timeout_err_cnt),
5041 CNTR_NORMAL,
5042 access_sdma_header_length_err_cnt),
5044 CNTR_NORMAL,
5045 access_sdma_header_address_err_cnt),
5047 CNTR_NORMAL,
5048 access_sdma_header_select_err_cnt),
5050 CNTR_NORMAL,
5051 access_sdma_reserved_9_err_cnt),
5053 CNTR_NORMAL,
5054 access_sdma_packet_desc_overflow_err_cnt),
5056 CNTR_NORMAL,
5057 access_sdma_length_mismatch_err_cnt),
5059 CNTR_NORMAL,
5060 access_sdma_halt_err_cnt),
5062 CNTR_NORMAL,
5063 access_sdma_mem_read_err_cnt),
5065 CNTR_NORMAL,
5066 access_sdma_first_desc_err_cnt),
5068 CNTR_NORMAL,
5069 access_sdma_tail_out_of_bounds_err_cnt),
5071 CNTR_NORMAL,
5072 access_sdma_too_long_err_cnt),
5074 CNTR_NORMAL,
5075 access_sdma_gen_mismatch_err_cnt),
5077 CNTR_NORMAL,
5078 access_sdma_wrong_dw_err_cnt),
5079 };
5083 CNTR_NORMAL),
5085 CNTR_NORMAL),
5087 CNTR_NORMAL),
5089 CNTR_NORMAL),
5091 CNTR_NORMAL),
5093 CNTR_NORMAL),
5095 CNTR_NORMAL),
5108 access_sw_link_dn_cnt),
5110 access_sw_link_up_cnt),
5112 access_sw_unknown_frame_cnt),
5114 access_sw_xmit_discards),
5117 access_sw_xmit_discards),
5119 access_xmit_constraint_errs),
5121 access_rcv_constraint_errs),
5136 access_sw_cpu_rc_acks),
5138 access_sw_cpu_rc_qacks),
5140 access_sw_cpu_rc_delayed_comp),
5221 };
5223 /* ======================================================================== */
5225 /* return true if this is chip revision revision a */
5227 {
5228 u8 chip_rev_minor =
5232 }
5234 /* return true if this is chip revision revision b */
5236 {
5237 u8 chip_rev_minor =
5241 }
5243 /* return true is kernel urg disabled for rcd */
5245 {
5246 u64 mask;
5252 }
5254 /*
5255 * Append string s to buffer buf. Arguments curp and len are the current
5256 * position and remaining length, respectively.
5257 *
5258 * return 0 on success, 1 on out of room
5259 */
5261 {
5267 /* add a comma, if first in the buffer */
5272 }
5274 len--;
5275 }
5277 /* copy the string */
5282 }
5284 len--;
5285 }
5287 done:
5288 /* write return values */
5293 }
5295 /*
5296 * Using the given flag table, print a comma separated string into
5297 * the buffer. End in '*' if the buffer is too short.
5298 */
5301 {
5308 /* make sure there is at least 2 so we can form "*" */
5319 }
5320 }
5322 /* any undocumented bits left? */
5326 }
5328 /* add * if ran out of room */
5330 /* may need to back up to add space for a '*' */
5334 }
5336 /* add final nul - space already allocated above */
5339 }
5341 /* first 8 CCE error interrupt source names */
5351 };
5353 /*
5354 * Return the miscellaneous error interrupt name.
5355 */
5357 {
5360 else
5365 }
5367 /*
5368 * Return the SDMA engine error interrupt name.
5369 */
5371 {
5374 }
5376 /*
5377 * Return the send context error interrupt name.
5378 */
5380 {
5383 }
5390 "TCritInt"
5391 };
5393 /*
5394 * Return the various interrupt name.
5395 */
5397 {
5400 else
5403 }
5405 /*
5406 * Return the DC interrupt name.
5407 */
5409 {
5415 };
5419 else
5422 }
5428 };
5430 /*
5431 * Return the SDMA engine interrupt name.
5432 */
5434 {
5435 /* what interrupt */
5437 /* which engine */
5442 else
5445 }
5447 /*
5448 * Return the receive available interrupt name.
5449 */
5451 {
5454 }
5456 /*
5457 * Return the receive urgent interrupt name.
5458 */
5460 {
5463 }
5465 /*
5466 * Return the send credit interrupt name.
5467 */
5469 {
5472 }
5474 /*
5475 * Return the reserved interrupt name.
5476 */
5478 {
5481 }
5484 {
5486 cce_err_status_flags,
5488 }
5491 {
5493 rxe_err_status_flags,
5495 }
5498 {
5501 }
5504 {
5506 pio_err_status_flags,
5508 }
5511 {
5513 sdma_err_status_flags,
5515 }
5518 {
5520 egress_err_status_flags,
5522 }
5525 {
5527 egress_err_info_flags,
5529 }
5532 {
5534 send_err_status_flags,
5536 }
5539 {
5543 /*
5544 * For most these errors, there is nothing that can be done except
5545 * report or record it.
5546 */
5552 /* this error requires a manual drop into SPC freeze mode */
5553 /* then a fix up */
5555 }
5560 /* maintain a counter over all cce_err_status errors */
5562 }
5563 }
5564 }
5566 /*
5567 * Check counters for receive errors that do not have an interrupt
5568 * associated with them.
5569 */
5570 #define RCVERR_CHECK_TIME 10
5572 {
5582 OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN);
5584 }
5588 }
5591 {
5593 /* Assume the hardware counter has been reset */
5596 }
5599 {
5602 }
5605 {
5615 /*
5616 * Freeze mode recovery is disabled for the errors
5617 * in RXE_FREEZE_ABORT_MASK
5618 */
5623 }
5628 }
5629 }
5632 {
5641 }
5642 }
5645 {
5658 }
5659 }
5662 {
5675 }
5676 }
5679 {
5681 }
5684 {
5686 }
5688 /*
5689 * We have had a "disallowed packet" error during egress. Determine the
5690 * integrity check which failed, and update relevant error counter, etc.
5691 *
5692 * Note that the SEND_EGRESS_ERR_INFO register has only a single
5693 * bit of state per integrity check, and so we can miss the reason for an
5694 * egress error if more than one packet fails the same integrity check
5695 * since we cleared the corresponding bit in SEND_EGRESS_ERR_INFO.
5696 */
5699 {
5705 /* clear down all observed info as quickly as possible after read */
5712 /* Eventually add other counters for each bit */
5716 /*
5717 * Count all applicable bits as individual errors and
5718 * attribute them to the packet that triggered this handler.
5719 * This may not be completely accurate due to limitations
5720 * on the available hardware error information. There is
5721 * a single information register and any number of error
5722 * packets may have occurred and contributed to it before
5723 * this routine is called. This means that:
5724 * a) If multiple packets with the same error occur before
5725 * this routine is called, earlier packets are missed.
5726 * There is only a single bit for each error type.
5727 * b) Errors may not be attributed to the correct VL.
5728 * The driver is attributing all bits in the info register
5729 * to the packet that triggered this call, but bits
5730 * could be an accumulation of different packets with
5731 * different VLs.
5732 * c) A single error packet may have multiple counts attached
5733 * to it. There is no way for the driver to know if
5734 * multiple bits set in the info register are due to a
5735 * single packet or multiple packets. The driver assumes
5736 * multiple packets.
5737 */
5746 }
5747 }
5748 }
5750 /*
5751 * Input value is a bit position within the SEND_EGRESS_ERR_STATUS
5752 * register. Does it represent a 'port inactive' error?
5753 */
5755 {
5758 }
5760 /*
5761 * Input value is a bit position within the SEND_EGRESS_ERR_STATUS
5762 * register. Does it represent a 'disallowed packet' error?
5763 */
5765 {
5768 }
5770 /*
5771 * Input value is a bit position of one of the SDMA engine disallowed
5772 * packet errors. Return which engine. Use of this must be guarded by
5773 * disallowed_pkt_err().
5774 */
5776 {
5778 }
5780 /*
5781 * Translate an SDMA engine to a VL. Return -1 if the tranlation cannot
5782 * be done.
5783 */
5785 {
5789 /* range check */
5799 }
5801 /*
5802 * Translate the send context (sofware index) into a VL. Return -1 if the
5803 * translation cannot be done.
5804 */
5806 {
5813 /* there is no information for user (PSM) and ack contexts */
5827 }
5830 {
5844 /* fls64() returns a 1-based offset, we want it zero based */
5856 }
5858 }
5869 }
5870 }
5873 {
5883 }
5884 }
5886 /*
5887 * The maximum number of times the error clear down will loop before
5888 * blocking a repeating error. This value is arbitrary.
5889 */
5890 #define MAX_CLEAR_COUNT 20
5892 /*
5893 * Clear and handle an error register. All error interrupts are funneled
5894 * through here to have a central location to correctly handle single-
5895 * or multi-shot errors.
5896 *
5897 * For non per-context registers, call this routine with a context value
5898 * of 0 so the per-context offset is zero.
5899 *
5900 * If the handler loops too many times, assume that something is wrong
5901 * and can't be fixed, so mask the error bits.
5902 */
5904 u32 context,
5906 {
5907 u64 reg;
5908 u32 count;
5910 /* read in a loop until no more errors are seen */
5919 count++;
5921 u64 mask;
5925 /*
5926 * Read-modify-write so any other masked bits
5927 * remain masked.
5928 */
5933 }
5934 }
5935 }
5937 /*
5938 * CCE block "misc" interrupt. Source is < 16.
5939 */
5941 {
5948 source);
5949 }
5950 }
5953 {
5955 sc_err_status_flags,
5957 }
5959 /*
5960 * Send context error interrupt. Source (hw_context) is < 160.
5961 *
5962 * All send context errors cause the send context to halt. The normal
5963 * clear-down mechanism cannot be used because we cannot clear the
5964 * error bits until several other long-running items are done first.
5965 * This is OK because with the context halted, nothing else is going
5966 * to happen on it anyway.
5967 */
5970 {
5974 u64 status;
5975 u32 sw_index;
5985 }
5994 }
5996 /* tell the software that a halt has begun */
6003 status));
6008 /*
6009 * Automatically restart halted kernel contexts out of interrupt
6010 * context. User contexts must ask the driver to restart the context.
6011 */
6016 /*
6017 * Update the counters for the corresponding status bits.
6018 * Note that these particular counters are aggregated over all
6019 * 160 contexts.
6020 */
6024 }
6025 }
6029 {
6034 #ifdef CONFIG_SDMA_VERBOSITY
6039 #endif
6043 /*
6044 * Update the counters for the corresponding status bits.
6045 * Note that these particular counters are aggregated over
6046 * all 16 DMA engines.
6047 */
6051 }
6052 }
6054 /*
6055 * CCE block SDMA error interrupt. Source is < 16.
6056 */
6058 {
6059 #ifdef CONFIG_SDMA_VERBOSITY
6065 source);
6067 #endif
6069 }
6071 /*
6072 * CCE block "various" interrupt. Source is < 8.
6073 */
6075 {
6078 /*
6079 * TCritInt cannot go through interrupt_clear_down()
6080 * because it is not a second tier interrupt. The handler
6081 * should be called directly.
6082 */
6087 else
6091 }
6094 {
6095 /* src_ctx is always zero */
6103 __func__);
6106 /*
6107 * Cable removed, reset all our information about the
6108 * cache and cable capabilities
6109 */
6112 /*
6113 * We don't set cache_refresh_required here as we expect
6114 * an interrupt when a cable is inserted
6115 */
6120 flags);
6121 /* Invert the ModPresent pin now to detect plug-in */
6127 OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED)) ||
6132 OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED);
6135 /*
6136 * The link is still in POLL. This means
6137 * that the normal link down processing
6138 * will not happen. We have to do it here
6139 * before turning the DC off.
6140 */
6142 }
6145 __func__);
6151 flags);
6153 /*
6154 * Stop inversion of ModPresent pin to detect
6155 * removal of the cable
6156 */
6163 }
6164 }
6168 __func__);
6172 }
6174 /* Schedule the QSFP work only if there is a cable attached. */
6177 }
6180 {
6189 }
6191 }
6194 {
6203 }
6205 }
6207 /*
6208 * Set the LCB selector - allow host access. The DCC selector always
6209 * points to the host.
6210 */
6212 {
6214 DC_DC8051_CFG_CSR_ACCESS_SEL_DCC_SMASK |
6215 DC_DC8051_CFG_CSR_ACCESS_SEL_LCB_SMASK);
6216 }
6218 /*
6219 * Clear the LCB selector - allow 8051 access. The DCC selector always
6220 * points to the host.
6221 */
6223 {
6225 DC_DC8051_CFG_CSR_ACCESS_SEL_DCC_SMASK);
6226 }
6228 /*
6229 * Acquire LCB access from the 8051. If the host already has access,
6230 * just increment a counter. Otherwise, inform the 8051 that the
6231 * host is taking access.
6232 *
6233 * Returns:
6234 * 0 on success
6235 * -EBUSY if the 8051 has control and cannot be disturbed
6236 * -errno if unable to acquire access from the 8051
6237 */
6239 {
6243 /*
6244 * Use the host link state lock so the operation of this routine
6245 * { link state check, selector change, count increment } can occur
6246 * as a unit against a link state change. Otherwise there is a
6247 * race between the state change and the count increment.
6248 */
6254 }
6256 /* this access is valid only when the link is up */
6262 }
6271 }
6273 }
6275 done:
6278 }
6280 /*
6281 * Release LCB access by decrementing the use count. If the count is moving
6282 * from 1 to 0, inform 8051 that it has control back.
6283 *
6284 * Returns:
6285 * 0 on success
6286 * -errno if unable to release access to the 8051
6287 */
6289 {
6292 /*
6293 * Use the host link state lock because the acquire needed it.
6294 * Here, we only need to keep { selector change, count decrement }
6295 * as a unit.
6296 */
6302 }
6306 __func__);
6308 }
6317 /* restore host access if the grant didn't work */
6320 }
6321 }
6323 done:
6326 }
6328 /*
6329 * Initialize LCB access variables and state. Called during driver load,
6330 * after most of the initialization is finished.
6331 *
6332 * The DC default is LCB access on for the host. The driver defaults to
6333 * leaving access to the 8051. Assign access now - this constrains the call
6334 * to this routine to be after all LCB set-up is done. In particular, after
6335 * hf1_init_dd() -> set_up_interrupts() -> clear_all_interrupts()
6336 */
6338 {
6340 }
6342 /*
6343 * Write a response back to a 8051 request.
6344 */
6346 {
6348 DC_DC8051_CFG_EXT_DEV_0_COMPLETED_SMASK |
6350 DC_DC8051_CFG_EXT_DEV_0_RETURN_CODE_SHIFT |
6352 }
6354 /*
6355 * Handle host requests from the 8051.
6356 */
6358 {
6360 u64 reg;
6362 u8 type;
6368 /* zero out COMPLETED so the response is seen */
6371 /* extract request details */
6385 type);
6389 /* Put the LCB, RX FPE and TX FPE into reset */
6391 /* Make sure the write completed */
6393 /* Hold the reset long enough to take effect */
6395 /* Take the LCB, RX FPE and TX FPE out of reset */
6411 }
6412 }
6414 /*
6415 * Set up allocation unit vaulue.
6416 */
6418 {
6421 /* do not modify other values in the register */
6425 }
6427 /*
6428 * Set up initial VL15 credits of the remote. Assumes the rest of
6429 * the CM credit registers are zero from a previous global or credit reset.
6430 * Shared limit for VL15 will always be 0.
6431 */
6433 {
6436 /* set initial values for total and shared credit limit */
6438 SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SMASK);
6440 /*
6441 * Set total limit to be equal to VL15 credits.
6442 * Leave shared limit at 0.
6443 */
6449 }
6451 /*
6452 * Zero all credit details from the previous connection and
6453 * reset the CM manager's internal counters.
6454 */
6456 {
6459 /* remove all previous VL credit limits */
6464 /* reset the CM block */
6466 /* reset cached value */
6468 }
6470 /* convert a vCU to a CU */
6472 {
6474 }
6476 /* convert a CU to a vCU */
6478 {
6480 }
6482 /* convert a vAU to an AU */
6484 {
6486 }
6489 {
6492 }
6494 /*
6495 * Graceful LCB shutdown. This leaves the LCB FIFOs in reset.
6496 */
6498 {
6499 u64 reg;
6501 /* clear lcb run: LCB_CFG_RUN.EN = 0 */
6503 /* set tx fifo reset: LCB_CFG_TX_FIFOS_RESET.VAL = 1 */
6506 /* set dcc reset csr: DCC_CFG_RESET.{reset_lcb,reset_rx_fpe} = 1 */
6516 }
6517 }
6519 /*
6520 * This routine should be called after the link has been transitioned to
6521 * OFFLINE (OFFLINE state has the side effect of putting the SerDes into
6522 * reset).
6523 *
6524 * The expectation is that the caller of this routine would have taken
6525 * care of properly transitioning the link into the correct state.
6526 * NOTE: the caller needs to acquire the dd->dc8051_lock lock
6527 * before calling this function.
6528 */
6530 {
6537 /* Shutdown the LCB */
6539 /*
6540 * Going to OFFLINE would have causes the 8051 to put the
6541 * SerDes into reset already. Just need to shut down the 8051,
6542 * itself.
6543 */
6545 }
6548 {
6552 }
6554 /*
6555 * Calling this after the DC has been brought out of reset should not
6556 * do any damage.
6557 * NOTE: the caller needs to acquire the dd->dc8051_lock lock
6558 * before calling this function.
6559 */
6561 {
6567 /* Take the 8051 out of reset */
6569 /* Wait until 8051 is ready */
6572 __func__);
6574 /* Take away reset for LCB and RX FPE (set in lcb_shutdown). */
6576 /* lcb_shutdown() with abort=1 does not restore these */
6579 }
6582 {
6586 }
6588 /*
6589 * These LCB adjustments are for the Aurora SerDes core in the FPGA.
6590 */
6592 {
6594 u32 version;
6599 /*
6600 * These LCB defaults on emulator _s are good, nothing to do here:
6601 * LCB_CFG_TX_FIFOS_RADR
6602 * LCB_CFG_RX_FIFOS_RADR
6603 * LCB_CFG_LN_DCLK
6604 * LCB_CFG_IGNORE_LOST_RCLK
6605 */
6608 /* else this is _p */
6615 /* release 0x12 and below */
6617 /*
6618 * LCB_CFG_RX_FIFOS_RADR.RST_VAL = 0x9
6619 * LCB_CFG_RX_FIFOS_RADR.OK_TO_JUMP_VAL = 0x9
6620 * LCB_CFG_RX_FIFOS_RADR.DO_NOT_JUMP_VAL = 0xa
6621 */
6622 rx_radr =
6626 /*
6627 * LCB_CFG_TX_FIFOS_RADR.ON_REINIT = 0 (default)
6628 * LCB_CFG_TX_FIFOS_RADR.RST_VAL = 6
6629 */
6632 /* release 0x13 up to 0x18 */
6633 /* LCB_CFG_RX_FIFOS_RADR = 0x988 */
6634 rx_radr =
6640 /* release 0x19 */
6641 /* LCB_CFG_RX_FIFOS_RADR = 0xa99 */
6642 rx_radr =
6648 /* release 0x1a */
6649 /* LCB_CFG_RX_FIFOS_RADR = 0x988 */
6650 rx_radr =
6657 /* release 0x1b and higher */
6658 /* LCB_CFG_RX_FIFOS_RADR = 0x877 */
6659 rx_radr =
6664 }
6667 /* LCB_CFG_IGNORE_LOST_RCLK.EN = 1 */
6669 DC_LCB_CFG_IGNORE_LOST_RCLK_EN_SMASK);
6671 }
6673 /*
6674 * Handle a SMA idle message
6675 *
6676 * This is a work-queue function outside of the interrupt.
6677 */
6679 {
6681 sma_message_work);
6683 u64 msg;
6686 /*
6687 * msg is bytes 1-4 of the 40-bit idle message - the command code
6688 * is stripped off
6689 */
6694 /*
6695 * React to the SMA message. Byte[1] (0 for us) is the command.
6696 */
6699 /*
6700 * See OPAv1 table 9-14 - HFI and External Switch Ports Key
6701 * State Transitions
6702 *
6703 * Only expected in INIT or ARMED, discard otherwise.
6704 */
6709 /*
6710 * See OPAv1 table 9-14 - HFI and External Switch Ports Key
6711 * State Transitions
6712 *
6713 * Can activate the node. Discard otherwise.
6714 */
6721 dd,
6723 __func__);
6724 }
6731 }
6732 }
6735 {
6736 u64 rcvctrl;
6745 }
6748 {
6750 }
6753 {
6755 }
6757 /*
6758 * Called from all interrupt handlers to start handling an SPC freeze.
6759 */
6761 {
6770 /* enter frozen mode */
6773 /* notify all SDMA engines that they are going into a freeze */
6778 /* do halt pre-handling on all enabled send contexts */
6783 }
6785 /* Send context are frozen. Notify user space */
6792 }
6793 /* queue non-interrupt handler */
6795 }
6797 /*
6798 * Wait until all 4 sub-blocks indicate that they have frozen or unfrozen,
6799 * depending on the "freeze" parameter.
6800 *
6801 * No need to return an error if it times out, our only option
6802 * is to proceed anyway.
6803 */
6805 {
6807 u64 reg;
6813 /* waiting until all indicators are set */
6817 /* waiting until all indicators are clear */
6820 }
6828 }
6830 }
6831 }
6833 /*
6834 * Do all freeze handling for the RXE block.
6835 */
6837 {
6841 /* disable port */
6844 /* disable all receive contexts */
6849 }
6850 }
6852 /*
6853 * Unfreeze handling for the RXE block - kernel contexts only.
6854 * This will also enable the port. User contexts will do unfreeze
6855 * handling on a per-context basis as they call into the driver.
6856 *
6857 */
6859 {
6860 u32 rcvmask;
6861 u16 i;
6864 /* enable all kernel contexts */
6868 /* Ensure all non-user contexts(including vnic) are enabled */
6873 }
6875 /* HFI1_RCVCTRL_TAILUPD_[ENB|DIS] needs to be set explicitly */
6880 }
6882 /* enable port */
6884 }
6886 /*
6887 * Non-interrupt SPC freeze handling.
6888 *
6889 * This is a work-queue function outside of the triggering interrupt.
6890 */
6892 {
6894 freeze_work);
6897 /* wait for freeze indicators on all affected blocks */
6900 /* SPC is now frozen */
6902 /* do send PIO freeze steps */
6905 /* do send DMA freeze steps */
6908 /* do send egress freeze steps - nothing to do */
6910 /* do receive freeze steps */
6913 /*
6914 * Unfreeze the hardware - clear the freeze, wait for each
6915 * block's frozen bit to clear, then clear the frozen flag.
6916 */
6925 }
6927 /* do send PIO unfreeze steps for kernel contexts */
6930 /* do send DMA unfreeze steps */
6933 /* do send egress unfreeze steps - nothing to do */
6935 /* do receive unfreeze steps for kernel contexts */
6938 /*
6939 * The unfreeze procedure touches global device registers when
6940 * it disables and re-enables RXE. Mark the device unfrozen
6941 * after all that is done so other parts of the driver waiting
6942 * for the device to unfreeze don't do things out of order.
6943 *
6944 * The above implies that the meaning of HFI1_FROZEN flag is
6945 * "Device has gone into freeze mode and freeze mode handling
6946 * is still in progress."
6947 *
6948 * The flag will be removed when freeze mode processing has
6949 * completed.
6950 */
6954 /* no longer frozen */
6955 }
6957 /**
6958 * update_xmit_counters - update PortXmitWait/PortVlXmitWait
6959 * counters.
6960 * @ppd: info of physical Hfi port
6961 * @link_width: new link width after link up or downgrade
6962 *
6963 * Update the PortXmitWait and PortVlXmitWait counters after
6964 * a link up or downgrade event to reflect a link width change.
6965 */
6967 {
6969 u16 tx_width;
6970 u16 link_speed;
6975 /*
6976 * There are C_VL_COUNT number of PortVLXmitWait counters.
6977 * Adding 1 to C_VL_COUNT to include the PortXmitWait counter.
6978 */
6981 }
6983 /*
6984 * Handle a link up interrupt from the 8051.
6985 *
6986 * This is a work-queue function outside of the interrupt.
6987 */
6989 {
6991 link_up_work);
6996 /* cache the read of DC_LCB_STS_ROUND_TRIP_LTP_CNT */
6998 /*
6999 * OPA specifies that certain counters are cleared on a transition
7000 * to link up, so do that.
7001 */
7003 /*
7004 * And (re)set link up default values.
7005 */
7008 /*
7009 * Set VL15 credits. Use cached value from verify cap interrupt.
7010 * In case of quick linkup or simulator, vl15 value will be set by
7011 * handle_linkup_change. VerifyCap interrupt handler will not be
7012 * called in those scenarios.
7013 */
7017 /* enforce link speed enabled */
7019 /* oops - current speed is not enabled, bounce */
7024 OPA_LINKDOWN_REASON_SPEED_POLICY);
7027 }
7028 }
7030 /*
7031 * Several pieces of LNI information were cached for SMA in ppd.
7032 * Reset these on link down
7033 */
7035 {
7040 }
7096 };
7098 /* return the neighbor link down reason string */
7100 {
7109 }
7111 /*
7112 * Handle a link down interrupt from the 8051.
7113 *
7114 * This is a work-queue function outside of the interrupt.
7115 */
7117 {
7119 u8 link_down_reason;
7121 link_down_work);
7131 /* Go offline first, then deal with reading/writing through 8051 */
7138 /* link down reason is only valid if the link was up */
7142 /* the link went down, no idle message reason */
7144 ldr_str);
7147 /*
7148 * The neighbor reason is only valid if an idle message
7149 * was received for it.
7150 */
7160 ldr_str);
7166 }
7168 /*
7169 * If no reason, assume peer-initiated but missed
7170 * LinkGoingDown idle flits.
7171 */
7175 /* went down while polling or going up */
7177 }
7181 /* inform the SMA when the link transitions from up to down */
7188 }
7192 /* disable the port */
7195 /*
7196 * If there is no cable attached, turn the DC off. Otherwise,
7197 * start the link bring up.
7198 */
7201 else
7203 }
7206 {
7208 link_bounce_work);
7210 /*
7211 * Only do something if the link is currently up.
7212 */
7219 }
7220 }
7222 /*
7223 * Mask conversion: Capability exchange to Port LTP. The capability
7224 * exchange has an implicit 16b CRC that is mandatory.
7225 */
7227 {
7238 }
7240 /*
7241 * Convert an OPA Port LTP mask to capability mask
7242 */
7244 {
7255 }
7257 /*
7258 * Convert a single DC LCB CRC mode to an OPA Port LTP mask.
7259 */
7261 {
7270 else
7274 }
7277 {
7282 }
7283 }
7285 /*
7286 * Convert the given link width to the OPA link width bitmask.
7287 */
7289 {
7292 /*
7293 * Simulator and quick linkup do not set the width.
7294 * Just set it to 4x without complaint.
7295 */
7305 /* fall through */
7307 }
7308 }
7310 /*
7311 * Do a population count on the bottom nibble.
7312 */
7315 };
7318 {
7320 }
7322 /*
7323 * Read the active lane information from the 8051 registers and return
7324 * their widths.
7325 *
7326 * Active lane information is found in these 8051 registers:
7327 * enable_lane_tx
7328 * enable_lane_rx
7329 */
7332 {
7334 u8 enable_lane_rx;
7335 u8 enable_lane_tx;
7336 u8 tx_polarity_inversion;
7337 u8 rx_polarity_inversion;
7338 u8 max_rate;
7340 /* read the active lanes */
7345 /* convert to counts */
7349 /*
7350 * Set link_speed_active here, overriding what was set in
7351 * handle_verify_cap(). The ASIC 8051 firmware does not correctly
7352 * set the max_rate field in handle_verify_cap until v0.19.
7353 */
7356 /* max_rate: 0 = 12.5G, 1 = 25G */
7365 /* fall through */
7369 }
7370 }
7377 }
7379 /*
7380 * Read verify_cap_local_fm_link_width[1] to obtain the link widths.
7381 * Valid after the end of VerifyCap and during LinkUp. Does not change
7382 * after link up. I.e. look elsewhere for downgrade information.
7383 *
7384 * Bits are:
7385 * + bits [7:4] contain the number of active transmitters
7386 * + bits [3:0] contain the number of active receivers
7387 * These are numbers 1 through 4 and can be different values if the
7388 * link is asymmetric.
7389 *
7390 * verify_cap_local_fm_link_width[0] retains its original value.
7391 */
7394 {
7406 /* print the active widths */
7408 }
7410 /*
7411 * Set ppd->link_width_active and ppd->link_width_downgrade_active using
7412 * hardware information when the link first comes up.
7413 *
7414 * The link width is not available until after VerifyCap.AllFramesReceived
7415 * (the trigger for handle_verify_cap), so this is outside that routine
7416 * and should be called when the 8051 signals linkup.
7417 */
7419 {
7422 /* get end-of-LNI link widths */
7425 /* use tx_width as the link is supposed to be symmetric on link up */
7427 /* link width downgrade active (LWD.A) starts out matching LW.A */
7430 /* per OPA spec, on link up LWD.E resets to LWD.S */
7432 /* cache the active egress rate (units {10^6 bits/sec]) */
7434 }
7436 /*
7437 * Handle a verify capabilities interrupt from the 8051.
7438 *
7439 * This is a work-queue function outside of the interrupt.
7440 */
7442 {
7444 link_vc_work);
7446 u64 reg;
7447 u8 power_management;
7448 u8 continuous;
7449 u8 vcu;
7450 u8 vau;
7451 u8 z;
7452 u16 vl15buf;
7453 u16 link_widths;
7454 u16 crc_mask;
7455 u16 crc_val;
7456 u16 device_id;
7458 u8 partner_supported_crc;
7459 u8 remote_tx_rate;
7460 u8 device_rev;
7473 /* print the active widths */
7486 /*
7487 * The peer vAU value just read is the peer receiver value. HFI does
7488 * not support a transmit vAU of 0 (AU == 8). We advertised that
7489 * with Z=1 in the fabric capabilities sent to the peer. The peer
7490 * will see our Z=1, and, if it advertised a vAU of 0, will move its
7491 * receive to vAU of 1 (AU == 16). Do the same here. We do not care
7492 * about the peer Z value - our sent vAU is 3 (hardwired) and is not
7493 * subject to the Z value exception.
7494 */
7499 /*
7500 * Set VL15 credits to 0 in global credit register. Cache remote VL15
7501 * credits value and wait for link-up interrupt ot set it.
7502 */
7506 /* set up the LCB CRC mode */
7509 /* order is important: use the lowest bit in common */
7516 else
7523 /* set (14b only) or clear sideband credit */
7531 }
7535 /* remote_tx_rate: 0 = 12.5G, 1 = 25G */
7543 }
7545 /* actual rate is highest bit of the ANDed rates */
7552 }
7557 }
7559 /*
7560 * Cache the values of the supported, enabled, and active
7561 * LTP CRC modes to return in 'portinfo' queries. But the bit
7562 * flags that are returned in the portinfo query differ from
7563 * what's in the link_crc_mask, crc_sizes, and crc_val
7564 * variables. Convert these here.
7565 */
7567 /* supported crc modes */
7570 /* enabled crc modes */
7572 /* active crc mode */
7574 /* set up the remote credit return table */
7577 /*
7578 * The LCB is reset on entry to handle_verify_cap(), so this must
7579 * be applied on every link up.
7580 *
7581 * Adjust LCB error kill enable to kill the link if
7582 * these RBUF errors are seen:
7583 * REPLAY_BUF_MBE_SMASK
7584 * FLIT_INPUT_BUF_MBE_SMASK
7585 */
7588 reg |= DC_LCB_CFG_LINK_KILL_EN_REPLAY_BUF_MBE_SMASK
7591 }
7593 /* pull LCB fifos out of reset - all fifo clocks must be stable */
7596 /* give 8051 access to the LCB CSRs */
7600 /* tell the 8051 to go to LinkUp */
7602 }
7604 /**
7605 * apply_link_downgrade_policy - Apply the link width downgrade enabled
7606 * policy against the current active link widths.
7607 * @ppd: info of physical Hfi port
7608 * @refresh_widths: True indicates link downgrade event
7609 * @return: True indicates a successful link downgrade. False indicates
7610 * link downgrade event failed and the link will bounce back to
7611 * default link width.
7612 *
7613 * Called when the enabled policy changes or the active link widths
7614 * change.
7615 * Refresh_widths indicates that a link downgrade occurred. The
7616 * link_downgraded variable is set by refresh_widths and
7617 * determines the success/failure of the policy application.
7618 */
7621 {
7624 u16 lwde;
7628 /* use the hls lock to avoid a race with actual link up */
7630 retry:
7632 /* only apply if the link is up */
7634 /* still going up..wait and retry */
7640 }
7643 __func__);
7644 }
7646 }
7654 }
7658 /* the 8051 reported a dead link as a downgrade */
7662 /* downgrade is disabled */
7664 /* bounce if not at starting active width */
7678 }
7681 /* Tx or Rx is outside the enabled policy */
7690 }
7692 done:
7697 OPA_LINKDOWN_REASON_WIDTH_POLICY);
7700 }
7703 }
7705 /*
7706 * Handle a link downgrade interrupt from the 8051.
7707 *
7708 * This is a work-queue function outside of the interrupt.
7709 */
7711 {
7713 link_downgrade_work);
7718 }
7721 {
7724 }
7727 {
7730 }
7733 {
7736 }
7739 {
7742 }
7745 {
7748 }
7751 {
7757 /* look at the flags */
7759 /* 8051 information set by firmware */
7760 /* read DC8051_DBG_ERR_INFO_SET_BY_8051 for details */
7765 DC_DC8051_DBG_ERR_INFO_SET_BY_8051_HOST_MSG_SHIFT)
7768 /*
7769 * Handle error flags.
7770 */
7772 /*
7773 * LNI error indications are cleared by the 8051
7774 * only when starting polling. Only pay attention
7775 * to them when in the states that occur during
7776 * LNI.
7777 */
7784 err &
7785 FAILED_LNI));
7786 }
7788 }
7789 /* unknown frames can happen durning LNI, just count */
7793 }
7795 /* report remaining errors, but do not do anything */
7798 err));
7799 }
7801 /*
7802 * Handle host message flags.
7803 */
7805 /*
7806 * Presently, the driver does a busy wait for
7807 * host requests to complete. This is only an
7808 * informational message.
7809 * NOTE: The 8051 clears the host message
7810 * information *on the next 8051 command*.
7811 * Therefore, when linkup is achieved,
7812 * this flag will still be set.
7813 */
7815 }
7819 }
7824 }
7828 }
7832 }
7835 /* no downgrade action needed if going down */
7839 }
7843 }
7847 }
7849 /* report remaining messages, but do not do anything */
7853 host_msg));
7854 }
7857 }
7859 /*
7860 * Lost the 8051 heartbeat. If this happens, we
7861 * receive constant interrupts about it. Disable
7862 * the interrupt after the first.
7863 */
7870 }
7872 /* report the error, but do not do anything */
7875 }
7878 /*
7879 * if the link is already going down or disabled, do not
7880 * queue another. If there's a link down entry already
7881 * queued, don't queue another one.
7882 */
7893 __func__);
7894 else
7896 }
7897 }
7898 }
7915 /* no 7 */
7918 };
7928 "BadSLID: Illegal SLID (0, using multicast as SLID, does not include security validation of SLID)",
7941 };
7943 #define OPA_LDR_FMCONFIG_OFFSET 16
7944 #define OPA_LDR_PORTRCV_OFFSET 0
7946 {
7958 /* set status bit */
7960 }
7962 }
7966 /* this counter saturates at (2^32) - 1 */
7970 }
7978 /* set status bit */
7980 }
7994 OPA_PI_MASK_FM_CFG_UNSUPPORTED_VL_MARKER) {
7996 /*
7997 * lcl_reason cannot be derived from info
7998 * for this error
7999 */
8000 lcl_reason =
8001 OPA_LINKDOWN_REASON_UNSUPPORTED_VL_MARKER;
8002 }
8009 }
8015 }
8017 /* just report this */
8019 extra);
8021 }
8030 OPA_EI_STATUS_SMASK)) {
8033 /* set status bit */
8035 OPA_EI_STATUS_SMASK;
8036 /*
8037 * save first 2 flits in the packet that caused
8038 * the error
8039 */
8042 }
8061 }
8067 }
8069 /* just report this */
8075 }
8078 /* informative only */
8081 }
8083 /* informative only */
8086 }
8091 /* report any remaining errors */
8101 __func__);
8104 }
8105 }
8108 {
8113 }
8115 /*
8116 * CCE block DC interrupt. Source is < 8.
8117 */
8119 {
8125 /*
8126 * This indicates that a parity error has occurred on the
8127 * address/control lines presented to the LBM. The error
8128 * is a single pulse, there is no associated error flag,
8129 * and it is non-maskable. This is because if a parity
8130 * error occurs on the request the request is dropped.
8131 * This should never occur, but it is nice to know if it
8132 * ever does.
8133 */
8137 }
8138 }
8140 /*
8141 * TX block send credit interrupt. Source is < 160.
8142 */
8144 {
8146 }
8148 /*
8149 * TX block SDMA interrupt. Source is < 48.
8150 *
8151 * SDMA interrupts are grouped by type:
8152 *
8153 * 0 - N-1 = SDma
8154 * N - 2N-1 = SDmaProgress
8155 * 2N - 3N-1 = SDmaIdle
8156 */
8158 {
8159 /* what interrupt */
8161 /* which engine */
8164 #ifdef CONFIG_SDMA_VERBOSITY
8168 #endif
8173 /* should not happen */
8175 }
8176 }
8178 /**
8179 * is_rcv_avail_int() - User receive context available IRQ handler
8180 * @dd: valid dd
8181 * @source: logical IRQ source (offset from IS_RCVAVAIL_START)
8182 *
8183 * RX block receive available interrupt. Source is < 160.
8184 *
8185 * This is the general interrupt handler for user (PSM) receive contexts,
8186 * and can only be used for non-threaded IRQs.
8187 */
8189 {
8199 }
8200 /* received an interrupt, but no rcd */
8203 /* received an interrupt, but are not using that context */
8205 }
8208 }
8210 /**
8211 * is_rcv_urgent_int() - User receive context urgent IRQ handler
8212 * @dd: valid dd
8213 * @source: logical IRQ source (offset from IS_RCVURGENT_START)
8214 *
8215 * RX block receive urgent interrupt. Source is < 160.
8216 *
8217 * NOTE: kernel receive contexts specifically do NOT enable this IRQ.
8218 */
8220 {
8230 }
8231 /* received an interrupt, but no rcd */
8234 /* received an interrupt, but are not using that context */
8236 }
8239 }
8241 /*
8242 * Reserved range interrupt. Should not be called in normal operation.
8243 */
8245 {
8250 }
8253 /*
8254 * start end
8255 * name func interrupt func
8256 */
8277 };
8279 /*
8280 * Interrupt source interrupt - called when the given source has an interrupt.
8281 * Source is a bit index into an array of 64-bit integers.
8282 */
8284 {
8287 /* avoids a double compare by walking the table in-order */
8293 }
8294 }
8295 /* fell off the end */
8297 }
8299 /**
8300 * gerneral_interrupt() - General interrupt handler
8301 * @irq: MSIx IRQ vector
8302 * @data: hfi1 devdata
8303 *
8304 * This is able to correctly handle all non-threaded interrupts. Receive
8305 * context DATA IRQs are threaded and are not supported by this handler.
8306 *
8307 */
8309 {
8312 u32 bit;
8318 /* phase 1: scan and clear all handled interrupts */
8323 }
8326 /* only clear if anything is set */
8329 }
8331 /* phase 2: call the appropriate handler */
8336 }
8339 }
8342 {
8345 u64 status;
8347 #ifdef CONFIG_SDMA_VERBOSITY
8351 #endif
8355 /* This read_csr is really bad in the hot path */
8360 /* clear the interrupt(s) */
8363 status);
8365 /* handle the interrupt(s) */
8370 }
8372 }
8374 /*
8375 * Clear the receive interrupt. Use a read of the interrupt clear CSR
8376 * to insure that the write completed. This does NOT guarantee that
8377 * queued DMA writes to memory from the chip are pushed.
8378 */
8380 {
8385 /* force the above write on the chip and get a value back */
8387 }
8389 /* force the receive interrupt */
8391 {
8393 }
8395 /*
8396 * Return non-zero if a packet is present.
8397 *
8398 * This routine is called when rechecking for packets after the RcvAvail
8399 * interrupt has been cleared down. First, do a quick check of memory for
8400 * a packet present. If not found, use an expensive CSR read of the context
8401 * tail to determine the actual tail. The CSR read is necessary because there
8402 * is no method to push pending DMAs to memory other than an interrupt and we
8403 * are trying to determine if we need to force an interrupt.
8404 */
8406 {
8407 u32 tail;
8412 /* fall back to a CSR read, correct indpendent of DMA_RTAIL */
8415 }
8417 /**
8418 * Common code for receive contexts interrupt handlers.
8419 * Update traces, increment kernel IRQ counter and
8420 * setup ASPM when needed.
8421 */
8423 {
8429 }
8431 /**
8432 * __hfi1_rcd_eoi_intr() - Make HW issue receive interrupt
8433 * when there are packets present in the queue. When calling
8434 * with interrupts enabled please use hfi1_rcd_eoi_intr.
8435 *
8436 * @rcd: valid receive context
8437 */
8439 {
8443 }
8445 /**
8446 * hfi1_rcd_eoi_intr() - End of Interrupt processing action
8447 *
8448 * @rcd: Ptr to hfi1_ctxtdata of receive context
8449 *
8450 * Hold IRQs so we can safely clear the interrupt and
8451 * recheck for a packet that may have arrived after the previous
8452 * check and the interrupt clear. If a packet arrived, force another
8453 * interrupt. This routine can be called at the end of receive packet
8454 * processing in interrupt service routines, interrupt service thread
8455 * and softirqs
8456 */
8458 {
8464 }
8466 /*
8467 * Receive packet IRQ handler. This routine expects to be on its own IRQ.
8468 * This routine will try to handle packets immediately (latency), but if
8469 * it finds too many, it will invoke the thread handler (bandwitdh). The
8470 * chip receive interrupt is *not* cleared down until this or the thread (if
8471 * invoked) is finished. The intent is to avoid extra interrupts while we
8472 * are processing packets anyway.
8473 */
8475 {
8481 /* receive interrupt remains blocked while processing packets */
8484 /*
8485 * Too many packets were seen while processing packets in this
8486 * IRQ handler. Invoke the handler thread. The receive interrupt
8487 * remains blocked.
8488 */
8494 }
8496 /*
8497 * Receive packet thread handler. This expects to be invoked with the
8498 * receive interrupt still blocked.
8499 */
8501 {
8504 /* receive interrupt is still blocked from the IRQ handler */
8510 }
8512 /* ========================================================================= */
8515 {
8516 u64 reg;
8521 }
8524 {
8525 u64 reg;
8530 }
8533 {
8534 u64 reg;
8537 /* clear current state, set new state */
8541 }
8543 /*
8544 * Use the 8051 to read a LCB CSR.
8545 */
8547 {
8548 u32 regno;
8556 }
8558 }
8560 /* register is an index of LCB registers: (offset - base) / 8 */
8566 }
8568 /*
8569 * Provide a cache for some of the LCB registers in case the LCB is
8570 * unavailable.
8571 * (The LCB is unavailable in certain link states, for example.)
8572 */
8574 u32 off;
8575 u64 val;
8576 };
8582 };
8585 {
8588 u64 val;
8593 /* Update if we get good data */
8596 }
8597 }
8600 {
8607 }
8608 }
8612 }
8614 /*
8615 * Read an LCB CSR. Access may not be in host control, so check.
8616 * Return 0 on success, -EBUSY on failure.
8617 */
8619 {
8622 /* if up, go through the 8051 for the value */
8625 /* if going up or down, check the cache, otherwise, no access */
8630 }
8632 /* otherwise, host has access */
8635 }
8637 /*
8638 * Use the 8051 to write a LCB CSR.
8639 */
8641 {
8642 u32 regno;
8651 }
8653 }
8655 /* register is an index of LCB registers: (offset - base) / 8 */
8661 }
8663 /*
8664 * Write an LCB CSR. Access may not be in host control, so check.
8665 * Return 0 on success, -EBUSY on failure.
8666 */
8668 {
8671 /* if up, go through the 8051 for the value */
8674 /* if going up or down, no access */
8677 /* otherwise, host has access */
8680 }
8682 /*
8683 * Returns:
8684 * < 0 = Linux error, not able to get access
8685 * > 0 = 8051 command RETURN_CODE
8686 */
8689 {
8698 /* We can't send any commands to the 8051 if it's in reset */
8702 }
8704 /*
8705 * If an 8051 host command timed out previously, then the 8051 is
8706 * stuck.
8707 *
8708 * On first timeout, attempt to reset and restart the entire DC
8709 * block (including 8051). (Is this too big of a hammer?)
8710 *
8711 * If the 8051 times out a second time, the reset did not bring it
8712 * back to healthy life. In that case, fail any subsequent commands.
8713 */
8718 type);
8721 }
8724 }
8726 /*
8727 * If there is no timeout, then the 8051 command interface is
8728 * waiting for a command.
8729 */
8731 /*
8732 * When writing a LCB CSR, out_data contains the full value to
8733 * to be written, while in_data contains the relative LCB
8734 * address in 7:0. Do the work here, rather than the caller,
8735 * of distrubting the write data to where it needs to go:
8736 *
8737 * Write data
8738 * 39:00 -> in_data[47:8]
8739 * 47:40 -> DC8051_CFG_EXT_DEV_0.RETURN_CODE
8740 * 63:48 -> DC8051_CFG_EXT_DEV_0.RSP_DATA
8741 */
8744 /* must preserve COMPLETED - it is tied to hardware */
8748 DC_DC8051_CFG_EXT_DEV_0_RETURN_CODE_SHIFT)
8750 DC_DC8051_CFG_EXT_DEV_0_RSP_DATA_SHIFT);
8752 }
8754 /*
8755 * Do two writes: the first to stabilize the type and req_data, the
8756 * second to activate.
8757 */
8759 << DC_DC8051_CFG_HOST_CMD_0_REQ_TYPE_SHIFT
8766 /* wait for completion, alternate: interrupt */
8780 }
8782 }
8788 /* top 16 bits are in a different register */
8793 }
8794 }
8798 /*
8799 * Clear command for next user.
8800 */
8803 fail:
8806 }
8809 {
8811 }
8815 {
8816 u64 data;
8827 }
8829 }
8831 /*
8832 * Read the 8051 firmware "registers". Use the RAM directly. Always
8833 * set the result, even on error.
8834 * Return 0 on success, -errno on failure
8835 */
8838 {
8839 u64 big_data;
8840 u32 addr;
8843 /* address start depends on the lane_id */
8847 else
8851 /* read is in 8-byte chunks, hardware will truncate the address down */
8855 /* extract the 4 bytes we want */
8858 else
8864 }
8867 }
8870 u8 continuous)
8871 {
8872 u32 frame;
8878 }
8882 {
8883 u32 frame;
8892 }
8896 {
8897 u32 frame;
8904 }
8907 u8 misc_bits,
8908 u8 flag_bits,
8909 u16 link_widths)
8910 {
8911 u32 frame;
8917 frame);
8918 }
8921 u8 device_rev)
8922 {
8923 u32 frame;
8928 }
8932 {
8933 u32 frame;
8939 }
8942 {
8943 u32 frame;
8944 u32 mask;
8948 /* Clear, then set field */
8952 frame);
8953 }
8957 {
8958 u32 frame;
8962 STS_FM_VERSION_MAJOR_MASK;
8964 STS_FM_VERSION_MINOR_MASK;
8968 STS_FM_VERSION_PATCH_MASK;
8969 }
8973 {
8974 u32 frame;
8981 }
8985 {
8986 u32 frame;
8994 }
8999 {
9000 u32 frame;
9007 }
9010 {
9011 u32 frame;
9015 }
9018 {
9020 }
9023 {
9025 }
9028 {
9029 u32 frame;
9039 }
9040 }
9043 {
9044 u32 frame;
9048 }
9051 {
9052 u32 frame;
9056 }
9063 {
9064 u32 frame;
9076 }
9079 u8 enable_lane_tx,
9080 u8 tx_polarity_inversion,
9081 u8 rx_polarity_inversion,
9082 u8 max_rate)
9083 {
9084 u32 frame;
9086 /* no need to mask, all variable sizes match field widths */
9092 }
9094 /*
9095 * Read an idle LCB message.
9096 *
9097 * Returns 0 on success, -EINVAL on error
9098 */
9100 {
9108 }
9110 /* return only the payload as we already know the type */
9113 }
9115 /*
9116 * Read an idle SMA message. To be done in response to a notification from
9117 * the 8051.
9118 *
9119 * Returns 0 on success, -EINVAL on error
9120 */
9122 {
9124 data);
9125 }
9127 /*
9128 * Send an idle LCB message.
9129 *
9130 * Returns 0 on success, -EINVAL on error
9131 */
9133 {
9142 }
9144 }
9146 /*
9147 * Send an idle SMA message.
9148 *
9149 * Returns 0 on success, -EINVAL on error
9150 */
9152 {
9153 u64 data;
9158 }
9160 /*
9161 * Initialize the LCB then do a quick link up. This may or may not be
9162 * in loopback.
9163 *
9164 * return 0 on success, -errno on error
9165 */
9167 {
9173 /* LCB_CFG_LOOPBACK.VAL = 2 */
9174 /* LCB_CFG_LANE_WIDTH.VAL = 0 */
9178 }
9180 /* start the LCBs */
9181 /* LCB_CFG_TX_FIFOS_RESET.VAL = 0 */
9184 /* simulator only loopback steps */
9186 /* LCB_CFG_RUN.EN = 1 */
9196 }
9199 /*
9200 * When doing quick linkup and not in loopback, both
9201 * sides must be done with LCB set-up before either
9202 * starts the quick linkup. Put a delay here so that
9203 * both sides can be started and have a chance to be
9204 * done with LCB set up before resuming.
9205 */
9210 }
9215 /*
9216 * State "quick" LinkUp request sets the physical link state to
9217 * LinkUp without a verify capability sequence.
9218 * This state is in simulator v37 and later.
9219 */
9232 }
9235 }
9237 /*
9238 * Do all special steps to set up loopback.
9239 */
9241 {
9244 /* all loopbacks should disable self GUID check */
9248 /*
9249 * The simulator has only one loopback option - LCB. Switch
9250 * to that option, which includes quick link up.
9251 *
9252 * Accept all valid loopback values.
9253 */
9260 }
9262 /*
9263 * SerDes loopback init sequence is handled in set_local_link_attributes
9264 */
9268 /* LCB loopback - handled at poll time */
9272 /* not supported in emulation due to emulation RTL changes */
9277 }
9279 }
9281 /* external cable loopback requires no extra steps */
9287 }
9289 /*
9290 * Translate from the OPA_LINK_WIDTH handed to us by the FM to bits
9291 * used in the Verify Capability link width attribute.
9292 */
9294 {
9299 u16 from;
9300 u16 to;
9306 };
9311 }
9313 }
9315 /*
9316 * Set link attributes before moving to polling.
9317 */
9319 {
9321 u8 enable_lane_tx;
9322 u8 tx_polarity_inversion;
9323 u8 rx_polarity_inversion;
9326 /* reset our fabric serdes to clear any lingering problems */
9329 /* set the local tx rate - need to read-modify-write */
9336 /* set the tx rate to the fastest enabled */
9339 else
9342 /* set the tx rate to all enabled */
9348 }
9360 ret);
9362 }
9364 /*
9365 * DC supports continuous updates.
9366 */
9373 /* z=1 in the next call: AU of 0 is not supported by the hardware */
9379 /*
9380 * SerDes loopback init sequence requires
9381 * setting bit 0 of MISC_CONFIG_BITS
9382 */
9386 /*
9387 * An external device configuration request is used to reset the LCB
9388 * to retry to obtain operational lanes when the first attempt is
9389 * unsuccesful.
9390 */
9400 /* let peer know who we are */
9405 set_local_link_attributes_fail:
9408 ret);
9410 }
9412 /*
9413 * Call this to start the link.
9414 * Do not do anything if the link is disabled.
9415 * Returns 0 if link is disabled, moved to polling, or the driver is not ready.
9416 */
9418 {
9419 /*
9420 * Tune the SerDes to a ballpark setting for optimal signal and bit
9421 * error rate. Needs to be done before starting the link.
9422 */
9428 __func__);
9430 }
9432 /*
9433 * FULL_MGMT_P_KEY is cleared from the pkey table, so that the
9434 * pkey table can be configured properly if the HFI unit is connected
9435 * to switch port with MgmtAllowed=NO
9436 */
9440 }
9443 {
9445 u64 mask;
9448 /*
9449 * Some QSFP cables have a quirk that asserts the IntN line as a side
9450 * effect of power up on plug-in. We ignore this false positive
9451 * interrupt until the module has finished powering up by waiting for
9452 * a minimum timeout of the module inrush initialization time of
9453 * 500 ms (SFF 8679 Table 5-6) to ensure the voltage rails in the
9454 * module have stabilized.
9455 */
9458 /*
9459 * Check for QSFP interrupt for t_init (SFF 8679 Table 8-1)
9460 */
9469 __func__);
9471 }
9473 }
9474 }
9477 {
9479 u64 mask;
9483 /*
9484 * Clear the status register to avoid an immediate interrupt
9485 * when we re-enable the IntN pin
9486 */
9488 QSFP_HFI0_INT_N);
9492 }
9494 }
9497 {
9501 /* Disable INT_N from triggering QSFP interrupts */
9504 /* Reset the QSFP */
9521 /*
9522 * Allow INT_N to trigger the QSFP interrupt to watch
9523 * for alarms and warnings
9524 */
9527 /*
9528 * After the reset, AOC transmitters are enabled by default. They need
9529 * to be turned off to complete the QSFP setup before they can be
9530 * enabled again.
9531 */
9533 }
9537 {
9543 __func__);
9548 __func__);
9550 /*
9551 * The remaining alarms/warnings don't matter if the link is down.
9552 */
9559 __func__);
9564 __func__);
9566 /* Byte 2 is vendor specific */
9571 __func__);
9576 __func__);
9581 __func__);
9586 __func__);
9591 __func__);
9596 __func__);
9601 __func__);
9606 __func__);
9611 __func__);
9616 __func__);
9621 __func__);
9626 __func__);
9628 /* Bytes 9-10 and 11-12 are reserved */
9629 /* Bytes 13-15 are vendor specific */
9632 }
9634 /* This routine will only be scheduled if the QSFP module present is asserted */
9636 {
9645 /* Sanity check */
9652 __func__);
9654 }
9656 /*
9657 * Turn DC back on after cable has been re-inserted. Up until
9658 * now, the DC has been in reset to save power.
9659 */
9667 /*
9668 * Allow INT_N to trigger the QSFP interrupt to watch
9669 * for alarms and warnings
9670 */
9674 }
9683 __func__);
9692 flags);
9693 }
9694 }
9695 }
9698 {
9700 u64 qsfp_mask;
9703 /* Clear current status to avoid spurious interrupts */
9705 qsfp_mask);
9707 qsfp_mask);
9711 /* Handle active low nature of INT_N and MODPRST_N pins */
9716 qsfp_mask);
9718 /* Enable the appropriate QSFP IRQ source */
9721 else
9723 }
9725 /*
9726 * Do a one-time initialize of the LCB block.
9727 */
9729 {
9730 /* simulator does not correctly handle LCB cclk loopback, skip */
9734 /* the DC has been reset earlier in the driver load */
9736 /* set LCB for cclk loopback on the port */
9744 }
9746 /*
9747 * Perform a test read on the QSFP. Return 0 on success, -ERRNO
9748 * on error.
9749 */
9751 {
9753 u8 status;
9755 /*
9756 * Report success if not a QSFP or, if it is a QSFP, but the cable is
9757 * not present
9758 */
9762 /* read byte 2, the status byte */
9770 }
9772 /*
9773 * Values for QSFP retry.
9774 *
9775 * Give up after 10s (20 x 500ms). The overall timeout was empirically
9776 * arrived at from experience on a large cluster.
9777 */
9778 #define MAX_QSFP_RETRIES 20
9781 /*
9782 * Try a QSFP read. If it fails, schedule a retry for later.
9783 * Called on first link activation after driver load.
9784 */
9786 {
9788 /* read failed */
9792 }
9800 }
9804 }
9806 /*
9807 * Workqueue function to start the link after a delay.
9808 */
9810 {
9814 }
9817 {
9819 u64 guid;
9830 }
9832 /* Set linkinit_reason on power up per OPA spec */
9835 /* one-time init of the LCB */
9842 }
9849 }
9853 }
9856 {
9859 /*
9860 * Shut down the link and keep it down. First turn off that the
9861 * driver wants to allow the link to be up (driver_link_ready).
9862 * Then make sure the link is not automatically restarted
9863 * (link_enabled). Cancel any pending restart. And finally
9864 * go offline.
9865 */
9876 OPA_LINKDOWN_REASON_REBOOT);
9879 /* disable the port */
9882 }
9885 {
9900 }
9903 }
9905 /*
9906 * index is the index into the receive array
9907 */
9910 {
9911 u64 reg;
9924 }
9928 reg = RCV_ARRAY_RT_WRITE_ENABLE_SMASK
9936 /*
9937 * Eager entries are written and flushed
9938 *
9939 * Expected entries are flushed every 4 writes
9940 */
9942 done:
9944 }
9947 {
9949 u32 i;
9951 /* this could be optimized */
9959 }
9983 "HFI1_IB_CFG_PORT"
9984 };
9987 {
9991 }
9994 {
10039 unimplemented:
10042 dd,
10044 __func__,
10047 }
10050 }
10052 /*
10053 * The largest MAD packet size.
10054 */
10055 #define MAX_MAD_PACKET 2048
10057 /*
10058 * Return the maximum header bytes that can go on the _wire_
10059 * for this device. This count includes the ICRC which is
10060 * not part of the packet held in memory but it is appended
10061 * by the HW.
10062 * This is dependent on the device's receive header entry size.
10063 * HFI allows this to be set per-receive context, but the
10064 * driver presently enforces a global value.
10065 */
10067 {
10068 /*
10069 * The maximum non-payload (MTU) bytes in LRH.PktLen are
10070 * the Receive Header Entry Size minus the PBC (or RHF) size
10071 * plus one DW for the ICRC appended by HW.
10072 *
10073 * dd->rcd[0].rcvhdrqentsize is in DW.
10074 * We use rcd[0] as all context will have the same value. Also,
10075 * the first kernel context would have been allocated by now so
10076 * we are guaranteed a valid value.
10077 */
10079 }
10081 /*
10082 * Set Send Length
10083 * @ppd - per port data
10084 *
10085 * Set the MTU by limiting how many DWs may be sent. The SendLenCheck*
10086 * registers compare against LRH.PktLen, so use the max bytes included
10087 * in the LRH.
10088 *
10089 * This routine changes all VL values except VL15, which it maintains at
10090 * the same value.
10091 */
10093 {
10099 SEND_LEN_CHECK1_LEN_VL15_SHIFT;
10101 u32 thres;
10110 else
10114 }
10117 /* adjust kernel credit return thresholds based on new MTUs */
10118 /* all kernel receive contexts have the same hdrqentsize */
10127 thres);
10128 }
10135 /* Adjust maximum MTU for the port in DC */
10141 DCC_CFG_PORT_CONFIG_MTU_CAP_SHIFT;
10143 }
10146 {
10152 u32 lid;
10154 /*
10155 * Program 0 in CSR if port lid is extended. This prevents
10156 * 9B packets being sent out for large lids.
10157 */
10159 c1 &= ~(DCC_CFG_PORT_CONFIG1_TARGET_DLID_SMASK
10167 /*
10168 * Iterate over all the send contexts and set their SLID check
10169 */
10171 SEND_CTXT_CHECK_SLID_MASK_SHIFT) |
10173 SEND_CTXT_CHECK_SLID_VALUE_SHIFT);
10179 }
10181 /* Now we have to do the same thing for the sdma engines */
10183 }
10186 {
10190 "VerifyCap"
10191 };
10197 }
10215 "Unable to identify preset equalization on sufficient lanes to meet the local link width policy",
10220 "Link partner completed the EstablishComm state, but the passing lanes do not meet the local link width policy",
10227 "Link partner completed the OptimizeEq state, but the passing lanes do not meet the local link width policy",
10234 "Link partner completed the VerifyCap state, but the passing lanes do not meet the local link width policy",
10240 };
10243 u32 code)
10244 {
10253 }
10255 /* describe the given last state complete frame */
10258 {
10260 u32 success;
10261 u32 state;
10262 u32 reason;
10263 u32 lanes;
10265 /*
10266 * Decode frame:
10267 * [ 0: 0] - success
10268 * [ 3: 1] - state
10269 * [ 7: 4] - next state timeout
10270 * [15: 8] - reason code
10271 * [31:16] - lanes
10272 */
10287 }
10289 /*
10290 * Read the last state complete frames and explain them. This routine
10291 * expects to be called if the link went down during link negotiation
10292 * and initialization (LNI). That is, anywhere between polling and link up.
10293 */
10295 {
10296 u32 last_local_state;
10297 u32 last_remote_state;
10302 /*
10303 * Don't report anything if there is nothing to report. A value of
10304 * 0 means the link was taken down while polling and there was no
10305 * training in-process.
10306 */
10312 }
10314 /* wait for wait_ms for LINK_TRANSFER_ACTIVE to go to 1 */
10316 {
10317 u64 reg;
10320 /* watch LCB_STS_LINK_TRANSFER_ACTIVE */
10330 }
10332 }
10334 }
10336 /* called when the logical link state is not down as it should be */
10338 {
10341 /*
10342 * Bring link up in LCB loopback
10343 */
10346 DC_LCB_CFG_IGNORE_LOST_RCLK_EN_SMASK);
10361 /*
10362 * Bring the link down again.
10363 */
10369 }
10371 /*
10372 * Helper for set_link_state(). Do not call except from that routine.
10373 * Expects ppd->hls_mutex to be held.
10374 *
10375 * @rem_reason value to be sent to the neighbor
10376 *
10377 * LinkDownReasons only set if transition succeeds.
10378 */
10380 {
10382 u32 previous_state;
10391 /* start offline transition */
10397 ret);
10399 }
10409 /* Disabling AOC transmitters */
10420 /* not fatal, but should warn */
10423 }
10424 }
10426 /*
10427 * Wait for the offline.Quiet transition if it hasn't happened yet. It
10428 * can take a while for the link to go down.
10429 */
10434 }
10436 /*
10437 * Now in charge of LCB - must be after the physical state is
10438 * offline.quiet and before host_link_state is changed.
10439 */
10443 /* make sure the logical state is also down */
10451 /*
10452 * The LNI has a mandatory wait time after the physical state
10453 * moves to Offline.Quiet. The wait time may be different
10454 * depending on how the link went down. The 8051 firmware
10455 * will observe the needed wait time and only move to ready
10456 * when that is completed. The largest of the quiet timeouts
10457 * is 6s, so wait that long and then at least 0.5s more for
10458 * other transitions, and another 0.5s for a buffer.
10459 */
10463 "After going offline, timed out waiting for the 8051 to become ready to accept host requests\n");
10464 /* state is really offline, so make it so */
10467 }
10469 /*
10470 * The state is now offline and the 8051 is ready to accept host
10471 * requests.
10472 * - change our state
10473 * - notify others if we were previously in a linkup state
10474 */
10477 /* went down while link was up */
10481 /* went down while attempting link up */
10484 /* The QSFP doesn't need to be reset on LNI failure */
10486 }
10488 /* the active link width (downgrade) is 0 on link down */
10494 }
10496 /* return the link state name */
10498 {
10513 };
10517 }
10519 /* return the link state reason name */
10521 {
10536 }
10537 }
10539 }
10541 /*
10542 * driver_pstate - convert the driver's notion of a port's
10543 * state (an HLS_*) into a physical state (a {IB,OPA}_PORTPHYSSTATE_*).
10544 * Return -1 (converted to a u32) to indicate error.
10545 */
10547 {
10572 }
10573 }
10575 /*
10576 * driver_lstate - convert the driver's notion of a port's
10577 * state (an HLS_*) into a logical state (a IB_PORT_*). Return -1
10578 * (converted to a u32) to indicate error.
10579 */
10581 {
10596 }
10597 }
10601 {
10607 }
10608 }
10610 /**
10611 * data_vls_operational() - Verify if data VL BCT credits and MTU
10612 * are both set.
10613 * @ppd: pointer to hfi1_pportdata structure
10614 *
10615 * Return: true - Ok, false -otherwise.
10616 */
10618 {
10620 u64 reg;
10630 }
10633 }
10635 /*
10636 * Change the physical and/or logical link state.
10637 *
10638 * Do not call this routine while inside an interrupt. It contains
10639 * calls to routines that can take multiple seconds to finish.
10640 *
10641 * Returns 0 on success, -errno on failure.
10642 */
10644 {
10656 /* interpret poll -> poll as a link bounce */
10666 /*
10667 * If we're going to a (HLS_*) link state that implies the logical
10668 * link state is neither of (IB_PORT_ARMED, IB_PORT_ACTIVE), then
10669 * reset is_sm_config_started to 0.
10670 */
10674 /*
10675 * Do nothing if the states match. Let a poll to poll link bounce
10676 * go through.
10677 */
10685 /*
10686 * Quick link up jumps from polling to here.
10687 *
10688 * Whether in normal or loopback mode, the
10689 * simulator jumps from polling to link up.
10690 * Accept that here.
10691 */
10692 /* OK */
10695 }
10697 /*
10698 * Wait for Link_Up physical state.
10699 * Physical and Logical states should already be
10700 * be transitioned to LinkUp and LinkInit respectively.
10701 */
10706 __func__);
10708 }
10714 __func__);
10716 }
10718 /* clear old transient LINKINIT_REASON code */
10721 OPA_LINKINIT_REASON_LINKUP;
10723 /* enable the port */
10729 /*
10730 * After link up, a new link width will have been set.
10731 * Update the xmit counters with regards to the new
10732 * link width.
10733 */
10746 __func__);
10749 }
10756 __func__);
10758 }
10761 /*
10762 * The simulator does not currently implement SMA messages,
10763 * so neighbor_normal is not set. Set it here when we first
10764 * move to Armed.
10765 */
10778 __func__);
10780 /* tell all engines to go running */
10785 /* Signal the IB layer that the port has went active */
10789 }
10796 /* Hand LED control to the DC */
10806 }
10811 }
10821 /* quick linkup does not go into polling */
10831 ret1);
10833 }
10834 }
10836 /*
10837 * Change the host link state after requesting DC8051 to
10838 * change its physical state so that we can ignore any
10839 * interrupt with stale LNI(XX) error, which will not be
10840 * cleared until DC8051 transitions to Polling state.
10841 */
10845 /*
10846 * If an error occurred above, go back to offline. The
10847 * caller may reschedule another attempt.
10848 */
10851 else
10855 /* link is disabled */
10858 /* allow any state to transition to disabled */
10860 /* must transition to offline first */
10866 }
10873 ret1);
10876 }
10881 __func__);
10883 }
10885 }
10892 /* allow any state to transition to offline */
10911 ret1);
10914 }
10925 }
10929 unexpected:
10935 done:
10942 }
10945 {
10946 u64 reg;
10954 /*
10955 * The VL Arbitrator high limit is sent in units of 4k
10956 * bytes, while HFI stores it in units of 64 bytes.
10957 */
10964 /* HFI only supports POLL as the default link down state */
10973 }
10975 /*
10976 * For link width, link width downgrade, and speed enable, always AND
10977 * the setting with what is actually supported. This has two benefits.
10978 * First, enabled can't have unsupported values, no matter what the
10979 * SM or FM might want. Second, the ALL_SUPPORTED wildcards that mean
10980 * "fill in with your supported value" have all the bits in the
10981 * field set, so simply ANDing with supported has the desired result.
10982 */
10994 /*
10995 * HFI does not follow IB specs, save this value
10996 * so we can report it, if asked.
10997 */
11001 /*
11002 * HFI does not follow IB specs, save this value
11003 * so we can report it, if asked.
11004 */
11023 }
11025 }
11027 /* begin functions related to vl arbitration table caching */
11029 {
11033 VL_ARB_LOW_PRIO_TABLE_SIZE);
11035 VL_ARB_HIGH_PRIO_TABLE_SIZE);
11037 /*
11038 * Note that we always return values directly from the
11039 * 'vl_arb_cache' (and do no CSR reads) in response to a
11040 * 'Get(VLArbTable)'. This is obviously correct after a
11041 * 'Set(VLArbTable)', since the cache will then be up to
11042 * date. But it's also correct prior to any 'Set(VLArbTable)'
11043 * since then both the cache, and the relevant h/w registers
11044 * will be zeroed.
11045 */
11049 }
11051 /*
11052 * vl_arb_lock_cache
11053 *
11054 * All other vl_arb_* functions should be called only after locking
11055 * the cache.
11056 */
11059 {
11064 }
11067 {
11069 }
11073 {
11075 }
11079 {
11081 }
11085 {
11087 }
11089 /* end functions related to vl arbitration table caching */
11093 {
11095 u64 reg;
11107 /*
11108 * Before adjusting VL arbitration weights, empty per-VL
11109 * FIFOs, otherwise a packet whose VL weight is being
11110 * set to 0 could get stuck in a FIFO with no chance to
11111 * egress.
11112 */
11117 dd,
11119 __func__);
11121 }
11124 /*
11125 * NOTE: The low priority shift and mask are used here, but
11126 * they are the same for both the low and high registers.
11127 */
11134 }
11140 err:
11144 }
11146 /*
11147 * Read one credit merge VL register.
11148 */
11151 {
11160 }
11162 /*
11163 * Read the current credit merge limits.
11164 */
11167 {
11168 u64 reg;
11171 /* not all entries are filled in */
11174 /* OPA and HFI have a 1-1 mapping */
11178 /* NOTE: assumes that VL* and VL15 CSRs are bit-wise identical */
11190 }
11193 {
11194 u64 reg;
11197 /* each register contains 16 SC->VLnt mappings, 4 bits each */
11204 }
11212 }
11214 }
11218 {
11224 }
11225 }
11228 {
11265 }
11268 u16 limit)
11269 {
11273 }
11275 /* change only the shared limit portion of SendCmGLobalCredit */
11277 {
11278 u64 reg;
11284 }
11286 /* change only the total credit limit portion of SendCmGLobalCredit */
11288 {
11289 u64 reg;
11295 }
11297 /* set the given per-VL shared limit */
11299 {
11300 u64 reg;
11301 u32 addr;
11305 else
11312 }
11314 /* set the given per-VL dedicated limit */
11316 {
11317 u64 reg;
11318 u32 addr;
11322 else
11329 }
11331 /* spin until the given per-VL status mask bits clear */
11334 {
11336 u64 reg;
11347 }
11352 /*
11353 * If this occurs, it is likely there was a credit loss on the link.
11354 * The only recovery from that is a link bounce.
11355 */
11358 }
11360 /*
11361 * The number of credits on the VLs may be changed while everything
11362 * is "live", but the following algorithm must be followed due to
11363 * how the hardware is actually implemented. In particular,
11364 * Return_Credit_Status[] is the only correct status check.
11365 *
11366 * if (reducing Global_Shared_Credit_Limit or any shared limit changing)
11367 * set Global_Shared_Credit_Limit = 0
11368 * use_all_vl = 1
11369 * mask0 = all VLs that are changing either dedicated or shared limits
11370 * set Shared_Limit[mask0] = 0
11371 * spin until Return_Credit_Status[use_all_vl ? all VL : mask0] == 0
11372 * if (changing any dedicated limit)
11373 * mask1 = all VLs that are lowering dedicated limits
11374 * lower Dedicated_Limit[mask1]
11375 * spin until Return_Credit_Status[mask1] == 0
11376 * raise Dedicated_Limits
11377 * raise Shared_Limits
11378 * raise Global_Shared_Credit_Limit
11379 *
11380 * lower = if the new limit is lower, set the limit to the new value
11381 * raise = if the new limit is higher than the current value (may be changed
11382 * earlier in the algorithm), set the new limit to the new value
11383 */
11386 {
11393 /*
11394 * A0: add the variable any_shared_limit_changing below and in the
11395 * algorithm above. If removing A0 support, it can be removed.
11396 */
11401 u16 cur_total;
11404 SEND_CM_CREDIT_USED_STATUS_VL0_RETURN_CREDIT_STATUS_SMASK
11405 | SEND_CM_CREDIT_USED_STATUS_VL1_RETURN_CREDIT_STATUS_SMASK
11406 | SEND_CM_CREDIT_USED_STATUS_VL2_RETURN_CREDIT_STATUS_SMASK
11407 | SEND_CM_CREDIT_USED_STATUS_VL3_RETURN_CREDIT_STATUS_SMASK
11408 | SEND_CM_CREDIT_USED_STATUS_VL4_RETURN_CREDIT_STATUS_SMASK
11409 | SEND_CM_CREDIT_USED_STATUS_VL5_RETURN_CREDIT_STATUS_SMASK
11410 | SEND_CM_CREDIT_USED_STATUS_VL6_RETURN_CREDIT_STATUS_SMASK
11411 | SEND_CM_CREDIT_USED_STATUS_VL7_RETURN_CREDIT_STATUS_SMASK
11414 #define valid_vl(idx) ((idx) < TXE_NUM_DATA_VL || (idx) == 15)
11417 /* find the new total credits, do sanity check on unused VLs */
11422 }
11429 }
11432 /* fetch the current values */
11435 /*
11436 * Create the masks we will use.
11437 */
11440 /*
11441 * NOTE: Assumes that the individual VL bits are adjacent and in
11442 * increasing order
11443 */
11444 stat_mask =
11445 SEND_CM_CREDIT_USED_STATUS_VL0_RETURN_CREDIT_STATUS_SMASK;
11458 this_shared_changing) {
11461 change_count++;
11462 }
11467 }
11468 }
11470 /* bracket the credit change with a total adjustment */
11474 /*
11475 * Start the credit change algorithm.
11476 */
11484 }
11493 }
11494 }
11510 }
11511 }
11515 /* now raise all dedicated that are going up */
11525 }
11526 }
11528 /* next raise all shared that are going up */
11536 }
11538 /* finally raise the global shared */
11544 /* bracket the credit change with a total adjustment */
11548 /*
11549 * Determine the actual number of operational VLS using the number of
11550 * dedicated and shared credits for each VL.
11551 */
11556 vl_count++;
11561 NULL);
11568 }
11570 }
11572 /*
11573 * Read the given fabric manager table. Return the size of the
11574 * table (in bytes) on success, and a negative error code on
11575 * failure.
11576 */
11579 {
11586 /*
11587 * OPA specifies 128 elements (of 2 bytes each), though
11588 * HFI supports only 16 elements in h/w.
11589 */
11596 /*
11597 * OPA specifies 128 elements (of 2 bytes each), though
11598 * HFI supports only 16 elements in h/w.
11599 */
11612 /* OPA specifies 128 elements, of 2 bytes each */
11617 /*
11618 * OPA specifies that this is the same size as the VL
11619 * arbitration tables (i.e., 256 bytes).
11620 */
11624 }
11626 }
11628 /*
11629 * Write the given fabric manager table.
11630 */
11632 {
11642 }
11653 }
11667 }
11669 }
11671 /*
11672 * Disable all data VLs.
11673 *
11674 * Return 0 if disabled, non-zero if the VLs cannot be disabled.
11675 */
11677 {
11684 }
11686 /*
11687 * open_fill_data_vls() - the counterpart to stop_drain_data_vls().
11688 * Just re-enables all data VLs (the "fill" part happens
11689 * automatically - the name was chosen for symmetry with
11690 * stop_drain_data_vls()).
11691 *
11692 * Return 0 if successful, non-zero if the VLs cannot be enabled.
11693 */
11695 {
11702 }
11704 /*
11705 * drain_data_vls() - assumes that disable_data_vls() has been called,
11706 * wait for occupancy (of per-VL FIFOs) for all contexts, and SDMA
11707 * engines to drop to 0.
11708 */
11710 {
11714 }
11716 /*
11717 * stop_drain_data_vls() - disable, then drain all per-VL fifos.
11718 *
11719 * Use open_fill_data_vls() to resume using data VLs. This pair is
11720 * meant to be used like this:
11721 *
11722 * stop_drain_data_vls(dd);
11723 * // do things with per-VL resources
11724 * open_fill_data_vls(dd);
11725 */
11727 {
11735 }
11737 /*
11738 * Convert a nanosecond time to a cclock count. No matter how slow
11739 * the cclock, a non-zero ns will always have a non-zero result.
11740 */
11742 {
11743 u32 cclocks;
11752 }
11754 /*
11755 * Convert a cclock count to nanoseconds. Not matter how slow
11756 * the cclock, a non-zero cclocks will always have a non-zero result.
11757 */
11759 {
11760 u32 ns;
11769 }
11771 /*
11772 * Dynamically adjust the receive interrupt timeout for a context based on
11773 * incoming packet rate.
11774 *
11775 * NOTE: Dynamic adjustment does not allow rcv_intr_count to be zero.
11776 */
11778 {
11782 /*
11783 * This algorithm doubles or halves the timeout depending on whether
11784 * the number of packets received in this interrupt were less than or
11785 * greater equal the interrupt count.
11786 *
11787 * The calculations below do not allow a steady state to be achieved.
11788 * Only at the endpoints it is possible to have an unchanging
11789 * timeout.
11790 */
11792 /*
11793 * Not enough packets arrived before the timeout, adjust
11794 * timeout downward.
11795 */
11800 /*
11801 * More than enough packets arrived before the timeout, adjust
11802 * timeout upward.
11803 */
11807 }
11810 /*
11811 * timeout cannot be larger than rcv_intr_timeout_csr which has already
11812 * been verified to be in range
11813 */
11816 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_SHIFT);
11817 }
11821 {
11823 u64 reg;
11826 /*
11827 * Need to write timeout register before updating RcvHdrHead to ensure
11828 * that a new value is used when the HW decides to restart counting.
11829 */
11836 }
11841 }
11844 {
11852 else
11856 }
11858 /*
11859 * Context Control and Receive Array encoding for buffer size:
11860 * 0x0 invalid
11861 * 0x1 4 KB
11862 * 0x2 8 KB
11863 * 0x3 16 KB
11864 * 0x4 32 KB
11865 * 0x5 64 KB
11866 * 0x6 128 KB
11867 * 0x7 256 KB
11868 * 0x8 512 KB (Receive Array only)
11869 * 0x9 1 MB (Receive Array only)
11870 * 0xa 2 MB (Receive Array only)
11871 *
11872 * 0xB-0xF - reserved (Receive Array only)
11873 *
11874 *
11875 * This routine assumes that the value has already been sanity checked.
11876 */
11878 {
11890 }
11892 }
11894 /**
11895 * encode_rcv_header_entry_size - return chip specific encoding for size
11896 * @size: size in dwords
11897 *
11898 * Convert a receive header entry size that to the encoding used in the CSR.
11899 *
11900 * Return a zero if the given size is invalid, otherwise the encoding.
11901 */
11903 {
11904 /* there are only 3 valid receive header entry sizes */
11912 }
11914 /**
11915 * hfi1_validate_rcvhdrcnt - validate hdrcnt
11916 * @dd: the device data
11917 * @thecnt: the header count
11918 */
11920 {
11924 }
11929 HFI1_MAX_HDRQ_EGRBUF_CNT);
11931 }
11937 }
11940 }
11942 /**
11943 * set_hdrq_regs - set header queue registers for context
11944 * @dd: the device data
11945 * @ctxt: the context
11946 * @entsize: the dword entry size
11947 * @hdrcnt: the number of header entries
11948 */
11950 {
11951 u64 reg;
11954 RCV_HDR_CNT_CNT_SHIFT;
11957 RCV_HDR_ENT_SIZE_ENT_SIZE_MASK) <<
11958 RCV_HDR_ENT_SIZE_ENT_SIZE_SHIFT;
11961 RCV_HDR_SIZE_HDR_SIZE_SHIFT;
11964 /*
11965 * Program dummy tail address for every receive context
11966 * before enabling any receive context
11967 */
11970 }
11974 {
11977 u16 ctxt;
11987 /* if the context already enabled, don't do the extra steps */
11990 /* reset the tail and hdr addresses, and sequence count */
11998 /* reset the cached receive header queue head value */
12001 /*
12002 * Zero the receive header queue so we don't get false
12003 * positives when checking the sequence number. The
12004 * sequence numbers could land exactly on the same spot.
12005 * E.g. a rcd restart before the receive header wrapped.
12006 */
12009 /* starting timeout */
12012 /* enable the context */
12015 /* clean the egr buffer size first */
12021 /* zero RcvHdrHead - set RcvHdrHead.Counter after enable */
12025 /* zero RcvEgrIndexHead */
12028 /* set eager count and base index */
12037 /*
12038 * Set TID (expected) count and base index.
12039 * rcd->expected_count is set to individual RcvArray entries,
12040 * not pairs, and the CSR takes a pair-count in groups of
12041 * four, so divide by 8.
12042 */
12052 }
12055 /*
12056 * When receive context is being disabled turn on tail
12057 * update with a dummy tail address and then disable
12058 * receive context.
12059 */
12063 /* Enabling RcvCtxtCtrl.TailUpd is intentional. */
12065 }
12068 }
12073 }
12078 }
12082 /* See comment on RcvCtxtCtrl.TailUpd above */
12085 }
12091 /*
12092 * In one-packet-per-eager mode, the size comes from
12093 * the RcvArray entry.
12094 */
12097 }
12118 /* work around sticky RcvCtxtStatus.BlockedRHQFull */
12132 }
12133 }
12136 /*
12137 * The interrupt timeout and count must be set after
12138 * the context is enabled to take effect.
12139 */
12140 /* set interrupt timeout */
12143 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_SHIFT);
12145 /* set RcvHdrHead.Counter, zero RcvHdrHead.Head (again) */
12148 }
12151 /*
12152 * If the context has been disabled and the Tail Update has
12153 * been cleared, set the RCV_HDR_TAIL_ADDR CSR to dummy address
12154 * so it doesn't contain an address that is invalid.
12155 */
12158 }
12161 {
12174 /* Get the start of the block of counters */
12177 /*
12178 * Now go and fill in each counter in the block.
12179 */
12184 /* Nothing */
12192 CNTR_MODE_R,
12195 CNTR,
12199 val;
12200 }
12205 j++) {
12206 val =
12213 val;
12214 }
12217 CNTR_INVALID_VL,
12221 }
12222 }
12223 }
12224 }
12226 }
12228 /*
12229 * Used by sysfs to create files for hfi stats to read
12230 */
12232 {
12250 /* Nothing */
12253 }
12259 CNTR_MODE_R,
12262 CNTR,
12266 }
12269 CNTR_INVALID_VL,
12270 CNTR_MODE_R,
12274 }
12275 }
12276 }
12278 }
12281 {
12299 }
12311 }
12312 }
12316 {
12317 u64 val;
12323 }
12329 /* If its a synthetic counter there is more work we need to do */
12332 /* No need to read already saturated */
12334 }
12337 /* 32bit counters can wrap multiple times */
12344 else
12345 upper++;
12346 }
12352 /* If we rolled we are saturated */
12355 }
12356 }
12363 }
12368 {
12369 u64 val;
12374 }
12386 data);
12387 }
12390 }
12397 }
12400 {
12411 }
12414 {
12425 }
12428 {
12440 /* We do not want to bother for disabled contexts */
12442 }
12445 }
12448 {
12460 /* We do not want to bother for disabled contexts */
12462 }
12465 }
12468 {
12469 u64 cur_tx;
12470 u64 cur_rx;
12471 u64 total_flits;
12477 update_cntr_work);
12479 /*
12480 * Rather than keep beating on the CSRs pick a minimal set that we can
12481 * check to watch for potential roll over. We can do this by looking at
12482 * the number of flits sent/recv. If the total flits exceeds 32bits then
12483 * we have to iterate all the counters and update.
12484 */
12492 CNTR,
12497 /*
12498 * May not be strictly necessary to update but it won't hurt and
12499 * simplifies the logic here.
12500 */
12513 }
12514 }
12525 }
12526 }
12536 }
12537 }
12538 }
12540 /*
12541 * We want the value in the register. The goal is to keep track
12542 * of the number of "ticks" not the counter value. In other
12543 * words if the register rolls we want to notice it and go ahead
12544 * and force an update.
12545 */
12559 }
12560 }
12563 {
12568 }
12572 {
12582 /* set up the stats timer; the add_timer is done at the end */
12585 /***********************/
12586 /* per device counters */
12587 /***********************/
12589 /* size names and determine how many we have*/
12597 }
12605 /* Add ",32" for 32-bit counters */
12608 sz++;
12610 }
12617 /* Add ",32" for 32-bit counters */
12620 sz++;
12622 }
12624 /* +1 for newline. */
12626 /* Add ",32" for 32-bit counters */
12631 }
12632 }
12634 /* allocate space for the counter values */
12636 GFP_KERNEL);
12644 /* allocate space for the counter names */
12650 /* fill in the names */
12653 /* Nothing */
12662 /* Counter is 32 bits */
12666 }
12669 }
12677 /* Counter is 32 bits */
12681 }
12684 }
12689 /* Counter is 32 bits */
12693 }
12696 }
12697 }
12699 /*********************/
12700 /* per port counters */
12701 /*********************/
12703 /*
12704 * Go through the counters for the overflows and disable the ones we
12705 * don't need. This varies based on platform so we need to do it
12706 * dynamically here.
12707 */
12712 }
12714 /* size port counter names and determine how many we have*/
12721 }
12729 /* Add ",32" for 32-bit counters */
12732 sz++;
12734 }
12736 /* +1 for newline */
12738 /* Add ",32" for 32-bit counters */
12743 }
12744 }
12746 /* allocate space for the counter names */
12752 /* fill in port cntr names */
12764 /* Counter is 32 bits */
12768 }
12771 }
12777 /* Counter is 32 bits */
12781 }
12784 }
12785 }
12787 /* allocate per port storage for counter values */
12797 }
12799 /* CPU counters need to be allocated and zeroed */
12812 bail:
12815 }
12818 {
12823 chip_lstate);
12824 /* fall through */
12833 }
12834 }
12837 {
12838 /* look at the HFI meta-states only */
12842 chip_pstate);
12843 /* fall through */
12856 }
12857 }
12859 /* return the OPA port logical state name */
12861 {
12869 };
12873 }
12875 /* return the OPA port physical state name */
12877 {
12891 };
12895 }
12897 /**
12898 * update_statusp - Update userspace status flag
12899 * @ppd: Port data structure
12900 * @state: port state information
12901 *
12902 * Actual port status is determined by the host_link_state value
12903 * in the ppd.
12904 *
12905 * host_link_state MUST be updated before updating the user space
12906 * statusp.
12907 */
12909 {
12910 /*
12911 * Set port status flags in the page mapped into userspace
12912 * memory. Do it here to ensure a reliable state - this is
12913 * the only function called by all state handling code.
12914 * Always set the flags due to the fact that the cache value
12915 * might have been changed explicitly outside of this
12916 * function.
12917 */
12923 HFI1_STATUS_IB_READY);
12931 }
12932 }
12935 }
12937 /**
12938 * wait_logical_linkstate - wait for an IB link state change to occur
12939 * @ppd: port device
12940 * @state: the state to wait for
12941 * @msecs: the number of milliseconds to wait
12942 *
12943 * Wait up to msecs milliseconds for IB link state change to occur.
12944 * For now, take the easy polling route.
12945 * Returns 0 if state reached, otherwise -ETIMEDOUT.
12946 */
12949 {
12951 u32 new_state;
12962 state);
12964 }
12966 }
12969 }
12972 {
12978 }
12980 /*
12981 * Read the physical hardware link state and check if it matches host
12982 * drivers anticipated state.
12983 */
12985 {
12994 }
12995 }
12997 /*
12998 * wait_physical_linkstate - wait for an physical link state change to occur
12999 * @ppd: port device
13000 * @state: the state to wait for
13001 * @msecs: the number of milliseconds to wait
13002 *
13003 * Wait up to msecs milliseconds for physical link state change to occur.
13004 * Returns 0 if state reached, otherwise -ETIMEDOUT.
13005 */
13008 {
13009 u32 read_state;
13020 state);
13022 }
13024 }
13028 }
13030 /*
13031 * wait_phys_link_offline_quiet_substates - wait for any offline substate
13032 * @ppd: port device
13033 * @msecs: the number of milliseconds to wait
13034 *
13035 * Wait up to msecs milliseconds for any offline physical link
13036 * state change to occur.
13037 * Returns 0 if at least one state is reached, otherwise -ETIMEDOUT.
13038 */
13041 {
13042 u32 read_state;
13055 }
13057 }
13061 }
13063 /*
13064 * wait_phys_link_out_of_offline - wait for any out of offline state
13065 * @ppd: port device
13066 * @msecs: the number of milliseconds to wait
13067 *
13068 * Wait up to msecs milliseconds for any out of offline physical link
13069 * state change to occur.
13070 * Returns 0 if at least one state is reached, otherwise -ETIMEDOUT.
13071 */
13074 {
13075 u32 read_state;
13088 }
13090 }
13094 }
13096 #define CLEAR_STATIC_RATE_CONTROL_SMASK(r) \
13097 (r &= ~SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK)
13099 #define SET_STATIC_RATE_CONTROL_SMASK(r) \
13100 (r |= SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK)
13103 {
13106 u64 reg;
13111 SEND_CTXT_CHECK_ENABLE);
13114 else
13118 }
13119 }
13122 {
13124 u64 reg;
13129 __func__);
13131 }
13134 ASIC_STS_THERM_CURR_TEMP_MASK);
13136 ASIC_STS_THERM_LO_TEMP_MASK);
13138 ASIC_STS_THERM_HI_TEMP_MASK);
13140 ASIC_STS_THERM_CRIT_TEMP_MASK);
13141 /* triggers is a 3-bit value - 1 bit per trigger. */
13145 }
13147 /* ========================================================================= */
13149 /**
13150 * read_mod_write() - Calculate the IRQ register index and set/clear the bits
13151 * @dd: valid devdata
13152 * @src: IRQ source to determine register index from
13153 * @bits: the bits to set or clear
13154 * @set: true == set the bits, false == clear the bits
13155 *
13156 */
13159 {
13160 u64 reg;
13167 else
13171 }
13173 /**
13174 * set_intr_bits() - Enable/disable a range (one or more) IRQ sources
13175 * @dd: valid devdata
13176 * @first: first IRQ source to set/clear
13177 * @last: last IRQ source (inclusive) to set/clear
13178 * @set: true == set the bits, false == clear the bits
13179 *
13180 * If first == last, set the exact source.
13181 */
13183 {
13185 u64 bit;
13186 u16 src;
13196 /* wrapped to next register? */
13200 }
13202 }
13206 }
13208 /*
13209 * Clear all interrupt sources on the chip.
13210 */
13212 {
13233 }
13235 /*
13236 * Remap the interrupt source from the general handler to the given MSI-X
13237 * interrupt.
13238 */
13240 {
13241 u64 reg;
13244 /* clear from the handled mask of the general interrupt */
13252 }
13254 /* direct the chip source to the given MSI-X interrupt */
13261 }
13264 {
13265 /*
13266 * SDMA engine interrupt sources grouped by type, rather than
13267 * engine. Per-engine interrupts are as follows:
13268 * SDMA
13269 * SDMAProgress
13270 * SDMAIdle
13271 */
13275 }
13277 /*
13278 * Set the general handler to accept all interrupts, remap all
13279 * chip interrupts back to MSI-X 0.
13280 */
13282 {
13285 /* all interrupts handled by the general handler */
13289 /* all chip interrupts map to MSI-X 0 */
13292 }
13294 /**
13295 * set_up_interrupts() - Initialize the IRQ resources and state
13296 * @dd: valid devdata
13297 *
13298 */
13300 {
13303 /* mask all interrupts */
13306 /* clear all pending interrupts */
13309 /* reset general handler mask, chip MSI-X mappings */
13312 /* ask for MSI-X interrupts */
13322 }
13324 /*
13325 * Set up context values in dd. Sets:
13326 *
13327 * num_rcv_contexts - number of contexts being used
13328 * n_krcv_queues - number of kernel contexts
13329 * first_dyn_alloc_ctxt - first dynamically allocated context
13330 * in array of contexts
13331 * freectxts - number of free user contexts
13332 * num_send_contexts - number of PIO send contexts being used
13333 * num_vnic_contexts - number of contexts reserved for VNIC
13334 */
13336 {
13344 u32 n_usr_ctxts;
13348 /*
13349 * Kernel receive contexts:
13350 * - Context 0 - control context (VL15/multicast/error)
13351 * - Context 1 - first kernel context
13352 * - Context 2 - second kernel context
13353 * ...
13354 */
13356 /*
13357 * n_krcvqs is the sum of module parameter kernel receive
13358 * contexts, krcvqs[]. It does not include the control
13359 * context, so add that.
13360 */
13362 else
13364 /*
13365 * Every kernel receive context needs an ACK send context.
13366 * one send context is allocated for each VL{0-7} and VL15
13367 */
13372 num_kernel_contexts);
13374 }
13376 /* Accommodate VNIC contexts if possible */
13380 }
13383 /*
13384 * User contexts:
13385 * - default to 1 user context per real (non-HT) CPU core if
13386 * num_user_contexts is negative
13387 */
13390 else
13392 /*
13393 * Adjust the counts given a global max.
13394 */
13399 n_usr_ctxts);
13400 /* recalculate */
13402 }
13404 /*
13405 * The RMT entries are currently allocated as shown below:
13406 * 1. QOS (0 to 128 entries);
13407 * 2. FECN (num_kernel_context - 1 + num_user_contexts +
13408 * num_vnic_contexts);
13409 * 3. VNIC (num_vnic_contexts).
13410 * It should be noted that FECN oversubscribe num_vnic_contexts
13411 * entries of RMT because both VNIC and PSM could allocate any receive
13412 * context between dd->first_dyn_alloc_text and dd->num_rcv_contexts,
13413 * and PSM FECN must reserve an RMT entry for each possible PSM receive
13414 * context.
13415 */
13423 n_usr_ctxts,
13424 user_rmt_reduced);
13425 /* recalculate */
13427 }
13431 /* the first N are kernel contexts, the rest are user/vnic contexts */
13440 rcv_contexts,
13446 /*
13447 * Receive array allocation:
13448 * All RcvArray entries are divided into groups of 8. This
13449 * is required by the hardware and will speed up writes to
13450 * consecutive entries by using write-combining of the entire
13451 * cacheline.
13452 *
13453 * The number of groups are evenly divided among all contexts.
13454 * any left over groups will be given to the first N user
13455 * contexts.
13456 */
13473 }
13474 /*
13475 * PIO send contexts
13476 */
13481 dd,
13483 send_contexts,
13490 }
13493 }
13495 /*
13496 * Set the device/port partition key table. The MAD code
13497 * will ensure that, at least, the partial management
13498 * partition key is present in the table.
13499 */
13501 {
13509 RCV_PARTITION_KEY_PARTITION_KEY_A_MASK) <<
13511 RCV_PARTITION_KEY_PARTITION_KEY_B_SHIFT);
13512 /* Each register holds 4 PKey values. */
13517 }
13518 }
13520 /* Always enable HW pkeys check when pkeys table is set */
13522 }
13524 /*
13525 * These CSRs and memories are uninitialized on reset and must be
13526 * written before reading to set the ECC/parity bits.
13527 *
13528 * NOTE: All user context CSRs that are not mmaped write-only
13529 * (e.g. the TID flows) must be initialized even if the driver never
13530 * reads them.
13531 */
13533 {
13536 /* CceIntMap */
13540 /* SendCtxtCreditReturnAddr */
13544 /* PIO Send buffers */
13545 /* SDMA Send buffers */
13546 /*
13547 * These are not normally read, and (presently) have no method
13548 * to be read, so are not pre-initialized
13549 */
13551 /* RcvHdrAddr */
13552 /* RcvHdrTailAddr */
13553 /* RcvTidFlowTable */
13559 }
13561 /* RcvArray */
13565 /* RcvQPMapTable */
13568 }
13570 /*
13571 * Use the ctrl_bits in CceCtrl to clear the status_bits in CceStatus.
13572 */
13574 u64 ctrl_bits)
13575 {
13577 u64 reg;
13579 /* is the condition present? */
13584 /* clear the condition */
13587 /* wait for the condition to clear */
13598 }
13600 }
13601 }
13603 /* set CCE CSRs to chip reset defaults */
13605 {
13608 /* CCE_REVISION read-only */
13609 /* CCE_REVISION2 read-only */
13610 /* CCE_CTRL - bits clear automatically */
13611 /* CCE_STATUS read-only, use CceCtrl to clear */
13617 /* CCE_ERR_STATUS read-only */
13620 /* CCE_ERR_FORCE leave alone */
13624 /* CCE_PCIE_CTRL leave alone */
13628 CCE_MSIX_TABLE_UPPER_RESETCSR);
13629 }
13631 /* CCE_MSIX_PBA read-only */
13634 }
13638 /* CCE_INT_STATUS read-only */
13641 /* CCE_INT_FORCE leave alone */
13642 /* CCE_INT_BLOCKED read-only */
13643 }
13646 }
13648 /* set MISC CSRs to chip reset defaults */
13650 {
13657 }
13658 /*
13659 * MISC_CFG_SHA_PRELOAD leave alone - always reads 0 and can
13660 * only be written 128-byte chunks
13661 */
13662 /* init RSA engine to clear lingering errors */
13666 /* MISC_STS_8051_DIGEST read-only */
13667 /* MISC_STS_SBM_DIGEST read-only */
13668 /* MISC_STS_PCIE_DIGEST read-only */
13669 /* MISC_STS_FAB_DIGEST read-only */
13670 /* MISC_ERR_STATUS read-only */
13673 /* MISC_ERR_FORCE leave alone */
13674 }
13676 /* set TXE CSRs to chip reset defaults */
13678 {
13681 /*
13682 * TXE Kernel CSRs
13683 */
13686 /* SEND_CONTEXTS read-only */
13687 /* SEND_DMA_ENGINES read-only */
13688 /* SEND_PIO_MEM_SIZE read-only */
13689 /* SEND_DMA_MEM_SIZE read-only */
13692 /* SEND_PIO_ERR_STATUS read-only */
13695 /* SEND_PIO_ERR_FORCE leave alone */
13696 /* SEND_DMA_ERR_STATUS read-only */
13699 /* SEND_DMA_ERR_FORCE leave alone */
13700 /* SEND_EGRESS_ERR_STATUS read-only */
13703 /* SEND_EGRESS_ERR_FORCE leave alone */
13712 /* SEND_ERR_STATUS read-only */
13715 /* SEND_ERR_FORCE read-only */
13728 /* SEND_CM_CREDIT_USED_STATUS read-only */
13737 /* SEND_CM_CREDIT_USED_VL read-only */
13738 /* SEND_CM_CREDIT_USED_VL15 read-only */
13739 /* SEND_EGRESS_CTXT_STATUS read-only */
13740 /* SEND_EGRESS_SEND_DMA_STATUS read-only */
13742 /* SEND_EGRESS_ERR_INFO read-only */
13743 /* SEND_EGRESS_ERR_SOURCE read-only */
13745 /*
13746 * TXE Per-Context CSRs
13747 */
13761 }
13763 /*
13764 * TXE Per-SDMA CSRs
13765 */
13768 /* SEND_DMA_STATUS read-only */
13772 /* SEND_DMA_HEAD read-only */
13775 /* SEND_DMA_IDLE_CNT read-only */
13778 /* SEND_DMA_DESC_FETCHED_CNT read-only */
13779 /* SEND_DMA_ENG_ERR_STATUS read-only */
13782 /* SEND_DMA_ENG_ERR_FORCE leave alone */
13790 }
13791 }
13793 /*
13794 * Expect on entry:
13795 * o Packet ingress is disabled, i.e. RcvCtrl.RcvPortEnable == 0
13796 */
13798 {
13799 u64 reg;
13802 /*
13803 * Wait for DMA to stop: RxRbufPktPending and RxPktInProgress are
13804 * clear.
13805 */
13812 /*
13813 * Give up after 1ms - maximum wait time.
13814 *
13815 * RBuf size is 136KiB. Slowest possible is PCIe Gen1 x1 at
13816 * 250MB/s bandwidth. Lower rate to 66% for overhead to get:
13817 * 136 KB / (66% * 250MB/s) = 844us
13818 */
13824 }
13826 }
13828 /* start the init - expect RcvCtrl to be 0 */
13831 /*
13832 * Read to force the write of Rcvtrl.RxRbufInit. There is a brief
13833 * period after the write before RcvStatus.RxRbufInitDone is valid.
13834 * The delay in the first run through the loop below is sufficient and
13835 * required before the first read of RcvStatus.RxRbufInintDone.
13836 */
13839 /* wait for the init to finish */
13842 /* delay is required first time through - see above */
13848 /* give up after 100us - slowest possible at 33MHz is 73us */
13852 __func__);
13854 }
13855 }
13856 }
13858 /* set RXE CSRs to chip reset defaults */
13860 {
13863 /*
13864 * RXE Kernel CSRs
13865 */
13868 /* RCV_STATUS read-only */
13869 /* RCV_CONTEXTS read-only */
13870 /* RCV_ARRAY_CNT read-only */
13871 /* RCV_BUF_SIZE read-only */
13876 /* this is a clear-down */
13878 RCV_ERR_INFO_RCV_EXCESS_BUFFER_OVERRUN_SMASK);
13879 /* RCV_ERR_STATUS read-only */
13882 /* RCV_ERR_FORCE leave alone */
13896 /*
13897 * RXE Kernel and User Per-Context CSRs
13898 */
13900 /* kernel */
13902 /* RCV_CTXT_STATUS read-only */
13914 /* user */
13915 /* RCV_HDR_TAIL read-only */
13917 /* RCV_EGR_INDEX_TAIL read-only */
13919 /* RCV_EGR_OFFSET_TAIL read-only */
13923 }
13924 }
13925 }
13927 /*
13928 * Set sc2vl tables.
13929 *
13930 * They power on to zeros, so to avoid send context errors
13931 * they need to be set:
13932 *
13933 * SC 0-7 -> VL 0-7 (respectively)
13934 * SC 15 -> VL 15
13935 * otherwise
13936 * -> VL 0
13937 */
13939 {
13941 /* init per architecture spec, constrained by hardware capability */
13943 /* HFI maps sent packets */
13969 /* DC maps received packets */
13979 /* initialize the cached sc2vl values consistently with h/w */
13983 else
13985 }
13986 }
13988 /*
13989 * Read chip sizes and then reset parts to sane, disabled, values. We cannot
13990 * depend on the chip going through a power-on reset - a driver may be loaded
13991 * and unloaded many times.
13992 *
13993 * Do not write any CSR values to the chip in this routine - there may be
13994 * a reset following the (possible) FLR in this routine.
13995 *
13996 */
13998 {
14002 /*
14003 * Put the HFI CSRs in a known state.
14004 * Combine this with a DC reset.
14005 *
14006 * Stop the device from doing anything while we do a
14007 * reset. We know there are no other active users of
14008 * the device since we are now in charge. Turn off
14009 * off all outbound and inbound traffic and make sure
14010 * the device does not generate any interrupts.
14011 */
14013 /* disable send contexts and SDMA engines */
14019 /* disable port (turn off RXE inbound traffic) and contexts */
14023 /* mask all interrupt sources */
14027 /*
14028 * DC Reset: do a full DC reset before the register clear.
14029 * A recommended length of time to hold is one CSR read,
14030 * so reread the CceDcCtrl. Then, hold the DC in reset
14031 * across the clear.
14032 */
14037 /*
14038 * A FLR will reset the SPC core and part of the PCIe.
14039 * The parts that need to be restored have already been
14040 * saved.
14041 */
14044 /* do the FLR, the DC reset will remain */
14047 /* restore command and BARs */
14051 __func__);
14053 }
14061 __func__);
14063 }
14064 }
14071 }
14072 /* clear the DC reset */
14075 /* Set the LED off */
14078 /*
14079 * Clear the QSFP reset.
14080 * An FLR enforces a 0 on all out pins. The driver does not touch
14081 * ASIC_QSFPn_OUT otherwise. This leaves RESET_N low and
14082 * anything plugged constantly in reset, if it pays attention
14083 * to RESET_N.
14084 * Prime examples of this are optical cables. Set all pins high.
14085 * I2CCLK and I2CDAT will change per direction, and INT_N and
14086 * MODPRS_N are input only and their value is ignored.
14087 */
14092 }
14095 {
14098 /* assign link credit variables */
14104 /* enough room for 8 MAD packets plus header - 17K */
14116 }
14118 }
14121 {
14122 /* user changed the KDETH_QP */
14124 /* out of range or illegal value */
14127 }
14133 SEND_BTH_QP_KDETH_QP_SHIFT);
14137 RCV_BTH_QP_KDETH_QP_SHIFT);
14138 }
14140 /**
14141 * hfi1_get_qp_map
14142 * @dd: device data
14143 * @idx: index to read
14144 */
14146 {
14151 }
14153 /**
14154 * init_qpmap_table
14155 * @dd - device data
14156 * @first_ctxt - first context
14157 * @last_ctxt - first context
14158 *
14159 * This return sets the qpn mapping table that
14160 * is indexed by qpn[8:1].
14161 *
14162 * The routine will round robin the 256 settings
14163 * from first_ctxt to last_ctxt.
14164 *
14165 * The first/last looks ahead to having specialized
14166 * receive contexts for mgmt and bypass. Normal
14167 * verbs traffic will assumed to be on a range
14168 * of receive contexts.
14169 */
14171 u32 first_ctxt,
14172 u32 last_ctxt)
14173 {
14181 ctxt++;
14188 }
14189 }
14193 }
14198 };
14201 u8 offset;
14202 u8 pkt_type;
14203 u32 field1_off;
14204 u32 field2_off;
14205 u32 index1_off;
14206 u32 index1_width;
14207 u32 index2_off;
14208 u32 index2_width;
14209 u32 mask1;
14210 u32 value1;
14211 u32 mask2;
14212 u32 value2;
14213 };
14215 /*
14216 * Return an initialized RMT map table for users to fill in. OK if it
14217 * returns NULL, indicating no table.
14218 */
14220 {
14228 }
14231 }
14233 /*
14234 * Write the final RMT map table to the chip and free the table. OK if
14235 * table is NULL.
14236 */
14239 {
14243 /* write table to chip */
14247 /* enable RSM */
14249 }
14250 }
14252 /*
14253 * Add a receive side mapping rule.
14254 */
14257 {
14274 }
14276 /*
14277 * Clear a receive side mapping rule.
14278 */
14280 {
14284 }
14286 /* return the number of RSM map table entries that will be used for QOS */
14289 {
14294 /* is QOS active at all? */
14300 /* determine bits for qpn */
14308 /* determine bits for vl */
14311 /* reject if too much is used */
14322 no_qos:
14328 }
14330 /**
14331 * init_qos - init RX qos
14332 * @dd - device data
14333 * @rmt - RSM map table
14334 *
14335 * This routine initializes Rule 0 and the RSM map table to implement
14336 * quality of service (qos).
14337 *
14338 * If all of the limit tests succeed, qos is applied based on the array
14339 * interpretation of krcvqs where entry 0 is VL0.
14340 *
14341 * The number of vl bits (n) and the number of qpn bits (m) are computed to
14342 * feed both the RSM map table and the single rule.
14343 */
14345 {
14349 u64 reg;
14358 /* enough room in the map table? */
14363 /* add qos entries to the the RSM map table */
14371 /* generate the index the hardware will produce */
14375 /* replace default with context number */
14377 reg &= ~(RCV_RSM_MAP_TABLE_RCV_CONTEXT_A_MASK
14383 }
14385 }
14400 /* add rule 0 */
14403 /* mark RSM map entries as used */
14405 /* map everything else to the mcast/err/vl15 context */
14409 bail:
14412 }
14416 {
14418 u64 reg;
14420 u8 offset;
14421 u32 total_cnt;
14424 /* Exclude context 0 */
14426 else
14431 /* there needs to be enough room in the map table */
14435 }
14437 /*
14438 * RSM will extract the destination context as an index into the
14439 * map table. The destination contexts are a sequential block
14440 * in the range start...num_rcv_contexts-1 (inclusive).
14441 * Map entries are accessed as offset + extracted value. Adjust
14442 * the added offset so this sequence can be placed anywhere in
14443 * the table - as long as the entries themselves do not wrap.
14444 * There are only enough bits in offset for the table size, so
14445 * start with that to allow for a "negative" offset.
14446 */
14451 /* replace with identity mapping */
14458 }
14460 /*
14461 * For RSM intercept of Expected FECN packets:
14462 * o packet type 0 - expected
14463 * o match on F (bit 95), using select/match 1, and
14464 * o match on SH (bit 133), using select/match 2.
14465 *
14466 * Use index 1 to extract the 8-bit receive context from DestQP
14467 * (start at bit 64). Use that as the RSM map table index.
14468 */
14482 /* add rule 1 */
14486 }
14488 /* Initialize RSM for VNIC */
14490 {
14493 u64 reg;
14494 u32 regoff;
14501 }
14507 /* Update RSM mapping table, 32 regs, 256 entries - 1 ctx per byte */
14511 /* Update map register with vnic context */
14515 /* Wrap up vnic ctx index */
14517 /* Write back map register */
14527 }
14528 }
14530 /* Add rule for vnic */
14533 /* Match 16B packets */
14537 /* Match ETH L4 packets */
14541 /* Calc context from veswid and entropy */
14548 /* Enable RSM if not already enabled */
14550 }
14553 {
14556 /* Disable RSM if used only by vnic */
14559 }
14562 {
14564 u64 val;
14566 /* enable all receive errors */
14573 /* set up QOS, including the QPN map table */
14577 /* record number of used rsm map entries for vnic */
14581 /*
14582 * make sure RcvCtrl.RcvWcb <= PCIe Device Control
14583 * Register Max_Payload_Size (PCI_EXP_DEVCTL in Linux PCIe config
14584 * space, PciCfgCap2.MaxPayloadSize in HFI). There is only one
14585 * invalid configuration: RcvCtrl.RcvWcb set to its max of 256 and
14586 * Max_PayLoad_Size set to its minimum of 128.
14587 *
14588 * Presently, RcvCtrl.RcvWcb is not modified from its default of 0
14589 * (64 bytes). Max_Payload_Size is possibly modified upward in
14590 * tune_pcie_caps() which is called after this routine.
14591 */
14593 /* Have 16 bytes (4DW) of bypass header available in header queue */
14597 RCV_BYPASS_HDR_SIZE_SHIFT);
14600 }
14603 {
14604 /* enable all CCE errors */
14606 /* enable *some* Misc errors */
14608 /* enable all DC errors, except LCB */
14611 }
14613 /*
14614 * Fill out the given AU table using the given CU. A CU is defined in terms
14615 * AUs. The table is a an encoding: given the index, how many AUs does that
14616 * represent?
14617 *
14618 * NOTE: Assumes that the register layout is the same for the
14619 * local and remote tables.
14620 */
14623 {
14628 SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE2_SHIFT |
14630 SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE3_SHIFT);
14633 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE4_SHIFT |
14635 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE5_SHIFT |
14637 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE6_SHIFT |
14639 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE7_SHIFT);
14640 }
14643 {
14645 SEND_CM_LOCAL_AU_TABLE4_TO7);
14646 }
14649 {
14651 SEND_CM_REMOTE_AU_TABLE4_TO7);
14652 }
14655 {
14658 /* enable all PIO, SDMA, general, and Egress errors */
14664 /* enable all per-context and per-SDMA engine errors */
14670 /* set the local CU to AU mapping */
14673 /*
14674 * Set reasonable default for Credit Return Timer
14675 * Don't set on Simulator - causes it to choke.
14676 */
14679 }
14682 u16 jkey)
14683 {
14684 u8 hw_ctxt;
14685 u64 reg;
14693 SEND_CTXT_CHECK_JOB_KEY_VALUE_SHIFT);
14694 /* JOB_KEY_ALLOW_PERMISSIVE is not allowed by default */
14698 /*
14699 * Enable send-side J_KEY integrity check, unless this is A0 h/w
14700 */
14705 }
14707 /* Enable J_KEY check on receive context. */
14710 RCV_KEY_CTRL_JOB_KEY_VALUE_SHIFT);
14714 }
14717 {
14718 u8 hw_ctxt;
14719 u64 reg;
14726 /*
14727 * Disable send-side J_KEY integrity check, unless this is A0 h/w.
14728 * This check would not have been enabled for A0 h/w, see
14729 * set_ctxt_jkey().
14730 */
14735 }
14736 /* Turn off the J_KEY on the receive side */
14740 }
14743 u16 pkey)
14744 {
14745 u8 hw_ctxt;
14746 u64 reg;
14753 SEND_CTXT_CHECK_PARTITION_KEY_VALUE_SHIFT;
14761 }
14764 {
14765 u8 hw_ctxt;
14766 u64 reg;
14778 }
14780 /*
14781 * Start doing the clean up the the chip. Our clean up happens in multiple
14782 * stages and this is just the first.
14783 */
14785 {
14790 }
14792 #define HFI_BASE_GUID(dev) \
14793 ((dev)->base_guid & ~(1ULL << GUID_HFI_INDEX_SHIFT))
14795 /*
14796 * Information can be shared between the two HFIs on the same ASIC
14797 * in the same OS. This function finds the peer device and sets
14798 * up a shared structure.
14799 */
14801 {
14807 /* pre-allocate the asic structure in case we are the first device */
14813 /* Find our peer device */
14818 }
14821 /* use already allocated structure */
14827 }
14831 /* first one through - set up i2c devices */
14836 }
14838 /*
14839 * Set dd->boardname. Use a generic name if a name is not returned from
14840 * EFI variable space.
14841 *
14842 * Return 0 on success, -ENOMEM if space could not be allocated.
14843 */
14845 {
14846 /* generic board description */
14856 /* use generic description */
14860 }
14862 }
14864 /*
14865 * Check the interrupt registers to make sure that they are mapped correctly.
14866 * It is intended to help user identify any mismapping by VMM when the driver
14867 * is running in a VM. This function should only be called before interrupt
14868 * is set up properly.
14869 *
14870 * Return 0 on success, -EINVAL on failure.
14871 */
14873 {
14874 u64 reg;
14876 u64 mask;
14878 /* Clear CceIntMask[0] to avoid raising any interrupts */
14885 /* Clear all interrupt status bits */
14891 /* Set all interrupt status bits */
14897 /* Restore the interrupt mask */
14902 err_exit:
14906 }
14908 /**
14909 * hfi1_init_dd() - Initialize most of the dd structure.
14910 * @dev: the pci_dev for hfi1_ib device
14911 * @ent: pci_device_id struct for this dev
14912 *
14913 * This is global, and is called directly at init to set up the
14914 * chip-specific function pointers for later use.
14915 */
14917 {
14920 u64 reg;
14926 "Functional simulator"
14927 };
14934 /* init common fields */
14936 /* DC supports 4 link widths */
14942 /* start out enabling only 4X */
14946 /* link width active is 0 when link is down */
14947 /* link width downgrade active is 0 when link is down */
14954 }
14957 /* Set the default MTU. */
14961 /*
14962 * Set the initial values to reasonable default, will be set
14963 * for real when link is up.
14964 */
14968 /* initialize supported LTP CRC mode */
14970 /* initialize enabled LTP CRC mode */
14972 /* start in offline */
14975 }
14977 /*
14978 * Do remaining PCIe setup and save PCIe values in dd.
14979 * Any error printing is already done by the init code.
14980 * On return, we have the chip mapped.
14981 */
14986 /* Save PCI space registers to rewrite after device reset */
14996 /*
14997 * Check interrupt registers mapping if the driver has no access to
14998 * the upstream component. In this case, it is likely that the driver
14999 * is running in a VM.
15000 */
15005 }
15007 /*
15008 * obtain the hardware ID - NOT related to unit, which is a
15009 * software enumeration
15010 */
15014 /* the variable size will remove unwanted bits */
15021 /* speeds the hardware can support */
15023 /* speeds allowed to run at */
15025 /* give a reasonable active value, will be set on link up */
15028 /* fix up link widths for emulation _p */
15035 OPA_LINK_WIDTH_1X;
15036 }
15037 /* insure num_vls isn't larger than number of sdma engines */
15044 }
15046 /*
15047 * Convert the ns parameter to the 64 * cclocks used in the CSR.
15048 * Limit the max if larger than the field holds. If timeout is
15049 * non-zero, then the calculated field will be at least 1.
15050 *
15051 * Must be after icode is set up - the cclock rate depends
15052 * on knowing the hardware being used.
15053 */
15056 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_MASK)
15058 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_MASK;
15062 /* needs to be done before we look for the peer device */
15065 /* set up shared ASIC data with peer device */
15070 /* obtain chip sizes, reset chip CSRs */
15075 /* read in the PCIe link speed information */
15080 /* call before get_platform_config(), after init_chip_resources() */
15085 /* Needs to be called before hfi1_firmware_init */
15088 /* read in firmware */
15093 /*
15094 * In general, the PCIe Gen3 transition must occur after the
15095 * chip has been idled (so it won't initiate any PCIe transactions
15096 * e.g. an interrupt) and before the driver changes any registers
15097 * (the transition will reset the registers).
15098 *
15099 * In particular, place this call after:
15100 * - init_chip() - the chip will not initiate any PCIe transactions
15101 * - pcie_speeds() - reads the current link speed
15102 * - hfi1_firmware_init() - the needed firmware is ready to be
15103 * downloaded
15104 */
15109 /*
15110 * This should probably occur in hfi1_pcie_init(), but historically
15111 * occurs after the do_pcie_gen3_transition() code.
15112 */
15115 /* start setting dd values and adjusting CSRs */
15136 /* set initial RXE CSRs */
15141 /* set initial TXE CSRs */
15143 /* set initial non-RXE, non-TXE CSRs */
15145 /* set up KDETH QP prefix in both RX and TX CSRs */
15152 /* send contexts must be set up before receive contexts */
15161 /*
15162 * Initialize aspm, to be done after gen3 transition and setting up
15163 * contexts and before enabling interrupts
15164 */
15171 /* sdma init */
15176 }
15178 /* use contexts created by hfi1_create_kctxts */
15187 /* set up LCB access - must be after set_up_interrupts() */
15190 /*
15191 * Serial number is created from the base guid:
15192 * [27:24] = base guid [38:35]
15193 * [23: 0] = base guid [23: 0]
15194 */
15219 /* The user refcount starts with one to inidicate an active device */
15224 bail_free_rcverr:
15226 bail_free_cntrs:
15228 bail_clear_intr:
15231 bail_cleanup:
15233 bail_free:
15235 bail:
15237 }
15240 u32 dw_len)
15241 {
15242 u32 delta_cycles;
15244 /* rates here are in units of 10^6 bits/sec */
15256 }
15258 /**
15259 * create_pbc - build a pbc for transmission
15260 * @flags: special case flags or-ed in built pbc
15261 * @srate: static rate
15262 * @vl: vl
15263 * @dwlen: dword length (header words + data words + pbc words)
15264 *
15265 * Create a PBC with the given flags, rate, VL, and length.
15266 *
15267 * NOTE: The PBC created will not insert any HCRC - all callers but one are
15268 * for verbs, which does not use this PSM feature. The lone other caller
15269 * is for the diagnostic interface which calls this if the user does not
15270 * supply their own PBC.
15271 */
15273 u32 dw_len)
15274 {
15280 pbc = flags
15288 }
15290 #define SBUS_THERMAL 0x4f
15291 #define SBUS_THERM_MONITOR_MODE 0x1
15293 #define THERM_FAILURE(dev, ret, reason) \
15294 dd_dev_err((dd), \
15296 (reason), (ret))
15298 /*
15299 * Initialize the thermal sensor.
15300 *
15301 * After initialization, enable polling of thermal sensor through
15302 * SBus interface. In order for this to work, the SBus Master
15303 * firmware has to be loaded due to the fact that the HW polling
15304 * logic uses SBus interrupts, which are not supported with
15305 * default firmware. Otherwise, no data will be returned through
15306 * the ASIC_STS_THERM CSR.
15307 */
15309 {
15320 }
15323 /* Disable polling of thermal readings */
15326 /* Thermal Sensor Initialization */
15327 /* Step 1: Reset the Thermal SBus Receiver */
15333 }
15334 /* Step 2: Set Reset bit in Thermal block */
15340 }
15341 /* Step 3: Write clock divider value (100MHz -> 2MHz) */
15347 }
15348 /* Step 4: Select temperature mode */
15350 WRITE_SBUS_RECEIVER,
15351 SBUS_THERM_MONITOR_MODE);
15355 }
15356 /* Step 5: De-assert block reset and start conversion */
15362 }
15363 /* Step 5.1: Wait for first conversion (21.5ms per spec) */
15366 /* Enable polling of thermal readings */
15369 /* Set initialized flag */
15374 done:
15377 }
15380 {
15382 /*
15383 * Thermal Critical Interrupt
15384 * Put the device into forced freeze mode, take link down to
15385 * offline, and put DC into reset.
15386 */
15391 /*
15392 * Shut DC down as much and as quickly as possible.
15393 *
15394 * Step 1: Take the link down to OFFLINE. This will cause the
15395 * 8051 to put the Serdes in reset. However, we don't want to
15396 * go through the entire link state machine since we want to
15397 * shutdown ASAP. Furthermore, this is not a graceful shutdown
15398 * but rather an attempt to save the chip.
15399 * Code below is almost the same as quiet_serdes() but avoids
15400 * all the extra work and the sleeps.
15401 */
15405 PLS_OFFLINE);
15406 /*
15407 * Step 2: Shutdown LCB and 8051
15408 * After shutdown, do not restore DC_CFG_RESET value.
15409 */
15411 }