drivers/infiniband/sw/rxe/rxe_opcode.h

   1 /*
   2  * Copyright (c) 2016 Mellanox Technologies Ltd. All rights reserved.
   3  * Copyright (c) 2015 System Fabric Works, Inc. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33
  34 #ifndef RXE_OPCODE_H
  35 #define RXE_OPCODE_H
  36
  37 /*
  38  * contains header bit mask definitions and header lengths
  39  * declaration of the rxe_opcode_info struct and
  40  * rxe_wr_opcode_info struct
  41  */
  42
  43 enum rxe_wr_mask {
  44         WR_INLINE_MASK                  = BIT(0),
  45         WR_ATOMIC_MASK                  = BIT(1),
  46         WR_SEND_MASK                    = BIT(2),
  47         WR_READ_MASK                    = BIT(3),
  48         WR_WRITE_MASK                   = BIT(4),
  49         WR_LOCAL_MASK                   = BIT(5),
  50         WR_REG_MASK                     = BIT(6),
  51
  52         WR_READ_OR_WRITE_MASK           = WR_READ_MASK | WR_WRITE_MASK,
  53         WR_READ_WRITE_OR_SEND_MASK      = WR_READ_OR_WRITE_MASK | WR_SEND_MASK,
  54         WR_WRITE_OR_SEND_MASK           = WR_WRITE_MASK | WR_SEND_MASK,
  55         WR_ATOMIC_OR_READ_MASK          = WR_ATOMIC_MASK | WR_READ_MASK,
  56 };
  57
  58 #define WR_MAX_QPT              (8)
  59
  60 struct rxe_wr_opcode_info {
  61         char                    *name;
  62         enum rxe_wr_mask        mask[WR_MAX_QPT];
  63 };
  64
  65 extern struct rxe_wr_opcode_info rxe_wr_opcode_info[];
  66
  67 enum rxe_hdr_type {
  68         RXE_LRH,
  69         RXE_GRH,
  70         RXE_BTH,
  71         RXE_RETH,
  72         RXE_AETH,
  73         RXE_ATMETH,
  74         RXE_ATMACK,
  75         RXE_IETH,
  76         RXE_RDETH,
  77         RXE_DETH,
  78         RXE_IMMDT,
  79         RXE_PAYLOAD,
  80         NUM_HDR_TYPES
  81 };
  82
  83 enum rxe_hdr_mask {
  84         RXE_LRH_MASK            = BIT(RXE_LRH),
  85         RXE_GRH_MASK            = BIT(RXE_GRH),
  86         RXE_BTH_MASK            = BIT(RXE_BTH),
  87         RXE_IMMDT_MASK          = BIT(RXE_IMMDT),
  88         RXE_RETH_MASK           = BIT(RXE_RETH),
  89         RXE_AETH_MASK           = BIT(RXE_AETH),
  90         RXE_ATMETH_MASK         = BIT(RXE_ATMETH),
  91         RXE_ATMACK_MASK         = BIT(RXE_ATMACK),
  92         RXE_IETH_MASK           = BIT(RXE_IETH),
  93         RXE_RDETH_MASK          = BIT(RXE_RDETH),
  94         RXE_DETH_MASK           = BIT(RXE_DETH),
  95         RXE_PAYLOAD_MASK        = BIT(RXE_PAYLOAD),
  96
  97         RXE_REQ_MASK            = BIT(NUM_HDR_TYPES + 0),
  98         RXE_ACK_MASK            = BIT(NUM_HDR_TYPES + 1),
  99         RXE_SEND_MASK           = BIT(NUM_HDR_TYPES + 2),
 100         RXE_WRITE_MASK          = BIT(NUM_HDR_TYPES + 3),
 101         RXE_READ_MASK           = BIT(NUM_HDR_TYPES + 4),
 102         RXE_ATOMIC_MASK         = BIT(NUM_HDR_TYPES + 5),
 103
 104         RXE_RWR_MASK            = BIT(NUM_HDR_TYPES + 6),
 105         RXE_COMP_MASK           = BIT(NUM_HDR_TYPES + 7),
 106
 107         RXE_START_MASK          = BIT(NUM_HDR_TYPES + 8),
 108         RXE_MIDDLE_MASK         = BIT(NUM_HDR_TYPES + 9),
 109         RXE_END_MASK            = BIT(NUM_HDR_TYPES + 10),
 110
 111         RXE_LOOPBACK_MASK       = BIT(NUM_HDR_TYPES + 12),
 112
 113         RXE_READ_OR_ATOMIC      = (RXE_READ_MASK | RXE_ATOMIC_MASK),
 114         RXE_WRITE_OR_SEND       = (RXE_WRITE_MASK | RXE_SEND_MASK),
 115 };
 116
 117 #define OPCODE_NONE             (-1)
 118 #define RXE_NUM_OPCODE          256
 119
 120 struct rxe_opcode_info {
 121         char                    *name;
 122         enum rxe_hdr_mask       mask;
 123         int                     length;
 124         int                     offset[NUM_HDR_TYPES];
 125 };
 126
 127 extern struct rxe_opcode_info rxe_opcode[RXE_NUM_OPCODE];
 128
 129 #endif /* RXE_OPCODE_H */