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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / net / ethernet / cavium / octeon / octeon_mgmt.c
blobe9575887a4f8f13f6e111ec5c6ce4990e8db08d7
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2009-2012 Cavium, Inc
7 */
8
9 #include <linux/platform_device.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/etherdevice.h>
12 #include <linux/capability.h>
13 #include <linux/net_tstamp.h>
14 #include <linux/interrupt.h>
15 #include <linux/netdevice.h>
16 #include <linux/spinlock.h>
17 #include <linux/if_vlan.h>
18 #include <linux/of_mdio.h>
19 #include <linux/module.h>
20 #include <linux/of_net.h>
21 #include <linux/init.h>
22 #include <linux/slab.h>
23 #include <linux/phy.h>
24 #include <linux/io.h>
25
26 #include <asm/octeon/octeon.h>
27 #include <asm/octeon/cvmx-mixx-defs.h>
28 #include <asm/octeon/cvmx-agl-defs.h>
29
30 #define DRV_NAME "octeon_mgmt"
31 #define DRV_VERSION "2.0"
32 #define DRV_DESCRIPTION \
33 "Cavium Networks Octeon MII (management) port Network Driver"
34
35 #define OCTEON_MGMT_NAPI_WEIGHT 16
36
37 /* Ring sizes that are powers of two allow for more efficient modulo
38 * opertions.
39 */
40 #define OCTEON_MGMT_RX_RING_SIZE 512
41 #define OCTEON_MGMT_TX_RING_SIZE 128
42
43 /* Allow 8 bytes for vlan and FCS. */
44 #define OCTEON_MGMT_RX_HEADROOM (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN)
45
46 union mgmt_port_ring_entry {
47 u64 d64;
48 struct {
49 #define RING_ENTRY_CODE_DONE 0xf
50 #define RING_ENTRY_CODE_MORE 0x10
51 #ifdef __BIG_ENDIAN_BITFIELD
52 u64 reserved_62_63:2;
53 /* Length of the buffer/packet in bytes */
54 u64 len:14;
55 /* For TX, signals that the packet should be timestamped */
56 u64 tstamp:1;
57 /* The RX error code */
58 u64 code:7;
59 /* Physical address of the buffer */
60 u64 addr:40;
61 #else
62 u64 addr:40;
63 u64 code:7;
64 u64 tstamp:1;
65 u64 len:14;
66 u64 reserved_62_63:2;
67 #endif
68 } s;
69 };
70
71 #define MIX_ORING1 0x0
72 #define MIX_ORING2 0x8
73 #define MIX_IRING1 0x10
74 #define MIX_IRING2 0x18
75 #define MIX_CTL 0x20
76 #define MIX_IRHWM 0x28
77 #define MIX_IRCNT 0x30
78 #define MIX_ORHWM 0x38
79 #define MIX_ORCNT 0x40
80 #define MIX_ISR 0x48
81 #define MIX_INTENA 0x50
82 #define MIX_REMCNT 0x58
83 #define MIX_BIST 0x78
84
85 #define AGL_GMX_PRT_CFG 0x10
86 #define AGL_GMX_RX_FRM_CTL 0x18
87 #define AGL_GMX_RX_FRM_MAX 0x30
88 #define AGL_GMX_RX_JABBER 0x38
89 #define AGL_GMX_RX_STATS_CTL 0x50
90
91 #define AGL_GMX_RX_STATS_PKTS_DRP 0xb0
92 #define AGL_GMX_RX_STATS_OCTS_DRP 0xb8
93 #define AGL_GMX_RX_STATS_PKTS_BAD 0xc0
94
95 #define AGL_GMX_RX_ADR_CTL 0x100
96 #define AGL_GMX_RX_ADR_CAM_EN 0x108
97 #define AGL_GMX_RX_ADR_CAM0 0x180
98 #define AGL_GMX_RX_ADR_CAM1 0x188
99 #define AGL_GMX_RX_ADR_CAM2 0x190
100 #define AGL_GMX_RX_ADR_CAM3 0x198
101 #define AGL_GMX_RX_ADR_CAM4 0x1a0
102 #define AGL_GMX_RX_ADR_CAM5 0x1a8
103
104 #define AGL_GMX_TX_CLK 0x208
105 #define AGL_GMX_TX_STATS_CTL 0x268
106 #define AGL_GMX_TX_CTL 0x270
107 #define AGL_GMX_TX_STAT0 0x280
108 #define AGL_GMX_TX_STAT1 0x288
109 #define AGL_GMX_TX_STAT2 0x290
110 #define AGL_GMX_TX_STAT3 0x298
111 #define AGL_GMX_TX_STAT4 0x2a0
112 #define AGL_GMX_TX_STAT5 0x2a8
113 #define AGL_GMX_TX_STAT6 0x2b0
114 #define AGL_GMX_TX_STAT7 0x2b8
115 #define AGL_GMX_TX_STAT8 0x2c0
116 #define AGL_GMX_TX_STAT9 0x2c8
117
118 struct octeon_mgmt {
119 struct net_device *netdev;
120 u64 mix;
121 u64 agl;
122 u64 agl_prt_ctl;
123 int port;
124 int irq;
125 bool has_rx_tstamp;
126 u64 *tx_ring;
127 dma_addr_t tx_ring_handle;
128 unsigned int tx_next;
129 unsigned int tx_next_clean;
130 unsigned int tx_current_fill;
131 /* The tx_list lock also protects the ring related variables */
132 struct sk_buff_head tx_list;
133
134 /* RX variables only touched in napi_poll. No locking necessary. */
135 u64 *rx_ring;
136 dma_addr_t rx_ring_handle;
137 unsigned int rx_next;
138 unsigned int rx_next_fill;
139 unsigned int rx_current_fill;
140 struct sk_buff_head rx_list;
141
142 spinlock_t lock;
143 unsigned int last_duplex;
144 unsigned int last_link;
145 unsigned int last_speed;
146 struct device *dev;
147 struct napi_struct napi;
148 struct tasklet_struct tx_clean_tasklet;
149 struct device_node *phy_np;
150 resource_size_t mix_phys;
151 resource_size_t mix_size;
152 resource_size_t agl_phys;
153 resource_size_t agl_size;
154 resource_size_t agl_prt_ctl_phys;
155 resource_size_t agl_prt_ctl_size;
156 };
157
158 static void octeon_mgmt_set_rx_irq(struct octeon_mgmt *p, int enable)
159 {
160 union cvmx_mixx_intena mix_intena;
161 unsigned long flags;
162
163 spin_lock_irqsave(&p->lock, flags);
164 mix_intena.u64 = cvmx_read_csr(p->mix + MIX_INTENA);
165 mix_intena.s.ithena = enable ? 1 : 0;
166 cvmx_write_csr(p->mix + MIX_INTENA, mix_intena.u64);
167 spin_unlock_irqrestore(&p->lock, flags);
168 }
169
170 static void octeon_mgmt_set_tx_irq(struct octeon_mgmt *p, int enable)
171 {
172 union cvmx_mixx_intena mix_intena;
173 unsigned long flags;
174
175 spin_lock_irqsave(&p->lock, flags);
176 mix_intena.u64 = cvmx_read_csr(p->mix + MIX_INTENA);
177 mix_intena.s.othena = enable ? 1 : 0;
178 cvmx_write_csr(p->mix + MIX_INTENA, mix_intena.u64);
179 spin_unlock_irqrestore(&p->lock, flags);
180 }
181
182 static void octeon_mgmt_enable_rx_irq(struct octeon_mgmt *p)
183 {
184 octeon_mgmt_set_rx_irq(p, 1);
185 }
186
187 static void octeon_mgmt_disable_rx_irq(struct octeon_mgmt *p)
188 {
189 octeon_mgmt_set_rx_irq(p, 0);
190 }
191
192 static void octeon_mgmt_enable_tx_irq(struct octeon_mgmt *p)
193 {
194 octeon_mgmt_set_tx_irq(p, 1);
195 }
196
197 static void octeon_mgmt_disable_tx_irq(struct octeon_mgmt *p)
198 {
199 octeon_mgmt_set_tx_irq(p, 0);
200 }
201
202 static unsigned int ring_max_fill(unsigned int ring_size)
203 {
204 return ring_size - 8;
205 }
206
207 static unsigned int ring_size_to_bytes(unsigned int ring_size)
208 {
209 return ring_size * sizeof(union mgmt_port_ring_entry);
210 }
211
212 static void octeon_mgmt_rx_fill_ring(struct net_device *netdev)
213 {
214 struct octeon_mgmt *p = netdev_priv(netdev);
215
216 while (p->rx_current_fill < ring_max_fill(OCTEON_MGMT_RX_RING_SIZE)) {
217 unsigned int size;
218 union mgmt_port_ring_entry re;
219 struct sk_buff *skb;
220
221 /* CN56XX pass 1 needs 8 bytes of padding. */
222 size = netdev->mtu + OCTEON_MGMT_RX_HEADROOM + 8 + NET_IP_ALIGN;
223
224 skb = netdev_alloc_skb(netdev, size);
225 if (!skb)
226 break;
227 skb_reserve(skb, NET_IP_ALIGN);
228 __skb_queue_tail(&p->rx_list, skb);
229
230 re.d64 = 0;
231 re.s.len = size;
232 re.s.addr = dma_map_single(p->dev, skb->data,
233 size,
234 DMA_FROM_DEVICE);
235
236 /* Put it in the ring. */
237 p->rx_ring[p->rx_next_fill] = re.d64;
238 dma_sync_single_for_device(p->dev, p->rx_ring_handle,
239 ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE),
240 DMA_BIDIRECTIONAL);
241 p->rx_next_fill =
242 (p->rx_next_fill + 1) % OCTEON_MGMT_RX_RING_SIZE;
243 p->rx_current_fill++;
244 /* Ring the bell. */
245 cvmx_write_csr(p->mix + MIX_IRING2, 1);
246 }
247 }
248
249 static void octeon_mgmt_clean_tx_buffers(struct octeon_mgmt *p)
250 {
251 union cvmx_mixx_orcnt mix_orcnt;
252 union mgmt_port_ring_entry re;
253 struct sk_buff *skb;
254 int cleaned = 0;
255 unsigned long flags;
256
257 mix_orcnt.u64 = cvmx_read_csr(p->mix + MIX_ORCNT);
258 while (mix_orcnt.s.orcnt) {
259 spin_lock_irqsave(&p->tx_list.lock, flags);
260
261 mix_orcnt.u64 = cvmx_read_csr(p->mix + MIX_ORCNT);
262
263 if (mix_orcnt.s.orcnt == 0) {
264 spin_unlock_irqrestore(&p->tx_list.lock, flags);
265 break;
266 }
267
268 dma_sync_single_for_cpu(p->dev, p->tx_ring_handle,
269 ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE),
270 DMA_BIDIRECTIONAL);
271
272 re.d64 = p->tx_ring[p->tx_next_clean];
273 p->tx_next_clean =
274 (p->tx_next_clean + 1) % OCTEON_MGMT_TX_RING_SIZE;
275 skb = __skb_dequeue(&p->tx_list);
276
277 mix_orcnt.u64 = 0;
278 mix_orcnt.s.orcnt = 1;
279
280 /* Acknowledge to hardware that we have the buffer. */
281 cvmx_write_csr(p->mix + MIX_ORCNT, mix_orcnt.u64);
282 p->tx_current_fill--;
283
284 spin_unlock_irqrestore(&p->tx_list.lock, flags);
285
286 dma_unmap_single(p->dev, re.s.addr, re.s.len,
287 DMA_TO_DEVICE);
288
289 /* Read the hardware TX timestamp if one was recorded */
290 if (unlikely(re.s.tstamp)) {
291 struct skb_shared_hwtstamps ts;
292 u64 ns;
293
294 memset(&ts, 0, sizeof(ts));
295 /* Read the timestamp */
296 ns = cvmx_read_csr(CVMX_MIXX_TSTAMP(p->port));
297 /* Remove the timestamp from the FIFO */
298 cvmx_write_csr(CVMX_MIXX_TSCTL(p->port), 0);
299 /* Tell the kernel about the timestamp */
300 ts.hwtstamp = ns_to_ktime(ns);
301 skb_tstamp_tx(skb, &ts);
302 }
303
304 dev_kfree_skb_any(skb);
305 cleaned++;
306
307 mix_orcnt.u64 = cvmx_read_csr(p->mix + MIX_ORCNT);
308 }
309
310 if (cleaned && netif_queue_stopped(p->netdev))
311 netif_wake_queue(p->netdev);
312 }
313
314 static void octeon_mgmt_clean_tx_tasklet(unsigned long arg)
315 {
316 struct octeon_mgmt *p = (struct octeon_mgmt *)arg;
317 octeon_mgmt_clean_tx_buffers(p);
318 octeon_mgmt_enable_tx_irq(p);
319 }
320
321 static void octeon_mgmt_update_rx_stats(struct net_device *netdev)
322 {
323 struct octeon_mgmt *p = netdev_priv(netdev);
324 unsigned long flags;
325 u64 drop, bad;
326
327 /* These reads also clear the count registers. */
328 drop = cvmx_read_csr(p->agl + AGL_GMX_RX_STATS_PKTS_DRP);
329 bad = cvmx_read_csr(p->agl + AGL_GMX_RX_STATS_PKTS_BAD);
330
331 if (drop || bad) {
332 /* Do an atomic update. */
333 spin_lock_irqsave(&p->lock, flags);
334 netdev->stats.rx_errors += bad;
335 netdev->stats.rx_dropped += drop;
336 spin_unlock_irqrestore(&p->lock, flags);
337 }
338 }
339
340 static void octeon_mgmt_update_tx_stats(struct net_device *netdev)
341 {
342 struct octeon_mgmt *p = netdev_priv(netdev);
343 unsigned long flags;
344
345 union cvmx_agl_gmx_txx_stat0 s0;
346 union cvmx_agl_gmx_txx_stat1 s1;
347
348 /* These reads also clear the count registers. */
349 s0.u64 = cvmx_read_csr(p->agl + AGL_GMX_TX_STAT0);
350 s1.u64 = cvmx_read_csr(p->agl + AGL_GMX_TX_STAT1);
351
352 if (s0.s.xsdef || s0.s.xscol || s1.s.scol || s1.s.mcol) {
353 /* Do an atomic update. */
354 spin_lock_irqsave(&p->lock, flags);
355 netdev->stats.tx_errors += s0.s.xsdef + s0.s.xscol;
356 netdev->stats.collisions += s1.s.scol + s1.s.mcol;
357 spin_unlock_irqrestore(&p->lock, flags);
358 }
359 }
360
361 /*
362 * Dequeue a receive skb and its corresponding ring entry. The ring
363 * entry is returned, *pskb is updated to point to the skb.
364 */
365 static u64 octeon_mgmt_dequeue_rx_buffer(struct octeon_mgmt *p,
366 struct sk_buff **pskb)
367 {
368 union mgmt_port_ring_entry re;
369
370 dma_sync_single_for_cpu(p->dev, p->rx_ring_handle,
371 ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE),
372 DMA_BIDIRECTIONAL);
373
374 re.d64 = p->rx_ring[p->rx_next];
375 p->rx_next = (p->rx_next + 1) % OCTEON_MGMT_RX_RING_SIZE;
376 p->rx_current_fill--;
377 *pskb = __skb_dequeue(&p->rx_list);
378
379 dma_unmap_single(p->dev, re.s.addr,
380 ETH_FRAME_LEN + OCTEON_MGMT_RX_HEADROOM,
381 DMA_FROM_DEVICE);
382
383 return re.d64;
384 }
385
386
387 static int octeon_mgmt_receive_one(struct octeon_mgmt *p)
388 {
389 struct net_device *netdev = p->netdev;
390 union cvmx_mixx_ircnt mix_ircnt;
391 union mgmt_port_ring_entry re;
392 struct sk_buff *skb;
393 struct sk_buff *skb2;
394 struct sk_buff *skb_new;
395 union mgmt_port_ring_entry re2;
396 int rc = 1;
397
398
399 re.d64 = octeon_mgmt_dequeue_rx_buffer(p, &skb);
400 if (likely(re.s.code == RING_ENTRY_CODE_DONE)) {
401 /* A good packet, send it up. */
402 skb_put(skb, re.s.len);
403 good:
404 /* Process the RX timestamp if it was recorded */
405 if (p->has_rx_tstamp) {
406 /* The first 8 bytes are the timestamp */
407 u64 ns = *(u64 *)skb->data;
408 struct skb_shared_hwtstamps *ts;
409 ts = skb_hwtstamps(skb);
410 ts->hwtstamp = ns_to_ktime(ns);
411 __skb_pull(skb, 8);
412 }
413 skb->protocol = eth_type_trans(skb, netdev);
414 netdev->stats.rx_packets++;
415 netdev->stats.rx_bytes += skb->len;
416 netif_receive_skb(skb);
417 rc = 0;
418 } else if (re.s.code == RING_ENTRY_CODE_MORE) {
419 /* Packet split across skbs. This can happen if we
420 * increase the MTU. Buffers that are already in the
421 * rx ring can then end up being too small. As the rx
422 * ring is refilled, buffers sized for the new MTU
423 * will be used and we should go back to the normal
424 * non-split case.
425 */
426 skb_put(skb, re.s.len);
427 do {
428 re2.d64 = octeon_mgmt_dequeue_rx_buffer(p, &skb2);
429 if (re2.s.code != RING_ENTRY_CODE_MORE
430 && re2.s.code != RING_ENTRY_CODE_DONE)
431 goto split_error;
432 skb_put(skb2, re2.s.len);
433 skb_new = skb_copy_expand(skb, 0, skb2->len,
434 GFP_ATOMIC);
435 if (!skb_new)
436 goto split_error;
437 if (skb_copy_bits(skb2, 0, skb_tail_pointer(skb_new),
438 skb2->len))
439 goto split_error;
440 skb_put(skb_new, skb2->len);
441 dev_kfree_skb_any(skb);
442 dev_kfree_skb_any(skb2);
443 skb = skb_new;
444 } while (re2.s.code == RING_ENTRY_CODE_MORE);
445 goto good;
446 } else {
447 /* Some other error, discard it. */
448 dev_kfree_skb_any(skb);
449 /* Error statistics are accumulated in
450 * octeon_mgmt_update_rx_stats.
451 */
452 }
453 goto done;
454 split_error:
455 /* Discard the whole mess. */
456 dev_kfree_skb_any(skb);
457 dev_kfree_skb_any(skb2);
458 while (re2.s.code == RING_ENTRY_CODE_MORE) {
459 re2.d64 = octeon_mgmt_dequeue_rx_buffer(p, &skb2);
460 dev_kfree_skb_any(skb2);
461 }
462 netdev->stats.rx_errors++;
463
464 done:
465 /* Tell the hardware we processed a packet. */
466 mix_ircnt.u64 = 0;
467 mix_ircnt.s.ircnt = 1;
468 cvmx_write_csr(p->mix + MIX_IRCNT, mix_ircnt.u64);
469 return rc;
470 }
471
472 static int octeon_mgmt_receive_packets(struct octeon_mgmt *p, int budget)
473 {
474 unsigned int work_done = 0;
475 union cvmx_mixx_ircnt mix_ircnt;
476 int rc;
477
478 mix_ircnt.u64 = cvmx_read_csr(p->mix + MIX_IRCNT);
479 while (work_done < budget && mix_ircnt.s.ircnt) {
480
481 rc = octeon_mgmt_receive_one(p);
482 if (!rc)
483 work_done++;
484
485 /* Check for more packets. */
486 mix_ircnt.u64 = cvmx_read_csr(p->mix + MIX_IRCNT);
487 }
488
489 octeon_mgmt_rx_fill_ring(p->netdev);
490
491 return work_done;
492 }
493
494 static int octeon_mgmt_napi_poll(struct napi_struct *napi, int budget)
495 {
496 struct octeon_mgmt *p = container_of(napi, struct octeon_mgmt, napi);
497 struct net_device *netdev = p->netdev;
498 unsigned int work_done = 0;
499
500 work_done = octeon_mgmt_receive_packets(p, budget);
501
502 if (work_done < budget) {
503 /* We stopped because no more packets were available. */
504 napi_complete_done(napi, work_done);
505 octeon_mgmt_enable_rx_irq(p);
506 }
507 octeon_mgmt_update_rx_stats(netdev);
508
509 return work_done;
510 }
511
512 /* Reset the hardware to clean state. */
513 static void octeon_mgmt_reset_hw(struct octeon_mgmt *p)
514 {
515 union cvmx_mixx_ctl mix_ctl;
516 union cvmx_mixx_bist mix_bist;
517 union cvmx_agl_gmx_bist agl_gmx_bist;
518
519 mix_ctl.u64 = 0;
520 cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64);
521 do {
522 mix_ctl.u64 = cvmx_read_csr(p->mix + MIX_CTL);
523 } while (mix_ctl.s.busy);
524 mix_ctl.s.reset = 1;
525 cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64);
526 cvmx_read_csr(p->mix + MIX_CTL);
527 octeon_io_clk_delay(64);
528
529 mix_bist.u64 = cvmx_read_csr(p->mix + MIX_BIST);
530 if (mix_bist.u64)
531 dev_warn(p->dev, "MIX failed BIST (0x%016llx)\n",
532 (unsigned long long)mix_bist.u64);
533
534 agl_gmx_bist.u64 = cvmx_read_csr(CVMX_AGL_GMX_BIST);
535 if (agl_gmx_bist.u64)
536 dev_warn(p->dev, "AGL failed BIST (0x%016llx)\n",
537 (unsigned long long)agl_gmx_bist.u64);
538 }
539
540 struct octeon_mgmt_cam_state {
541 u64 cam[6];
542 u64 cam_mask;
543 int cam_index;
544 };
545
546 static void octeon_mgmt_cam_state_add(struct octeon_mgmt_cam_state *cs,
547 unsigned char *addr)
548 {
549 int i;
550
551 for (i = 0; i < 6; i++)
552 cs->cam[i] |= (u64)addr[i] << (8 * (cs->cam_index));
553 cs->cam_mask |= (1ULL << cs->cam_index);
554 cs->cam_index++;
555 }
556
557 static void octeon_mgmt_set_rx_filtering(struct net_device *netdev)
558 {
559 struct octeon_mgmt *p = netdev_priv(netdev);
560 union cvmx_agl_gmx_rxx_adr_ctl adr_ctl;
561 union cvmx_agl_gmx_prtx_cfg agl_gmx_prtx;
562 unsigned long flags;
563 unsigned int prev_packet_enable;
564 unsigned int cam_mode = 1; /* 1 - Accept on CAM match */
565 unsigned int multicast_mode = 1; /* 1 - Reject all multicast. */
566 struct octeon_mgmt_cam_state cam_state;
567 struct netdev_hw_addr *ha;
568 int available_cam_entries;
569
570 memset(&cam_state, 0, sizeof(cam_state));
571
572 if ((netdev->flags & IFF_PROMISC) || netdev->uc.count > 7) {
573 cam_mode = 0;
574 available_cam_entries = 8;
575 } else {
576 /* One CAM entry for the primary address, leaves seven
577 * for the secondary addresses.
578 */
579 available_cam_entries = 7 - netdev->uc.count;
580 }
581
582 if (netdev->flags & IFF_MULTICAST) {
583 if (cam_mode == 0 || (netdev->flags & IFF_ALLMULTI) ||
584 netdev_mc_count(netdev) > available_cam_entries)
585 multicast_mode = 2; /* 2 - Accept all multicast. */
586 else
587 multicast_mode = 0; /* 0 - Use CAM. */
588 }
589
590 if (cam_mode == 1) {
591 /* Add primary address. */
592 octeon_mgmt_cam_state_add(&cam_state, netdev->dev_addr);
593 netdev_for_each_uc_addr(ha, netdev)
594 octeon_mgmt_cam_state_add(&cam_state, ha->addr);
595 }
596 if (multicast_mode == 0) {
597 netdev_for_each_mc_addr(ha, netdev)
598 octeon_mgmt_cam_state_add(&cam_state, ha->addr);
599 }
600
601 spin_lock_irqsave(&p->lock, flags);
602
603 /* Disable packet I/O. */
604 agl_gmx_prtx.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG);
605 prev_packet_enable = agl_gmx_prtx.s.en;
606 agl_gmx_prtx.s.en = 0;
607 cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, agl_gmx_prtx.u64);
608
609 adr_ctl.u64 = 0;
610 adr_ctl.s.cam_mode = cam_mode;
611 adr_ctl.s.mcst = multicast_mode;
612 adr_ctl.s.bcst = 1; /* Allow broadcast */
613
614 cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CTL, adr_ctl.u64);
615
616 cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM0, cam_state.cam[0]);
617 cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM1, cam_state.cam[1]);
618 cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM2, cam_state.cam[2]);
619 cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM3, cam_state.cam[3]);
620 cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM4, cam_state.cam[4]);
621 cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM5, cam_state.cam[5]);
622 cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM_EN, cam_state.cam_mask);
623
624 /* Restore packet I/O. */
625 agl_gmx_prtx.s.en = prev_packet_enable;
626 cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, agl_gmx_prtx.u64);
627
628 spin_unlock_irqrestore(&p->lock, flags);
629 }
630
631 static int octeon_mgmt_set_mac_address(struct net_device *netdev, void *addr)
632 {
633 int r = eth_mac_addr(netdev, addr);
634
635 if (r)
636 return r;
637
638 octeon_mgmt_set_rx_filtering(netdev);
639
640 return 0;
641 }
642
643 static int octeon_mgmt_change_mtu(struct net_device *netdev, int new_mtu)
644 {
645 struct octeon_mgmt *p = netdev_priv(netdev);
646 int max_packet = new_mtu + ETH_HLEN + ETH_FCS_LEN;
647
648 netdev->mtu = new_mtu;
649
650 /* HW lifts the limit if the frame is VLAN tagged
651 * (+4 bytes per each tag, up to two tags)
652 */
653 cvmx_write_csr(p->agl + AGL_GMX_RX_FRM_MAX, max_packet);
654 /* Set the hardware to truncate packets larger than the MTU. The jabber
655 * register must be set to a multiple of 8 bytes, so round up. JABBER is
656 * an unconditional limit, so we need to account for two possible VLAN
657 * tags.
658 */
659 cvmx_write_csr(p->agl + AGL_GMX_RX_JABBER,
660 (max_packet + 7 + VLAN_HLEN * 2) & 0xfff8);
661
662 return 0;
663 }
664
665 static irqreturn_t octeon_mgmt_interrupt(int cpl, void *dev_id)
666 {
667 struct net_device *netdev = dev_id;
668 struct octeon_mgmt *p = netdev_priv(netdev);
669 union cvmx_mixx_isr mixx_isr;
670
671 mixx_isr.u64 = cvmx_read_csr(p->mix + MIX_ISR);
672
673 /* Clear any pending interrupts */
674 cvmx_write_csr(p->mix + MIX_ISR, mixx_isr.u64);
675 cvmx_read_csr(p->mix + MIX_ISR);
676
677 if (mixx_isr.s.irthresh) {
678 octeon_mgmt_disable_rx_irq(p);
679 napi_schedule(&p->napi);
680 }
681 if (mixx_isr.s.orthresh) {
682 octeon_mgmt_disable_tx_irq(p);
683 tasklet_schedule(&p->tx_clean_tasklet);
684 }
685
686 return IRQ_HANDLED;
687 }
688
689 static int octeon_mgmt_ioctl_hwtstamp(struct net_device *netdev,
690 struct ifreq *rq, int cmd)
691 {
692 struct octeon_mgmt *p = netdev_priv(netdev);
693 struct hwtstamp_config config;
694 union cvmx_mio_ptp_clock_cfg ptp;
695 union cvmx_agl_gmx_rxx_frm_ctl rxx_frm_ctl;
696 bool have_hw_timestamps = false;
697
698 if (copy_from_user(&config, rq->ifr_data, sizeof(config)))
699 return -EFAULT;
700
701 if (config.flags) /* reserved for future extensions */
702 return -EINVAL;
703
704 /* Check the status of hardware for tiemstamps */
705 if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
706 /* Get the current state of the PTP clock */
707 ptp.u64 = cvmx_read_csr(CVMX_MIO_PTP_CLOCK_CFG);
708 if (!ptp.s.ext_clk_en) {
709 /* The clock has not been configured to use an
710 * external source. Program it to use the main clock
711 * reference.
712 */
713 u64 clock_comp = (NSEC_PER_SEC << 32) / octeon_get_io_clock_rate();
714 if (!ptp.s.ptp_en)
715 cvmx_write_csr(CVMX_MIO_PTP_CLOCK_COMP, clock_comp);
716 netdev_info(netdev,
717 "PTP Clock using sclk reference @ %lldHz\n",
718 (NSEC_PER_SEC << 32) / clock_comp);
719 } else {
720 /* The clock is already programmed to use a GPIO */
721 u64 clock_comp = cvmx_read_csr(CVMX_MIO_PTP_CLOCK_COMP);
722 netdev_info(netdev,
723 "PTP Clock using GPIO%d @ %lld Hz\n",
724 ptp.s.ext_clk_in, (NSEC_PER_SEC << 32) / clock_comp);
725 }
726
727 /* Enable the clock if it wasn't done already */
728 if (!ptp.s.ptp_en) {
729 ptp.s.ptp_en = 1;
730 cvmx_write_csr(CVMX_MIO_PTP_CLOCK_CFG, ptp.u64);
731 }
732 have_hw_timestamps = true;
733 }
734
735 if (!have_hw_timestamps)
736 return -EINVAL;
737
738 switch (config.tx_type) {
739 case HWTSTAMP_TX_OFF:
740 case HWTSTAMP_TX_ON:
741 break;
742 default:
743 return -ERANGE;
744 }
745
746 switch (config.rx_filter) {
747 case HWTSTAMP_FILTER_NONE:
748 p->has_rx_tstamp = false;
749 rxx_frm_ctl.u64 = cvmx_read_csr(p->agl + AGL_GMX_RX_FRM_CTL);
750 rxx_frm_ctl.s.ptp_mode = 0;
751 cvmx_write_csr(p->agl + AGL_GMX_RX_FRM_CTL, rxx_frm_ctl.u64);
752 break;
753 case HWTSTAMP_FILTER_ALL:
754 case HWTSTAMP_FILTER_SOME:
755 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
756 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
757 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
758 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
759 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
760 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
761 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
762 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
763 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
764 case HWTSTAMP_FILTER_PTP_V2_EVENT:
765 case HWTSTAMP_FILTER_PTP_V2_SYNC:
766 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
767 case HWTSTAMP_FILTER_NTP_ALL:
768 p->has_rx_tstamp = have_hw_timestamps;
769 config.rx_filter = HWTSTAMP_FILTER_ALL;
770 if (p->has_rx_tstamp) {
771 rxx_frm_ctl.u64 = cvmx_read_csr(p->agl + AGL_GMX_RX_FRM_CTL);
772 rxx_frm_ctl.s.ptp_mode = 1;
773 cvmx_write_csr(p->agl + AGL_GMX_RX_FRM_CTL, rxx_frm_ctl.u64);
774 }
775 break;
776 default:
777 return -ERANGE;
778 }
779
780 if (copy_to_user(rq->ifr_data, &config, sizeof(config)))
781 return -EFAULT;
782
783 return 0;
784 }
785
786 static int octeon_mgmt_ioctl(struct net_device *netdev,
787 struct ifreq *rq, int cmd)
788 {
789 switch (cmd) {
790 case SIOCSHWTSTAMP:
791 return octeon_mgmt_ioctl_hwtstamp(netdev, rq, cmd);
792 default:
793 return phy_do_ioctl(netdev, rq, cmd);
794 }
795 }
796
797 static void octeon_mgmt_disable_link(struct octeon_mgmt *p)
798 {
799 union cvmx_agl_gmx_prtx_cfg prtx_cfg;
800
801 /* Disable GMX before we make any changes. */
802 prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG);
803 prtx_cfg.s.en = 0;
804 prtx_cfg.s.tx_en = 0;
805 prtx_cfg.s.rx_en = 0;
806 cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64);
807
808 if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
809 int i;
810 for (i = 0; i < 10; i++) {
811 prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG);
812 if (prtx_cfg.s.tx_idle == 1 || prtx_cfg.s.rx_idle == 1)
813 break;
814 mdelay(1);
815 i++;
816 }
817 }
818 }
819
820 static void octeon_mgmt_enable_link(struct octeon_mgmt *p)
821 {
822 union cvmx_agl_gmx_prtx_cfg prtx_cfg;
823
824 /* Restore the GMX enable state only if link is set */
825 prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG);
826 prtx_cfg.s.tx_en = 1;
827 prtx_cfg.s.rx_en = 1;
828 prtx_cfg.s.en = 1;
829 cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64);
830 }
831
832 static void octeon_mgmt_update_link(struct octeon_mgmt *p)
833 {
834 struct net_device *ndev = p->netdev;
835 struct phy_device *phydev = ndev->phydev;
836 union cvmx_agl_gmx_prtx_cfg prtx_cfg;
837
838 prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG);
839
840 if (!phydev->link)
841 prtx_cfg.s.duplex = 1;
842 else
843 prtx_cfg.s.duplex = phydev->duplex;
844
845 switch (phydev->speed) {
846 case 10:
847 prtx_cfg.s.speed = 0;
848 prtx_cfg.s.slottime = 0;
849
850 if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
851 prtx_cfg.s.burst = 1;
852 prtx_cfg.s.speed_msb = 1;
853 }
854 break;
855 case 100:
856 prtx_cfg.s.speed = 0;
857 prtx_cfg.s.slottime = 0;
858
859 if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
860 prtx_cfg.s.burst = 1;
861 prtx_cfg.s.speed_msb = 0;
862 }
863 break;
864 case 1000:
865 /* 1000 MBits is only supported on 6XXX chips */
866 if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
867 prtx_cfg.s.speed = 1;
868 prtx_cfg.s.speed_msb = 0;
869 /* Only matters for half-duplex */
870 prtx_cfg.s.slottime = 1;
871 prtx_cfg.s.burst = phydev->duplex;
872 }
873 break;
874 case 0: /* No link */
875 default:
876 break;
877 }
878
879 /* Write the new GMX setting with the port still disabled. */
880 cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64);
881
882 /* Read GMX CFG again to make sure the config is completed. */
883 prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG);
884
885 if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
886 union cvmx_agl_gmx_txx_clk agl_clk;
887 union cvmx_agl_prtx_ctl prtx_ctl;
888
889 prtx_ctl.u64 = cvmx_read_csr(p->agl_prt_ctl);
890 agl_clk.u64 = cvmx_read_csr(p->agl + AGL_GMX_TX_CLK);
891 /* MII (both speeds) and RGMII 1000 speed. */
892 agl_clk.s.clk_cnt = 1;
893 if (prtx_ctl.s.mode == 0) { /* RGMII mode */
894 if (phydev->speed == 10)
895 agl_clk.s.clk_cnt = 50;
896 else if (phydev->speed == 100)
897 agl_clk.s.clk_cnt = 5;
898 }
899 cvmx_write_csr(p->agl + AGL_GMX_TX_CLK, agl_clk.u64);
900 }
901 }
902
903 static void octeon_mgmt_adjust_link(struct net_device *netdev)
904 {
905 struct octeon_mgmt *p = netdev_priv(netdev);
906 struct phy_device *phydev = netdev->phydev;
907 unsigned long flags;
908 int link_changed = 0;
909
910 if (!phydev)
911 return;
912
913 spin_lock_irqsave(&p->lock, flags);
914
915
916 if (!phydev->link && p->last_link)
917 link_changed = -1;
918
919 if (phydev->link &&
920 (p->last_duplex != phydev->duplex ||
921 p->last_link != phydev->link ||
922 p->last_speed != phydev->speed)) {
923 octeon_mgmt_disable_link(p);
924 link_changed = 1;
925 octeon_mgmt_update_link(p);
926 octeon_mgmt_enable_link(p);
927 }
928
929 p->last_link = phydev->link;
930 p->last_speed = phydev->speed;
931 p->last_duplex = phydev->duplex;
932
933 spin_unlock_irqrestore(&p->lock, flags);
934
935 if (link_changed != 0) {
936 if (link_changed > 0)
937 netdev_info(netdev, "Link is up - %d/%s\n",
938 phydev->speed, phydev->duplex == DUPLEX_FULL ? "Full" : "Half");
939 else
940 netdev_info(netdev, "Link is down\n");
941 }
942 }
943
944 static int octeon_mgmt_init_phy(struct net_device *netdev)
945 {
946 struct octeon_mgmt *p = netdev_priv(netdev);
947 struct phy_device *phydev = NULL;
948
949 if (octeon_is_simulation() || p->phy_np == NULL) {
950 /* No PHYs in the simulator. */
951 netif_carrier_on(netdev);
952 return 0;
953 }
954
955 phydev = of_phy_connect(netdev, p->phy_np,
956 octeon_mgmt_adjust_link, 0,
957 PHY_INTERFACE_MODE_MII);
958
959 if (!phydev)
960 return -ENODEV;
961
962 return 0;
963 }
964
965 static int octeon_mgmt_open(struct net_device *netdev)
966 {
967 struct octeon_mgmt *p = netdev_priv(netdev);
968 union cvmx_mixx_ctl mix_ctl;
969 union cvmx_agl_gmx_inf_mode agl_gmx_inf_mode;
970 union cvmx_mixx_oring1 oring1;
971 union cvmx_mixx_iring1 iring1;
972 union cvmx_agl_gmx_rxx_frm_ctl rxx_frm_ctl;
973 union cvmx_mixx_irhwm mix_irhwm;
974 union cvmx_mixx_orhwm mix_orhwm;
975 union cvmx_mixx_intena mix_intena;
976 struct sockaddr sa;
977
978 /* Allocate ring buffers. */
979 p->tx_ring = kzalloc(ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE),
980 GFP_KERNEL);
981 if (!p->tx_ring)
982 return -ENOMEM;
983 p->tx_ring_handle =
984 dma_map_single(p->dev, p->tx_ring,
985 ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE),
986 DMA_BIDIRECTIONAL);
987 p->tx_next = 0;
988 p->tx_next_clean = 0;
989 p->tx_current_fill = 0;
990
991
992 p->rx_ring = kzalloc(ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE),
993 GFP_KERNEL);
994 if (!p->rx_ring)
995 goto err_nomem;
996 p->rx_ring_handle =
997 dma_map_single(p->dev, p->rx_ring,
998 ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE),
999 DMA_BIDIRECTIONAL);
1000
1001 p->rx_next = 0;
1002 p->rx_next_fill = 0;
1003 p->rx_current_fill = 0;
1004
1005 octeon_mgmt_reset_hw(p);
1006
1007 mix_ctl.u64 = cvmx_read_csr(p->mix + MIX_CTL);
1008
1009 /* Bring it out of reset if needed. */
1010 if (mix_ctl.s.reset) {
1011 mix_ctl.s.reset = 0;
1012 cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64);
1013 do {
1014 mix_ctl.u64 = cvmx_read_csr(p->mix + MIX_CTL);
1015 } while (mix_ctl.s.reset);
1016 }
1017
1018 if (OCTEON_IS_MODEL(OCTEON_CN5XXX)) {
1019 agl_gmx_inf_mode.u64 = 0;
1020 agl_gmx_inf_mode.s.en = 1;
1021 cvmx_write_csr(CVMX_AGL_GMX_INF_MODE, agl_gmx_inf_mode.u64);
1022 }
1023 if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)
1024 || OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
1025 /* Force compensation values, as they are not
1026 * determined properly by HW
1027 */
1028 union cvmx_agl_gmx_drv_ctl drv_ctl;
1029
1030 drv_ctl.u64 = cvmx_read_csr(CVMX_AGL_GMX_DRV_CTL);
1031 if (p->port) {
1032 drv_ctl.s.byp_en1 = 1;
1033 drv_ctl.s.nctl1 = 6;
1034 drv_ctl.s.pctl1 = 6;
1035 } else {
1036 drv_ctl.s.byp_en = 1;
1037 drv_ctl.s.nctl = 6;
1038 drv_ctl.s.pctl = 6;
1039 }
1040 cvmx_write_csr(CVMX_AGL_GMX_DRV_CTL, drv_ctl.u64);
1041 }
1042
1043 oring1.u64 = 0;
1044 oring1.s.obase = p->tx_ring_handle >> 3;
1045 oring1.s.osize = OCTEON_MGMT_TX_RING_SIZE;
1046 cvmx_write_csr(p->mix + MIX_ORING1, oring1.u64);
1047
1048 iring1.u64 = 0;
1049 iring1.s.ibase = p->rx_ring_handle >> 3;
1050 iring1.s.isize = OCTEON_MGMT_RX_RING_SIZE;
1051 cvmx_write_csr(p->mix + MIX_IRING1, iring1.u64);
1052
1053 memcpy(sa.sa_data, netdev->dev_addr, ETH_ALEN);
1054 octeon_mgmt_set_mac_address(netdev, &sa);
1055
1056 octeon_mgmt_change_mtu(netdev, netdev->mtu);
1057
1058 /* Enable the port HW. Packets are not allowed until
1059 * cvmx_mgmt_port_enable() is called.
1060 */
1061 mix_ctl.u64 = 0;
1062 mix_ctl.s.crc_strip = 1; /* Strip the ending CRC */
1063 mix_ctl.s.en = 1; /* Enable the port */
1064 mix_ctl.s.nbtarb = 0; /* Arbitration mode */
1065 /* MII CB-request FIFO programmable high watermark */
1066 mix_ctl.s.mrq_hwm = 1;
1067 #ifdef __LITTLE_ENDIAN
1068 mix_ctl.s.lendian = 1;
1069 #endif
1070 cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64);
1071
1072 /* Read the PHY to find the mode of the interface. */
1073 if (octeon_mgmt_init_phy(netdev)) {
1074 dev_err(p->dev, "Cannot initialize PHY on MIX%d.\n", p->port);
1075 goto err_noirq;
1076 }
1077
1078 /* Set the mode of the interface, RGMII/MII. */
1079 if (OCTEON_IS_MODEL(OCTEON_CN6XXX) && netdev->phydev) {
1080 union cvmx_agl_prtx_ctl agl_prtx_ctl;
1081 int rgmii_mode =
1082 (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
1083 netdev->phydev->supported) |
1084 linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
1085 netdev->phydev->supported)) != 0;
1086
1087 agl_prtx_ctl.u64 = cvmx_read_csr(p->agl_prt_ctl);
1088 agl_prtx_ctl.s.mode = rgmii_mode ? 0 : 1;
1089 cvmx_write_csr(p->agl_prt_ctl, agl_prtx_ctl.u64);
1090
1091 /* MII clocks counts are based on the 125Mhz
1092 * reference, which has an 8nS period. So our delays
1093 * need to be multiplied by this factor.
1094 */
1095 #define NS_PER_PHY_CLK 8
1096
1097 /* Take the DLL and clock tree out of reset */
1098 agl_prtx_ctl.u64 = cvmx_read_csr(p->agl_prt_ctl);
1099 agl_prtx_ctl.s.clkrst = 0;
1100 if (rgmii_mode) {
1101 agl_prtx_ctl.s.dllrst = 0;
1102 agl_prtx_ctl.s.clktx_byp = 0;
1103 }
1104 cvmx_write_csr(p->agl_prt_ctl, agl_prtx_ctl.u64);
1105 cvmx_read_csr(p->agl_prt_ctl); /* Force write out before wait */
1106
1107 /* Wait for the DLL to lock. External 125 MHz
1108 * reference clock must be stable at this point.
1109 */
1110 ndelay(256 * NS_PER_PHY_CLK);
1111
1112 /* Enable the interface */
1113 agl_prtx_ctl.u64 = cvmx_read_csr(p->agl_prt_ctl);
1114 agl_prtx_ctl.s.enable = 1;
1115 cvmx_write_csr(p->agl_prt_ctl, agl_prtx_ctl.u64);
1116
1117 /* Read the value back to force the previous write */
1118 agl_prtx_ctl.u64 = cvmx_read_csr(p->agl_prt_ctl);
1119
1120 /* Enable the compensation controller */
1121 agl_prtx_ctl.s.comp = 1;
1122 agl_prtx_ctl.s.drv_byp = 0;
1123 cvmx_write_csr(p->agl_prt_ctl, agl_prtx_ctl.u64);
1124 /* Force write out before wait. */
1125 cvmx_read_csr(p->agl_prt_ctl);
1126
1127 /* For compensation state to lock. */
1128 ndelay(1040 * NS_PER_PHY_CLK);
1129
1130 /* Default Interframe Gaps are too small. Recommended
1131 * workaround is.
1132 *
1133 * AGL_GMX_TX_IFG[IFG1]=14
1134 * AGL_GMX_TX_IFG[IFG2]=10
1135 */
1136 cvmx_write_csr(CVMX_AGL_GMX_TX_IFG, 0xae);
1137 }
1138
1139 octeon_mgmt_rx_fill_ring(netdev);
1140
1141 /* Clear statistics. */
1142 /* Clear on read. */
1143 cvmx_write_csr(p->agl + AGL_GMX_RX_STATS_CTL, 1);
1144 cvmx_write_csr(p->agl + AGL_GMX_RX_STATS_PKTS_DRP, 0);
1145 cvmx_write_csr(p->agl + AGL_GMX_RX_STATS_PKTS_BAD, 0);
1146
1147 cvmx_write_csr(p->agl + AGL_GMX_TX_STATS_CTL, 1);
1148 cvmx_write_csr(p->agl + AGL_GMX_TX_STAT0, 0);
1149 cvmx_write_csr(p->agl + AGL_GMX_TX_STAT1, 0);
1150
1151 /* Clear any pending interrupts */
1152 cvmx_write_csr(p->mix + MIX_ISR, cvmx_read_csr(p->mix + MIX_ISR));
1153
1154 if (request_irq(p->irq, octeon_mgmt_interrupt, 0, netdev->name,
1155 netdev)) {
1156 dev_err(p->dev, "request_irq(%d) failed.\n", p->irq);
1157 goto err_noirq;
1158 }
1159
1160 /* Interrupt every single RX packet */
1161 mix_irhwm.u64 = 0;
1162 mix_irhwm.s.irhwm = 0;
1163 cvmx_write_csr(p->mix + MIX_IRHWM, mix_irhwm.u64);
1164
1165 /* Interrupt when we have 1 or more packets to clean. */
1166 mix_orhwm.u64 = 0;
1167 mix_orhwm.s.orhwm = 0;
1168 cvmx_write_csr(p->mix + MIX_ORHWM, mix_orhwm.u64);
1169
1170 /* Enable receive and transmit interrupts */
1171 mix_intena.u64 = 0;
1172 mix_intena.s.ithena = 1;
1173 mix_intena.s.othena = 1;
1174 cvmx_write_csr(p->mix + MIX_INTENA, mix_intena.u64);
1175
1176 /* Enable packet I/O. */
1177
1178 rxx_frm_ctl.u64 = 0;
1179 rxx_frm_ctl.s.ptp_mode = p->has_rx_tstamp ? 1 : 0;
1180 rxx_frm_ctl.s.pre_align = 1;
1181 /* When set, disables the length check for non-min sized pkts
1182 * with padding in the client data.
1183 */
1184 rxx_frm_ctl.s.pad_len = 1;
1185 /* When set, disables the length check for VLAN pkts */
1186 rxx_frm_ctl.s.vlan_len = 1;
1187 /* When set, PREAMBLE checking is less strict */
1188 rxx_frm_ctl.s.pre_free = 1;
1189 /* Control Pause Frames can match station SMAC */
1190 rxx_frm_ctl.s.ctl_smac = 0;
1191 /* Control Pause Frames can match globally assign Multicast address */
1192 rxx_frm_ctl.s.ctl_mcst = 1;
1193 /* Forward pause information to TX block */
1194 rxx_frm_ctl.s.ctl_bck = 1;
1195 /* Drop Control Pause Frames */
1196 rxx_frm_ctl.s.ctl_drp = 1;
1197 /* Strip off the preamble */
1198 rxx_frm_ctl.s.pre_strp = 1;
1199 /* This port is configured to send PREAMBLE+SFD to begin every
1200 * frame. GMX checks that the PREAMBLE is sent correctly.
1201 */
1202 rxx_frm_ctl.s.pre_chk = 1;
1203 cvmx_write_csr(p->agl + AGL_GMX_RX_FRM_CTL, rxx_frm_ctl.u64);
1204
1205 /* Configure the port duplex, speed and enables */
1206 octeon_mgmt_disable_link(p);
1207 if (netdev->phydev)
1208 octeon_mgmt_update_link(p);
1209 octeon_mgmt_enable_link(p);
1210
1211 p->last_link = 0;
1212 p->last_speed = 0;
1213 /* PHY is not present in simulator. The carrier is enabled
1214 * while initializing the phy for simulator, leave it enabled.
1215 */
1216 if (netdev->phydev) {
1217 netif_carrier_off(netdev);
1218 phy_start_aneg(netdev->phydev);
1219 }
1220
1221 netif_wake_queue(netdev);
1222 napi_enable(&p->napi);
1223
1224 return 0;
1225 err_noirq:
1226 octeon_mgmt_reset_hw(p);
1227 dma_unmap_single(p->dev, p->rx_ring_handle,
1228 ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE),
1229 DMA_BIDIRECTIONAL);
1230 kfree(p->rx_ring);
1231 err_nomem:
1232 dma_unmap_single(p->dev, p->tx_ring_handle,
1233 ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE),
1234 DMA_BIDIRECTIONAL);
1235 kfree(p->tx_ring);
1236 return -ENOMEM;
1237 }
1238
1239 static int octeon_mgmt_stop(struct net_device *netdev)
1240 {
1241 struct octeon_mgmt *p = netdev_priv(netdev);
1242
1243 napi_disable(&p->napi);
1244 netif_stop_queue(netdev);
1245
1246 if (netdev->phydev)
1247 phy_disconnect(netdev->phydev);
1248
1249 netif_carrier_off(netdev);
1250
1251 octeon_mgmt_reset_hw(p);
1252
1253 free_irq(p->irq, netdev);
1254
1255 /* dma_unmap is a nop on Octeon, so just free everything. */
1256 skb_queue_purge(&p->tx_list);
1257 skb_queue_purge(&p->rx_list);
1258
1259 dma_unmap_single(p->dev, p->rx_ring_handle,
1260 ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE),
1261 DMA_BIDIRECTIONAL);
1262 kfree(p->rx_ring);
1263
1264 dma_unmap_single(p->dev, p->tx_ring_handle,
1265 ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE),
1266 DMA_BIDIRECTIONAL);
1267 kfree(p->tx_ring);
1268
1269 return 0;
1270 }
1271
1272 static netdev_tx_t
1273 octeon_mgmt_xmit(struct sk_buff *skb, struct net_device *netdev)
1274 {
1275 struct octeon_mgmt *p = netdev_priv(netdev);
1276 union mgmt_port_ring_entry re;
1277 unsigned long flags;
1278 netdev_tx_t rv = NETDEV_TX_BUSY;
1279
1280 re.d64 = 0;
1281 re.s.tstamp = ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) != 0);
1282 re.s.len = skb->len;
1283 re.s.addr = dma_map_single(p->dev, skb->data,
1284 skb->len,
1285 DMA_TO_DEVICE);
1286
1287 spin_lock_irqsave(&p->tx_list.lock, flags);
1288
1289 if (unlikely(p->tx_current_fill >= ring_max_fill(OCTEON_MGMT_TX_RING_SIZE) - 1)) {
1290 spin_unlock_irqrestore(&p->tx_list.lock, flags);
1291 netif_stop_queue(netdev);
1292 spin_lock_irqsave(&p->tx_list.lock, flags);
1293 }
1294
1295 if (unlikely(p->tx_current_fill >=
1296 ring_max_fill(OCTEON_MGMT_TX_RING_SIZE))) {
1297 spin_unlock_irqrestore(&p->tx_list.lock, flags);
1298 dma_unmap_single(p->dev, re.s.addr, re.s.len,
1299 DMA_TO_DEVICE);
1300 goto out;
1301 }
1302
1303 __skb_queue_tail(&p->tx_list, skb);
1304
1305 /* Put it in the ring. */
1306 p->tx_ring[p->tx_next] = re.d64;
1307 p->tx_next = (p->tx_next + 1) % OCTEON_MGMT_TX_RING_SIZE;
1308 p->tx_current_fill++;
1309
1310 spin_unlock_irqrestore(&p->tx_list.lock, flags);
1311
1312 dma_sync_single_for_device(p->dev, p->tx_ring_handle,
1313 ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE),
1314 DMA_BIDIRECTIONAL);
1315
1316 netdev->stats.tx_packets++;
1317 netdev->stats.tx_bytes += skb->len;
1318
1319 /* Ring the bell. */
1320 cvmx_write_csr(p->mix + MIX_ORING2, 1);
1321
1322 netif_trans_update(netdev);
1323 rv = NETDEV_TX_OK;
1324 out:
1325 octeon_mgmt_update_tx_stats(netdev);
1326 return rv;
1327 }
1328
1329 #ifdef CONFIG_NET_POLL_CONTROLLER
1330 static void octeon_mgmt_poll_controller(struct net_device *netdev)
1331 {
1332 struct octeon_mgmt *p = netdev_priv(netdev);
1333
1334 octeon_mgmt_receive_packets(p, 16);
1335 octeon_mgmt_update_rx_stats(netdev);
1336 }
1337 #endif
1338
1339 static void octeon_mgmt_get_drvinfo(struct net_device *netdev,
1340 struct ethtool_drvinfo *info)
1341 {
1342 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1343 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1344 strlcpy(info->fw_version, "N/A", sizeof(info->fw_version));
1345 strlcpy(info->bus_info, "N/A", sizeof(info->bus_info));
1346 }
1347
1348 static int octeon_mgmt_nway_reset(struct net_device *dev)
1349 {
1350 if (!capable(CAP_NET_ADMIN))
1351 return -EPERM;
1352
1353 if (dev->phydev)
1354 return phy_start_aneg(dev->phydev);
1355
1356 return -EOPNOTSUPP;
1357 }
1358
1359 static const struct ethtool_ops octeon_mgmt_ethtool_ops = {
1360 .get_drvinfo = octeon_mgmt_get_drvinfo,
1361 .nway_reset = octeon_mgmt_nway_reset,
1362 .get_link = ethtool_op_get_link,
1363 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1364 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1365 };
1366
1367 static const struct net_device_ops octeon_mgmt_ops = {
1368 .ndo_open = octeon_mgmt_open,
1369 .ndo_stop = octeon_mgmt_stop,
1370 .ndo_start_xmit = octeon_mgmt_xmit,
1371 .ndo_set_rx_mode = octeon_mgmt_set_rx_filtering,
1372 .ndo_set_mac_address = octeon_mgmt_set_mac_address,
1373 .ndo_do_ioctl = octeon_mgmt_ioctl,
1374 .ndo_change_mtu = octeon_mgmt_change_mtu,
1375 #ifdef CONFIG_NET_POLL_CONTROLLER
1376 .ndo_poll_controller = octeon_mgmt_poll_controller,
1377 #endif
1378 };
1379
1380 static int octeon_mgmt_probe(struct platform_device *pdev)
1381 {
1382 struct net_device *netdev;
1383 struct octeon_mgmt *p;
1384 const __be32 *data;
1385 const u8 *mac;
1386 struct resource *res_mix;
1387 struct resource *res_agl;
1388 struct resource *res_agl_prt_ctl;
1389 int len;
1390 int result;
1391
1392 netdev = alloc_etherdev(sizeof(struct octeon_mgmt));
1393 if (netdev == NULL)
1394 return -ENOMEM;
1395
1396 SET_NETDEV_DEV(netdev, &pdev->dev);
1397
1398 platform_set_drvdata(pdev, netdev);
1399 p = netdev_priv(netdev);
1400 netif_napi_add(netdev, &p->napi, octeon_mgmt_napi_poll,
1401 OCTEON_MGMT_NAPI_WEIGHT);
1402
1403 p->netdev = netdev;
1404 p->dev = &pdev->dev;
1405 p->has_rx_tstamp = false;
1406
1407 data = of_get_property(pdev->dev.of_node, "cell-index", &len);
1408 if (data && len == sizeof(*data)) {
1409 p->port = be32_to_cpup(data);
1410 } else {
1411 dev_err(&pdev->dev, "no 'cell-index' property\n");
1412 result = -ENXIO;
1413 goto err;
1414 }
1415
1416 snprintf(netdev->name, IFNAMSIZ, "mgmt%d", p->port);
1417
1418 result = platform_get_irq(pdev, 0);
1419 if (result < 0)
1420 goto err;
1421
1422 p->irq = result;
1423
1424 res_mix = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1425 if (res_mix == NULL) {
1426 dev_err(&pdev->dev, "no 'reg' resource\n");
1427 result = -ENXIO;
1428 goto err;
1429 }
1430
1431 res_agl = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1432 if (res_agl == NULL) {
1433 dev_err(&pdev->dev, "no 'reg' resource\n");
1434 result = -ENXIO;
1435 goto err;
1436 }
1437
1438 res_agl_prt_ctl = platform_get_resource(pdev, IORESOURCE_MEM, 3);
1439 if (res_agl_prt_ctl == NULL) {
1440 dev_err(&pdev->dev, "no 'reg' resource\n");
1441 result = -ENXIO;
1442 goto err;
1443 }
1444
1445 p->mix_phys = res_mix->start;
1446 p->mix_size = resource_size(res_mix);
1447 p->agl_phys = res_agl->start;
1448 p->agl_size = resource_size(res_agl);
1449 p->agl_prt_ctl_phys = res_agl_prt_ctl->start;
1450 p->agl_prt_ctl_size = resource_size(res_agl_prt_ctl);
1451
1452
1453 if (!devm_request_mem_region(&pdev->dev, p->mix_phys, p->mix_size,
1454 res_mix->name)) {
1455 dev_err(&pdev->dev, "request_mem_region (%s) failed\n",
1456 res_mix->name);
1457 result = -ENXIO;
1458 goto err;
1459 }
1460
1461 if (!devm_request_mem_region(&pdev->dev, p->agl_phys, p->agl_size,
1462 res_agl->name)) {
1463 result = -ENXIO;
1464 dev_err(&pdev->dev, "request_mem_region (%s) failed\n",
1465 res_agl->name);
1466 goto err;
1467 }
1468
1469 if (!devm_request_mem_region(&pdev->dev, p->agl_prt_ctl_phys,
1470 p->agl_prt_ctl_size, res_agl_prt_ctl->name)) {
1471 result = -ENXIO;
1472 dev_err(&pdev->dev, "request_mem_region (%s) failed\n",
1473 res_agl_prt_ctl->name);
1474 goto err;
1475 }
1476
1477 p->mix = (u64)devm_ioremap(&pdev->dev, p->mix_phys, p->mix_size);
1478 p->agl = (u64)devm_ioremap(&pdev->dev, p->agl_phys, p->agl_size);
1479 p->agl_prt_ctl = (u64)devm_ioremap(&pdev->dev, p->agl_prt_ctl_phys,
1480 p->agl_prt_ctl_size);
1481 if (!p->mix || !p->agl || !p->agl_prt_ctl) {
1482 dev_err(&pdev->dev, "failed to map I/O memory\n");
1483 result = -ENOMEM;
1484 goto err;
1485 }
1486
1487 spin_lock_init(&p->lock);
1488
1489 skb_queue_head_init(&p->tx_list);
1490 skb_queue_head_init(&p->rx_list);
1491 tasklet_init(&p->tx_clean_tasklet,
1492 octeon_mgmt_clean_tx_tasklet, (unsigned long)p);
1493
1494 netdev->priv_flags |= IFF_UNICAST_FLT;
1495
1496 netdev->netdev_ops = &octeon_mgmt_ops;
1497 netdev->ethtool_ops = &octeon_mgmt_ethtool_ops;
1498
1499 netdev->min_mtu = 64 - OCTEON_MGMT_RX_HEADROOM;
1500 netdev->max_mtu = 16383 - OCTEON_MGMT_RX_HEADROOM - VLAN_HLEN;
1501
1502 mac = of_get_mac_address(pdev->dev.of_node);
1503
1504 if (!IS_ERR(mac))
1505 ether_addr_copy(netdev->dev_addr, mac);
1506 else
1507 eth_hw_addr_random(netdev);
1508
1509 p->phy_np = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0);
1510
1511 result = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
1512 if (result)
1513 goto err;
1514
1515 netif_carrier_off(netdev);
1516 result = register_netdev(netdev);
1517 if (result)
1518 goto err;
1519
1520 dev_info(&pdev->dev, "Version " DRV_VERSION "\n");
1521 return 0;
1522
1523 err:
1524 of_node_put(p->phy_np);
1525 free_netdev(netdev);
1526 return result;
1527 }
1528
1529 static int octeon_mgmt_remove(struct platform_device *pdev)
1530 {
1531 struct net_device *netdev = platform_get_drvdata(pdev);
1532 struct octeon_mgmt *p = netdev_priv(netdev);
1533
1534 unregister_netdev(netdev);
1535 of_node_put(p->phy_np);
1536 free_netdev(netdev);
1537 return 0;
1538 }
1539
1540 static const struct of_device_id octeon_mgmt_match[] = {
1541 {
1542 .compatible = "cavium,octeon-5750-mix",
1543 },
1544 {},
1545 };
1546 MODULE_DEVICE_TABLE(of, octeon_mgmt_match);
1547
1548 static struct platform_driver octeon_mgmt_driver = {
1549 .driver = {
1550 .name = "octeon_mgmt",
1551 .of_match_table = octeon_mgmt_match,
1552 },
1553 .probe = octeon_mgmt_probe,
1554 .remove = octeon_mgmt_remove,
1555 };
1556
1557 extern void octeon_mdiobus_force_mod_depencency(void);
1558
1559 static int __init octeon_mgmt_mod_init(void)
1560 {
1561 /* Force our mdiobus driver module to be loaded first. */
1562 octeon_mdiobus_force_mod_depencency();
1563 return platform_driver_register(&octeon_mgmt_driver);
1564 }
1565
1566 static void __exit octeon_mgmt_mod_exit(void)
1567 {
1568 platform_driver_unregister(&octeon_mgmt_driver);
1569 }
1570
1571 module_init(octeon_mgmt_mod_init);
1572 module_exit(octeon_mgmt_mod_exit);
1573
1574 MODULE_DESCRIPTION(DRV_DESCRIPTION);
1575 MODULE_AUTHOR("David Daney");
1576 MODULE_LICENSE("GPL");
1577 MODULE_VERSION(DRV_VERSION);
Linux with added FPC-III support