| blob | 844fdcf55118b232204ab87dac45b25dba5b6d18 |
1 /*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
35 #include <linux/delay.h>
42 /**
43 * t4_wait_op_done_val - wait until an operation is completed
44 * @adapter: the adapter performing the operation
45 * @reg: the register to check for completion
46 * @mask: a single-bit field within @reg that indicates completion
47 * @polarity: the value of the field when the operation is completed
48 * @attempts: number of check iterations
49 * @delay: delay in usecs between iterations
50 * @valp: where to store the value of the register at completion time
51 *
52 * Wait until an operation is completed by checking a bit in a register
53 * up to @attempts times. If @valp is not NULL the value of the register
54 * at the time it indicated completion is stored there. Returns 0 if the
55 * operation completes and -EAGAIN otherwise.
56 */
59 {
67 }
72 }
73 }
77 {
80 }
82 /**
83 * t4_set_reg_field - set a register field to a value
84 * @adapter: the adapter to program
85 * @addr: the register address
86 * @mask: specifies the portion of the register to modify
87 * @val: the new value for the register field
88 *
89 * Sets a register field specified by the supplied mask to the
90 * given value.
91 */
93 u32 val)
94 {
99 }
101 /**
102 * t4_read_indirect - read indirectly addressed registers
103 * @adap: the adapter
104 * @addr_reg: register holding the indirect address
105 * @data_reg: register holding the value of the indirect register
106 * @vals: where the read register values are stored
107 * @nregs: how many indirect registers to read
108 * @start_idx: index of first indirect register to read
109 *
110 * Reads registers that are accessed indirectly through an address/data
111 * register pair.
112 */
116 {
120 start_idx++;
121 }
122 }
124 /**
125 * t4_write_indirect - write indirectly addressed registers
126 * @adap: the adapter
127 * @addr_reg: register holding the indirect addresses
128 * @data_reg: register holding the value for the indirect registers
129 * @vals: values to write
130 * @nregs: how many indirect registers to write
131 * @start_idx: address of first indirect register to write
132 *
133 * Writes a sequential block of registers that are accessed indirectly
134 * through an address/data register pair.
135 */
139 {
143 }
144 }
146 /*
147 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
148 * mechanism. This guarantees that we get the real value even if we're
149 * operating within a Virtual Machine and the Hypervisor is trapping our
150 * Configuration Space accesses.
151 */
153 {
158 else
167 /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
168 * Configuration Space read. (None of the other fields matter when
169 * ENABLE is 0 so a simple register write is easier than a
170 * read-modify-write via t4_set_reg_field().)
171 */
173 }
175 /*
176 * t4_report_fw_error - report firmware error
177 * @adap: the adapter
178 *
179 * The adapter firmware can indicate error conditions to the host.
180 * If the firmware has indicated an error, print out the reason for
181 * the firmware error.
182 */
184 {
194 };
195 u32 pcie_fw;
202 }
203 }
205 /*
206 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
207 */
209 u32 mbox_addr)
210 {
213 }
215 /*
216 * Handle a FW assertion reported in a mailbox.
217 */
219 {
227 }
229 /**
230 * t4_record_mbox - record a Firmware Mailbox Command/Reply in the log
231 * @adapter: the adapter
232 * @cmd: the Firmware Mailbox Command or Reply
233 * @size: command length in bytes
234 * @access: the time (ms) needed to access the Firmware Mailbox
235 * @execute: the time (ms) the command spent being executed
236 */
240 {
257 }
259 /**
260 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
261 * @adap: the adapter
262 * @mbox: index of the mailbox to use
263 * @cmd: the command to write
264 * @size: command length in bytes
265 * @rpl: where to optionally store the reply
266 * @sleep_ok: if true we may sleep while awaiting command completion
267 * @timeout: time to wait for command to finish before timing out
268 *
269 * Sends the given command to FW through the selected mailbox and waits
270 * for the FW to execute the command. If @rpl is not %NULL it is used to
271 * store the FW's reply to the command. The command and its optional
272 * reply are of the same length. FW can take up to %FW_CMD_MAX_TIMEOUT ms
273 * to respond. @sleep_ok determines whether we may sleep while awaiting
274 * the response. If sleeping is allowed we use progressive backoff
275 * otherwise we spin.
276 *
277 * The return value is 0 on success or a negative errno on failure. A
278 * failure can happen either because we are not able to execute the
279 * command or FW executes it but signals an error. In the latter case
280 * the return value is the error code indicated by FW (negated).
281 */
284 {
287 };
292 u32 v;
293 u64 res;
299 u32 pcie_fw;
304 /*
305 * If the device is off-line, as in EEH, commands will time out.
306 * Fail them early so we don't waste time waiting.
307 */
311 /* If we have a negative timeout, that implies that we can't sleep. */
315 }
317 /* Queue ourselves onto the mailbox access list. When our entry is at
318 * the front of the list, we have rights to access the mailbox. So we
319 * wait [for a while] till we're at the front [or bail out with an
320 * EBUSY] ...
321 */
330 /* If we've waited too long, return a busy indication. This
331 * really ought to be based on our initial position in the
332 * mailbox access list but this is a start. We very rarely
333 * contend on access to the mailbox ...
334 */
343 }
345 /* If we're at the head, break out and start the mailbox
346 * protocol.
347 */
352 /* Delay for a bit before checking again ... */
356 delay_idx++;
360 }
361 }
363 /* Loop trying to get ownership of the mailbox. Return an error
364 * if we can't gain ownership.
365 */
376 }
378 /* Copy in the new mailbox command and send it on its way ... */
396 delay_idx++;
406 }
416 }
427 }
428 }
440 }
444 {
446 FW_CMD_MAX_TIMEOUT);
447 }
450 {
451 u32 edc_ecc_err_addr_reg;
452 u32 rdata_reg;
457 }
461 }
472 rdata_reg,
484 }
486 /**
487 * t4_memory_rw_init - Get memory window relative offset, base, and size.
488 * @adap: the adapter
489 * @win: PCI-E Memory Window to use
490 * @mtype: memory type: MEM_EDC0, MEM_EDC1, MEM_HMA or MEM_MC
491 * @mem_off: memory relative offset with respect to @mtype.
492 * @mem_base: configured memory base address.
493 * @mem_aperture: configured memory window aperture.
494 *
495 * Get the configured memory window's relative offset, base, and size.
496 */
499 {
502 /* Offset into the region of memory which is being accessed
503 * MEM_EDC0 = 0
504 * MEM_EDC1 = 1
505 * MEM_MC = 2 -- MEM_MC for chips with only 1 memory controller
506 * MEM_MC1 = 3 -- for chips with 2 memory controllers (e.g. T5)
507 * MEM_HMA = 4
508 */
516 MA_EXT_MEMORY0_BAR_A));
518 }
520 /* Each PCI-E Memory Window is programmed with a window size -- or
521 * "aperture" -- which controls the granularity of its mapping onto
522 * adapter memory. We need to grab that aperture in order to know
523 * how to use the specified window. The window is also programmed
524 * with the base address of the Memory Window in BAR0's address
525 * space. For T4 this is an absolute PCI-E Bus Address. For T5
526 * the address is relative to BAR0.
527 */
530 win));
531 /* a dead adapter will return 0xffffffff for PIO reads */
541 }
543 /**
544 * t4_memory_update_win - Move memory window to specified address.
545 * @adap: the adapter
546 * @win: PCI-E Memory Window to use
547 * @addr: location to move.
548 *
549 * Move memory window to specified address.
550 */
552 {
555 addr);
556 /* Read it back to ensure that changes propagate before we
557 * attempt to use the new value.
558 */
561 }
563 /**
564 * t4_memory_rw_residual - Read/Write residual data.
565 * @adap: the adapter
566 * @off: relative offset within residual to start read/write.
567 * @addr: address within indicated memory type.
568 * @buf: host memory buffer
569 * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
570 *
571 * Read/Write residual data less than 32-bits.
572 */
575 {
577 u32 word;
594 }
595 }
597 /**
598 * t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
599 * @adap: the adapter
600 * @win: PCI-E Memory Window to use
601 * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
602 * @addr: address within indicated memory type
603 * @len: amount of memory to transfer
604 * @hbuf: host memory buffer
605 * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
606 *
607 * Reads/writes an [almost] arbitrary memory region in the firmware: the
608 * firmware memory address and host buffer must be aligned on 32-bit
609 * boundaries; the length may be arbitrary. The memory is transferred as
610 * a raw byte sequence from/to the firmware's memory. If this memory
611 * contains data structures which contain multi-byte integers, it's the
612 * caller's responsibility to perform appropriate byte order conversions.
613 */
616 {
622 /* Argument sanity checks ...
623 */
628 /* It's convenient to be able to handle lengths which aren't a
629 * multiple of 32-bits because we often end up transferring files to
630 * the firmware. So we'll handle that by normalizing the length here
631 * and then handling any residual transfer at the end.
632 */
641 /* Determine the PCIE_MEM_ACCESS_OFFSET */
646 /* Calculate our initial PCI-E Memory Window Position and Offset into
647 * that Window.
648 */
652 /* Set up initial PCI-E Memory Window to cover the start of our
653 * transfer.
654 */
657 /* Transfer data to/from the adapter as long as there's an integral
658 * number of 32-bit transfers to complete.
659 *
660 * A note on Endianness issues:
661 *
662 * The "register" reads and writes below from/to the PCI-E Memory
663 * Window invoke the standard adapter Big-Endian to PCI-E Link
664 * Little-Endian "swizzel." As a result, if we have the following
665 * data in adapter memory:
666 *
667 * Memory: ... | b0 | b1 | b2 | b3 | ...
668 * Address: i+0 i+1 i+2 i+3
669 *
670 * Then a read of the adapter memory via the PCI-E Memory Window
671 * will yield:
672 *
673 * x = readl(i)
674 * 31 0
675 * [ b3 | b2 | b1 | b0 ]
676 *
677 * If this value is stored into local memory on a Little-Endian system
678 * it will show up correctly in local memory as:
679 *
680 * ( ..., b0, b1, b2, b3, ... )
681 *
682 * But on a Big-Endian system, the store will show up in memory
683 * incorrectly swizzled as:
684 *
685 * ( ..., b3, b2, b1, b0, ... )
686 *
687 * So we need to account for this in the reads and writes to the
688 * PCI-E Memory Window below by undoing the register read/write
689 * swizzels.
690 */
695 else
701 /* If we've reached the end of our current window aperture,
702 * move the PCI-E Memory Window on to the next. Note that
703 * doing this here after "len" may be 0 allows us to set up
704 * the PCI-E Memory Window for a possible final residual
705 * transfer below ...
706 */
711 }
712 }
714 /* If the original transfer had a length which wasn't a multiple of
715 * 32-bits, now's where we need to finish off the transfer of the
716 * residual amount. The PCI-E Memory Window has already been moved
717 * above (if necessary) to cover this final transfer.
718 */
724 }
726 /* Return the specified PCI-E Configuration Space register from our Physical
727 * Function. We try first via a Firmware LDST Command since we prefer to let
728 * the firmware own all of these registers, but if that fails we go for it
729 * directly ourselves.
730 */
732 {
735 /* If fw_attach != 0, construct and send the Firmware LDST Command to
736 * retrieve the specified PCI-E Configuration Space register.
737 */
744 FW_CMD_REQUEST_F |
745 FW_CMD_READ_F |
746 ldst_addrspace);
753 /* If the LDST Command succeeds, return the result, otherwise
754 * fall through to reading it directly ourselves ...
755 */
760 else
761 /* Read the desired Configuration Space register via the PCI-E
762 * Backdoor mechanism.
763 */
766 }
768 /* Get the window based on base passed to it.
769 * Window aperture is currently unhandled, but there is no use case for it
770 * right now
771 */
773 u32 memwin_base)
774 {
775 u32 ret;
778 u32 bar0;
780 /* Truncation intentional: we only read the bottom 32-bits of
781 * the 64-bit BAR0/BAR1 ... We use the hardware backdoor
782 * mechanism to read BAR0 instead of using
783 * pci_resource_start() because we could be operating from
784 * within a Virtual Machine which is trapping our accesses to
785 * our Configuration Space and we need to set up the PCI-E
786 * Memory Window decoders with the actual addresses which will
787 * be coming across the PCI-E link.
788 */
795 /* For T5, only relative offset inside the PCIe BAR is passed */
797 }
799 }
801 /* Get the default utility window (win0) used by everyone */
803 {
806 }
808 /* Set up memory window for accessing adapter memory ranges. (Read
809 * back MA register to ensure that changes propagate before we attempt
810 * to use the new values.)
811 */
813 {
820 }
822 /**
823 * t4_get_regs_len - return the size of the chips register set
824 * @adapter: the adapter
825 *
826 * Returns the size of the chip's BAR0 register space.
827 */
829 {
839 }
844 }
846 /**
847 * t4_get_regs - read chip registers into provided buffer
848 * @adap: the adapter
849 * @buf: register buffer
850 * @buf_size: size (in bytes) of register buffer
851 *
852 * If the provided register buffer isn't large enough for the chip's
853 * full register range, the register dump will be truncated to the
854 * register buffer's size.
855 */
857 {
1315 };
2082 };
2643 };
2650 /* Select the right set of register ranges to dump depending on the
2651 * adapter chip type.
2652 */
2673 }
2675 /* Clear the register buffer and insert the appropriate register
2676 * values selected by the above register ranges.
2677 */
2684 /* Iterate across the register range filling in the register
2685 * buffer but don't write past the end of the register buffer.
2686 */
2690 }
2691 }
2692 }
2694 #define EEPROM_STAT_ADDR 0x7bfc
2695 #define VPD_BASE 0x400
2696 #define VPD_BASE_OLD 0
2697 #define VPD_LEN 1024
2698 #define CHELSIO_VPD_UNIQUE_ID 0x82
2700 /**
2701 * t4_eeprom_ptov - translate a physical EEPROM address to virtual
2702 * @phys_addr: the physical EEPROM address
2703 * @fn: the PCI function number
2704 * @sz: size of function-specific area
2705 *
2706 * Translate a physical EEPROM address to virtual. The first 1K is
2707 * accessed through virtual addresses starting at 31K, the rest is
2708 * accessed through virtual addresses starting at 0.
2709 *
2710 * The mapping is as follows:
2711 * [0..1K) -> [31K..32K)
2712 * [1K..1K+A) -> [31K-A..31K)
2713 * [1K+A..ES) -> [0..ES-A-1K)
2714 *
2715 * where A = @fn * @sz, and ES = EEPROM size.
2716 */
2718 {
2727 }
2729 /**
2730 * t4_seeprom_wp - enable/disable EEPROM write protection
2731 * @adapter: the adapter
2732 * @enable: whether to enable or disable write protection
2733 *
2734 * Enables or disables write protection on the serial EEPROM.
2735 */
2737 {
2741 }
2743 /**
2744 * t4_get_raw_vpd_params - read VPD parameters from VPD EEPROM
2745 * @adapter: adapter to read
2746 * @p: where to store the parameters
2747 *
2748 * Reads card parameters stored in VPD EEPROM.
2749 */
2751 {
2761 /* Card information normally starts at VPD_BASE but early cards had
2762 * it at 0.
2763 */
2768 /* The VPD shall have a unique identifier specified by the PCI SIG.
2769 * For chelsio adapters, the identifier is 0x82. The first byte of a VPD
2770 * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software
2771 * is expected to automatically put this entry at the
2772 * beginning of the VPD.
2773 */
2784 }
2795 }
2803 }
2805 #define FIND_VPD_KW(var, name) do { \
2806 var = pci_vpd_find_info_keyword(vpd, kw_offset, vpdr_len, name); \
2807 if (var < 0) { \
2809 ret = -EINVAL; \
2810 goto out; \
2811 } \
2812 var += PCI_VPD_INFO_FLD_HDR_SIZE; \
2813 } while (0)
2824 }
2830 #undef FIND_VPD_KW
2845 out:
2848 }
2850 /**
2851 * t4_get_vpd_params - read VPD parameters & retrieve Core Clock
2852 * @adapter: adapter to read
2853 * @p: where to store the parameters
2854 *
2855 * Reads card parameters stored in VPD EEPROM and retrieves the Core
2856 * Clock. This can only be called after a connection to the firmware
2857 * is established.
2858 */
2860 {
2864 /* Grab the raw VPD parameters.
2865 */
2870 /* Ask firmware for the Core Clock since it knows how to translate the
2871 * Reference Clock ('V2') VPD field into a Core Clock value ...
2872 */
2883 }
2885 /**
2886 * t4_get_pfres - retrieve VF resource limits
2887 * @adapter: the adapter
2888 *
2889 * Retrieves configured resource limits and capabilities for a physical
2890 * function. The results are stored in @adapter->pfres.
2891 */
2893 {
2897 u32 word;
2899 /* Execute PFVF Read command to get VF resource limits; bail out early
2900 * with error on command failure.
2901 */
2904 FW_CMD_REQUEST_F |
2905 FW_CMD_READ_F |
2913 /* Extract PF resource limits and return success.
2914 */
2934 }
2936 /* serial flash and firmware constants */
2940 /* flash command opcodes */
2948 };
2950 /**
2951 * sf1_read - read data from the serial flash
2952 * @adapter: the adapter
2953 * @byte_cnt: number of bytes to read
2954 * @cont: whether another operation will be chained
2955 * @lock: whether to lock SF for PL access only
2956 * @valp: where to store the read data
2957 *
2958 * Reads up to 4 bytes of data from the serial flash. The location of
2959 * the read needs to be specified prior to calling this by issuing the
2960 * appropriate commands to the serial flash.
2961 */
2964 {
2977 }
2979 /**
2980 * sf1_write - write data to the serial flash
2981 * @adapter: the adapter
2982 * @byte_cnt: number of bytes to write
2983 * @cont: whether another operation will be chained
2984 * @lock: whether to lock SF for PL access only
2985 * @val: value to write
2986 *
2987 * Writes up to 4 bytes of data to the serial flash. The location of
2988 * the write needs to be specified prior to calling this by issuing the
2989 * appropriate commands to the serial flash.
2990 */
2993 {
3002 }
3004 /**
3005 * flash_wait_op - wait for a flash operation to complete
3006 * @adapter: the adapter
3007 * @attempts: max number of polls of the status register
3008 * @delay: delay between polls in ms
3009 *
3010 * Wait for a flash operation to complete by polling the status register.
3011 */
3013 {
3015 u32 status;
3027 }
3028 }
3030 /**
3031 * t4_read_flash - read words from serial flash
3032 * @adapter: the adapter
3033 * @addr: the start address for the read
3034 * @nwords: how many 32-bit words to read
3035 * @data: where to store the read data
3036 * @byte_oriented: whether to store data as bytes or as words
3037 *
3038 * Read the specified number of 32-bit words from the serial flash.
3039 * If @byte_oriented is set the read data is stored as a byte array
3040 * (i.e., big-endian), otherwise as 32-bit words in the platform's
3041 * natural endianness.
3042 */
3045 {
3065 }
3067 }
3069 /**
3070 * t4_write_flash - write up to a page of data to the serial flash
3071 * @adapter: the adapter
3072 * @addr: the start address to write
3073 * @n: length of data to write in bytes
3074 * @data: the data to write
3075 *
3076 * Writes up to a page of data (256 bytes) to the serial flash starting
3077 * at the given address. All the data must be written to the same page.
3078 */
3081 {
3103 }
3110 /* Read the page to verify the write succeeded */
3118 addr);
3120 }
3123 unlock:
3126 }
3128 /**
3129 * t4_get_fw_version - read the firmware version
3130 * @adapter: the adapter
3131 * @vers: where to place the version
3132 *
3133 * Reads the FW version from flash.
3134 */
3136 {
3140 }
3142 /**
3143 * t4_get_bs_version - read the firmware bootstrap version
3144 * @adapter: the adapter
3145 * @vers: where to place the version
3146 *
3147 * Reads the FW Bootstrap version from flash.
3148 */
3150 {
3154 }
3156 /**
3157 * t4_get_tp_version - read the TP microcode version
3158 * @adapter: the adapter
3159 * @vers: where to place the version
3160 *
3161 * Reads the TP microcode version from flash.
3162 */
3164 {
3168 }
3170 /**
3171 * t4_get_exprom_version - return the Expansion ROM version (if any)
3172 * @adapter: the adapter
3173 * @vers: where to place the version
3174 *
3175 * Reads the Expansion ROM header from FLASH and returns the version
3176 * number (if present) through the @vers return value pointer. We return
3177 * this in the Firmware Version Format since it's convenient. Return
3178 * 0 on success, -ENOENT if no Expansion ROM is present.
3179 */
3181 {
3205 }
3207 /**
3208 * t4_get_vpd_version - return the VPD version
3209 * @adapter: the adapter
3210 * @vers: where to place the version
3211 *
3212 * Reads the VPD via the Firmware interface (thus this can only be called
3213 * once we're ready to issue Firmware commands). The format of the
3214 * VPD version is adapter specific. Returns 0 on success, an error on
3215 * failure.
3216 *
3217 * Note that early versions of the Firmware didn't include the ability
3218 * to retrieve the VPD version, so we zero-out the return-value parameter
3219 * in that case to avoid leaving it with garbage in it.
3220 *
3221 * Also note that the Firmware will return its cached copy of the VPD
3222 * Revision ID, not the actual Revision ID as written in the Serial
3223 * EEPROM. This is only an issue if a new VPD has been written and the
3224 * Firmware/Chip haven't yet gone through a RESET sequence. So it's best
3225 * to defer calling this routine till after a FW_RESET_CMD has been issued
3226 * if the Host Driver will be performing a full adapter initialization.
3227 */
3229 {
3230 u32 vpdrev_param;
3240 }
3242 /**
3243 * t4_get_scfg_version - return the Serial Configuration version
3244 * @adapter: the adapter
3245 * @vers: where to place the version
3246 *
3247 * Reads the Serial Configuration Version via the Firmware interface
3248 * (thus this can only be called once we're ready to issue Firmware
3249 * commands). The format of the Serial Configuration version is
3250 * adapter specific. Returns 0 on success, an error on failure.
3251 *
3252 * Note that early versions of the Firmware didn't include the ability
3253 * to retrieve the Serial Configuration version, so we zero-out the
3254 * return-value parameter in that case to avoid leaving it with
3255 * garbage in it.
3256 *
3257 * Also note that the Firmware will return its cached copy of the Serial
3258 * Initialization Revision ID, not the actual Revision ID as written in
3259 * the Serial EEPROM. This is only an issue if a new VPD has been written
3260 * and the Firmware/Chip haven't yet gone through a RESET sequence. So
3261 * it's best to defer calling this routine till after a FW_RESET_CMD has
3262 * been issued if the Host Driver will be performing a full adapter
3263 * initialization.
3264 */
3266 {
3267 u32 scfgrev_param;
3277 }
3279 /**
3280 * t4_get_version_info - extract various chip/firmware version information
3281 * @adapter: the adapter
3282 *
3283 * Reads various chip/firmware version numbers and stores them into the
3284 * adapter Adapter Parameters structure. If any of the efforts fails
3285 * the first failure will be returned, but all of the version numbers
3286 * will be read.
3287 */
3289 {
3292 #define FIRST_RET(__getvinfo) \
3293 do { \
3294 int __ret = __getvinfo; \
3295 if (__ret && !ret) \
3296 ret = __ret; \
3297 } while (0)
3306 #undef FIRST_RET
3308 }
3310 /**
3311 * t4_dump_version_info - dump all of the adapter configuration IDs
3312 * @adapter: the adapter
3313 *
3314 * Dumps all of the various bits of adapter configuration version/revision
3315 * IDs information. This is typically called at some point after
3316 * t4_get_version_info() has been called.
3317 */
3319 {
3320 /* Device information */
3327 /* Firmware Version */
3330 else
3337 /* Bootstrap Firmware Version. (Some adapters don't have Bootstrap
3338 * Firmware, so dev_info() is more appropriate here.)
3339 */
3342 else
3349 /* TP Microcode Version */
3352 else
3360 /* Expansion ROM version */
3363 else
3371 /* Serial Configuration version */
3375 /* VPD Version */
3378 }
3380 /**
3381 * t4_check_fw_version - check if the FW is supported with this driver
3382 * @adap: the adapter
3383 *
3384 * Checks if an adapter's FW is compatible with the driver. Returns 0
3385 * if there's exact match, a negative error if the version could not be
3386 * read or there's a major version mismatch
3387 */
3389 {
3395 /* Try multiple times before returning error */
3426 }
3431 "Card has firmware version %u.%u.%u, minimum "
3435 }
3437 }
3439 /* Is the given firmware API compatible with the one the driver was compiled
3440 * with?
3441 */
3443 {
3445 /* short circuit if it's the exact same firmware version */
3449 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
3453 #undef SAME_INTF
3456 }
3458 /* The firmware in the filesystem is usable, but should it be installed?
3459 * This routine explains itself in detail if it indicates the filesystem
3460 * firmware should be installed.
3461 */
3464 {
3470 }
3475 }
3479 install:
3488 }
3494 {
3501 /* Read the header of the firmware on the card */
3511 }
3519 }
3523 /* Common case: the firmware on the card is an exact match and
3524 * the filesystem one is an exact match too, or the filesystem
3525 * one is absent/incompatible.
3526 */
3537 }
3539 /* Installed successfully, update the cached header too. */
3543 }
3553 "chip state %d, "
3554 "driver compiled with %d.%d.%d.%d, "
3556 state,
3565 }
3567 /* We're using whatever's on the card and it's known to be good. */
3571 bye:
3573 }
3575 /**
3576 * t4_flash_erase_sectors - erase a range of flash sectors
3577 * @adapter: the adapter
3578 * @start: the first sector to erase
3579 * @end: the last sector to erase
3580 *
3581 * Erases the sectors in the given inclusive range.
3582 */
3584 {
3599 }
3600 start++;
3601 }
3604 }
3606 /**
3607 * t4_flash_cfg_addr - return the address of the flash configuration file
3608 * @adapter: the adapter
3609 *
3610 * Return the address within the flash where the Firmware Configuration
3611 * File is stored.
3612 */
3614 {
3617 else
3619 }
3621 /* Return TRUE if the specified firmware matches the adapter. I.e. T4
3622 * firmware for T4 adapters, T5 firmware for T5 adapters, etc. We go ahead
3623 * and emit an error message for mismatched firmware to save our caller the
3624 * effort ...
3625 */
3628 {
3629 /* The expression below will return FALSE for any unsupported adapter
3630 * which will keep us "honest" in the future ...
3631 */
3641 }
3643 /**
3644 * t4_load_fw - download firmware
3645 * @adap: the adapter
3646 * @fw_data: the firmware image to write
3647 * @size: image size
3648 *
3649 * Write the supplied firmware image to the card's serial flash.
3650 */
3652 {
3653 u32 csum;
3667 }
3672 }
3677 }
3680 fw_size);
3682 }
3693 }
3700 /*
3701 * We write the correct version at the end so the driver can see a bad
3702 * version if the FW write fails. Start by writing a copy of the
3703 * first page with a bad version.
3704 */
3718 }
3723 out:
3726 ret);
3727 else
3730 }
3732 /**
3733 * t4_phy_fw_ver - return current PHY firmware version
3734 * @adap: the adapter
3735 * @phy_fw_ver: return value buffer for PHY firmware version
3736 *
3737 * Returns the current version of external PHY firmware on the
3738 * adapter.
3739 */
3741 {
3755 }
3757 /**
3758 * t4_load_phy_fw - download port PHY firmware
3759 * @adap: the adapter
3760 * @win: the PCI-E Memory Window index to use for t4_memory_rw()
3761 * @win_lock: the lock to use to guard the memory copy
3762 * @phy_fw_version: function to check PHY firmware versions
3763 * @phy_fw_data: the PHY firmware image to write
3764 * @phy_fw_size: image size
3765 *
3766 * Transfer the specified PHY firmware to the adapter. If a non-NULL
3767 * @phy_fw_version is supplied, then it will be used to determine if
3768 * it's necessary to perform the transfer by comparing the version
3769 * of any existing adapter PHY firmware with that of the passed in
3770 * PHY firmware image. If @win_lock is non-NULL then it will be used
3771 * around the call to t4_memory_rw() which transfers the PHY firmware
3772 * to the adapter.
3773 *
3774 * A negative error number will be returned if an error occurs. If
3775 * version number support is available and there's no need to upgrade
3776 * the firmware, 0 will be returned. If firmware is successfully
3777 * transferred to the adapter, 1 will be returned.
3778 *
3779 * NOTE: some adapters only have local RAM to store the PHY firmware. As
3780 * a result, a RESET of the adapter would cause that RAM to lose its
3781 * contents. Thus, loading PHY firmware on such adapters must happen
3782 * after any FW_RESET_CMDs ...
3783 */
3788 {
3794 /* If we have version number support, then check to see if the adapter
3795 * already has up-to-date PHY firmware loaded.
3796 */
3807 }
3808 }
3810 /* Ask the firmware where it wants us to copy the PHY firmware image.
3811 * The size of the file requires a special version of the READ command
3812 * which will pass the file size via the values field in PARAMS_CMD and
3813 * retrieve the return value from firmware and place it in the same
3814 * buffer values
3815 */
3828 /* Copy the supplied PHY Firmware image to the adapter memory location
3829 * allocated by the adapter firmware.
3830 */
3835 T4_MEMORY_WRITE);
3841 /* Tell the firmware that the PHY firmware image has been written to
3842 * RAM and it can now start copying it over to the PHYs. The chip
3843 * firmware will RESET the affected PHYs as part of this operation
3844 * leaving them running the new PHY firmware image.
3845 */
3853 /* If we have version number support, then check to see that the new
3854 * firmware got loaded properly.
3855 */
3863 "version on adapter %#x, "
3867 }
3868 }
3871 }
3873 /**
3874 * t4_fwcache - firmware cache operation
3875 * @adap: the adapter
3876 * @op : the operation (flush or flush and invalidate)
3877 */
3879 {
3895 }
3900 {
3922 req++;
3923 rsp++;
3924 }
3927 }
3929 }
3932 {
3933 u32 cfg;
3947 }
3948 }
3950 }
3953 {
3964 }
3965 }
3967 /* The ADVERT_MASK is used to mask out all of the Advertised Firmware Port
3968 * Capabilities which we control with separate controls -- see, for instance,
3969 * Pause Frames and Forward Error Correction. In order to determine what the
3970 * full set of Advertised Port Capabilities are, the base Advertised Port
3971 * Capabilities (masked by ADVERT_MASK) must be combined with the Advertised
3972 * Port Capabilities associated with those other controls. See
3973 * t4_link_acaps() for how this is done.
3974 */
3975 #define ADVERT_MASK (FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_M) | \
3976 FW_PORT_CAP32_ANEG)
3978 /**
3979 * fwcaps16_to_caps32 - convert 16-bit Port Capabilities to 32-bits
3980 * @caps16: a 16-bit Port Capabilities value
3981 *
3982 * Returns the equivalent 32-bit Port Capabilities value.
3983 */
3985 {
3988 #define CAP16_TO_CAP32(__cap) \
3989 do { \
3990 if (caps16 & FW_PORT_CAP_##__cap) \
3991 caps32 |= FW_PORT_CAP32_##__cap; \
3992 } while (0)
4011 #undef CAP16_TO_CAP32
4014 }
4016 /**
4017 * fwcaps32_to_caps16 - convert 32-bit Port Capabilities to 16-bits
4018 * @caps32: a 32-bit Port Capabilities value
4019 *
4020 * Returns the equivalent 16-bit Port Capabilities value. Note that
4021 * not all 32-bit Port Capabilities can be represented in the 16-bit
4022 * Port Capabilities and some fields/values may not make it.
4023 */
4025 {
4028 #define CAP32_TO_CAP16(__cap) \
4029 do { \
4030 if (caps32 & FW_PORT_CAP32_##__cap) \
4031 caps16 |= FW_PORT_CAP_##__cap; \
4032 } while (0)
4051 #undef CAP32_TO_CAP16
4054 }
4056 /* Translate Firmware Port Capabilities Pause specification to Common Code */
4058 {
4067 }
4069 /* Translate Common Code Pause specification into Firmware Port Capabilities */
4071 {
4072 /* Translate orthogonal RX/TX Pause Controls for L1 Configure
4073 * commands, etc.
4074 */
4084 /* Translate orthogonal Pause controls into IEEE 802.3 Pause,
4085 * Asymmetrical Pause for use in reporting to upper layer OS code, etc.
4086 * Note that these bits are ignored in L1 Configure commands.
4087 */
4091 else
4093 FW_PORT_CAP32_802_3_PAUSE;
4096 }
4099 }
4101 /* Translate Firmware Forward Error Correction specification to Common Code */
4103 {
4112 }
4114 /* Translate Common Code Forward Error Correction specification to Firmware */
4116 {
4125 }
4127 /**
4128 * t4_link_acaps - compute Link Advertised Port Capabilities
4129 * @adapter: the adapter
4130 * @port: the Port ID
4131 * @lc: the Port's Link Configuration
4132 *
4133 * Synthesize the Advertised Port Capabilities we'll be using based on
4134 * the base Advertised Port Capabilities (which have been filtered by
4135 * ADVERT_MASK) plus the individual controls for things like Pause
4136 * Frames, Forward Error Correction, MDI, etc.
4137 */
4140 {
4147 /* Convert driver coding of Pause Frame Flow Control settings into the
4148 * Firmware's API.
4149 */
4152 /* Convert Common Code Forward Error Control settings into the
4153 * Firmware's API. If the current Requested FEC has "Automatic"
4154 * (IEEE 802.3) specified, then we use whatever the Firmware
4155 * sent us as part of its IEEE 802.3-based interpretation of
4156 * the Transceiver Module EPROM FEC parameters. Otherwise we
4157 * use whatever is in the current Requested FEC settings.
4158 */
4161 else
4165 /* Figure out what our Requested Port Capabilities are going to be.
4166 * Note parallel structure in t4_handle_get_port_info() and
4167 * init_link_config().
4168 */
4179 }
4181 /* Some Requested Port Capabilities are trivially wrong if they exceed
4182 * the Physical Port Capabilities. We can check that here and provide
4183 * moderately useful feedback in the system log.
4184 *
4185 * Note that older Firmware doesn't have FW_PORT_CAP32_FORCE_PAUSE, so
4186 * we need to exclude this from this check in order to maintain
4187 * compatibility ...
4188 */
4190 dev_err(adapter->pdev_dev, "Requested Port Capabilities %#x exceed Physical Port Capabilities %#x\n",
4193 }
4196 }
4198 /**
4199 * t4_link_l1cfg_core - apply link configuration to MAC/PHY
4200 * @adapter: the adapter
4201 * @mbox: the Firmware Mailbox to use
4202 * @port: the Port ID
4203 * @lc: the Port's Link Configuration
4204 * @sleep_ok: if true we may sleep while awaiting command completion
4205 * @timeout: time to wait for command to finish before timing out
4206 * (negative implies @sleep_ok=false)
4207 *
4208 * Set up a port's MAC and PHY according to a desired link configuration.
4209 * - If the PHY can auto-negotiate first decide what to advertise, then
4210 * enable/disable auto-negotiation as desired, and reset.
4211 * - If the PHY does not auto-negotiate just reset it.
4212 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
4213 * otherwise do it later based on the outcome of auto-negotiation.
4214 */
4218 {
4221 fw_port_cap32_t rcap;
4227 }
4229 /* Compute our Requested Port Capabilities and send that on to the
4230 * Firmware.
4231 */
4239 ? FW_PORT_ACTION_L1_CFG
4244 else
4250 /* Unfortunately, even if the Requested Port Capabilities "fit" within
4251 * the Physical Port Capabilities, some combinations of features may
4252 * still not be legal. For example, 40Gb/s and Reed-Solomon Forward
4253 * Error Correction. So if the Firmware rejects the L1 Configure
4254 * request, flag that here.
4255 */
4261 }
4263 }
4265 /**
4266 * t4_restart_aneg - restart autonegotiation
4267 * @adap: the adapter
4268 * @mbox: mbox to use for the FW command
4269 * @port: the port id
4270 *
4271 * Restarts autonegotiation for the selected port.
4272 */
4274 {
4284 ? FW_PORT_ACTION_L1_CFG
4289 else
4292 }
4302 };
4304 /**
4305 * t4_handle_intr_status - table driven interrupt handler
4306 * @adapter: the adapter that generated the interrupt
4307 * @reg: the interrupt status register to process
4308 * @acts: table of interrupt actions
4309 *
4310 * A table driven interrupt handler that applies a set of masks to an
4311 * interrupt status word and performs the corresponding actions if the
4312 * interrupts described by the mask have occurred. The actions include
4313 * optionally emitting a warning or alert message. The table is terminated
4314 * by an entry specifying mask 0. Returns the number of fatal interrupt
4315 * conditions.
4316 */
4319 {
4328 fatal++;
4337 }
4342 }
4344 /*
4345 * Interrupt handler for the PCIE module.
4346 */
4348 {
4356 };
4368 };
4402 };
4442 };
4448 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A,
4449 sysbus_intr_info) +
4451 PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A,
4452 pcie_port_intr_info) +
4454 pcie_intr_info);
4455 else
4457 t5_pcie_intr_info);
4461 }
4463 /*
4464 * TP interrupt handler.
4465 */
4467 {
4472 };
4476 }
4478 /*
4479 * SGE interrupt handler.
4480 */
4482 {
4483 u64 v;
4484 u32 err;
4508 };
4516 };
4525 }
4530 t4t5_sge_intr_info);
4540 UNCAPTURED_ERROR_F);
4541 }
4545 }
4547 #define CIM_OBQ_INTR (OBQULP0PARERR_F | OBQULP1PARERR_F | OBQULP2PARERR_F |\
4548 OBQULP3PARERR_F | OBQSGEPARERR_F | OBQNCSIPARERR_F)
4549 #define CIM_IBQ_INTR (IBQTP0PARERR_F | IBQTP1PARERR_F | IBQULPPARERR_F |\
4550 IBQSGEHIPARERR_F | IBQSGELOPARERR_F | IBQNCSIPARERR_F)
4552 /*
4553 * CIM interrupt handler.
4554 */
4556 {
4567 };
4598 };
4607 /* When the Firmware detects an internal error which normally
4608 * wouldn't raise a Host Interrupt, it forces a CIM Timer0 interrupt
4609 * in order to make sure the Host sees the Firmware Crash. So
4610 * if we have a Timer0 interrupt and don't see a Firmware Crash,
4611 * ignore the Timer0 interrupt.
4612 */
4619 TIMER0INT_F);
4622 cim_intr_info) +
4624 cim_upintr_info);
4627 }
4629 /*
4630 * ULP RX interrupt handler.
4631 */
4633 {
4638 };
4642 }
4644 /*
4645 * ULP TX interrupt handler.
4646 */
4648 {
4660 };
4664 }
4666 /*
4667 * PM TX interrupt handler.
4668 */
4670 {
4683 };
4687 }
4689 /*
4690 * PM RX interrupt handler.
4691 */
4693 {
4703 };
4707 }
4709 /*
4710 * CPL switch interrupt handler.
4711 */
4713 {
4722 };
4726 }
4728 /*
4729 * LE interrupt handler.
4730 */
4732 {
4741 };
4750 };
4756 }
4758 /*
4759 * MPS interrupt handler.
4760 */
4762 {
4766 };
4778 };
4786 /* MPS Tx Bubble is normal for T6 */
4790 };
4797 };
4801 };
4805 };
4809 };
4815 };
4820 mps_rx_intr_info) +
4823 ? t6_mps_tx_intr_info
4826 mps_trc_intr_info) +
4828 mps_stat_sram_intr_info) +
4830 mps_stat_tx_intr_info) +
4832 mps_stat_rx_intr_info) +
4834 mps_cls_intr_info);
4840 }
4842 #define MEM_INT_MASK (PERR_INT_CAUSE_F | ECC_CE_INT_CAUSE_F | \
4843 ECC_UE_INT_CAUSE_F)
4845 /*
4846 * EDC/MC interrupt handler.
4847 */
4849 {
4864 }
4868 }
4884 }
4892 }
4894 /*
4895 * MA interrupt handler.
4896 */
4898 {
4909 MA_PARITY_ERROR_STATUS2_A));
4910 }
4917 }
4920 }
4922 /*
4923 * SMB interrupt handler.
4924 */
4926 {
4932 };
4936 }
4938 /*
4939 * NC-SI interrupt handler.
4940 */
4942 {
4949 };
4953 }
4955 /*
4956 * XGMAC interrupt handler.
4957 */
4959 {
4964 else
4975 port);
4978 port);
4981 }
4983 /*
4984 * PL interrupt handler.
4985 */
4987 {
4992 };
4996 }
4998 #define PF_INTR_MASK (PFSW_F)
4999 #define GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | EDC0_F | \
5000 EDC1_F | LE_F | TP_F | MA_F | PM_TX_F | PM_RX_F | ULP_RX_F | \
5001 CPL_SWITCH_F | SGE_F | ULP_TX_F | SF_F)
5003 /**
5004 * t4_slow_intr_handler - control path interrupt handler
5005 * @adapter: the adapter
5006 *
5007 * T4 interrupt handler for non-data global interrupt events, e.g., errors.
5008 * The designation 'slow' is because it involves register reads, while
5009 * data interrupts typically don't involve any MMIOs.
5010 */
5012 {
5013 /* There are rare cases where a PL_INT_CAUSE bit may end up getting
5014 * set when the corresponding PL_INT_ENABLE bit isn't set. It's
5015 * easiest just to mask that case here.
5016 */
5070 /* Clear the interrupts just processed for which we are the master. */
5074 }
5076 /**
5077 * t4_intr_enable - enable interrupts
5078 * @adapter: the adapter whose interrupts should be enabled
5079 *
5080 * Enable PF-specific interrupts for the calling function and the top-level
5081 * interrupt concentrator for global interrupts. Interrupts are already
5082 * enabled at each module, here we just enable the roots of the interrupt
5083 * hierarchies.
5084 *
5085 * Note: this function should be called only when the driver manages
5086 * non PF-specific interrupts from the various HW modules. Only one PCI
5087 * function at a time should be doing this.
5088 */
5090 {
5107 }
5109 /**
5110 * t4_intr_disable - disable interrupts
5111 * @adapter: the adapter whose interrupts should be disabled
5112 *
5113 * Disable interrupts. We only disable the top-level interrupt
5114 * concentrators. The caller must be a PCI function managing global
5115 * interrupts.
5116 */
5118 {
5130 }
5133 {
5136 else
5138 }
5140 /**
5141 * t4_config_rss_range - configure a portion of the RSS mapping table
5142 * @adapter: the adapter
5143 * @mbox: mbox to use for the FW command
5144 * @viid: virtual interface whose RSS subtable is to be written
5145 * @start: start entry in the table to write
5146 * @n: how many table entries to write
5147 * @rspq: values for the response queue lookup table
5148 * @nrspq: number of values in @rspq
5149 *
5150 * Programs the selected part of the VI's RSS mapping table with the
5151 * provided values. If @nrspq < @n the supplied values are used repeatedly
5152 * until the full table range is populated.
5153 *
5154 * The caller must ensure the values in @rspq are in the range allowed for
5155 * @viid.
5156 */
5159 {
5171 /* each fw_rss_ind_tbl_cmd takes up to 32 entries */
5197 }
5202 }
5204 }
5206 /**
5207 * t4_config_glbl_rss - configure the global RSS mode
5208 * @adapter: the adapter
5209 * @mbox: mbox to use for the FW command
5210 * @mode: global RSS mode
5211 * @flags: mode-specific flags
5212 *
5213 * Sets the global RSS mode.
5214 */
5217 {
5234 }
5236 /**
5237 * t4_config_vi_rss - configure per VI RSS settings
5238 * @adapter: the adapter
5239 * @mbox: mbox to use for the FW command
5240 * @viid: the VI id
5241 * @flags: RSS flags
5242 * @defq: id of the default RSS queue for the VI.
5243 *
5244 * Configures VI-specific RSS properties.
5245 */
5248 {
5259 }
5261 /* Read an RSS table row */
5263 {
5267 }
5269 /**
5270 * t4_read_rss - read the contents of the RSS mapping table
5271 * @adapter: the adapter
5272 * @map: holds the contents of the RSS mapping table
5273 *
5274 * Reads the contents of the RSS hash->queue mapping table.
5275 */
5277 {
5279 u32 val;
5288 }
5290 }
5293 {
5295 }
5297 /**
5298 * t4_tp_fw_ldst_rw - Access TP indirect register through LDST
5299 * @adap: the adapter
5300 * @cmd: TP fw ldst address space type
5301 * @vals: where the indirect register values are stored/written
5302 * @nregs: how many indirect registers to read/write
5303 * @start_idx: index of first indirect register to read/write
5304 * @rw: Read (1) or Write (0)
5305 * @sleep_ok: if true we may sleep while awaiting command completion
5306 *
5307 * Access TP indirect registers through LDST
5308 */
5312 {
5320 FW_CMD_REQUEST_F |
5322 FW_CMD_WRITE_F) |
5329 sleep_ok);
5335 }
5337 }
5339 /**
5340 * t4_tp_indirect_rw - Read/Write TP indirect register through LDST or backdoor
5341 * @adap: the adapter
5342 * @reg_addr: Address Register
5343 * @reg_data: Data register
5344 * @buff: where the indirect register values are stored/written
5345 * @nregs: how many indirect registers to read/write
5346 * @start_index: index of first indirect register to read/write
5347 * @rw: READ(1) or WRITE(0)
5348 * @sleep_ok: if true we may sleep while awaiting command completion
5349 *
5350 * Read/Write TP indirect registers through LDST if possible.
5351 * Else, use backdoor access
5352 **/
5356 {
5372 }
5376 sleep_ok);
5378 indirect_access:
5383 start_index);
5384 else
5386 start_index);
5387 }
5388 }
5390 /**
5391 * t4_tp_pio_read - Read TP PIO registers
5392 * @adap: the adapter
5393 * @buff: where the indirect register values are written
5394 * @nregs: how many indirect registers to read
5395 * @start_index: index of first indirect register to read
5396 * @sleep_ok: if true we may sleep while awaiting command completion
5397 *
5398 * Read TP PIO Registers
5399 **/
5402 {
5405 }
5407 /**
5408 * t4_tp_pio_write - Write TP PIO registers
5409 * @adap: the adapter
5410 * @buff: where the indirect register values are stored
5411 * @nregs: how many indirect registers to write
5412 * @start_index: index of first indirect register to write
5413 * @sleep_ok: if true we may sleep while awaiting command completion
5414 *
5415 * Write TP PIO Registers
5416 **/
5419 {
5422 }
5424 /**
5425 * t4_tp_tm_pio_read - Read TP TM PIO registers
5426 * @adap: the adapter
5427 * @buff: where the indirect register values are written
5428 * @nregs: how many indirect registers to read
5429 * @start_index: index of first indirect register to read
5430 * @sleep_ok: if true we may sleep while awaiting command completion
5431 *
5432 * Read TP TM PIO Registers
5433 **/
5436 {
5439 }
5441 /**
5442 * t4_tp_mib_read - Read TP MIB registers
5443 * @adap: the adapter
5444 * @buff: where the indirect register values are written
5445 * @nregs: how many indirect registers to read
5446 * @start_index: index of first indirect register to read
5447 * @sleep_ok: if true we may sleep while awaiting command completion
5448 *
5449 * Read TP MIB Registers
5450 **/
5453 {
5456 }
5458 /**
5459 * t4_read_rss_key - read the global RSS key
5460 * @adap: the adapter
5461 * @key: 10-entry array holding the 320-bit RSS key
5462 * @sleep_ok: if true we may sleep while awaiting command completion
5463 *
5464 * Reads the global 320-bit RSS key.
5465 */
5467 {
5469 }
5471 /**
5472 * t4_write_rss_key - program one of the RSS keys
5473 * @adap: the adapter
5474 * @key: 10-entry array holding the 320-bit RSS key
5475 * @idx: which RSS key to write
5476 * @sleep_ok: if true we may sleep while awaiting command completion
5477 *
5478 * Writes one of the RSS keys with the given 320-bit value. If @idx is
5479 * 0..15 the corresponding entry in the RSS key table is written,
5480 * otherwise the global RSS key is written.
5481 */
5484 {
5488 /* T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
5489 * allows access to key addresses 16-63 by using KeyWrAddrX
5490 * as index[5:4](upper 2) into key table
5491 */
5503 else
5506 }
5507 }
5509 /**
5510 * t4_read_rss_pf_config - read PF RSS Configuration Table
5511 * @adapter: the adapter
5512 * @index: the entry in the PF RSS table to read
5513 * @valp: where to store the returned value
5514 * @sleep_ok: if true we may sleep while awaiting command completion
5515 *
5516 * Reads the PF RSS Configuration Table at the specified index and returns
5517 * the value found there.
5518 */
5521 {
5523 }
5525 /**
5526 * t4_read_rss_vf_config - read VF RSS Configuration Table
5527 * @adapter: the adapter
5528 * @index: the entry in the VF RSS table to read
5529 * @vfl: where to store the returned VFL
5530 * @vfh: where to store the returned VFH
5531 * @sleep_ok: if true we may sleep while awaiting command completion
5532 *
5533 * Reads the VF RSS Configuration Table at the specified index and returns
5534 * the (VFL, VFH) values found there.
5535 */
5538 {
5547 }
5549 /* Request that the index'th VF Table values be read into VFL/VFH.
5550 */
5556 /* Grab the VFL/VFH values ...
5557 */
5560 }
5562 /**
5563 * t4_read_rss_pf_map - read PF RSS Map
5564 * @adapter: the adapter
5565 * @sleep_ok: if true we may sleep while awaiting command completion
5566 *
5567 * Reads the PF RSS Map register and returns its value.
5568 */
5570 {
5571 u32 pfmap;
5575 }
5577 /**
5578 * t4_read_rss_pf_mask - read PF RSS Mask
5579 * @adapter: the adapter
5580 * @sleep_ok: if true we may sleep while awaiting command completion
5581 *
5582 * Reads the PF RSS Mask register and returns its value.
5583 */
5585 {
5586 u32 pfmask;
5590 }
5592 /**
5593 * t4_tp_get_tcp_stats - read TP's TCP MIB counters
5594 * @adap: the adapter
5595 * @v4: holds the TCP/IP counter values
5596 * @v6: holds the TCP/IPv6 counter values
5597 * @sleep_ok: if true we may sleep while awaiting command completion
5598 *
5599 * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
5600 * Either @v4 or @v6 may be %NULL to skip the corresponding stats.
5601 */
5604 {
5607 #define STAT_IDX(x) ((TP_MIB_TCP_##x##_A) - TP_MIB_TCP_OUT_RST_A)
5608 #define STAT(x) val[STAT_IDX(x)]
5609 #define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
5618 }
5626 }
5627 #undef STAT64
5628 #undef STAT
5629 #undef STAT_IDX
5630 }
5632 /**
5633 * t4_tp_get_err_stats - read TP's error MIB counters
5634 * @adap: the adapter
5635 * @st: holds the counter values
5636 * @sleep_ok: if true we may sleep while awaiting command completion
5637 *
5638 * Returns the values of TP's error counters.
5639 */
5642 {
5646 sleep_ok);
5648 sleep_ok);
5650 sleep_ok);
5656 sleep_ok);
5662 sleep_ok);
5663 }
5665 /**
5666 * t4_tp_get_cpl_stats - read TP's CPL MIB counters
5667 * @adap: the adapter
5668 * @st: holds the counter values
5669 * @sleep_ok: if true we may sleep while awaiting command completion
5670 *
5671 * Returns the values of TP's CPL counters.
5672 */
5675 {
5681 }
5683 /**
5684 * t4_tp_get_rdma_stats - read TP's RDMA MIB counters
5685 * @adap: the adapter
5686 * @st: holds the counter values
5687 * @sleep_ok: if true we may sleep while awaiting command completion
5688 *
5689 * Returns the values of TP's RDMA counters.
5690 */
5693 {
5695 sleep_ok);
5696 }
5698 /**
5699 * t4_get_fcoe_stats - read TP's FCoE MIB counters for a port
5700 * @adap: the adapter
5701 * @idx: the port index
5702 * @st: holds the counter values
5703 * @sleep_ok: if true we may sleep while awaiting command completion
5704 *
5705 * Returns the values of TP's FCoE counters for the selected port.
5706 */
5709 {
5713 sleep_ok);
5719 sleep_ok);
5722 }
5724 /**
5725 * t4_get_usm_stats - read TP's non-TCP DDP MIB counters
5726 * @adap: the adapter
5727 * @st: holds the counter values
5728 * @sleep_ok: if true we may sleep while awaiting command completion
5729 *
5730 * Returns the values of TP's counters for non-TCP directly-placed packets.
5731 */
5734 {
5741 }
5743 /**
5744 * t4_read_mtu_tbl - returns the values in the HW path MTU table
5745 * @adap: the adapter
5746 * @mtus: where to store the MTU values
5747 * @mtu_log: where to store the MTU base-2 log (may be %NULL)
5748 *
5749 * Reads the HW path MTU table.
5750 */
5752 {
5753 u32 v;
5763 }
5764 }
5766 /**
5767 * t4_read_cong_tbl - reads the congestion control table
5768 * @adap: the adapter
5769 * @incr: where to store the alpha values
5770 *
5771 * Reads the additive increments programmed into the HW congestion
5772 * control table.
5773 */
5775 {
5784 }
5785 }
5787 /**
5788 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
5789 * @adap: the adapter
5790 * @addr: the indirect TP register address
5791 * @mask: specifies the field within the register to modify
5792 * @val: new value for the field
5793 *
5794 * Sets a field of an indirect TP register to the given value.
5795 */
5798 {
5802 }
5804 /**
5805 * init_cong_ctrl - initialize congestion control parameters
5806 * @a: the alpha values for congestion control
5807 * @b: the beta values for congestion control
5808 *
5809 * Initialize the congestion control parameters.
5810 */
5812 {
5846 }
5848 /* The minimum additive increment value for the congestion control table */
5849 #define CC_MIN_INCR 2U
5851 /**
5852 * t4_load_mtus - write the MTU and congestion control HW tables
5853 * @adap: the adapter
5854 * @mtus: the values for the MTU table
5855 * @alpha: the values for the congestion control alpha parameter
5856 * @beta: the values for the congestion control beta parameter
5857 *
5858 * Write the HW MTU table with the supplied MTUs and the high-speed
5859 * congestion control table with the supplied alpha, beta, and MTUs.
5860 * We write the two tables together because the additive increments
5861 * depend on the MTUs.
5862 */
5865 {
5870 };
5879 log2--;
5887 CC_MIN_INCR);
5891 }
5892 }
5893 }
5895 /* Calculates a rate in bytes/s given the number of 256-byte units per 4K core
5896 * clocks. The formula is
5897 *
5898 * bytes/s = bytes256 * 256 * ClkFreq / 4096
5899 *
5900 * which is equivalent to
5901 *
5902 * bytes/s = 62.5 * bytes256 * ClkFreq_ms
5903 */
5905 {
5909 }
5911 /**
5912 * t4_get_chan_txrate - get the current per channel Tx rates
5913 * @adap: the adapter
5914 * @nic_rate: rates for NIC traffic
5915 * @ofld_rate: rates for offloaded traffic
5916 *
5917 * Return the current Tx rates in bytes/s for NIC and offloaded traffic
5918 * for each channel.
5919 */
5921 {
5922 u32 v;
5930 }
5938 }
5939 }
5941 /**
5942 * t4_set_trace_filter - configure one of the tracing filters
5943 * @adap: the adapter
5944 * @tp: the desired trace filter parameters
5945 * @idx: which filter to configure
5946 * @enable: whether to enable or disable the filter
5947 *
5948 * Configures one of the tracing filters available in HW. If @enable is
5949 * %0 @tp is not examined and may be %NULL. The user is responsible to
5950 * set the single/multiple trace mode by writing to MPS_TRC_CFG_A register
5951 */
5954 {
5961 }
5965 /* If multiple tracers are enabled, then maximum
5966 * capture size is 2.5KB (FIFO size of a single channel)
5967 * minus 2 flits for CPL_TRACE_PKT header.
5968 */
5972 /* If multiple tracers are disabled, to avoid deadlocks
5973 * maximum packet capture size of 9600 bytes is recommended.
5974 * Also in this mode, only trace0 can be enabled and running.
5975 */
5978 }
5985 /* stop the tracer we'll be changing */
5995 }
6007 }
6009 /**
6010 * t4_get_trace_filter - query one of the tracing filters
6011 * @adap: the adapter
6012 * @tp: the current trace filter parameters
6013 * @idx: which trace filter to query
6014 * @enabled: non-zero if the filter is enabled
6015 *
6016 * Returns the current settings of one of the HW tracing filters.
6017 */
6020 {
6036 }
6049 }
6050 }
6052 /**
6053 * t4_pmtx_get_stats - returns the HW stats from PMTX
6054 * @adap: the adapter
6055 * @cnt: where to store the count statistics
6056 * @cycles: where to store the cycle statistics
6057 *
6058 * Returns performance statistics from PMTX.
6059 */
6061 {
6073 PM_TX_DBG_STAT_MSB_A);
6075 }
6076 }
6077 }
6079 /**
6080 * t4_pmrx_get_stats - returns the HW stats from PMRX
6081 * @adap: the adapter
6082 * @cnt: where to store the count statistics
6083 * @cycles: where to store the cycle statistics
6084 *
6085 * Returns performance statistics from PMRX.
6086 */
6088 {
6100 PM_RX_DBG_STAT_MSB_A);
6102 }
6103 }
6104 }
6106 /**
6107 * compute_mps_bg_map - compute the MPS Buffer Group Map for a Port
6108 * @adap: the adapter
6109 * @pidx: the port index
6110 *
6111 * Computes and returns a bitmap indicating which MPS buffer groups are
6112 * associated with the given Port. Bit i is set if buffer group i is
6113 * used by the Port.
6114 */
6117 {
6130 }
6136 }
6138 }
6144 }
6146 /**
6147 * t4_get_mps_bg_map - return the buffer groups associated with a port
6148 * @adapter: the adapter
6149 * @pidx: the port index
6150 *
6151 * Returns a bitmap indicating which MPS buffer groups are associated
6152 * with the given Port. Bit i is set if buffer group i is used by the
6153 * Port.
6154 */
6156 {
6165 }
6167 /* If we've already retrieved/computed this, just return the result.
6168 */
6173 /* Newer Firmware can tell us what the MPS Buffer Group Map is.
6174 * If we're talking to such Firmware, let it tell us. If the new
6175 * API isn't supported, revert back to old hardcoded way. The value
6176 * obtained from Firmware is encoded in below format:
6177 *
6178 * val = (( MPSBGMAP[Port 3] << 24 ) |
6179 * ( MPSBGMAP[Port 2] << 16 ) |
6180 * ( MPSBGMAP[Port 1] << 8 ) |
6181 * ( MPSBGMAP[Port 0] << 0 ))
6182 */
6194 /* Store the BG Map for all of the Ports in order to
6195 * avoid more calls to the Firmware in the future.
6196 */
6201 }
6202 }
6204 /* Either we're not talking to the Firmware or we're dealing with
6205 * older Firmware which doesn't support the new API to get the MPS
6206 * Buffer Group Map. Fall back to computing it ourselves.
6207 */
6210 }
6212 /**
6213 * t4_get_tp_e2c_map - return the E2C channel map associated with a port
6214 * @adapter: the adapter
6215 * @pidx: the port index
6216 */
6218 {
6228 }
6230 /* FW version >= 1.16.44.0 can determine E2C channel map using
6231 * FW_PARAMS_PARAM_DEV_TPCHMAP API.
6232 */
6241 }
6243 /**
6244 * t4_get_tp_ch_map - return TP ingress channels associated with a port
6245 * @adapter: the adapter
6246 * @pidx: the port index
6247 *
6248 * Returns a bitmap indicating which TP Ingress Channels are associated
6249 * with a given Port. Bit i is set if TP Ingress Channel i is used by
6250 * the Port.
6251 */
6253 {
6261 }
6266 /* Note that this happens to be the same values as the MPS
6267 * Buffer Group Map for these Chips. But we replicate the code
6268 * here because they're really separate concepts.
6269 */
6274 }
6281 }
6283 }
6288 }
6290 /**
6291 * t4_get_port_type_description - return Port Type string description
6292 * @port_type: firmware Port Type enumeration
6293 */
6295 {
6319 "KR_XLAUI"
6320 };
6325 }
6327 /**
6328 * t4_get_port_stats_offset - collect port stats relative to a previous
6329 * snapshot
6330 * @adap: The adapter
6331 * @idx: The port
6332 * @stats: Current stats to fill
6333 * @offset: Previous stats snapshot
6334 */
6338 {
6347 }
6349 /**
6350 * t4_get_port_stats - collect port statistics
6351 * @adap: the adapter
6352 * @idx: the port index
6353 * @p: the stats structure to fill
6354 *
6355 * Collect statistics related to the given port from HW.
6356 */
6358 {
6362 #define GET_STAT(name) \
6363 t4_read_reg64(adap, \
6364 (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \
6365 T5_PORT_REG(idx, MPS_PORT_STAT_##name##_L)))
6366 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
6397 }
6431 }
6442 #undef GET_STAT
6443 #undef GET_STAT_COM
6444 }
6446 /**
6447 * t4_get_lb_stats - collect loopback port statistics
6448 * @adap: the adapter
6449 * @idx: the loopback port index
6450 * @p: the stats structure to fill
6451 *
6452 * Return HW statistics for the given loopback port.
6453 */
6455 {
6458 #define GET_STAT(name) \
6459 t4_read_reg64(adap, \
6460 (is_t4(adap->params.chip) ? \
6461 PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L) : \
6462 T5_PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L)))
6463 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
6490 #undef GET_STAT
6491 #undef GET_STAT_COM
6492 }
6494 /* t4_mk_filtdelwr - create a delete filter WR
6495 * @ftid: the filter ID
6496 * @wr: the filter work request to populate
6497 * @qid: ingress queue to receive the delete notification
6498 *
6499 * Creates a filter work request to delete the supplied filter. If @qid is
6500 * negative the delete notification is suppressed.
6501 */
6503 {
6513 }
6515 #define INIT_CMD(var, cmd, rd_wr) do { \
6516 (var).op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_##cmd##_CMD) | \
6517 FW_CMD_REQUEST_F | \
6518 FW_CMD_##rd_wr##_F); \
6519 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
6520 } while (0)
6524 {
6525 u32 ldst_addrspace;
6531 FW_CMD_REQUEST_F |
6532 FW_CMD_WRITE_F |
6533 ldst_addrspace);
6539 }
6541 /**
6542 * t4_mdio_rd - read a PHY register through MDIO
6543 * @adap: the adapter
6544 * @mbox: mailbox to use for the FW command
6545 * @phy_addr: the PHY address
6546 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
6547 * @reg: the register to read
6548 * @valp: where to store the value
6549 *
6550 * Issues a FW command through the given mailbox to read a PHY register.
6551 */
6554 {
6556 u32 ldst_addrspace;
6563 ldst_addrspace);
6573 }
6575 /**
6576 * t4_mdio_wr - write a PHY register through MDIO
6577 * @adap: the adapter
6578 * @mbox: mailbox to use for the FW command
6579 * @phy_addr: the PHY address
6580 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
6581 * @reg: the register to write
6582 * @valp: value to write
6583 *
6584 * Issues a FW command through the given mailbox to write a PHY register.
6585 */
6588 {
6589 u32 ldst_addrspace;
6596 ldst_addrspace);
6604 }
6606 /**
6607 * t4_sge_decode_idma_state - decode the idma state
6608 * @adap: the adapter
6609 * @state: the state idma is stuck in
6610 */
6612 {
6649 };
6684 };
6717 };
6719 SGE_DEBUG_DATA_LOW_INDEX_2_A,
6720 SGE_DEBUG_DATA_LOW_INDEX_3_A,
6721 SGE_DEBUG_DATA_HIGH_INDEX_10_A,
6722 };
6728 /* Select the right set of decode strings to dump depending on the
6729 * adapter chip type.
6730 */
6751 }
6759 }
6763 else
6769 }
6771 /**
6772 * t4_sge_ctxt_flush - flush the SGE context cache
6773 * @adap: the adapter
6774 * @mbox: mailbox to use for the FW command
6775 * @ctx_type: Egress or Ingress
6776 *
6777 * Issues a FW command through the given mailbox to flush the
6778 * SGE context cache.
6779 */
6781 {
6783 u32 ldst_addrspace;
6788 FW_LDST_ADDRSPC_SGE_EGRC :
6789 FW_LDST_ADDRSPC_SGE_INGC);
6792 ldst_addrspace);
6798 }
6800 /**
6801 * t4_read_sge_dbqtimers - read SGE Doorbell Queue Timer values
6802 * @adap - the adapter
6803 * @ndbqtimers: size of the provided SGE Doorbell Queue Timer table
6804 * @dbqtimers: SGE Doorbell Queue Timer table
6805 *
6806 * Reads the SGE Doorbell Queue Timer values into the provided table.
6807 * Returns 0 on success (Firmware and Hardware support this feature),
6808 * an error on failure.
6809 */
6812 {
6837 }
6839 }
6841 /**
6842 * t4_fw_hello - establish communication with FW
6843 * @adap: the adapter
6844 * @mbox: mailbox to use for the FW command
6845 * @evt_mbox: mailbox to receive async FW events
6846 * @master: specifies the caller's willingness to be the device master
6847 * @state: returns the current device state (if non-NULL)
6848 *
6849 * Issues a command to establish communication with FW. Returns either
6850 * an error (negative integer) or the mailbox of the Master PF.
6851 */
6854 {
6857 u32 v;
6861 retry:
6871 FW_HELLO_CMD_CLEARINIT_F);
6873 /*
6874 * Issue the HELLO command to the firmware. If it's not successful
6875 * but indicates that we got a "busy" or "timeout" condition, retry
6876 * the HELLO until we exhaust our retry limit. If we do exceed our
6877 * retry limit, check to see if the firmware left us any error
6878 * information and report that if so.
6879 */
6887 }
6896 else
6898 }
6900 /*
6901 * If we're not the Master PF then we need to wait around for the
6902 * Master PF Driver to finish setting up the adapter.
6903 *
6904 * Note that we also do this wait if we're a non-Master-capable PF and
6905 * there is no current Master PF; a Master PF may show up momentarily
6906 * and we wouldn't want to fail pointlessly. (This can happen when an
6907 * OS loads lots of different drivers rapidly at the same time). In
6908 * this case, the Master PF returned by the firmware will be
6909 * PCIE_FW_MASTER_M so the test below will work ...
6910 */
6915 /*
6916 * Wait for the firmware to either indicate an error or
6917 * initialized state. If we see either of these we bail out
6918 * and report the issue to the caller. If we exhaust the
6919 * "hello timeout" and we haven't exhausted our retries, try
6920 * again. Otherwise bail with a timeout error.
6921 */
6923 u32 pcie_fw;
6928 /*
6929 * If neither Error nor Initialized are indicated
6930 * by the firmware keep waiting till we exhaust our
6931 * timeout ... and then retry if we haven't exhausted
6932 * our retries ...
6933 */
6941 }
6943 }
6945 /*
6946 * We either have an Error or Initialized condition
6947 * report errors preferentially.
6948 */
6954 }
6956 /*
6957 * If we arrived before a Master PF was selected and
6958 * there's not a valid Master PF, grab its identity
6959 * for our caller.
6960 */
6965 }
6966 }
6969 }
6971 /**
6972 * t4_fw_bye - end communication with FW
6973 * @adap: the adapter
6974 * @mbox: mailbox to use for the FW command
6975 *
6976 * Issues a command to terminate communication with FW.
6977 */
6979 {
6985 }
6987 /**
6988 * t4_init_cmd - ask FW to initialize the device
6989 * @adap: the adapter
6990 * @mbox: mailbox to use for the FW command
6991 *
6992 * Issues a command to FW to partially initialize the device. This
6993 * performs initialization that generally doesn't depend on user input.
6994 */
6996 {
7002 }
7004 /**
7005 * t4_fw_reset - issue a reset to FW
7006 * @adap: the adapter
7007 * @mbox: mailbox to use for the FW command
7008 * @reset: specifies the type of reset to perform
7009 *
7010 * Issues a reset command of the specified type to FW.
7011 */
7013 {
7020 }
7022 /**
7023 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
7024 * @adap: the adapter
7025 * @mbox: mailbox to use for the FW RESET command (if desired)
7026 * @force: force uP into RESET even if FW RESET command fails
7027 *
7028 * Issues a RESET command to firmware (if desired) with a HALT indication
7029 * and then puts the microprocessor into RESET state. The RESET command
7030 * will only be issued if a legitimate mailbox is provided (mbox <=
7031 * PCIE_FW_MASTER_M).
7032 *
7033 * This is generally used in order for the host to safely manipulate the
7034 * adapter without fear of conflicting with whatever the firmware might
7035 * be doing. The only way out of this state is to RESTART the firmware
7036 * ...
7037 */
7039 {
7042 /*
7043 * If a legitimate mailbox is provided, issue a RESET command
7044 * with a HALT indication.
7045 */
7054 }
7056 /*
7057 * Normally we won't complete the operation if the firmware RESET
7058 * command fails but if our caller insists we'll go ahead and put the
7059 * uP into RESET. This can be useful if the firmware is hung or even
7060 * missing ... We'll have to take the risk of putting the uP into
7061 * RESET without the cooperation of firmware in that case.
7062 *
7063 * We also force the firmware's HALT flag to be on in case we bypassed
7064 * the firmware RESET command above or we're dealing with old firmware
7065 * which doesn't have the HALT capability. This will serve as a flag
7066 * for the incoming firmware to know that it's coming out of a HALT
7067 * rather than a RESET ... if it's new enough to understand that ...
7068 */
7072 PCIE_FW_HALT_F);
7073 }
7075 /*
7076 * And we always return the result of the firmware RESET command
7077 * even when we force the uP into RESET ...
7078 */
7080 }
7082 /**
7083 * t4_fw_restart - restart the firmware by taking the uP out of RESET
7084 * @adap: the adapter
7085 * @reset: if we want to do a RESET to restart things
7086 *
7087 * Restart firmware previously halted by t4_fw_halt(). On successful
7088 * return the previous PF Master remains as the new PF Master and there
7089 * is no need to issue a new HELLO command, etc.
7090 *
7091 * We do this in two ways:
7092 *
7093 * 1. If we're dealing with newer firmware we'll simply want to take
7094 * the chip's microprocessor out of RESET. This will cause the
7095 * firmware to start up from its start vector. And then we'll loop
7096 * until the firmware indicates it's started again (PCIE_FW.HALT
7097 * reset to 0) or we timeout.
7098 *
7099 * 2. If we're dealing with older firmware then we'll need to RESET
7100 * the chip since older firmware won't recognize the PCIE_FW.HALT
7101 * flag and automatically RESET itself on startup.
7102 */
7104 {
7106 /*
7107 * Since we're directing the RESET instead of the firmware
7108 * doing it automatically, we need to clear the PCIE_FW.HALT
7109 * bit.
7110 */
7113 /*
7114 * If we've been given a valid mailbox, first try to get the
7115 * firmware to do the RESET. If that works, great and we can
7116 * return success. Otherwise, if we haven't been given a
7117 * valid mailbox or the RESET command failed, fall back to
7118 * hitting the chip with a hammer.
7119 */
7126 }
7139 }
7141 }
7143 }
7145 /**
7146 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW
7147 * @adap: the adapter
7148 * @mbox: mailbox to use for the FW RESET command (if desired)
7149 * @fw_data: the firmware image to write
7150 * @size: image size
7151 * @force: force upgrade even if firmware doesn't cooperate
7152 *
7153 * Perform all of the steps necessary for upgrading an adapter's
7154 * firmware image. Normally this requires the cooperation of the
7155 * existing firmware in order to halt all existing activities
7156 * but if an invalid mailbox token is passed in we skip that step
7157 * (though we'll still put the adapter microprocessor into RESET in
7158 * that case).
7159 *
7160 * On successful return the new firmware will have been loaded and
7161 * the adapter will have been fully RESET losing all previous setup
7162 * state. On unsuccessful return the adapter may be completely hosed ...
7163 * positive errno indicates that the adapter is ~probably~ intact, a
7164 * negative errno indicates that things are looking bad ...
7165 */
7168 {
7175 /* Disable CXGB4_FW_OK flag so that mbox commands with CXGB4_FW_OK flag
7176 * set wont be sent when we are flashing FW.
7177 */
7188 /*
7189 * If there was a Firmware Configuration File stored in FLASH,
7190 * there's a good chance that it won't be compatible with the new
7191 * Firmware. In order to prevent difficult to diagnose adapter
7192 * initialization issues, we clear out the Firmware Configuration File
7193 * portion of the FLASH . The user will need to re-FLASH a new
7194 * Firmware Configuration File which is compatible with the new
7195 * Firmware if that's desired.
7196 */
7199 /*
7200 * Older versions of the firmware don't understand the new
7201 * PCIE_FW.HALT flag and so won't know to perform a RESET when they
7202 * restart. So for newly loaded older firmware we'll have to do the
7203 * RESET for it so it starts up on a clean slate. We can tell if
7204 * the newly loaded firmware will handle this right by checking
7205 * its header flags to see if it advertises the capability.
7206 */
7210 /* Grab potentially new Firmware Device Log parameters so we can see
7211 * how healthy the new Firmware is. It's okay to contact the new
7212 * Firmware for these parameters even though, as far as it's
7213 * concerned, we've never said "HELLO" to it ...
7214 */
7216 out:
7219 }
7221 /**
7222 * t4_fl_pkt_align - return the fl packet alignment
7223 * @adap: the adapter
7224 *
7225 * T4 has a single field to specify the packing and padding boundary.
7226 * T5 onwards has separate fields for this and hence the alignment for
7227 * next packet offset is maximum of these two.
7228 *
7229 */
7231 {
7237 /* T4 uses a single control field to specify both the PCIe Padding and
7238 * Packing Boundary. T5 introduced the ability to specify these
7239 * separately. The actual Ingress Packet Data alignment boundary
7240 * within Packed Buffer Mode is the maximum of these two
7241 * specifications. (Note that it makes no real practical sense to
7242 * have the Padding Boundary be larger than the Packing Boundary but you
7243 * could set the chip up that way and, in fact, legacy T4 code would
7244 * end doing this because it would initialize the Padding Boundary and
7245 * leave the Packing Boundary initialized to 0 (16 bytes).)
7246 * Padding Boundary values in T6 starts from 8B,
7247 * where as it is 32B for T4 and T5.
7248 */
7251 else
7258 /* T5 has a weird interpretation of one of the PCIe Packing
7259 * Boundary values. No idea why ...
7260 */
7265 else
7267 INGPACKBOUNDARY_SHIFT_X);
7270 }
7272 }
7274 /**
7275 * t4_fixup_host_params - fix up host-dependent parameters
7276 * @adap: the adapter
7277 * @page_size: the host's Base Page Size
7278 * @cache_line_size: the host's Cache Line Size
7279 *
7280 * Various registers in T4 contain values which are dependent on the
7281 * host's Base Page and Cache Line Sizes. This function will fix all of
7282 * those registers with the appropriate values as passed in ...
7283 */
7286 {
7306 EGRSTATUSPAGESIZE_F,
7308 INGPADBOUNDARY_SHIFT_X) |
7314 /* T5 introduced the separation of the Free List Padding and
7315 * Packing Boundaries. Thus, we can select a smaller Padding
7316 * Boundary to avoid uselessly chewing up PCIe Link and Memory
7317 * Bandwidth, and use a Packing Boundary which is large enough
7318 * to avoid false sharing between CPUs, etc.
7319 *
7320 * For the PCI Link, the smaller the Padding Boundary the
7321 * better. For the Memory Controller, a smaller Padding
7322 * Boundary is better until we cross under the Memory Line
7323 * Size (the minimum unit of transfer to/from Memory). If we
7324 * have a Padding Boundary which is smaller than the Memory
7325 * Line Size, that'll involve a Read-Modify-Write cycle on the
7326 * Memory Controller which is never good.
7327 */
7329 /* We want the Packing Boundary to be based on the Cache Line
7330 * Size in order to help avoid False Sharing performance
7331 * issues between CPUs, etc. We also want the Packing
7332 * Boundary to incorporate the PCI-E Maximum Payload Size. We
7333 * get best performance when the Packing Boundary is a
7334 * multiple of the Maximum Payload Size.
7335 */
7339 u16 devctl;
7341 /* The PCIe Device Control Maximum Payload Size field
7342 * [bits 7:5] encodes sizes as powers of 2 starting at
7343 * 128 bytes.
7344 */
7351 }
7353 /* N.B. T5/T6 have a crazy special interpretation of the "0"
7354 * value for the Packing Boundary. This corresponds to 16
7355 * bytes instead of the expected 32 bytes. So if we want 32
7356 * bytes, the best we can really do is 64 bytes ...
7357 */
7369 }
7371 /* Use the smallest Ingress Padding which isn't smaller than
7372 * the Memory Controller Read/Write Size. We'll take that as
7373 * being 8 bytes since we don't know of any system with a
7374 * wider Memory Controller Bus Width.
7375 */
7378 else
7383 EGRSTATUSPAGESIZE_F,
7389 }
7390 /*
7391 * Adjust various SGE Free List Host Buffer Sizes.
7392 *
7393 * This is something of a crock since we're using fixed indices into
7394 * the array which are also known by the sge.c code and the T4
7395 * Firmware Configuration File. We need to come up with a much better
7396 * approach to managing this array. For now, the first four entries
7397 * are:
7398 *
7399 * 0: Host Page Size
7400 * 1: 64KB
7401 * 2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
7402 * 3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
7403 *
7404 * For the single-MTU buffers in unpacked mode we need to include
7405 * space for the SGE Control Packet Shift, 14 byte Ethernet header,
7406 * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
7407 * Padding boundary. All of these are accommodated in the Factory
7408 * Default Firmware Configuration File but we need to adjust it for
7409 * this host's cache line size.
7410 */
7422 }
7424 /**
7425 * t4_fw_initialize - ask FW to initialize the device
7426 * @adap: the adapter
7427 * @mbox: mailbox to use for the FW command
7428 *
7429 * Issues a command to FW to partially initialize the device. This
7430 * performs initialization that generally doesn't depend on user input.
7431 */
7433 {
7439 }
7441 /**
7442 * t4_query_params_rw - query FW or device parameters
7443 * @adap: the adapter
7444 * @mbox: mailbox to use for the FW command
7445 * @pf: the PF
7446 * @vf: the VF
7447 * @nparams: the number of parameters
7448 * @params: the parameter names
7449 * @val: the parameter values
7450 * @rw: Write and read flag
7451 * @sleep_ok: if true, we may sleep awaiting mbox cmd completion
7452 *
7453 * Reads the value of FW or device parameters. Up to 7 parameters can be
7454 * queried at once.
7455 */
7459 {
7478 p++;
7479 }
7486 }
7491 {
7494 }
7499 {
7502 }
7504 /**
7505 * t4_set_params_timeout - sets FW or device parameters
7506 * @adap: the adapter
7507 * @mbox: mailbox to use for the FW command
7508 * @pf: the PF
7509 * @vf: the VF
7510 * @nparams: the number of parameters
7511 * @params: the parameter names
7512 * @val: the parameter values
7513 * @timeout: the timeout time
7514 *
7515 * Sets the value of FW or device parameters. Up to 7 parameters can be
7516 * specified at once.
7517 */
7522 {
7539 }
7542 }
7544 /**
7545 * t4_set_params - sets FW or device parameters
7546 * @adap: the adapter
7547 * @mbox: mailbox to use for the FW command
7548 * @pf: the PF
7549 * @vf: the VF
7550 * @nparams: the number of parameters
7551 * @params: the parameter names
7552 * @val: the parameter values
7553 *
7554 * Sets the value of FW or device parameters. Up to 7 parameters can be
7555 * specified at once.
7556 */
7560 {
7562 FW_CMD_MAX_TIMEOUT);
7563 }
7565 /**
7566 * t4_cfg_pfvf - configure PF/VF resource limits
7567 * @adap: the adapter
7568 * @mbox: mailbox to use for the FW command
7569 * @pf: the PF being configured
7570 * @vf: the VF being configured
7571 * @txq: the max number of egress queues
7572 * @txq_eth_ctrl: the max number of egress Ethernet or control queues
7573 * @rxqi: the max number of interrupt-capable ingress queues
7574 * @rxq: the max number of interruptless ingress queues
7575 * @tc: the PCI traffic class
7576 * @vi: the max number of virtual interfaces
7577 * @cmask: the channel access rights mask for the PF/VF
7578 * @pmask: the port access rights mask for the PF/VF
7579 * @nexact: the maximum number of exact MPS filters
7580 * @rcaps: read capabilities
7581 * @wxcaps: write/execute capabilities
7582 *
7583 * Configures resource limits and capabilities for a physical or virtual
7584 * function.
7585 */
7591 {
7611 }
7613 /**
7614 * t4_alloc_vi - allocate a virtual interface
7615 * @adap: the adapter
7616 * @mbox: mailbox to use for the FW command
7617 * @port: physical port associated with the VI
7618 * @pf: the PF owning the VI
7619 * @vf: the VF owning the VI
7620 * @nmac: number of MAC addresses needed (1 to 5)
7621 * @mac: the MAC addresses of the VI
7622 * @rss_size: size of RSS table slice associated with this VI
7623 *
7624 * Allocates a virtual interface for the given physical port. If @mac is
7625 * not %NULL it contains the MAC addresses of the VI as assigned by FW.
7626 * @mac should be large enough to hold @nmac Ethernet addresses, they are
7627 * stored consecutively so the space needed is @nmac * 6 bytes.
7628 * Returns a negative error number or the non-negative VI id.
7629 */
7633 {
7654 /* Fall through */
7657 /* Fall through */
7660 /* Fall through */
7663 }
7664 }
7675 }
7677 /**
7678 * t4_free_vi - free a virtual interface
7679 * @adap: the adapter
7680 * @mbox: mailbox to use for the FW command
7681 * @pf: the PF owning the VI
7682 * @vf: the VF owning the VI
7683 * @viid: virtual interface identifiler
7684 *
7685 * Free a previously allocated virtual interface.
7686 */
7689 {
7694 FW_CMD_REQUEST_F |
7695 FW_CMD_EXEC_F |
7702 }
7704 /**
7705 * t4_set_rxmode - set Rx properties of a virtual interface
7706 * @adap: the adapter
7707 * @mbox: mailbox to use for the FW command
7708 * @viid: the VI id
7709 * @mtu: the new MTU or -1
7710 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
7711 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
7712 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
7713 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
7714 * @sleep_ok: if true we may sleep while awaiting command completion
7715 *
7716 * Sets Rx properties of a virtual interface.
7717 */
7721 {
7724 /* convert to FW values */
7748 }
7750 /**
7751 * t4_free_encap_mac_filt - frees MPS entry at given index
7752 * @adap: the adapter
7753 * @viid: the VI id
7754 * @idx: index of MPS entry to be freed
7755 * @sleep_ok: call is allowed to sleep
7756 *
7757 * Frees the MPS entry at supplied index
7758 *
7759 * Returns a negative error number or zero on success
7760 */
7763 {
7768 u32 exact;
7777 exact |
7785 }
7787 /**
7788 * t4_free_raw_mac_filt - Frees a raw mac entry in mps tcam
7789 * @adap: the adapter
7790 * @viid: the VI id
7791 * @addr: the MAC address
7792 * @mask: the mask
7793 * @idx: index of the entry in mps tcam
7794 * @lookup_type: MAC address for inner (1) or outer (0) header
7795 * @port_id: the port index
7796 * @sleep_ok: call is allowed to sleep
7797 *
7798 * Removes the mac entry at the specified index using raw mac interface.
7799 *
7800 * Returns a negative error number on failure.
7801 */
7805 {
7808 u32 val;
7821 FW_VI_MAC_ID_BASED_FREE);
7823 /* Lookup Type. Outer header: 0, Inner header: 1 */
7826 /* Lookup mask and port mask */
7830 /* Copy the address and the mask */
7835 }
7837 /**
7838 * t4_alloc_encap_mac_filt - Adds a mac entry in mps tcam with VNI support
7839 * @adap: the adapter
7840 * @viid: the VI id
7841 * @mac: the MAC address
7842 * @mask: the mask
7843 * @vni: the VNI id for the tunnel protocol
7844 * @vni_mask: mask for the VNI id
7845 * @dip_hit: to enable DIP match for the MPS entry
7846 * @lookup_type: MAC address for inner (1) or outer (0) header
7847 * @sleep_ok: call is allowed to sleep
7848 *
7849 * Allocates an MPS entry with specified MAC address and VNI value.
7850 *
7851 * Returns a negative error number or the allocated index for this mac.
7852 */
7857 {
7861 u32 val;
7884 }
7886 /**
7887 * t4_alloc_raw_mac_filt - Adds a mac entry in mps tcam
7888 * @adap: the adapter
7889 * @viid: the VI id
7890 * @mac: the MAC address
7891 * @mask: the mask
7892 * @idx: index at which to add this entry
7893 * @port_id: the port index
7894 * @lookup_type: MAC address for inner (1) or outer (0) header
7895 * @sleep_ok: call is allowed to sleep
7896 *
7897 * Adds the mac entry at the specified index using raw mac interface.
7898 *
7899 * Returns a negative error number or the allocated index for this mac.
7900 */
7904 {
7908 u32 val;
7918 /* Specify that this is an inner mac address */
7921 /* Lookup Type. Outer header: 0, Inner header: 1 */
7924 /* Lookup mask and port mask */
7928 /* Copy the address and the mask */
7937 }
7940 }
7942 /**
7943 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
7944 * @adap: the adapter
7945 * @mbox: mailbox to use for the FW command
7946 * @viid: the VI id
7947 * @free: if true any existing filters for this VI id are first removed
7948 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
7949 * @addr: the MAC address(es)
7950 * @idx: where to store the index of each allocated filter
7951 * @hash: pointer to hash address filter bitmap
7952 * @sleep_ok: call is allowed to sleep
7953 *
7954 * Allocates an exact-match filter for each of the supplied addresses and
7955 * sets it to the corresponding address. If @idx is not %NULL it should
7956 * have at least @naddr entries, each of which will be set to the index of
7957 * the filter allocated for the corresponding MAC address. If a filter
7958 * could not be allocated for an address its index is set to 0xffff.
7959 * If @hash is not %NULL addresses that fail to allocate an exact filter
7960 * are hashed and update the hash filter bitmap pointed at by @hash.
7961 *
7962 * Returns a negative error number or the number of filters allocated.
7963 */
7967 {
7987 FW_CMD_REQUEST_F |
7988 FW_CMD_WRITE_F |
7999 FW_VI_MAC_ADD_MAC));
8002 }
8004 /* It's okay if we run out of space in our MAC address arena.
8005 * Some of the addresses we submit may get stored so we need
8006 * to run through the reply to see what the results were ...
8007 */
8020 nfilters++;
8024 }
8029 }
8034 }
8036 /**
8037 * t4_free_mac_filt - frees exact-match filters of given MAC addresses
8038 * @adap: the adapter
8039 * @mbox: mailbox to use for the FW command
8040 * @viid: the VI id
8041 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
8042 * @addr: the MAC address(es)
8043 * @sleep_ok: call is allowed to sleep
8044 *
8045 * Frees the exact-match filter for each of the supplied addresses
8046 *
8047 * Returns a negative error number or the number of filters freed.
8048 */
8052 {
8057 NUM_MPS_CLS_SRAM_L_INSTANCES :
8058 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
8066 ? rem
8075 FW_CMD_REQUEST_F |
8076 FW_CMD_WRITE_F |
8085 FW_VI_MAC_CMD_VALID_F |
8088 }
8099 nfilters++;
8100 }
8104 }
8109 }
8111 /**
8112 * t4_change_mac - modifies the exact-match filter for a MAC address
8113 * @adap: the adapter
8114 * @mbox: mailbox to use for the FW command
8115 * @viid: the VI id
8116 * @idx: index of existing filter for old value of MAC address, or -1
8117 * @addr: the new MAC address value
8118 * @persist: whether a new MAC allocation should be persistent
8119 * @add_smt: if true also add the address to the HW SMT
8120 *
8121 * Modifies an exact-match filter and sets it to the new MAC address.
8122 * Note that in general it is not possible to modify the value of a given
8123 * filter so the generic way to modify an address filter is to free the one
8124 * being used by the old address value and allocate a new filter for the
8125 * new address value. @idx can be -1 if the address is a new addition.
8126 *
8127 * Returns a negative error number or the index of the filter with the new
8128 * MAC value.
8129 */
8132 {
8162 /* In T4/T5, SMT contains 256 SMAC entries
8163 * organized in 128 rows of 2 entries each.
8164 * In T6, SMT contains 256 SMAC entries in
8165 * 256 rows.
8166 */
8168 CHELSIO_T5)
8170 else
8172 }
8173 }
8174 }
8176 }
8178 /**
8179 * t4_set_addr_hash - program the MAC inexact-match hash filter
8180 * @adap: the adapter
8181 * @mbox: mailbox to use for the FW command
8182 * @viid: the VI id
8183 * @ucast: whether the hash filter should also match unicast addresses
8184 * @vec: the value to be written to the hash filter
8185 * @sleep_ok: call is allowed to sleep
8186 *
8187 * Sets the 64-bit inexact-match hash filter for a virtual interface.
8188 */
8191 {
8203 }
8205 /**
8206 * t4_enable_vi_params - enable/disable a virtual interface
8207 * @adap: the adapter
8208 * @mbox: mailbox to use for the FW command
8209 * @viid: the VI id
8210 * @rx_en: 1=enable Rx, 0=disable Rx
8211 * @tx_en: 1=enable Tx, 0=disable Tx
8212 * @dcb_en: 1=enable delivery of Data Center Bridging messages.
8213 *
8214 * Enables/disables a virtual interface. Note that setting DCB Enable
8215 * only makes sense when enabling a Virtual Interface ...
8216 */
8219 {
8231 }
8233 /**
8234 * t4_enable_vi - enable/disable a virtual interface
8235 * @adap: the adapter
8236 * @mbox: mailbox to use for the FW command
8237 * @viid: the VI id
8238 * @rx_en: 1=enable Rx, 0=disable Rx
8239 * @tx_en: 1=enable Tx, 0=disable Tx
8240 *
8241 * Enables/disables a virtual interface.
8242 */
8245 {
8247 }
8249 /**
8250 * t4_enable_pi_params - enable/disable a Port's Virtual Interface
8251 * @adap: the adapter
8252 * @mbox: mailbox to use for the FW command
8253 * @pi: the Port Information structure
8254 * @rx_en: 1=enable Rx, 0=disable Rx
8255 * @tx_en: 1=enable Tx, 0=disable Tx
8256 * @dcb_en: 1=enable delivery of Data Center Bridging messages.
8257 *
8258 * Enables/disables a Port's Virtual Interface. Note that setting DCB
8259 * Enable only makes sense when enabling a Virtual Interface ...
8260 * If the Virtual Interface enable/disable operation is successful,
8261 * we notify the OS-specific code of a potential Link Status change
8262 * via the OS Contract API t4_os_link_changed().
8263 */
8267 {
8275 }
8277 /**
8278 * t4_identify_port - identify a VI's port by blinking its LED
8279 * @adap: the adapter
8280 * @mbox: mailbox to use for the FW command
8281 * @viid: the VI id
8282 * @nblinks: how many times to blink LED at 2.5 Hz
8283 *
8284 * Identifies a VI's port by blinking its LED.
8285 */
8288 {
8298 }
8300 /**
8301 * t4_iq_stop - stop an ingress queue and its FLs
8302 * @adap: the adapter
8303 * @mbox: mailbox to use for the FW command
8304 * @pf: the PF owning the queues
8305 * @vf: the VF owning the queues
8306 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
8307 * @iqid: ingress queue id
8308 * @fl0id: FL0 queue id or 0xffff if no attached FL0
8309 * @fl1id: FL1 queue id or 0xffff if no attached FL1
8310 *
8311 * Stops an ingress queue and its associated FLs, if any. This causes
8312 * any current or future data/messages destined for these queues to be
8313 * tossed.
8314 */
8318 {
8331 }
8333 /**
8334 * t4_iq_free - free an ingress queue and its FLs
8335 * @adap: the adapter
8336 * @mbox: mailbox to use for the FW command
8337 * @pf: the PF owning the queues
8338 * @vf: the VF owning the queues
8339 * @iqtype: the ingress queue type
8340 * @iqid: ingress queue id
8341 * @fl0id: FL0 queue id or 0xffff if no attached FL0
8342 * @fl1id: FL1 queue id or 0xffff if no attached FL1
8343 *
8344 * Frees an ingress queue and its associated FLs, if any.
8345 */
8349 {
8362 }
8364 /**
8365 * t4_eth_eq_free - free an Ethernet egress queue
8366 * @adap: the adapter
8367 * @mbox: mailbox to use for the FW command
8368 * @pf: the PF owning the queue
8369 * @vf: the VF owning the queue
8370 * @eqid: egress queue id
8371 *
8372 * Frees an Ethernet egress queue.
8373 */
8376 {
8387 }
8389 /**
8390 * t4_ctrl_eq_free - free a control egress queue
8391 * @adap: the adapter
8392 * @mbox: mailbox to use for the FW command
8393 * @pf: the PF owning the queue
8394 * @vf: the VF owning the queue
8395 * @eqid: egress queue id
8396 *
8397 * Frees a control egress queue.
8398 */
8401 {
8412 }
8414 /**
8415 * t4_ofld_eq_free - free an offload egress queue
8416 * @adap: the adapter
8417 * @mbox: mailbox to use for the FW command
8418 * @pf: the PF owning the queue
8419 * @vf: the VF owning the queue
8420 * @eqid: egress queue id
8421 *
8422 * Frees a control egress queue.
8423 */
8426 {
8437 }
8439 /**
8440 * t4_link_down_rc_str - return a string for a Link Down Reason Code
8441 * @adap: the adapter
8442 * @link_down_rc: Link Down Reason Code
8443 *
8444 * Returns a string representation of the Link Down Reason Code.
8445 */
8447 {
8457 };
8463 }
8465 /**
8466 * Return the highest speed set in the port capabilities, in Mb/s.
8467 */
8469 {
8470 #define TEST_SPEED_RETURN(__caps_speed, __speed) \
8471 do { \
8472 if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \
8473 return __speed; \
8474 } while (0)
8486 #undef TEST_SPEED_RETURN
8489 }
8491 /**
8492 * fwcap_to_fwspeed - return highest speed in Port Capabilities
8493 * @acaps: advertised Port Capabilities
8494 *
8495 * Get the highest speed for the port from the advertised Port
8496 * Capabilities. It will be either the highest speed from the list of
8497 * speeds or whatever user has set using ethtool.
8498 */
8500 {
8501 #define TEST_SPEED_RETURN(__caps_speed) \
8502 do { \
8503 if (acaps & FW_PORT_CAP32_SPEED_##__caps_speed) \
8504 return FW_PORT_CAP32_SPEED_##__caps_speed; \
8505 } while (0)
8517 #undef TEST_SPEED_RETURN
8520 }
8522 /**
8523 * lstatus_to_fwcap - translate old lstatus to 32-bit Port Capabilities
8524 * @lstatus: old FW_PORT_ACTION_GET_PORT_INFO lstatus value
8525 *
8526 * Translates old FW_PORT_ACTION_GET_PORT_INFO lstatus field into new
8527 * 32-bit Port Capabilities value.
8528 */
8530 {
8533 /* Unfortunately the format of the Link Status in the old
8534 * 16-bit Port Information message isn't the same as the
8535 * 16-bit Port Capabilities bitfield used everywhere else ...
8536 */
8555 }
8557 /**
8558 * t4_handle_get_port_info - process a FW reply message
8559 * @pi: the port info
8560 * @rpl: start of the FW message
8561 *
8562 * Processes a GET_PORT_INFO FW reply message.
8563 */
8565 {
8575 /* Extract the various fields from the Port Information message.
8576 */
8591 }
8594 u32 lstatus32;
8606 }
8612 }
8619 /* Reset state for communicating new Transceiver Module status and
8620 * whether the OS-dependent layer wants us to redo the current
8621 * "sticky" L1 Configure Link Parameters.
8622 */
8627 /* With the newer SFP28 and QSFP28 Transceiver Module Types,
8628 * various fundamental Port Capabilities which used to be
8629 * immutable can now change radically. We can now have
8630 * Speeds, Auto-Negotiation, Forward Error Correction, etc.
8631 * all change based on what Transceiver Module is inserted.
8632 * So we need to record the Physical "Port" Capabilities on
8633 * every Transceiver Module change.
8634 */
8637 /* When a new Transceiver Module is inserted, the Firmware
8638 * will examine its i2c EPROM to determine its type and
8639 * general operating parameters including things like Forward
8640 * Error Control, etc. Various IEEE 802.3 standards dictate
8641 * how to interpret these i2c values to determine default
8642 * "sutomatic" settings. We record these for future use when
8643 * the user explicitly requests these standards-based values.
8644 */
8647 /* Some versions of the early T6 Firmware "cheated" when
8648 * handling different Transceiver Modules by changing the
8649 * underlaying Port Type reported to the Host Drivers. As
8650 * such we need to capture whatever Port Type the Firmware
8651 * sends us and record it in case it's different from what we
8652 * were told earlier. Unfortunately, since Firmware is
8653 * forever, we'll need to keep this code here forever, but in
8654 * later T6 Firmware it should just be an assignment of the
8655 * same value already recorded.
8656 */
8659 /* Record new Module Type information.
8660 */
8663 /* Let the OS-dependent layer know if we have a new
8664 * Transceiver Module inserted.
8665 */
8669 }
8674 /* something changed */
8681 }
8691 /* If we're not physically capable of Auto-Negotiation, note
8692 * this as Auto-Negotiation disabled. Otherwise, we track
8693 * what Auto-Negotiation settings we have. Note parallel
8694 * structure in t4_link_l1cfg_core() and init_link_config().
8695 */
8701 /* When Autoneg is disabled, user needs to set
8702 * single speed.
8703 * Similar to cxgb4_ethtool.c: set_link_ksettings
8704 */
8708 }
8711 }
8713 /* If we have a new Transceiver Module and the OS-dependent code has
8714 * told us that it wants us to redo whatever "sticky" L1 Configuration
8715 * Link Parameters are set, do that now.
8716 */
8721 /* Save the current L1 Configuration and restore it if an
8722 * error occurs. We probably should fix the l1_cfg*()
8723 * routines not to change the link_config when an error
8724 * occurs ...
8725 */
8732 }
8733 }
8736 }
8738 /**
8739 * t4_update_port_info - retrieve and update port information if changed
8740 * @pi: the port_info
8741 *
8742 * We issue a Get Port Information Command to the Firmware and, if
8743 * successful, we check to see if anything is different from what we
8744 * last recorded and update things accordingly.
8745 */
8747 {
8758 ? FW_PORT_ACTION_GET_PORT_INFO
8768 }
8770 /**
8771 * t4_get_link_params - retrieve basic link parameters for given port
8772 * @pi: the port
8773 * @link_okp: value return pointer for link up/down
8774 * @speedp: value return pointer for speed (Mb/s)
8775 * @mtup: value return pointer for mtu
8776 *
8777 * Retrieves basic link parameters for a port: link up/down, speed (Mb/s),
8778 * and MTU for a specified port. A negative error is returned on
8779 * failure; 0 on success.
8780 */
8783 {
8787 fw_port_cap32_t linkattr;
8795 ? FW_PORT_ACTION_GET_PORT_INFO
8812 u32 lstatus32 =
8819 }
8829 }
8831 /**
8832 * t4_handle_fw_rpl - process a FW reply message
8833 * @adap: the adapter
8834 * @rpl: start of the FW message
8835 *
8836 * Processes a FW message, such as link state change messages.
8837 */
8839 {
8842 /* This might be a port command ... this simplifies the following
8843 * conditionals ... We can get away with pre-dereferencing
8844 * action_to_len16 because it's in the first 16 bytes and all messages
8845 * will be at least that long.
8846 */
8862 }
8867 opcode);
8869 }
8871 }
8874 {
8875 u16 val;
8881 }
8882 }
8884 /**
8885 * init_link_config - initialize a link's SW state
8886 * @lc: pointer to structure holding the link state
8887 * @pcaps: link Port Capabilities
8888 * @acaps: link current Advertised Port Capabilities
8889 *
8890 * Initializes the SW state maintained for each link, including the link's
8891 * capabilities and default speed/flow-control/autonegotiation settings.
8892 */
8894 fw_port_cap32_t acaps)
8895 {
8903 /* For Forward Error Control, we default to whatever the Firmware
8904 * tells us the Link is currently advertising.
8905 */
8909 /* If the Port is capable of Auto-Negtotiation, initialize it as
8910 * "enabled" and copy over all of the Physical Port Capabilities
8911 * to the Advertised Port Capabilities. Otherwise mark it as
8912 * Auto-Negotiate disabled and select the highest supported speed
8913 * for the link. Note parallel structure in t4_link_l1cfg_core()
8914 * and t4_handle_get_port_info().
8915 */
8924 }
8925 }
8927 #define CIM_PF_NOACCESS 0xeeeeeeee
8930 {
8931 u32 whoami;
8940 }
8943 u32 vendor_and_model_id;
8944 u32 size_mb;
8945 };
8948 {
8949 /* Table for non-Numonix supported flash parts. Numonix parts are left
8950 * to the preexisting code. All flash parts have 64KB sectors.
8951 */
8954 };
8961 /* Issue a Read ID Command to the Flash part. We decode supported
8962 * Flash parts and their sizes from this. There's a newer Query
8963 * Command which can retrieve detailed geometry information but many
8964 * Flash parts don't support it.
8965 */
8974 /* Check to see if it's one of our non-standard supported Flash parts.
8975 */
8982 }
8984 /* Decode Flash part size. The code below looks repetitive with
8985 * common encodings, but that's not guaranteed in the JEDEC
8986 * specification for the Read JEDEC ID command. The only thing that
8987 * we're guaranteed by the JEDEC specification is where the
8988 * Manufacturer ID is in the returned result. After that each
8989 * Manufacturer ~could~ encode things completely differently.
8990 * Note, all Flash parts must have 64KB sectors.
8991 */
8995 /* This Density -> Size decoding table is taken from Micron
8996 * Data Sheets.
8997 */
9027 }
9029 }
9031 /* This Density -> Size decoding table is taken from ISSI
9032 * Data Sheets.
9033 */
9042 }
9044 }
9046 /* This Density -> Size decoding table is taken from Macronix
9047 * Data Sheets.
9048 */
9057 }
9059 }
9061 /* This Density -> Size decoding table is taken from Winbond
9062 * Data Sheets.
9063 */
9072 }
9074 }
9075 }
9077 /* If we didn't recognize the FLASH part, that's no real issue: the
9078 * Hardware/Software contract says that Hardware will _*ALWAYS*_
9079 * use a FLASH part which is at least 4MB in size and has 64KB
9080 * sectors. The unrecognized FLASH part is likely to be much larger
9081 * than 4MB, but that's all we really need.
9082 */
9085 flashid);
9087 }
9089 /* Store decoded Flash size and fall through into vetting code. */
9093 found:
9098 }
9100 /**
9101 * t4_prep_adapter - prepare SW and HW for operation
9102 * @adapter: the adapter
9103 * @reset: if true perform a HW reset
9104 *
9105 * Initialize adapter SW state for the various HW modules, set initial
9106 * values for some adapter tunables, take PHYs out of reset, and
9107 * initialize the MDIO interface.
9108 */
9110 {
9113 u32 pl_rev;
9122 }
9124 /* Retrieve adapter's device ID
9125 */
9134 NUM_MPS_CLS_SRAM_L_INSTANCES;
9139 /* Congestion map is for 4 channels so that
9140 * MPS can have 4 priority per port.
9141 */
9148 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
9159 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
9164 /* Congestion map will be for 2 channels so that
9165 * MPS can have 8 priority per port.
9166 */
9171 device_id);
9173 }
9178 /*
9179 * Default port for debugging in case we can't reach FW.
9180 */
9185 /* Set PCIe completion timeout to 4 seconds. */
9189 }
9191 /**
9192 * t4_shutdown_adapter - shut down adapter, host & wire
9193 * @adapter: the adapter
9194 *
9195 * Perform an emergency shutdown of the adapter and stop it from
9196 * continuing any further communication on the ports or DMA to the
9197 * host. This is typically used when the adapter and/or firmware
9198 * have crashed and we want to prevent any further accidental
9199 * communication with the rest of the world. This will also force
9200 * the port Link Status to go down -- if register writes work --
9201 * which should help our peers figure out that we're down.
9202 */
9204 {
9217 }
9221 }
9223 /**
9224 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information
9225 * @adapter: the adapter
9226 * @qid: the Queue ID
9227 * @qtype: the Ingress or Egress type for @qid
9228 * @user: true if this request is for a user mode queue
9229 * @pbar2_qoffset: BAR2 Queue Offset
9230 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
9231 *
9232 * Returns the BAR2 SGE Queue Registers information associated with the
9233 * indicated Absolute Queue ID. These are passed back in return value
9234 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
9235 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
9236 *
9237 * This may return an error which indicates that BAR2 SGE Queue
9238 * registers aren't available. If an error is not returned, then the
9239 * following values are returned:
9240 *
9241 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
9242 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
9243 *
9244 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
9245 * require the "Inferred Queue ID" ability may be used. E.g. the
9246 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
9247 * then these "Inferred Queue ID" register may not be used.
9248 */
9255 {
9260 /* T4 doesn't support BAR2 SGE Queue registers for kernel mode queues */
9264 /* Get our SGE Page Size parameters.
9265 */
9269 /* Get the right Queues per Page parameters for our Queue.
9270 */
9276 /* Calculate the basics of the BAR2 SGE Queue register area:
9277 * o The BAR2 page the Queue registers will be in.
9278 * o The BAR2 Queue ID.
9279 * o The BAR2 Queue ID Offset into the BAR2 page.
9280 */
9285 /* If the BAR2 Queue ID Offset is less than the Page Size, then the
9286 * hardware will infer the Absolute Queue ID simply from the writes to
9287 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
9288 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply
9289 * write to the first BAR2 SGE Queue Area within the BAR2 Page with
9290 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
9291 * from the BAR2 Page and BAR2 Queue ID.
9292 *
9293 * One important censequence of this is that some BAR2 SGE registers
9294 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
9295 * there. But other registers synthesize the SGE Queue ID purely
9296 * from the writes to the registers -- the Write Combined Doorbell
9297 * Buffer is a good example. These BAR2 SGE Registers are only
9298 * available for those BAR2 SGE Register areas where the SGE Absolute
9299 * Queue ID can be inferred from simple writes.
9300 */
9306 }
9311 }
9313 /**
9314 * t4_init_devlog_params - initialize adapter->params.devlog
9315 * @adap: the adapter
9316 *
9317 * Initialize various fields of the adapter's Firmware Device Log
9318 * Parameters structure.
9319 */
9321 {
9323 u32 pf_dparams;
9328 /* If we're dealing with newer firmware, the Device Log Parameters
9329 * are stored in a designated register which allows us to access the
9330 * Device Log even if we can't talk to the firmware.
9331 */
9332 pf_dparams =
9345 }
9347 /* Otherwise, ask the firmware for it's Device Log Parameters.
9348 */
9358 devlog_meminfo =
9365 }
9367 /**
9368 * t4_init_sge_params - initialize adap->params.sge
9369 * @adapter: the adapter
9370 *
9371 * Initialize various fields of the adapter's SGE Parameters structure.
9372 */
9374 {
9379 /* Extract the SGE Page Size for our PF.
9380 */
9386 /* Extract the SGE Egress and Ingess Queues Per Page for our PF.
9387 */
9396 }
9398 /**
9399 * t4_init_tp_params - initialize adap->params.tp
9400 * @adap: the adapter
9401 * @sleep_ok: if true we may sleep while awaiting command completion
9402 *
9403 * Initialize various fields of the adapter's TP Parameters structure.
9404 */
9406 {
9415 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
9419 /* Cache the adapter's Compressed Filter Mode/Mask and global Ingress
9420 * Configuration.
9421 */
9426 /* Read current value */
9442 /* Incase of older-fw (which doesn't expose the api
9443 * FW_PARAM_DEV_FILTER_MODE_MASK) and newer-driver (which uses
9444 * the fw api) combination, fall-back to older method of reading
9445 * the filter mode from indirect-register
9446 */
9450 /* With the older-fw and newer-driver combination we might run
9451 * into an issue when user wants to use hash filter region but
9452 * the filter_mask is zero, in this case filter_mask validation
9453 * is tough. To avoid that we set the filter_mask same as filter
9454 * mode, which will behave exactly as the older way of ignoring
9455 * the filter mask validation.
9456 */
9458 }
9463 /* For T6, cache the adapter's compressed error vector
9464 * and passing outer header info for encapsulated packets.
9465 */
9469 }
9471 /* Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
9472 * shift positions of several elements of the Compressed Filter Tuple
9473 * for this adapter which we need frequently ...
9474 */
9481 PROTOCOL_F);
9483 ETHERTYPE_F);
9485 MACMATCH_F);
9487 MPSHITTYPE_F);
9489 FRAGMENTATION_F);
9491 /* If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
9492 * represents the presence of an Outer VLAN instead of a VNIC ID.
9493 */
9502 }
9504 /**
9505 * t4_filter_field_shift - calculate filter field shift
9506 * @adap: the adapter
9507 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
9508 *
9509 * Return the shift position of a filter field within the Compressed
9510 * Filter Tuple. The filter field is specified via its selection bit
9511 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN.
9512 */
9514 {
9554 }
9555 }
9557 }
9560 {
9578 }
9580 }
9582 /**
9583 * t4_init_portinfo - allocate a virtual interface and initialize port_info
9584 * @pi: the port_info
9585 * @mbox: mailbox to use for the FW command
9586 * @port: physical port associated with the VI
9587 * @pf: the PF owning the VI
9588 * @vf: the VF owning the VI
9589 * @mac: the MAC address of the VI
9590 *
9591 * Allocates a virtual interface for the given physical port. If @mac is
9592 * not %NULL it contains the MAC address of the VI as assigned by FW.
9593 * @mac should be large enough to hold an Ethernet address.
9594 * Returns < 0 on error.
9595 */
9598 {
9609 /* If we haven't yet determined whether we're talking to Firmware
9610 * which knows the new 32-bit Port Capabilities, it's time to find
9611 * out now. This will also tell new Firmware to send us Port Status
9612 * Updates using the new 32-bit Port Capabilities version of the
9613 * Port Information message.
9614 */
9624 }
9632 ? FW_PORT_ACTION_GET_PORT_INFO
9639 /* Extract the various fields from the Port Information message.
9640 */
9659 }
9672 /* If fw supports returning the VIN as part of FW_VI_CMD,
9673 * save the returned values.
9674 */
9679 /* Retrieve the values from VIID */
9682 }
9690 }
9693 {
9701 j++;
9708 j++;
9709 }
9711 }
9713 /**
9714 * t4_read_cimq_cfg - read CIM queue configuration
9715 * @adap: the adapter
9716 * @base: holds the queue base addresses in bytes
9717 * @size: holds the queue sizes in bytes
9718 * @thres: holds the queue full thresholds in bytes
9719 *
9720 * Returns the current configuration of the CIM queues, starting with
9721 * the IBQs, then the OBQs.
9722 */
9724 {
9733 /* value is in 256-byte units */
9737 }
9742 /* value is in 256-byte units */
9745 }
9746 }
9748 /**
9749 * t4_read_cim_ibq - read the contents of a CIM inbound queue
9750 * @adap: the adapter
9751 * @qid: the queue index
9752 * @data: where to store the queue contents
9753 * @n: capacity of @data in 32-bit words
9754 *
9755 * Reads the contents of the selected CIM queue starting at address 0 up
9756 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
9757 * error and the number of 32-bit words actually read on success.
9758 */
9760 {
9772 /* It might take 3-10ms before the IBQ debug read access is allowed.
9773 * Wait for 1 Sec with a delay of 1 usec.
9774 */
9779 IBQDBGEN_F);
9785 }
9788 }
9790 /**
9791 * t4_read_cim_obq - read the contents of a CIM outbound queue
9792 * @adap: the adapter
9793 * @qid: the queue index
9794 * @data: where to store the queue contents
9795 * @n: capacity of @data in 32-bit words
9796 *
9797 * Reads the contents of the selected CIM queue starting at address 0 up
9798 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
9799 * error and the number of 32-bit words actually read on success.
9800 */
9802 {
9822 OBQDBGEN_F);
9828 }
9831 }
9833 /**
9834 * t4_cim_read - read a block from CIM internal address space
9835 * @adap: the adapter
9836 * @addr: the start address within the CIM address space
9837 * @n: number of words to read
9838 * @valp: where to store the result
9839 *
9840 * Reads a block of 4-byte words from the CIM intenal address space.
9841 */
9844 {
9856 }
9858 }
9860 /**
9861 * t4_cim_write - write a block into CIM internal address space
9862 * @adap: the adapter
9863 * @addr: the start address within the CIM address space
9864 * @n: number of words to write
9865 * @valp: set of values to write
9866 *
9867 * Writes a block of 4-byte words into the CIM intenal address space.
9868 */
9871 {
9882 }
9884 }
9888 {
9890 }
9892 /**
9893 * t4_cim_read_la - read CIM LA capture buffer
9894 * @adap: the adapter
9895 * @la_buf: where to store the LA data
9896 * @wrptr: the HW write pointer within the capture buffer
9897 *
9898 * Reads the contents of the CIM LA buffer with the most recent entry at
9899 * the end of the returned data and with the entry at @wrptr first.
9900 * We try to leave the LA in the running state we find it in.
9901 */
9903 {
9915 }
9936 }
9941 /* Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to
9942 * identify the 32-bit portion of the full 312-bit data
9943 */
9946 else
9947 idx++;
9948 /* address can't exceed 0xfff */
9950 }
9951 restart:
9957 }
9959 }
9961 /**
9962 * t4_tp_read_la - read TP LA capture buffer
9963 * @adap: the adapter
9964 * @la_buf: where to store the LA data
9965 * @wrptr: the HW write pointer within the capture buffer
9966 *
9967 * Reads the contents of the TP LA buffer with the most recent entry at
9968 * the end of the returned data and with the entry at @wrptr first.
9969 * We leave the LA in the running state we find it in.
9970 */
9972 {
9997 }
9999 /* Wipe out last entry if it isn't valid */
10006 }
10008 /* SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in
10009 * seconds). If we find one of the SGE Ingress DMA State Machines in the same
10010 * state for more than the Warning Threshold then we'll issue a warning about
10011 * a potential hang. We'll repeat the warning as the SGE Ingress DMA Channel
10012 * appears to be hung every Warning Repeat second till the situation clears.
10013 * If the situation clears, we'll note that as well.
10014 */
10015 #define SGE_IDMA_WARN_THRESH 1
10016 #define SGE_IDMA_WARN_REPEAT 300
10018 /**
10019 * t4_idma_monitor_init - initialize SGE Ingress DMA Monitor
10020 * @adapter: the adapter
10021 * @idma: the adapter IDMA Monitor state
10022 *
10023 * Initialize the state of an SGE Ingress DMA Monitor.
10024 */
10027 {
10028 /* Initialize the state variables for detecting an SGE Ingress DMA
10029 * hang. The SGE has internal counters which count up on each clock
10030 * tick whenever the SGE finds its Ingress DMA State Engines in the
10031 * same state they were on the previous clock tick. The clock used is
10032 * the Core Clock so we have a limit on the maximum "time" they can
10033 * record; typically a very small number of seconds. For instance,
10034 * with a 600MHz Core Clock, we can only count up to a bit more than
10035 * 7s. So we'll synthesize a larger counter in order to not run the
10036 * risk of having the "timers" overflow and give us the flexibility to
10037 * maintain a Hung SGE State Machine of our own which operates across
10038 * a longer time frame.
10039 */
10043 }
10045 /**
10046 * t4_idma_monitor - monitor SGE Ingress DMA state
10047 * @adapter: the adapter
10048 * @idma: the adapter IDMA Monitor state
10049 * @hz: number of ticks/second
10050 * @ticks: number of ticks since the last IDMA Monitor call
10051 */
10055 {
10058 /* Read the SGE Debug Ingress DMA Same State Count registers. These
10059 * are counters inside the SGE which count up on each clock when the
10060 * SGE finds its Ingress DMA State Engines in the same states they
10061 * were in the previous clock. The counters will peg out at
10062 * 0xffffffff without wrapping around so once they pass the 1s
10063 * threshold they'll stay above that till the IDMA state changes.
10064 */
10072 /* If the Ingress DMA Same State Counter ("timer") is less
10073 * than 1s, then we can reset our synthesized Stall Timer and
10074 * continue. If we have previously emitted warnings about a
10075 * potential stalled Ingress Queue, issue a note indicating
10076 * that the Ingress Queue has resumed forward progress.
10077 */
10086 }
10088 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz
10089 * domain. The first time we get here it'll be because we
10090 * passed the 1s Threshold; each additional time it'll be
10091 * because the RX Timer Callback is being fired on its regular
10092 * schedule.
10093 *
10094 * If the stall is below our Potential Hung Ingress Queue
10095 * Warning Threshold, continue.
10096 */
10103 }
10108 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds.
10109 */
10114 /* Read and save the SGE IDMA State and Queue ID information.
10115 * We do this every time in case it changes across time ...
10116 * can't be too careful ...
10117 */
10132 }
10133 }
10135 /**
10136 * t4_load_cfg - download config file
10137 * @adap: the adapter
10138 * @cfg_data: the cfg text file to write
10139 * @size: text file size
10140 *
10141 * Write the supplied config text file to the card's serial flash.
10142 */
10144 {
10159 FLASH_CFG_MAX_SIZE);
10161 }
10164 sf_sec_size);
10167 /* If size == 0 then we're simply erasing the FLASH sectors associated
10168 * with the on-adapter Firmware Configuration File.
10169 */
10173 /* this will write to the flash up to SF_PAGE_SIZE at a time */
10177 else
10185 }
10187 out:
10192 }
10194 /**
10195 * t4_set_vf_mac - Set MAC address for the specified VF
10196 * @adapter: The adapter
10197 * @vf: one of the VFs instantiated by the specified PF
10198 * @naddr: the number of MAC addresses
10199 * @addr: the MAC address(es) to be set to the specified VF
10200 */
10203 {
10208 FW_CMD_REQUEST_F |
10209 FW_CMD_WRITE_F |
10213 /* Note: Do not enable the ACL */
10230 }
10233 }
10235 /**
10236 * t4_read_pace_tbl - read the pace table
10237 * @adap: the adapter
10238 * @pace_vals: holds the returned values
10239 *
10240 * Returns the values of TP's pace table in microseconds.
10241 */
10243 {
10250 }
10251 }
10253 /**
10254 * t4_get_tx_sched - get the configuration of a Tx HW traffic scheduler
10255 * @adap: the adapter
10256 * @sched: the scheduler index
10257 * @kbps: the byte rate in Kbps
10258 * @ipg: the interpacket delay in tenths of nanoseconds
10259 * @sleep_ok: if true we may sleep while awaiting command completion
10260 *
10261 * Return the current configuration of a HW Tx scheduler.
10262 */
10265 {
10280 }
10281 }
10289 }
10290 }
10292 /* t4_sge_ctxt_rd - read an SGE context through FW
10293 * @adap: the adapter
10294 * @mbox: mailbox to use for the FW command
10295 * @cid: the context id
10296 * @ctype: the context type
10297 * @data: where to store the context data
10298 *
10299 * Issues a FW command through the given mailbox to read an SGE context.
10300 */
10303 {
10309 else
10327 }
10329 }
10331 /**
10332 * t4_sge_ctxt_rd_bd - read an SGE context bypassing FW
10333 * @adap: the adapter
10334 * @cid: the context id
10335 * @ctype: the context type
10336 * @data: where to store the context data
10337 *
10338 * Reads an SGE context directly, bypassing FW. This is only for
10339 * debugging when FW is unavailable.
10340 */
10343 {
10352 }
10357 {
10362 FW_CMD_REQUEST_F |
10363 FW_CMD_WRITE_F);
10381 }
10383 /**
10384 * t4_i2c_rd - read I2C data from adapter
10385 * @adap: the adapter
10386 * @port: Port number if per-port device; <0 if not
10387 * @devid: per-port device ID or absolute device ID
10388 * @offset: byte offset into device I2C space
10389 * @len: byte length of I2C space data
10390 * @buf: buffer in which to return I2C data
10391 *
10392 * Reads the I2C data from the indicated device and location.
10393 */
10397 {
10405 /* Dont allow reads that spans multiple pages */
10412 FW_CMD_REQUEST_F |
10413 FW_CMD_READ_F |
10434 }
10437 }
10439 /**
10440 * t4_set_vlan_acl - Set a VLAN id for the specified VF
10441 * @adapter: the adapter
10442 * @mbox: mailbox to use for the FW command
10443 * @vf: one of the VFs instantiated by the specified PF
10444 * @vlan: The vlanid to be set
10445 */
10447 u16 vlan)
10448 {
10455 FW_CMD_REQUEST_F |
10456 FW_CMD_WRITE_F |
10457 FW_CMD_EXEC_F |
10461 /* Drop all packets that donot match vlan id */
10468 }
10471 }