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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / net / wireless / realtek / rtlwifi / rtl8192de / hw.c
blob146fe144f5f59a0e535d7e989490ecba388e783e
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2012 Realtek Corporation.*/
3
4 #include "../wifi.h"
5 #include "../efuse.h"
6 #include "../base.h"
7 #include "../regd.h"
8 #include "../cam.h"
9 #include "../ps.h"
10 #include "../pci.h"
11 #include "reg.h"
12 #include "def.h"
13 #include "phy.h"
14 #include "dm.h"
15 #include "fw.h"
16 #include "led.h"
17 #include "sw.h"
18 #include "hw.h"
19
20 u32 rtl92de_read_dword_dbi(struct ieee80211_hw *hw, u16 offset, u8 direct)
21 {
22 struct rtl_priv *rtlpriv = rtl_priv(hw);
23 u32 value;
24
25 rtl_write_word(rtlpriv, REG_DBI_CTRL, (offset & 0xFFC));
26 rtl_write_byte(rtlpriv, REG_DBI_FLAG, BIT(1) | direct);
27 udelay(10);
28 value = rtl_read_dword(rtlpriv, REG_DBI_RDATA);
29 return value;
30 }
31
32 void rtl92de_write_dword_dbi(struct ieee80211_hw *hw,
33 u16 offset, u32 value, u8 direct)
34 {
35 struct rtl_priv *rtlpriv = rtl_priv(hw);
36
37 rtl_write_word(rtlpriv, REG_DBI_CTRL, ((offset & 0xFFC) | 0xF000));
38 rtl_write_dword(rtlpriv, REG_DBI_WDATA, value);
39 rtl_write_byte(rtlpriv, REG_DBI_FLAG, BIT(0) | direct);
40 }
41
42 static void _rtl92de_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
43 u8 set_bits, u8 clear_bits)
44 {
45 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
46 struct rtl_priv *rtlpriv = rtl_priv(hw);
47
48 rtlpci->reg_bcn_ctrl_val |= set_bits;
49 rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
50 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
51 }
52
53 static void _rtl92de_stop_tx_beacon(struct ieee80211_hw *hw)
54 {
55 struct rtl_priv *rtlpriv = rtl_priv(hw);
56 u8 tmp1byte;
57
58 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
59 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
60 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff);
61 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
62 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
63 tmp1byte &= ~(BIT(0));
64 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
65 }
66
67 static void _rtl92de_resume_tx_beacon(struct ieee80211_hw *hw)
68 {
69 struct rtl_priv *rtlpriv = rtl_priv(hw);
70 u8 tmp1byte;
71
72 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
73 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
74 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0x0a);
75 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
76 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
77 tmp1byte |= BIT(0);
78 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
79 }
80
81 static void _rtl92de_enable_bcn_sub_func(struct ieee80211_hw *hw)
82 {
83 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(1));
84 }
85
86 static void _rtl92de_disable_bcn_sub_func(struct ieee80211_hw *hw)
87 {
88 _rtl92de_set_bcn_ctrl_reg(hw, BIT(1), 0);
89 }
90
91 void rtl92de_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
92 {
93 struct rtl_priv *rtlpriv = rtl_priv(hw);
94 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
95 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
96
97 switch (variable) {
98 case HW_VAR_RCR:
99 *((u32 *) (val)) = rtlpci->receive_config;
100 break;
101 case HW_VAR_RF_STATE:
102 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
103 break;
104 case HW_VAR_FWLPS_RF_ON:{
105 enum rf_pwrstate rfstate;
106 u32 val_rcr;
107
108 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,
109 (u8 *)(&rfstate));
110 if (rfstate == ERFOFF) {
111 *((bool *) (val)) = true;
112 } else {
113 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
114 val_rcr &= 0x00070000;
115 if (val_rcr)
116 *((bool *) (val)) = false;
117 else
118 *((bool *) (val)) = true;
119 }
120 break;
121 }
122 case HW_VAR_FW_PSMODE_STATUS:
123 *((bool *) (val)) = ppsc->fw_current_inpsmode;
124 break;
125 case HW_VAR_CORRECT_TSF:{
126 u64 tsf;
127 u32 *ptsf_low = (u32 *)&tsf;
128 u32 *ptsf_high = ((u32 *)&tsf) + 1;
129
130 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
131 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
132 *((u64 *) (val)) = tsf;
133 break;
134 }
135 case HW_VAR_INT_MIGRATION:
136 *((bool *)(val)) = rtlpriv->dm.interrupt_migration;
137 break;
138 case HW_VAR_INT_AC:
139 *((bool *)(val)) = rtlpriv->dm.disable_tx_int;
140 break;
141 case HAL_DEF_WOWLAN:
142 break;
143 default:
144 pr_err("switch case %#x not processed\n", variable);
145 break;
146 }
147 }
148
149 void rtl92de_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
150 {
151 struct rtl_priv *rtlpriv = rtl_priv(hw);
152 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
153 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
154 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
155 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
156 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
157 u8 idx;
158
159 switch (variable) {
160 case HW_VAR_ETHER_ADDR:
161 for (idx = 0; idx < ETH_ALEN; idx++) {
162 rtl_write_byte(rtlpriv, (REG_MACID + idx),
163 val[idx]);
164 }
165 break;
166 case HW_VAR_BASIC_RATE: {
167 u16 rate_cfg = ((u16 *) val)[0];
168 u8 rate_index = 0;
169
170 rate_cfg = rate_cfg & 0x15f;
171 if (mac->vendor == PEER_CISCO &&
172 ((rate_cfg & 0x150) == 0))
173 rate_cfg |= 0x01;
174 rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
175 rtl_write_byte(rtlpriv, REG_RRSR + 1,
176 (rate_cfg >> 8) & 0xff);
177 while (rate_cfg > 0x1) {
178 rate_cfg = (rate_cfg >> 1);
179 rate_index++;
180 }
181 if (rtlhal->fw_version > 0xe)
182 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
183 rate_index);
184 break;
185 }
186 case HW_VAR_BSSID:
187 for (idx = 0; idx < ETH_ALEN; idx++) {
188 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
189 val[idx]);
190 }
191 break;
192 case HW_VAR_SIFS:
193 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
194 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
195 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
196 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
197 if (!mac->ht_enable)
198 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
199 0x0e0e);
200 else
201 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
202 *((u16 *) val));
203 break;
204 case HW_VAR_SLOT_TIME: {
205 u8 e_aci;
206
207 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
208 "HW_VAR_SLOT_TIME %x\n", val[0]);
209 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
210 for (e_aci = 0; e_aci < AC_MAX; e_aci++)
211 rtlpriv->cfg->ops->set_hw_reg(hw,
212 HW_VAR_AC_PARAM,
213 (&e_aci));
214 break;
215 }
216 case HW_VAR_ACK_PREAMBLE: {
217 u8 reg_tmp;
218 u8 short_preamble = (bool) (*val);
219
220 reg_tmp = (mac->cur_40_prime_sc) << 5;
221 if (short_preamble)
222 reg_tmp |= 0x80;
223 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
224 break;
225 }
226 case HW_VAR_AMPDU_MIN_SPACE: {
227 u8 min_spacing_to_set;
228 u8 sec_min_space;
229
230 min_spacing_to_set = *val;
231 if (min_spacing_to_set <= 7) {
232 sec_min_space = 0;
233 if (min_spacing_to_set < sec_min_space)
234 min_spacing_to_set = sec_min_space;
235 mac->min_space_cfg = ((mac->min_space_cfg & 0xf8) |
236 min_spacing_to_set);
237 *val = min_spacing_to_set;
238 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
239 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
240 mac->min_space_cfg);
241 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
242 mac->min_space_cfg);
243 }
244 break;
245 }
246 case HW_VAR_SHORTGI_DENSITY: {
247 u8 density_to_set;
248
249 density_to_set = *val;
250 mac->min_space_cfg = rtlpriv->rtlhal.minspace_cfg;
251 mac->min_space_cfg |= (density_to_set << 3);
252 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
253 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
254 mac->min_space_cfg);
255 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
256 mac->min_space_cfg);
257 break;
258 }
259 case HW_VAR_AMPDU_FACTOR: {
260 u8 factor_toset;
261 u32 regtoset;
262 u8 *ptmp_byte = NULL;
263 u8 index;
264
265 if (rtlhal->macphymode == DUALMAC_DUALPHY)
266 regtoset = 0xb9726641;
267 else if (rtlhal->macphymode == DUALMAC_SINGLEPHY)
268 regtoset = 0x66626641;
269 else
270 regtoset = 0xb972a841;
271 factor_toset = *val;
272 if (factor_toset <= 3) {
273 factor_toset = (1 << (factor_toset + 2));
274 if (factor_toset > 0xf)
275 factor_toset = 0xf;
276 for (index = 0; index < 4; index++) {
277 ptmp_byte = (u8 *)(&regtoset) + index;
278 if ((*ptmp_byte & 0xf0) >
279 (factor_toset << 4))
280 *ptmp_byte = (*ptmp_byte & 0x0f)
281 | (factor_toset << 4);
282 if ((*ptmp_byte & 0x0f) > factor_toset)
283 *ptmp_byte = (*ptmp_byte & 0xf0)
284 | (factor_toset);
285 }
286 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, regtoset);
287 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
288 "Set HW_VAR_AMPDU_FACTOR: %#x\n",
289 factor_toset);
290 }
291 break;
292 }
293 case HW_VAR_AC_PARAM: {
294 u8 e_aci = *val;
295 rtl92d_dm_init_edca_turbo(hw);
296 if (rtlpci->acm_method != EACMWAY2_SW)
297 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ACM_CTRL,
298 &e_aci);
299 break;
300 }
301 case HW_VAR_ACM_CTRL: {
302 u8 e_aci = *val;
303 union aci_aifsn *p_aci_aifsn =
304 (union aci_aifsn *)(&(mac->ac[0].aifs));
305 u8 acm = p_aci_aifsn->f.acm;
306 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
307
308 acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
309 if (acm) {
310 switch (e_aci) {
311 case AC0_BE:
312 acm_ctrl |= ACMHW_BEQEN;
313 break;
314 case AC2_VI:
315 acm_ctrl |= ACMHW_VIQEN;
316 break;
317 case AC3_VO:
318 acm_ctrl |= ACMHW_VOQEN;
319 break;
320 default:
321 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
322 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
323 acm);
324 break;
325 }
326 } else {
327 switch (e_aci) {
328 case AC0_BE:
329 acm_ctrl &= (~ACMHW_BEQEN);
330 break;
331 case AC2_VI:
332 acm_ctrl &= (~ACMHW_VIQEN);
333 break;
334 case AC3_VO:
335 acm_ctrl &= (~ACMHW_VOQEN);
336 break;
337 default:
338 pr_err("switch case %#x not processed\n",
339 e_aci);
340 break;
341 }
342 }
343 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
344 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
345 acm_ctrl);
346 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
347 break;
348 }
349 case HW_VAR_RCR:
350 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
351 rtlpci->receive_config = ((u32 *) (val))[0];
352 break;
353 case HW_VAR_RETRY_LIMIT: {
354 u8 retry_limit = val[0];
355
356 rtl_write_word(rtlpriv, REG_RL,
357 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
358 retry_limit << RETRY_LIMIT_LONG_SHIFT);
359 break;
360 }
361 case HW_VAR_DUAL_TSF_RST:
362 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
363 break;
364 case HW_VAR_EFUSE_BYTES:
365 rtlefuse->efuse_usedbytes = *((u16 *) val);
366 break;
367 case HW_VAR_EFUSE_USAGE:
368 rtlefuse->efuse_usedpercentage = *val;
369 break;
370 case HW_VAR_IO_CMD:
371 rtl92d_phy_set_io_cmd(hw, (*(enum io_type *)val));
372 break;
373 case HW_VAR_WPA_CONFIG:
374 rtl_write_byte(rtlpriv, REG_SECCFG, *val);
375 break;
376 case HW_VAR_SET_RPWM:
377 rtl92d_fill_h2c_cmd(hw, H2C_PWRM, 1, (val));
378 break;
379 case HW_VAR_H2C_FW_PWRMODE:
380 break;
381 case HW_VAR_FW_PSMODE_STATUS:
382 ppsc->fw_current_inpsmode = *((bool *) val);
383 break;
384 case HW_VAR_H2C_FW_JOINBSSRPT: {
385 u8 mstatus = (*val);
386 u8 tmp_regcr, tmp_reg422;
387 bool recover = false;
388
389 if (mstatus == RT_MEDIA_CONNECT) {
390 rtlpriv->cfg->ops->set_hw_reg(hw,
391 HW_VAR_AID, NULL);
392 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
393 rtl_write_byte(rtlpriv, REG_CR + 1,
394 (tmp_regcr | BIT(0)));
395 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(3));
396 _rtl92de_set_bcn_ctrl_reg(hw, BIT(4), 0);
397 tmp_reg422 = rtl_read_byte(rtlpriv,
398 REG_FWHW_TXQ_CTRL + 2);
399 if (tmp_reg422 & BIT(6))
400 recover = true;
401 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
402 tmp_reg422 & (~BIT(6)));
403 rtl92d_set_fw_rsvdpagepkt(hw, 0);
404 _rtl92de_set_bcn_ctrl_reg(hw, BIT(3), 0);
405 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(4));
406 if (recover)
407 rtl_write_byte(rtlpriv,
408 REG_FWHW_TXQ_CTRL + 2,
409 tmp_reg422);
410 rtl_write_byte(rtlpriv, REG_CR + 1,
411 (tmp_regcr & ~(BIT(0))));
412 }
413 rtl92d_set_fw_joinbss_report_cmd(hw, (*val));
414 break;
415 }
416 case HW_VAR_AID: {
417 u16 u2btmp;
418 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
419 u2btmp &= 0xC000;
420 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
421 mac->assoc_id));
422 break;
423 }
424 case HW_VAR_CORRECT_TSF: {
425 u8 btype_ibss = val[0];
426
427 if (btype_ibss)
428 _rtl92de_stop_tx_beacon(hw);
429 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(3));
430 rtl_write_dword(rtlpriv, REG_TSFTR,
431 (u32) (mac->tsf & 0xffffffff));
432 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
433 (u32) ((mac->tsf >> 32) & 0xffffffff));
434 _rtl92de_set_bcn_ctrl_reg(hw, BIT(3), 0);
435 if (btype_ibss)
436 _rtl92de_resume_tx_beacon(hw);
437
438 break;
439 }
440 case HW_VAR_INT_MIGRATION: {
441 bool int_migration = *(bool *) (val);
442
443 if (int_migration) {
444 /* Set interrupt migration timer and
445 * corresponding Tx/Rx counter.
446 * timer 25ns*0xfa0=100us for 0xf packets.
447 * 0x306:Rx, 0x307:Tx */
448 rtl_write_dword(rtlpriv, REG_INT_MIG, 0xfe000fa0);
449 rtlpriv->dm.interrupt_migration = int_migration;
450 } else {
451 /* Reset all interrupt migration settings. */
452 rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
453 rtlpriv->dm.interrupt_migration = int_migration;
454 }
455 break;
456 }
457 case HW_VAR_INT_AC: {
458 bool disable_ac_int = *((bool *) val);
459
460 /* Disable four ACs interrupts. */
461 if (disable_ac_int) {
462 /* Disable VO, VI, BE and BK four AC interrupts
463 * to gain more efficient CPU utilization.
464 * When extremely highly Rx OK occurs,
465 * we will disable Tx interrupts.
466 */
467 rtlpriv->cfg->ops->update_interrupt_mask(hw, 0,
468 RT_AC_INT_MASKS);
469 rtlpriv->dm.disable_tx_int = disable_ac_int;
470 /* Enable four ACs interrupts. */
471 } else {
472 rtlpriv->cfg->ops->update_interrupt_mask(hw,
473 RT_AC_INT_MASKS, 0);
474 rtlpriv->dm.disable_tx_int = disable_ac_int;
475 }
476 break;
477 }
478 default:
479 pr_err("switch case %#x not processed\n", variable);
480 break;
481 }
482 }
483
484 static bool _rtl92de_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
485 {
486 struct rtl_priv *rtlpriv = rtl_priv(hw);
487 bool status = true;
488 long count = 0;
489 u32 value = _LLT_INIT_ADDR(address) |
490 _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
491
492 rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
493 do {
494 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
495 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
496 break;
497 if (count > POLLING_LLT_THRESHOLD) {
498 pr_err("Failed to polling write LLT done at address %d!\n",
499 address);
500 status = false;
501 break;
502 }
503 } while (++count);
504 return status;
505 }
506
507 static bool _rtl92de_llt_table_init(struct ieee80211_hw *hw)
508 {
509 struct rtl_priv *rtlpriv = rtl_priv(hw);
510 unsigned short i;
511 u8 txpktbuf_bndy;
512 u8 maxpage;
513 bool status;
514 u32 value32; /* High+low page number */
515 u8 value8; /* normal page number */
516
517 if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) {
518 maxpage = 255;
519 txpktbuf_bndy = 246;
520 value8 = 0;
521 value32 = 0x80bf0d29;
522 } else {
523 maxpage = 127;
524 txpktbuf_bndy = 123;
525 value8 = 0;
526 value32 = 0x80750005;
527 }
528
529 /* Set reserved page for each queue */
530 /* 11. RQPN 0x200[31:0] = 0x80BD1C1C */
531 /* load RQPN */
532 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8);
533 rtl_write_dword(rtlpriv, REG_RQPN, value32);
534
535 /* 12. TXRKTBUG_PG_BNDY 0x114[31:0] = 0x27FF00F6 */
536 /* TXRKTBUG_PG_BNDY */
537 rtl_write_dword(rtlpriv, REG_TRXFF_BNDY,
538 (rtl_read_word(rtlpriv, REG_TRXFF_BNDY + 2) << 16 |
539 txpktbuf_bndy));
540
541 /* 13. TDECTRL[15:8] 0x209[7:0] = 0xF6 */
542 /* Beacon Head for TXDMA */
543 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
544
545 /* 14. BCNQ_PGBNDY 0x424[7:0] = 0xF6 */
546 /* BCNQ_PGBNDY */
547 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
548 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
549
550 /* 15. WMAC_LBK_BF_HD 0x45D[7:0] = 0xF6 */
551 /* WMAC_LBK_BF_HD */
552 rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
553
554 /* Set Tx/Rx page size (Tx must be 128 Bytes, */
555 /* Rx can be 64,128,256,512,1024 bytes) */
556 /* 16. PBP [7:0] = 0x11 */
557 /* TRX page size */
558 rtl_write_byte(rtlpriv, REG_PBP, 0x11);
559
560 /* 17. DRV_INFO_SZ = 0x04 */
561 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
562
563 /* 18. LLT_table_init(Adapter); */
564 for (i = 0; i < (txpktbuf_bndy - 1); i++) {
565 status = _rtl92de_llt_write(hw, i, i + 1);
566 if (true != status)
567 return status;
568 }
569
570 /* end of list */
571 status = _rtl92de_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
572 if (true != status)
573 return status;
574
575 /* Make the other pages as ring buffer */
576 /* This ring buffer is used as beacon buffer if we */
577 /* config this MAC as two MAC transfer. */
578 /* Otherwise used as local loopback buffer. */
579 for (i = txpktbuf_bndy; i < maxpage; i++) {
580 status = _rtl92de_llt_write(hw, i, (i + 1));
581 if (true != status)
582 return status;
583 }
584
585 /* Let last entry point to the start entry of ring buffer */
586 status = _rtl92de_llt_write(hw, maxpage, txpktbuf_bndy);
587 if (true != status)
588 return status;
589
590 return true;
591 }
592
593 static void _rtl92de_gen_refresh_led_state(struct ieee80211_hw *hw)
594 {
595 struct rtl_priv *rtlpriv = rtl_priv(hw);
596 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
597 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
598 struct rtl_led *pled0 = &rtlpriv->ledctl.sw_led0;
599
600 if (rtlpci->up_first_time)
601 return;
602 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
603 rtl92de_sw_led_on(hw, pled0);
604 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
605 rtl92de_sw_led_on(hw, pled0);
606 else
607 rtl92de_sw_led_off(hw, pled0);
608 }
609
610 static bool _rtl92de_init_mac(struct ieee80211_hw *hw)
611 {
612 struct rtl_priv *rtlpriv = rtl_priv(hw);
613 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
614 unsigned char bytetmp;
615 unsigned short wordtmp;
616 u16 retry;
617
618 rtl92d_phy_set_poweron(hw);
619 /* Add for resume sequence of power domain according
620 * to power document V11. Chapter V.11.... */
621 /* 0. RSV_CTRL 0x1C[7:0] = 0x00 */
622 /* unlock ISO/CLK/Power control register */
623 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
624 rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x05);
625
626 /* 1. AFE_XTAL_CTRL [7:0] = 0x0F enable XTAL */
627 /* 2. SPS0_CTRL 0x11[7:0] = 0x2b enable SPS into PWM mode */
628 /* 3. delay (1ms) this is not necessary when initially power on */
629
630 /* C. Resume Sequence */
631 /* a. SPS0_CTRL 0x11[7:0] = 0x2b */
632 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
633
634 /* b. AFE_XTAL_CTRL [7:0] = 0x0F */
635 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0F);
636
637 /* c. DRV runs power on init flow */
638
639 /* auto enable WLAN */
640 /* 4. APS_FSMCO 0x04[8] = 1; wait till 0x04[8] = 0 */
641 /* Power On Reset for MAC Block */
642 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) | BIT(0);
643 udelay(2);
644 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
645 udelay(2);
646
647 /* 5. Wait while 0x04[8] == 0 goto 2, otherwise goto 1 */
648 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
649 udelay(50);
650 retry = 0;
651 while ((bytetmp & BIT(0)) && retry < 1000) {
652 retry++;
653 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
654 udelay(50);
655 }
656
657 /* Enable Radio off, GPIO, and LED function */
658 /* 6. APS_FSMCO 0x04[15:0] = 0x0012 when enable HWPDN */
659 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x1012);
660
661 /* release RF digital isolation */
662 /* 7. SYS_ISO_CTRL 0x01[1] = 0x0; */
663 /*Set REG_SYS_ISO_CTRL 0x1=0x82 to prevent wake# problem. */
664 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x82);
665 udelay(2);
666
667 /* make sure that BB reset OK. */
668 /* rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); */
669
670 /* Disable REG_CR before enable it to assure reset */
671 rtl_write_word(rtlpriv, REG_CR, 0x0);
672
673 /* Release MAC IO register reset */
674 rtl_write_word(rtlpriv, REG_CR, 0x2ff);
675
676 /* clear stopping tx/rx dma */
677 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0x0);
678
679 /* rtl_write_word(rtlpriv,REG_CR+2, 0x2); */
680
681 /* System init */
682 /* 18. LLT_table_init(Adapter); */
683 if (!_rtl92de_llt_table_init(hw))
684 return false;
685
686 /* Clear interrupt and enable interrupt */
687 /* 19. HISR 0x124[31:0] = 0xffffffff; */
688 /* HISRE 0x12C[7:0] = 0xFF */
689 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
690 rtl_write_byte(rtlpriv, REG_HISRE, 0xff);
691
692 /* 20. HIMR 0x120[31:0] |= [enable INT mask bit map]; */
693 /* 21. HIMRE 0x128[7:0] = [enable INT mask bit map] */
694 /* The IMR should be enabled later after all init sequence
695 * is finished. */
696
697 /* 22. PCIE configuration space configuration */
698 /* 23. Ensure PCIe Device 0x80[15:0] = 0x0143 (ASPM+CLKREQ), */
699 /* and PCIe gated clock function is enabled. */
700 /* PCIE configuration space will be written after
701 * all init sequence.(Or by BIOS) */
702
703 rtl92d_phy_config_maccoexist_rfpage(hw);
704
705 /* THe below section is not related to power document Vxx . */
706 /* This is only useful for driver and OS setting. */
707 /* -------------------Software Relative Setting---------------------- */
708 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
709 wordtmp &= 0xf;
710 wordtmp |= 0xF771;
711 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
712
713 /* Reported Tx status from HW for rate adaptive. */
714 /* This should be realtive to power on step 14. But in document V11 */
715 /* still not contain the description.!!! */
716 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
717
718 /* Set Tx/Rx page size (Tx must be 128 Bytes,
719 * Rx can be 64,128,256,512,1024 bytes) */
720 /* rtl_write_byte(rtlpriv,REG_PBP, 0x11); */
721
722 /* Set RCR register */
723 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
724 /* rtl_write_byte(rtlpriv,REG_RX_DRVINFO_SZ, 4); */
725
726 /* Set TCR register */
727 rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
728
729 /* disable earlymode */
730 rtl_write_byte(rtlpriv, 0x4d0, 0x0);
731
732 /* Set TX/RX descriptor physical address(from OS API). */
733 rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
734 rtlpci->tx_ring[BEACON_QUEUE].dma);
735 rtl_write_dword(rtlpriv, REG_MGQ_DESA, rtlpci->tx_ring[MGNT_QUEUE].dma);
736 rtl_write_dword(rtlpriv, REG_VOQ_DESA, rtlpci->tx_ring[VO_QUEUE].dma);
737 rtl_write_dword(rtlpriv, REG_VIQ_DESA, rtlpci->tx_ring[VI_QUEUE].dma);
738 rtl_write_dword(rtlpriv, REG_BEQ_DESA, rtlpci->tx_ring[BE_QUEUE].dma);
739 rtl_write_dword(rtlpriv, REG_BKQ_DESA, rtlpci->tx_ring[BK_QUEUE].dma);
740 rtl_write_dword(rtlpriv, REG_HQ_DESA, rtlpci->tx_ring[HIGH_QUEUE].dma);
741 /* Set RX Desc Address */
742 rtl_write_dword(rtlpriv, REG_RX_DESA,
743 rtlpci->rx_ring[RX_MPDU_QUEUE].dma);
744
745 /* if we want to support 64 bit DMA, we should set it here,
746 * but now we do not support 64 bit DMA*/
747
748 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x33);
749
750 /* Reset interrupt migration setting when initialization */
751 rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
752
753 /* Reconsider when to do this operation after asking HWSD. */
754 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
755 rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6));
756 do {
757 retry++;
758 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
759 } while ((retry < 200) && !(bytetmp & BIT(7)));
760
761 /* After MACIO reset,we must refresh LED state. */
762 _rtl92de_gen_refresh_led_state(hw);
763
764 /* Reset H2C protection register */
765 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
766
767 return true;
768 }
769
770 static void _rtl92de_hw_configure(struct ieee80211_hw *hw)
771 {
772 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
773 struct rtl_priv *rtlpriv = rtl_priv(hw);
774 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
775 u8 reg_bw_opmode = BW_OPMODE_20MHZ;
776 u32 reg_rrsr;
777
778 reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
779 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8);
780 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
781 rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr);
782 rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
783 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0);
784 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80);
785 rtl_write_word(rtlpriv, REG_RL, 0x0707);
786 rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802);
787 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
788 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
789 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
790 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
791 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
792 /* Aggregation threshold */
793 if (rtlhal->macphymode == DUALMAC_DUALPHY)
794 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb9726641);
795 else if (rtlhal->macphymode == DUALMAC_SINGLEPHY)
796 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x66626641);
797 else
798 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841);
799 rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2);
800 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0x0a);
801 rtlpci->reg_bcn_ctrl_val = 0x1f;
802 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
803 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
804 rtl_write_byte(rtlpriv, REG_PIFS, 0x1C);
805 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
806 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
807 /* For throughput */
808 rtl_write_word(rtlpriv, REG_FAST_EDCA_CTRL, 0x6666);
809 /* ACKTO for IOT issue. */
810 rtl_write_byte(rtlpriv, REG_ACKTO, 0x40);
811 /* Set Spec SIFS (used in NAV) */
812 rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010);
813 rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010);
814 /* Set SIFS for CCK */
815 rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010);
816 /* Set SIFS for OFDM */
817 rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010);
818 /* Set Multicast Address. */
819 rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff);
820 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff);
821 switch (rtlpriv->phy.rf_type) {
822 case RF_1T2R:
823 case RF_1T1R:
824 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_1T << 3);
825 break;
826 case RF_2T2R:
827 case RF_2T2R_GREEN:
828 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_2T << 3);
829 break;
830 }
831 }
832
833 static void _rtl92de_enable_aspm_back_door(struct ieee80211_hw *hw)
834 {
835 struct rtl_priv *rtlpriv = rtl_priv(hw);
836 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
837
838 rtl_write_byte(rtlpriv, 0x34b, 0x93);
839 rtl_write_word(rtlpriv, 0x350, 0x870c);
840 rtl_write_byte(rtlpriv, 0x352, 0x1);
841 if (ppsc->support_backdoor)
842 rtl_write_byte(rtlpriv, 0x349, 0x1b);
843 else
844 rtl_write_byte(rtlpriv, 0x349, 0x03);
845 rtl_write_word(rtlpriv, 0x350, 0x2718);
846 rtl_write_byte(rtlpriv, 0x352, 0x1);
847 }
848
849 void rtl92de_enable_hw_security_config(struct ieee80211_hw *hw)
850 {
851 struct rtl_priv *rtlpriv = rtl_priv(hw);
852 u8 sec_reg_value;
853
854 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
855 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
856 rtlpriv->sec.pairwise_enc_algorithm,
857 rtlpriv->sec.group_enc_algorithm);
858 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
859 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
860 "not open hw encryption\n");
861 return;
862 }
863 sec_reg_value = SCR_TXENCENABLE | SCR_RXENCENABLE;
864 if (rtlpriv->sec.use_defaultkey) {
865 sec_reg_value |= SCR_TXUSEDK;
866 sec_reg_value |= SCR_RXUSEDK;
867 }
868 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
869 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
870 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
871 "The SECR-value %x\n", sec_reg_value);
872 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
873 }
874
875 int rtl92de_hw_init(struct ieee80211_hw *hw)
876 {
877 struct rtl_priv *rtlpriv = rtl_priv(hw);
878 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
879 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
880 struct rtl_phy *rtlphy = &(rtlpriv->phy);
881 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
882 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
883 bool rtstatus = true;
884 u8 tmp_u1b;
885 int i;
886 int err;
887 unsigned long flags;
888
889 rtlpci->being_init_adapter = true;
890 rtlpci->init_ready = false;
891 spin_lock_irqsave(&globalmutex_for_power_and_efuse, flags);
892 /* we should do iqk after disable/enable */
893 rtl92d_phy_reset_iqk_result(hw);
894 /* rtlpriv->intf_ops->disable_aspm(hw); */
895 rtstatus = _rtl92de_init_mac(hw);
896 if (!rtstatus) {
897 pr_err("Init MAC failed\n");
898 err = 1;
899 spin_unlock_irqrestore(&globalmutex_for_power_and_efuse, flags);
900 return err;
901 }
902 err = rtl92d_download_fw(hw);
903 spin_unlock_irqrestore(&globalmutex_for_power_and_efuse, flags);
904 if (err) {
905 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
906 "Failed to download FW. Init HW without FW..\n");
907 return 1;
908 }
909 rtlhal->last_hmeboxnum = 0;
910 rtlpriv->psc.fw_current_inpsmode = false;
911
912 tmp_u1b = rtl_read_byte(rtlpriv, 0x605);
913 tmp_u1b = tmp_u1b | 0x30;
914 rtl_write_byte(rtlpriv, 0x605, tmp_u1b);
915
916 if (rtlhal->earlymode_enable) {
917 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
918 "EarlyMode Enabled!!!\n");
919
920 tmp_u1b = rtl_read_byte(rtlpriv, 0x4d0);
921 tmp_u1b = tmp_u1b | 0x1f;
922 rtl_write_byte(rtlpriv, 0x4d0, tmp_u1b);
923
924 rtl_write_byte(rtlpriv, 0x4d3, 0x80);
925
926 tmp_u1b = rtl_read_byte(rtlpriv, 0x605);
927 tmp_u1b = tmp_u1b | 0x40;
928 rtl_write_byte(rtlpriv, 0x605, tmp_u1b);
929 }
930
931 if (mac->rdg_en) {
932 rtl_write_byte(rtlpriv, REG_RD_CTRL, 0xff);
933 rtl_write_word(rtlpriv, REG_RD_NAV_NXT, 0x200);
934 rtl_write_byte(rtlpriv, REG_RD_RESP_PKT_TH, 0x05);
935 }
936
937 rtl92d_phy_mac_config(hw);
938 /* because last function modify RCR, so we update
939 * rcr var here, or TP will unstable for receive_config
940 * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
941 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252*/
942 rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
943 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
944
945 rtl92d_phy_bb_config(hw);
946
947 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
948 /* set before initialize RF */
949 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf);
950
951 /* config RF */
952 rtl92d_phy_rf_config(hw);
953
954 /* After read predefined TXT, we must set BB/MAC/RF
955 * register as our requirement */
956 /* After load BB,RF params,we need do more for 92D. */
957 rtl92d_update_bbrf_configuration(hw);
958 /* set default value after initialize RF, */
959 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0);
960 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
961 RF_CHNLBW, RFREG_OFFSET_MASK);
962 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
963 RF_CHNLBW, RFREG_OFFSET_MASK);
964
965 /*---- Set CCK and OFDM Block "ON"----*/
966 if (rtlhal->current_bandtype == BAND_ON_2_4G)
967 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
968 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
969 if (rtlhal->interfaceindex == 0) {
970 /* RFPGA0_ANALOGPARAMETER2: cck clock select,
971 * set to 20MHz by default */
972 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) |
973 BIT(11), 3);
974 } else {
975 /* Mac1 */
976 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(11) |
977 BIT(10), 3);
978 }
979
980 _rtl92de_hw_configure(hw);
981
982 /* reset hw sec */
983 rtl_cam_reset_all_entry(hw);
984 rtl92de_enable_hw_security_config(hw);
985
986 /* Read EEPROM TX power index and PHY_REG_PG.txt to capture correct */
987 /* TX power index for different rate set. */
988 rtl92d_phy_get_hw_reg_originalvalue(hw);
989 rtl92d_phy_set_txpower_level(hw, rtlphy->current_channel);
990
991 ppsc->rfpwr_state = ERFON;
992
993 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
994
995 _rtl92de_enable_aspm_back_door(hw);
996 /* rtlpriv->intf_ops->enable_aspm(hw); */
997
998 rtl92d_dm_init(hw);
999 rtlpci->being_init_adapter = false;
1000
1001 if (ppsc->rfpwr_state == ERFON) {
1002 rtl92d_phy_lc_calibrate(hw);
1003 /* 5G and 2.4G must wait sometime to let RF LO ready */
1004 if (rtlhal->macphymode == DUALMAC_DUALPHY) {
1005 u32 tmp_rega;
1006 for (i = 0; i < 10000; i++) {
1007 udelay(MAX_STALL_TIME);
1008
1009 tmp_rega = rtl_get_rfreg(hw,
1010 (enum radio_path)RF90_PATH_A,
1011 0x2a, MASKDWORD);
1012
1013 if (((tmp_rega & BIT(11)) == BIT(11)))
1014 break;
1015 }
1016 /* check that loop was successful. If not, exit now */
1017 if (i == 10000) {
1018 rtlpci->init_ready = false;
1019 return 1;
1020 }
1021 }
1022 }
1023 rtlpci->init_ready = true;
1024 return err;
1025 }
1026
1027 static enum version_8192d _rtl92de_read_chip_version(struct ieee80211_hw *hw)
1028 {
1029 struct rtl_priv *rtlpriv = rtl_priv(hw);
1030 enum version_8192d version = VERSION_NORMAL_CHIP_92D_SINGLEPHY;
1031 u32 value32;
1032
1033 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1034 if (!(value32 & 0x000f0000)) {
1035 version = VERSION_TEST_CHIP_92D_SINGLEPHY;
1036 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "TEST CHIP!!!\n");
1037 } else {
1038 version = VERSION_NORMAL_CHIP_92D_SINGLEPHY;
1039 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Normal CHIP!!!\n");
1040 }
1041 return version;
1042 }
1043
1044 static int _rtl92de_set_media_status(struct ieee80211_hw *hw,
1045 enum nl80211_iftype type)
1046 {
1047 struct rtl_priv *rtlpriv = rtl_priv(hw);
1048 u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1049 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1050 u8 bcnfunc_enable;
1051
1052 bt_msr &= 0xfc;
1053
1054 if (type == NL80211_IFTYPE_UNSPECIFIED ||
1055 type == NL80211_IFTYPE_STATION) {
1056 _rtl92de_stop_tx_beacon(hw);
1057 _rtl92de_enable_bcn_sub_func(hw);
1058 } else if (type == NL80211_IFTYPE_ADHOC ||
1059 type == NL80211_IFTYPE_AP) {
1060 _rtl92de_resume_tx_beacon(hw);
1061 _rtl92de_disable_bcn_sub_func(hw);
1062 } else {
1063 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1064 "Set HW_VAR_MEDIA_STATUS: No such media status(%x)\n",
1065 type);
1066 }
1067 bcnfunc_enable = rtl_read_byte(rtlpriv, REG_BCN_CTRL);
1068 switch (type) {
1069 case NL80211_IFTYPE_UNSPECIFIED:
1070 bt_msr |= MSR_NOLINK;
1071 ledaction = LED_CTL_LINK;
1072 bcnfunc_enable &= 0xF7;
1073 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1074 "Set Network type to NO LINK!\n");
1075 break;
1076 case NL80211_IFTYPE_ADHOC:
1077 bt_msr |= MSR_ADHOC;
1078 bcnfunc_enable |= 0x08;
1079 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1080 "Set Network type to Ad Hoc!\n");
1081 break;
1082 case NL80211_IFTYPE_STATION:
1083 bt_msr |= MSR_INFRA;
1084 ledaction = LED_CTL_LINK;
1085 bcnfunc_enable &= 0xF7;
1086 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1087 "Set Network type to STA!\n");
1088 break;
1089 case NL80211_IFTYPE_AP:
1090 bt_msr |= MSR_AP;
1091 bcnfunc_enable |= 0x08;
1092 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1093 "Set Network type to AP!\n");
1094 break;
1095 default:
1096 pr_err("Network type %d not supported!\n", type);
1097 return 1;
1098 }
1099 rtl_write_byte(rtlpriv, MSR, bt_msr);
1100 rtlpriv->cfg->ops->led_control(hw, ledaction);
1101 if ((bt_msr & MSR_MASK) == MSR_AP)
1102 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1103 else
1104 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1105 return 0;
1106 }
1107
1108 void rtl92de_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1109 {
1110 struct rtl_priv *rtlpriv = rtl_priv(hw);
1111 u32 reg_rcr;
1112
1113 if (rtlpriv->psc.rfpwr_state != ERFON)
1114 return;
1115
1116 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1117
1118 if (check_bssid) {
1119 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1120 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1121 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(4));
1122 } else if (!check_bssid) {
1123 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1124 _rtl92de_set_bcn_ctrl_reg(hw, BIT(4), 0);
1125 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1126 }
1127 }
1128
1129 int rtl92de_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1130 {
1131 struct rtl_priv *rtlpriv = rtl_priv(hw);
1132
1133 if (_rtl92de_set_media_status(hw, type))
1134 return -EOPNOTSUPP;
1135
1136 /* check bssid */
1137 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1138 if (type != NL80211_IFTYPE_AP)
1139 rtl92de_set_check_bssid(hw, true);
1140 } else {
1141 rtl92de_set_check_bssid(hw, false);
1142 }
1143 return 0;
1144 }
1145
1146 /* do iqk or reload iqk */
1147 /* windows just rtl92d_phy_reload_iqk_setting in set channel,
1148 * but it's very strict for time sequence so we add
1149 * rtl92d_phy_reload_iqk_setting here */
1150 void rtl92d_linked_set_reg(struct ieee80211_hw *hw)
1151 {
1152 struct rtl_priv *rtlpriv = rtl_priv(hw);
1153 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1154 u8 indexforchannel;
1155 u8 channel = rtlphy->current_channel;
1156
1157 indexforchannel = rtl92d_get_rightchnlplace_for_iqk(channel);
1158 if (!rtlphy->iqk_matrix[indexforchannel].iqk_done) {
1159 RT_TRACE(rtlpriv, COMP_SCAN | COMP_INIT, DBG_DMESG,
1160 "Do IQK for channel:%d\n", channel);
1161 rtl92d_phy_iq_calibrate(hw);
1162 }
1163 }
1164
1165 /* don't set REG_EDCA_BE_PARAM here because
1166 * mac80211 will send pkt when scan */
1167 void rtl92de_set_qos(struct ieee80211_hw *hw, int aci)
1168 {
1169 rtl92d_dm_init_edca_turbo(hw);
1170 }
1171
1172 void rtl92de_enable_interrupt(struct ieee80211_hw *hw)
1173 {
1174 struct rtl_priv *rtlpriv = rtl_priv(hw);
1175 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1176
1177 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1178 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1179 rtlpci->irq_enabled = true;
1180 }
1181
1182 void rtl92de_disable_interrupt(struct ieee80211_hw *hw)
1183 {
1184 struct rtl_priv *rtlpriv = rtl_priv(hw);
1185 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1186
1187 rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED);
1188 rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED);
1189 rtlpci->irq_enabled = false;
1190 }
1191
1192 static void _rtl92de_poweroff_adapter(struct ieee80211_hw *hw)
1193 {
1194 struct rtl_priv *rtlpriv = rtl_priv(hw);
1195 u8 u1b_tmp;
1196 unsigned long flags;
1197
1198 rtlpriv->intf_ops->enable_aspm(hw);
1199 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1200 rtl_set_bbreg(hw, RFPGA0_XCD_RFPARAMETER, BIT(3), 0);
1201 rtl_set_bbreg(hw, RFPGA0_XCD_RFPARAMETER, BIT(15), 0);
1202
1203 /* 0x20:value 05-->04 */
1204 rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x04);
1205
1206 /* ==== Reset digital sequence ====== */
1207 rtl92d_firmware_selfreset(hw);
1208
1209 /* f. SYS_FUNC_EN 0x03[7:0]=0x51 reset MCU, MAC register, DCORE */
1210 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x51);
1211
1212 /* g. MCUFWDL 0x80[1:0]=0 reset MCU ready status */
1213 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1214
1215 /* ==== Pull GPIO PIN to balance level and LED control ====== */
1216
1217 /* h. GPIO_PIN_CTRL 0x44[31:0]=0x000 */
1218 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00000000);
1219
1220 /* i. Value = GPIO_PIN_CTRL[7:0] */
1221 u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL);
1222
1223 /* j. GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); */
1224 /* write external PIN level */
1225 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL,
1226 0x00FF0000 | (u1b_tmp << 8));
1227
1228 /* k. GPIO_MUXCFG 0x42 [15:0] = 0x0780 */
1229 rtl_write_word(rtlpriv, REG_GPIO_IO_SEL, 0x0790);
1230
1231 /* l. LEDCFG 0x4C[15:0] = 0x8080 */
1232 rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080);
1233
1234 /* ==== Disable analog sequence === */
1235
1236 /* m. AFE_PLL_CTRL[7:0] = 0x80 disable PLL */
1237 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80);
1238
1239 /* n. SPS0_CTRL 0x11[7:0] = 0x22 enter PFM mode */
1240 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23);
1241
1242 /* o. AFE_XTAL_CTRL 0x24[7:0] = 0x0E disable XTAL, if No BT COEX */
1243 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0e);
1244
1245 /* p. RSV_CTRL 0x1C[7:0] = 0x0E lock ISO/CLK/Power control register */
1246 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1247
1248 /* ==== interface into suspend === */
1249
1250 /* q. APS_FSMCO[15:8] = 0x58 PCIe suspend mode */
1251 /* According to power document V11, we need to set this */
1252 /* value as 0x18. Otherwise, we may not L0s sometimes. */
1253 /* This indluences power consumption. Bases on SD1's test, */
1254 /* set as 0x00 do not affect power current. And if it */
1255 /* is set as 0x18, they had ever met auto load fail problem. */
1256 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x10);
1257
1258 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1259 "In PowerOff,reg0x%x=%X\n",
1260 REG_SPS0_CTRL, rtl_read_byte(rtlpriv, REG_SPS0_CTRL));
1261 /* r. Note: for PCIe interface, PON will not turn */
1262 /* off m-bias and BandGap in PCIe suspend mode. */
1263
1264 /* 0x17[7] 1b': power off in process 0b' : power off over */
1265 if (rtlpriv->rtlhal.macphymode != SINGLEMAC_SINGLEPHY) {
1266 spin_lock_irqsave(&globalmutex_power, flags);
1267 u1b_tmp = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS);
1268 u1b_tmp &= (~BIT(7));
1269 rtl_write_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS, u1b_tmp);
1270 spin_unlock_irqrestore(&globalmutex_power, flags);
1271 }
1272
1273 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<=======\n");
1274 }
1275
1276 void rtl92de_card_disable(struct ieee80211_hw *hw)
1277 {
1278 struct rtl_priv *rtlpriv = rtl_priv(hw);
1279 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1280 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1281 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1282 enum nl80211_iftype opmode;
1283
1284 mac->link_state = MAC80211_NOLINK;
1285 opmode = NL80211_IFTYPE_UNSPECIFIED;
1286 _rtl92de_set_media_status(hw, opmode);
1287
1288 if (rtlpci->driver_is_goingto_unload ||
1289 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1290 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1291 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1292 /* Power sequence for each MAC. */
1293 /* a. stop tx DMA */
1294 /* b. close RF */
1295 /* c. clear rx buf */
1296 /* d. stop rx DMA */
1297 /* e. reset MAC */
1298
1299 /* a. stop tx DMA */
1300 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE);
1301 udelay(50);
1302
1303 /* b. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue */
1304
1305 /* c. ========RF OFF sequence========== */
1306 /* 0x88c[23:20] = 0xf. */
1307 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf);
1308 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
1309
1310 /* APSD_CTRL 0x600[7:0] = 0x40 */
1311 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
1312
1313 /* Close antenna 0,0xc04,0xd04 */
1314 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0);
1315 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0);
1316
1317 /* SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB state machine */
1318 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1319
1320 /* Mac0 can not do Global reset. Mac1 can do. */
1321 /* SYS_FUNC_EN 0x02[7:0] = 0xE0 reset BB state machine */
1322 if (rtlpriv->rtlhal.interfaceindex == 1)
1323 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE0);
1324 udelay(50);
1325
1326 /* d. stop tx/rx dma before disable REG_CR (0x100) to fix */
1327 /* dma hang issue when disable/enable device. */
1328 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xff);
1329 udelay(50);
1330 rtl_write_byte(rtlpriv, REG_CR, 0x0);
1331 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "==> Do power off.......\n");
1332 if (rtl92d_phy_check_poweroff(hw))
1333 _rtl92de_poweroff_adapter(hw);
1334 return;
1335 }
1336
1337 void rtl92de_interrupt_recognized(struct ieee80211_hw *hw,
1338 struct rtl_int *intvec)
1339 {
1340 struct rtl_priv *rtlpriv = rtl_priv(hw);
1341 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1342
1343 intvec->inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1344 rtl_write_dword(rtlpriv, ISR, intvec->inta);
1345 }
1346
1347 void rtl92de_set_beacon_related_registers(struct ieee80211_hw *hw)
1348 {
1349 struct rtl_priv *rtlpriv = rtl_priv(hw);
1350 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1351 u16 bcn_interval, atim_window;
1352
1353 bcn_interval = mac->beacon_interval;
1354 atim_window = 2;
1355 rtl92de_disable_interrupt(hw);
1356 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1357 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1358 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1359 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x20);
1360 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G)
1361 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x30);
1362 else
1363 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x20);
1364 rtl_write_byte(rtlpriv, 0x606, 0x30);
1365 }
1366
1367 void rtl92de_set_beacon_interval(struct ieee80211_hw *hw)
1368 {
1369 struct rtl_priv *rtlpriv = rtl_priv(hw);
1370 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1371 u16 bcn_interval = mac->beacon_interval;
1372
1373 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1374 "beacon_interval:%d\n", bcn_interval);
1375 rtl92de_disable_interrupt(hw);
1376 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1377 rtl92de_enable_interrupt(hw);
1378 }
1379
1380 void rtl92de_update_interrupt_mask(struct ieee80211_hw *hw,
1381 u32 add_msr, u32 rm_msr)
1382 {
1383 struct rtl_priv *rtlpriv = rtl_priv(hw);
1384 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1385
1386 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, "add_msr:%x, rm_msr:%x\n",
1387 add_msr, rm_msr);
1388 if (add_msr)
1389 rtlpci->irq_mask[0] |= add_msr;
1390 if (rm_msr)
1391 rtlpci->irq_mask[0] &= (~rm_msr);
1392 rtl92de_disable_interrupt(hw);
1393 rtl92de_enable_interrupt(hw);
1394 }
1395
1396 static void _rtl92de_readpowervalue_fromprom(struct txpower_info *pwrinfo,
1397 u8 *rom_content, bool autoloadfail)
1398 {
1399 u32 rfpath, eeaddr, group, offset1, offset2;
1400 u8 i;
1401
1402 memset(pwrinfo, 0, sizeof(struct txpower_info));
1403 if (autoloadfail) {
1404 for (group = 0; group < CHANNEL_GROUP_MAX; group++) {
1405 for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) {
1406 if (group < CHANNEL_GROUP_MAX_2G) {
1407 pwrinfo->cck_index[rfpath][group] =
1408 EEPROM_DEFAULT_TXPOWERLEVEL_2G;
1409 pwrinfo->ht40_1sindex[rfpath][group] =
1410 EEPROM_DEFAULT_TXPOWERLEVEL_2G;
1411 } else {
1412 pwrinfo->ht40_1sindex[rfpath][group] =
1413 EEPROM_DEFAULT_TXPOWERLEVEL_5G;
1414 }
1415 pwrinfo->ht40_2sindexdiff[rfpath][group] =
1416 EEPROM_DEFAULT_HT40_2SDIFF;
1417 pwrinfo->ht20indexdiff[rfpath][group] =
1418 EEPROM_DEFAULT_HT20_DIFF;
1419 pwrinfo->ofdmindexdiff[rfpath][group] =
1420 EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
1421 pwrinfo->ht40maxoffset[rfpath][group] =
1422 EEPROM_DEFAULT_HT40_PWRMAXOFFSET;
1423 pwrinfo->ht20maxoffset[rfpath][group] =
1424 EEPROM_DEFAULT_HT20_PWRMAXOFFSET;
1425 }
1426 }
1427 for (i = 0; i < 3; i++) {
1428 pwrinfo->tssi_a[i] = EEPROM_DEFAULT_TSSI;
1429 pwrinfo->tssi_b[i] = EEPROM_DEFAULT_TSSI;
1430 }
1431 return;
1432 }
1433
1434 /* Maybe autoload OK,buf the tx power index value is not filled.
1435 * If we find it, we set it to default value. */
1436 for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) {
1437 for (group = 0; group < CHANNEL_GROUP_MAX_2G; group++) {
1438 eeaddr = EEPROM_CCK_TX_PWR_INX_2G + (rfpath * 3)
1439 + group;
1440 pwrinfo->cck_index[rfpath][group] =
1441 (rom_content[eeaddr] == 0xFF) ?
1442 (eeaddr > 0x7B ?
1443 EEPROM_DEFAULT_TXPOWERLEVEL_5G :
1444 EEPROM_DEFAULT_TXPOWERLEVEL_2G) :
1445 rom_content[eeaddr];
1446 }
1447 }
1448 for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) {
1449 for (group = 0; group < CHANNEL_GROUP_MAX; group++) {
1450 offset1 = group / 3;
1451 offset2 = group % 3;
1452 eeaddr = EEPROM_HT40_1S_TX_PWR_INX_2G + (rfpath * 3) +
1453 offset2 + offset1 * 21;
1454 pwrinfo->ht40_1sindex[rfpath][group] =
1455 (rom_content[eeaddr] == 0xFF) ? (eeaddr > 0x7B ?
1456 EEPROM_DEFAULT_TXPOWERLEVEL_5G :
1457 EEPROM_DEFAULT_TXPOWERLEVEL_2G) :
1458 rom_content[eeaddr];
1459 }
1460 }
1461 /* These just for 92D efuse offset. */
1462 for (group = 0; group < CHANNEL_GROUP_MAX; group++) {
1463 for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) {
1464 int base1 = EEPROM_HT40_2S_TX_PWR_INX_DIFF_2G;
1465
1466 offset1 = group / 3;
1467 offset2 = group % 3;
1468
1469 if (rom_content[base1 + offset2 + offset1 * 21] != 0xFF)
1470 pwrinfo->ht40_2sindexdiff[rfpath][group] =
1471 (rom_content[base1 +
1472 offset2 + offset1 * 21] >> (rfpath * 4))
1473 & 0xF;
1474 else
1475 pwrinfo->ht40_2sindexdiff[rfpath][group] =
1476 EEPROM_DEFAULT_HT40_2SDIFF;
1477 if (rom_content[EEPROM_HT20_TX_PWR_INX_DIFF_2G + offset2
1478 + offset1 * 21] != 0xFF)
1479 pwrinfo->ht20indexdiff[rfpath][group] =
1480 (rom_content[EEPROM_HT20_TX_PWR_INX_DIFF_2G
1481 + offset2 + offset1 * 21] >> (rfpath * 4))
1482 & 0xF;
1483 else
1484 pwrinfo->ht20indexdiff[rfpath][group] =
1485 EEPROM_DEFAULT_HT20_DIFF;
1486 if (rom_content[EEPROM_OFDM_TX_PWR_INX_DIFF_2G + offset2
1487 + offset1 * 21] != 0xFF)
1488 pwrinfo->ofdmindexdiff[rfpath][group] =
1489 (rom_content[EEPROM_OFDM_TX_PWR_INX_DIFF_2G
1490 + offset2 + offset1 * 21] >> (rfpath * 4))
1491 & 0xF;
1492 else
1493 pwrinfo->ofdmindexdiff[rfpath][group] =
1494 EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
1495 if (rom_content[EEPROM_HT40_MAX_PWR_OFFSET_2G + offset2
1496 + offset1 * 21] != 0xFF)
1497 pwrinfo->ht40maxoffset[rfpath][group] =
1498 (rom_content[EEPROM_HT40_MAX_PWR_OFFSET_2G
1499 + offset2 + offset1 * 21] >> (rfpath * 4))
1500 & 0xF;
1501 else
1502 pwrinfo->ht40maxoffset[rfpath][group] =
1503 EEPROM_DEFAULT_HT40_PWRMAXOFFSET;
1504 if (rom_content[EEPROM_HT20_MAX_PWR_OFFSET_2G + offset2
1505 + offset1 * 21] != 0xFF)
1506 pwrinfo->ht20maxoffset[rfpath][group] =
1507 (rom_content[EEPROM_HT20_MAX_PWR_OFFSET_2G +
1508 offset2 + offset1 * 21] >> (rfpath * 4)) &
1509 0xF;
1510 else
1511 pwrinfo->ht20maxoffset[rfpath][group] =
1512 EEPROM_DEFAULT_HT20_PWRMAXOFFSET;
1513 }
1514 }
1515 if (rom_content[EEPROM_TSSI_A_5G] != 0xFF) {
1516 /* 5GL */
1517 pwrinfo->tssi_a[0] = rom_content[EEPROM_TSSI_A_5G] & 0x3F;
1518 pwrinfo->tssi_b[0] = rom_content[EEPROM_TSSI_B_5G] & 0x3F;
1519 /* 5GM */
1520 pwrinfo->tssi_a[1] = rom_content[EEPROM_TSSI_AB_5G] & 0x3F;
1521 pwrinfo->tssi_b[1] =
1522 (rom_content[EEPROM_TSSI_AB_5G] & 0xC0) >> 6 |
1523 (rom_content[EEPROM_TSSI_AB_5G + 1] & 0x0F) << 2;
1524 /* 5GH */
1525 pwrinfo->tssi_a[2] = (rom_content[EEPROM_TSSI_AB_5G + 1] &
1526 0xF0) >> 4 |
1527 (rom_content[EEPROM_TSSI_AB_5G + 2] & 0x03) << 4;
1528 pwrinfo->tssi_b[2] = (rom_content[EEPROM_TSSI_AB_5G + 2] &
1529 0xFC) >> 2;
1530 } else {
1531 for (i = 0; i < 3; i++) {
1532 pwrinfo->tssi_a[i] = EEPROM_DEFAULT_TSSI;
1533 pwrinfo->tssi_b[i] = EEPROM_DEFAULT_TSSI;
1534 }
1535 }
1536 }
1537
1538 static void _rtl92de_read_txpower_info(struct ieee80211_hw *hw,
1539 bool autoload_fail, u8 *hwinfo)
1540 {
1541 struct rtl_priv *rtlpriv = rtl_priv(hw);
1542 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1543 struct txpower_info pwrinfo;
1544 u8 tempval[2], i, pwr, diff;
1545 u32 ch, rfpath, group;
1546
1547 _rtl92de_readpowervalue_fromprom(&pwrinfo, hwinfo, autoload_fail);
1548 if (!autoload_fail) {
1549 /* bit0~2 */
1550 rtlefuse->eeprom_regulatory = (hwinfo[EEPROM_RF_OPT1] & 0x7);
1551 rtlefuse->eeprom_thermalmeter =
1552 hwinfo[EEPROM_THERMAL_METER] & 0x1f;
1553 rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_K];
1554 tempval[0] = hwinfo[EEPROM_IQK_DELTA] & 0x03;
1555 tempval[1] = (hwinfo[EEPROM_LCK_DELTA] & 0x0C) >> 2;
1556 rtlefuse->txpwr_fromeprom = true;
1557 if (IS_92D_D_CUT(rtlpriv->rtlhal.version) ||
1558 IS_92D_E_CUT(rtlpriv->rtlhal.version)) {
1559 rtlefuse->internal_pa_5g[0] =
1560 !((hwinfo[EEPROM_TSSI_A_5G] & BIT(6)) >> 6);
1561 rtlefuse->internal_pa_5g[1] =
1562 !((hwinfo[EEPROM_TSSI_B_5G] & BIT(6)) >> 6);
1563 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1564 "Is D cut,Internal PA0 %d Internal PA1 %d\n",
1565 rtlefuse->internal_pa_5g[0],
1566 rtlefuse->internal_pa_5g[1]);
1567 }
1568 rtlefuse->eeprom_c9 = hwinfo[EEPROM_RF_OPT6];
1569 rtlefuse->eeprom_cc = hwinfo[EEPROM_RF_OPT7];
1570 } else {
1571 rtlefuse->eeprom_regulatory = 0;
1572 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
1573 rtlefuse->crystalcap = EEPROM_DEFAULT_CRYSTALCAP;
1574 tempval[0] = tempval[1] = 3;
1575 }
1576
1577 /* Use default value to fill parameters if
1578 * efuse is not filled on some place. */
1579
1580 /* ThermalMeter from EEPROM */
1581 if (rtlefuse->eeprom_thermalmeter < 0x06 ||
1582 rtlefuse->eeprom_thermalmeter > 0x1c)
1583 rtlefuse->eeprom_thermalmeter = 0x12;
1584 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1585
1586 /* check XTAL_K */
1587 if (rtlefuse->crystalcap == 0xFF)
1588 rtlefuse->crystalcap = 0;
1589 if (rtlefuse->eeprom_regulatory > 3)
1590 rtlefuse->eeprom_regulatory = 0;
1591
1592 for (i = 0; i < 2; i++) {
1593 switch (tempval[i]) {
1594 case 0:
1595 tempval[i] = 5;
1596 break;
1597 case 1:
1598 tempval[i] = 4;
1599 break;
1600 case 2:
1601 tempval[i] = 3;
1602 break;
1603 case 3:
1604 default:
1605 tempval[i] = 0;
1606 break;
1607 }
1608 }
1609
1610 rtlefuse->delta_iqk = tempval[0];
1611 if (tempval[1] > 0)
1612 rtlefuse->delta_lck = tempval[1] - 1;
1613 if (rtlefuse->eeprom_c9 == 0xFF)
1614 rtlefuse->eeprom_c9 = 0x00;
1615 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1616 "EEPROMRegulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1617 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1618 "ThermalMeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1619 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1620 "CrystalCap = 0x%x\n", rtlefuse->crystalcap);
1621 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1622 "Delta_IQK = 0x%x Delta_LCK = 0x%x\n",
1623 rtlefuse->delta_iqk, rtlefuse->delta_lck);
1624
1625 for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) {
1626 for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++) {
1627 group = rtl92d_get_chnlgroup_fromarray((u8) ch);
1628 if (ch < CHANNEL_MAX_NUMBER_2G)
1629 rtlefuse->txpwrlevel_cck[rfpath][ch] =
1630 pwrinfo.cck_index[rfpath][group];
1631 rtlefuse->txpwrlevel_ht40_1s[rfpath][ch] =
1632 pwrinfo.ht40_1sindex[rfpath][group];
1633 rtlefuse->txpwr_ht20diff[rfpath][ch] =
1634 pwrinfo.ht20indexdiff[rfpath][group];
1635 rtlefuse->txpwr_legacyhtdiff[rfpath][ch] =
1636 pwrinfo.ofdmindexdiff[rfpath][group];
1637 rtlefuse->pwrgroup_ht20[rfpath][ch] =
1638 pwrinfo.ht20maxoffset[rfpath][group];
1639 rtlefuse->pwrgroup_ht40[rfpath][ch] =
1640 pwrinfo.ht40maxoffset[rfpath][group];
1641 pwr = pwrinfo.ht40_1sindex[rfpath][group];
1642 diff = pwrinfo.ht40_2sindexdiff[rfpath][group];
1643 rtlefuse->txpwrlevel_ht40_2s[rfpath][ch] =
1644 (pwr > diff) ? (pwr - diff) : 0;
1645 }
1646 }
1647 }
1648
1649 static void _rtl92de_read_macphymode_from_prom(struct ieee80211_hw *hw,
1650 u8 *content)
1651 {
1652 struct rtl_priv *rtlpriv = rtl_priv(hw);
1653 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1654 u8 macphy_crvalue = content[EEPROM_MAC_FUNCTION];
1655
1656 if (macphy_crvalue & BIT(3)) {
1657 rtlhal->macphymode = SINGLEMAC_SINGLEPHY;
1658 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1659 "MacPhyMode SINGLEMAC_SINGLEPHY\n");
1660 } else {
1661 rtlhal->macphymode = DUALMAC_DUALPHY;
1662 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1663 "MacPhyMode DUALMAC_DUALPHY\n");
1664 }
1665 }
1666
1667 static void _rtl92de_read_macphymode_and_bandtype(struct ieee80211_hw *hw,
1668 u8 *content)
1669 {
1670 _rtl92de_read_macphymode_from_prom(hw, content);
1671 rtl92d_phy_config_macphymode(hw);
1672 rtl92d_phy_config_macphymode_info(hw);
1673 }
1674
1675 static void _rtl92de_efuse_update_chip_version(struct ieee80211_hw *hw)
1676 {
1677 struct rtl_priv *rtlpriv = rtl_priv(hw);
1678 enum version_8192d chipver = rtlpriv->rtlhal.version;
1679 u8 cutvalue[2];
1680 u16 chipvalue;
1681
1682 rtlpriv->intf_ops->read_efuse_byte(hw, EEPROME_CHIP_VERSION_H,
1683 &cutvalue[1]);
1684 rtlpriv->intf_ops->read_efuse_byte(hw, EEPROME_CHIP_VERSION_L,
1685 &cutvalue[0]);
1686 chipvalue = (cutvalue[1] << 8) | cutvalue[0];
1687 switch (chipvalue) {
1688 case 0xAA55:
1689 chipver |= CHIP_92D_C_CUT;
1690 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "C-CUT!!!\n");
1691 break;
1692 case 0x9966:
1693 chipver |= CHIP_92D_D_CUT;
1694 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "D-CUT!!!\n");
1695 break;
1696 case 0xCC33:
1697 chipver |= CHIP_92D_E_CUT;
1698 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "E-CUT!!!\n");
1699 break;
1700 default:
1701 chipver |= CHIP_92D_D_CUT;
1702 pr_err("Unknown CUT!\n");
1703 break;
1704 }
1705 rtlpriv->rtlhal.version = chipver;
1706 }
1707
1708 static void _rtl92de_read_adapter_info(struct ieee80211_hw *hw)
1709 {
1710 struct rtl_priv *rtlpriv = rtl_priv(hw);
1711 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1712 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1713 int params[] = {RTL8190_EEPROM_ID, EEPROM_VID, EEPROM_DID,
1714 EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR_MAC0_92D,
1715 EEPROM_CHANNEL_PLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID,
1716 COUNTRY_CODE_WORLD_WIDE_13};
1717 int i;
1718 u16 usvalue;
1719 u8 *hwinfo;
1720
1721 hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL);
1722 if (!hwinfo)
1723 return;
1724
1725 if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params))
1726 goto exit;
1727
1728 _rtl92de_efuse_update_chip_version(hw);
1729 _rtl92de_read_macphymode_and_bandtype(hw, hwinfo);
1730
1731 /* Read Permanent MAC address for 2nd interface */
1732 if (rtlhal->interfaceindex != 0) {
1733 for (i = 0; i < 6; i += 2) {
1734 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR_MAC1_92D + i];
1735 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
1736 }
1737 }
1738 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR,
1739 rtlefuse->dev_addr);
1740 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "%pM\n", rtlefuse->dev_addr);
1741 _rtl92de_read_txpower_info(hw, rtlefuse->autoload_failflag, hwinfo);
1742
1743 /* Read Channel Plan */
1744 switch (rtlhal->bandset) {
1745 case BAND_ON_2_4G:
1746 rtlefuse->channel_plan = COUNTRY_CODE_TELEC;
1747 break;
1748 case BAND_ON_5G:
1749 rtlefuse->channel_plan = COUNTRY_CODE_FCC;
1750 break;
1751 case BAND_ON_BOTH:
1752 rtlefuse->channel_plan = COUNTRY_CODE_FCC;
1753 break;
1754 default:
1755 rtlefuse->channel_plan = COUNTRY_CODE_FCC;
1756 break;
1757 }
1758 rtlefuse->txpwr_fromeprom = true;
1759 exit:
1760 kfree(hwinfo);
1761 }
1762
1763 void rtl92de_read_eeprom_info(struct ieee80211_hw *hw)
1764 {
1765 struct rtl_priv *rtlpriv = rtl_priv(hw);
1766 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1767 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1768 u8 tmp_u1b;
1769
1770 rtlhal->version = _rtl92de_read_chip_version(hw);
1771 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
1772 rtlefuse->autoload_status = tmp_u1b;
1773 if (tmp_u1b & BIT(4)) {
1774 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
1775 rtlefuse->epromtype = EEPROM_93C46;
1776 } else {
1777 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
1778 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1779 }
1780 if (tmp_u1b & BIT(5)) {
1781 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1782
1783 rtlefuse->autoload_failflag = false;
1784 _rtl92de_read_adapter_info(hw);
1785 } else {
1786 pr_err("Autoload ERR!!\n");
1787 }
1788 return;
1789 }
1790
1791 static void rtl92de_update_hal_rate_table(struct ieee80211_hw *hw,
1792 struct ieee80211_sta *sta)
1793 {
1794 struct rtl_priv *rtlpriv = rtl_priv(hw);
1795 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1796 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1797 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1798 u32 ratr_value;
1799 u8 ratr_index = 0;
1800 u8 nmode = mac->ht_enable;
1801 u8 mimo_ps = IEEE80211_SMPS_OFF;
1802 u16 shortgi_rate;
1803 u32 tmp_ratr_value;
1804 u8 curtxbw_40mhz = mac->bw_40;
1805 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1806 1 : 0;
1807 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1808 1 : 0;
1809 enum wireless_mode wirelessmode = mac->mode;
1810
1811 if (rtlhal->current_bandtype == BAND_ON_5G)
1812 ratr_value = sta->supp_rates[1] << 4;
1813 else
1814 ratr_value = sta->supp_rates[0];
1815 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1816 sta->ht_cap.mcs.rx_mask[0] << 12);
1817 switch (wirelessmode) {
1818 case WIRELESS_MODE_A:
1819 ratr_value &= 0x00000FF0;
1820 break;
1821 case WIRELESS_MODE_B:
1822 if (ratr_value & 0x0000000c)
1823 ratr_value &= 0x0000000d;
1824 else
1825 ratr_value &= 0x0000000f;
1826 break;
1827 case WIRELESS_MODE_G:
1828 ratr_value &= 0x00000FF5;
1829 break;
1830 case WIRELESS_MODE_N_24G:
1831 case WIRELESS_MODE_N_5G:
1832 nmode = 1;
1833 if (mimo_ps == IEEE80211_SMPS_STATIC) {
1834 ratr_value &= 0x0007F005;
1835 } else {
1836 u32 ratr_mask;
1837
1838 if (get_rf_type(rtlphy) == RF_1T2R ||
1839 get_rf_type(rtlphy) == RF_1T1R) {
1840 ratr_mask = 0x000ff005;
1841 } else {
1842 ratr_mask = 0x0f0ff005;
1843 }
1844
1845 ratr_value &= ratr_mask;
1846 }
1847 break;
1848 default:
1849 if (rtlphy->rf_type == RF_1T2R)
1850 ratr_value &= 0x000ff0ff;
1851 else
1852 ratr_value &= 0x0f0ff0ff;
1853
1854 break;
1855 }
1856 ratr_value &= 0x0FFFFFFF;
1857 if (nmode && ((curtxbw_40mhz && curshortgi_40mhz) ||
1858 (!curtxbw_40mhz && curshortgi_20mhz))) {
1859 ratr_value |= 0x10000000;
1860 tmp_ratr_value = (ratr_value >> 12);
1861 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
1862 if ((1 << shortgi_rate) & tmp_ratr_value)
1863 break;
1864 }
1865 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
1866 (shortgi_rate << 4) | (shortgi_rate);
1867 }
1868 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
1869 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n",
1870 rtl_read_dword(rtlpriv, REG_ARFR0));
1871 }
1872
1873 static void rtl92de_update_hal_rate_mask(struct ieee80211_hw *hw,
1874 struct ieee80211_sta *sta, u8 rssi_level, bool update_bw)
1875 {
1876 struct rtl_priv *rtlpriv = rtl_priv(hw);
1877 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1878 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1879 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1880 struct rtl_sta_info *sta_entry = NULL;
1881 u32 ratr_bitmap;
1882 u8 ratr_index;
1883 u8 curtxbw_40mhz = (sta->bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0;
1884 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1885 1 : 0;
1886 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1887 1 : 0;
1888 enum wireless_mode wirelessmode = 0;
1889 bool shortgi = false;
1890 u32 value[2];
1891 u8 macid = 0;
1892 u8 mimo_ps = IEEE80211_SMPS_OFF;
1893
1894 sta_entry = (struct rtl_sta_info *) sta->drv_priv;
1895 mimo_ps = sta_entry->mimo_ps;
1896 wirelessmode = sta_entry->wireless_mode;
1897 if (mac->opmode == NL80211_IFTYPE_STATION)
1898 curtxbw_40mhz = mac->bw_40;
1899 else if (mac->opmode == NL80211_IFTYPE_AP ||
1900 mac->opmode == NL80211_IFTYPE_ADHOC)
1901 macid = sta->aid + 1;
1902
1903 if (rtlhal->current_bandtype == BAND_ON_5G)
1904 ratr_bitmap = sta->supp_rates[1] << 4;
1905 else
1906 ratr_bitmap = sta->supp_rates[0];
1907 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1908 sta->ht_cap.mcs.rx_mask[0] << 12);
1909 switch (wirelessmode) {
1910 case WIRELESS_MODE_B:
1911 ratr_index = RATR_INX_WIRELESS_B;
1912 if (ratr_bitmap & 0x0000000c)
1913 ratr_bitmap &= 0x0000000d;
1914 else
1915 ratr_bitmap &= 0x0000000f;
1916 break;
1917 case WIRELESS_MODE_G:
1918 ratr_index = RATR_INX_WIRELESS_GB;
1919
1920 if (rssi_level == 1)
1921 ratr_bitmap &= 0x00000f00;
1922 else if (rssi_level == 2)
1923 ratr_bitmap &= 0x00000ff0;
1924 else
1925 ratr_bitmap &= 0x00000ff5;
1926 break;
1927 case WIRELESS_MODE_A:
1928 ratr_index = RATR_INX_WIRELESS_G;
1929 ratr_bitmap &= 0x00000ff0;
1930 break;
1931 case WIRELESS_MODE_N_24G:
1932 case WIRELESS_MODE_N_5G:
1933 if (wirelessmode == WIRELESS_MODE_N_24G)
1934 ratr_index = RATR_INX_WIRELESS_NGB;
1935 else
1936 ratr_index = RATR_INX_WIRELESS_NG;
1937 if (mimo_ps == IEEE80211_SMPS_STATIC) {
1938 if (rssi_level == 1)
1939 ratr_bitmap &= 0x00070000;
1940 else if (rssi_level == 2)
1941 ratr_bitmap &= 0x0007f000;
1942 else
1943 ratr_bitmap &= 0x0007f005;
1944 } else {
1945 if (rtlphy->rf_type == RF_1T2R ||
1946 rtlphy->rf_type == RF_1T1R) {
1947 if (curtxbw_40mhz) {
1948 if (rssi_level == 1)
1949 ratr_bitmap &= 0x000f0000;
1950 else if (rssi_level == 2)
1951 ratr_bitmap &= 0x000ff000;
1952 else
1953 ratr_bitmap &= 0x000ff015;
1954 } else {
1955 if (rssi_level == 1)
1956 ratr_bitmap &= 0x000f0000;
1957 else if (rssi_level == 2)
1958 ratr_bitmap &= 0x000ff000;
1959 else
1960 ratr_bitmap &= 0x000ff005;
1961 }
1962 } else {
1963 if (curtxbw_40mhz) {
1964 if (rssi_level == 1)
1965 ratr_bitmap &= 0x0f0f0000;
1966 else if (rssi_level == 2)
1967 ratr_bitmap &= 0x0f0ff000;
1968 else
1969 ratr_bitmap &= 0x0f0ff015;
1970 } else {
1971 if (rssi_level == 1)
1972 ratr_bitmap &= 0x0f0f0000;
1973 else if (rssi_level == 2)
1974 ratr_bitmap &= 0x0f0ff000;
1975 else
1976 ratr_bitmap &= 0x0f0ff005;
1977 }
1978 }
1979 }
1980 if ((curtxbw_40mhz && curshortgi_40mhz) ||
1981 (!curtxbw_40mhz && curshortgi_20mhz)) {
1982
1983 if (macid == 0)
1984 shortgi = true;
1985 else if (macid == 1)
1986 shortgi = false;
1987 }
1988 break;
1989 default:
1990 ratr_index = RATR_INX_WIRELESS_NGB;
1991
1992 if (rtlphy->rf_type == RF_1T2R)
1993 ratr_bitmap &= 0x000ff0ff;
1994 else
1995 ratr_bitmap &= 0x0f0ff0ff;
1996 break;
1997 }
1998
1999 value[0] = (ratr_bitmap & 0x0fffffff) | (ratr_index << 28);
2000 value[1] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
2001 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2002 "ratr_bitmap :%x value0:%x value1:%x\n",
2003 ratr_bitmap, value[0], value[1]);
2004 rtl92d_fill_h2c_cmd(hw, H2C_RA_MASK, 5, (u8 *) value);
2005 if (macid != 0)
2006 sta_entry->ratr_index = ratr_index;
2007 }
2008
2009 void rtl92de_update_hal_rate_tbl(struct ieee80211_hw *hw,
2010 struct ieee80211_sta *sta, u8 rssi_level, bool update_bw)
2011 {
2012 struct rtl_priv *rtlpriv = rtl_priv(hw);
2013
2014 if (rtlpriv->dm.useramask)
2015 rtl92de_update_hal_rate_mask(hw, sta, rssi_level, update_bw);
2016 else
2017 rtl92de_update_hal_rate_table(hw, sta);
2018 }
2019
2020 void rtl92de_update_channel_access_setting(struct ieee80211_hw *hw)
2021 {
2022 struct rtl_priv *rtlpriv = rtl_priv(hw);
2023 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2024 u16 sifs_timer;
2025
2026 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2027 &mac->slot_time);
2028 if (!mac->ht_enable)
2029 sifs_timer = 0x0a0a;
2030 else
2031 sifs_timer = 0x1010;
2032 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2033 }
2034
2035 bool rtl92de_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2036 {
2037 struct rtl_priv *rtlpriv = rtl_priv(hw);
2038 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2039 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2040 enum rf_pwrstate e_rfpowerstate_toset;
2041 u8 u1tmp;
2042 bool actuallyset = false;
2043 unsigned long flag;
2044
2045 if (rtlpci->being_init_adapter)
2046 return false;
2047 if (ppsc->swrf_processing)
2048 return false;
2049 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2050 if (ppsc->rfchange_inprogress) {
2051 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2052 return false;
2053 } else {
2054 ppsc->rfchange_inprogress = true;
2055 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2056 }
2057 rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, rtl_read_byte(rtlpriv,
2058 REG_MAC_PINMUX_CFG) & ~(BIT(3)));
2059 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
2060 e_rfpowerstate_toset = (u1tmp & BIT(3)) ? ERFON : ERFOFF;
2061 if (ppsc->hwradiooff && (e_rfpowerstate_toset == ERFON)) {
2062 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2063 "GPIOChangeRF - HW Radio ON, RF ON\n");
2064 e_rfpowerstate_toset = ERFON;
2065 ppsc->hwradiooff = false;
2066 actuallyset = true;
2067 } else if (!ppsc->hwradiooff && (e_rfpowerstate_toset == ERFOFF)) {
2068 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2069 "GPIOChangeRF - HW Radio OFF, RF OFF\n");
2070 e_rfpowerstate_toset = ERFOFF;
2071 ppsc->hwradiooff = true;
2072 actuallyset = true;
2073 }
2074 if (actuallyset) {
2075 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2076 ppsc->rfchange_inprogress = false;
2077 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2078 } else {
2079 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2080 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2081 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2082 ppsc->rfchange_inprogress = false;
2083 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2084 }
2085 *valid = 1;
2086 return !ppsc->hwradiooff;
2087 }
2088
2089 void rtl92de_set_key(struct ieee80211_hw *hw, u32 key_index,
2090 u8 *p_macaddr, bool is_group, u8 enc_algo,
2091 bool is_wepkey, bool clear_all)
2092 {
2093 struct rtl_priv *rtlpriv = rtl_priv(hw);
2094 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2095 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2096 u8 *macaddr = p_macaddr;
2097 u32 entry_id;
2098 bool is_pairwise = false;
2099 static u8 cam_const_addr[4][6] = {
2100 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2101 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2102 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2103 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2104 };
2105 static u8 cam_const_broad[] = {
2106 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2107 };
2108
2109 if (clear_all) {
2110 u8 idx;
2111 u8 cam_offset = 0;
2112 u8 clear_number = 5;
2113 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2114 for (idx = 0; idx < clear_number; idx++) {
2115 rtl_cam_mark_invalid(hw, cam_offset + idx);
2116 rtl_cam_empty_entry(hw, cam_offset + idx);
2117
2118 if (idx < 5) {
2119 memset(rtlpriv->sec.key_buf[idx], 0,
2120 MAX_KEY_LEN);
2121 rtlpriv->sec.key_len[idx] = 0;
2122 }
2123 }
2124 } else {
2125 switch (enc_algo) {
2126 case WEP40_ENCRYPTION:
2127 enc_algo = CAM_WEP40;
2128 break;
2129 case WEP104_ENCRYPTION:
2130 enc_algo = CAM_WEP104;
2131 break;
2132 case TKIP_ENCRYPTION:
2133 enc_algo = CAM_TKIP;
2134 break;
2135 case AESCCMP_ENCRYPTION:
2136 enc_algo = CAM_AES;
2137 break;
2138 default:
2139 pr_err("switch case %#x not processed\n",
2140 enc_algo);
2141 enc_algo = CAM_TKIP;
2142 break;
2143 }
2144 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2145 macaddr = cam_const_addr[key_index];
2146 entry_id = key_index;
2147 } else {
2148 if (is_group) {
2149 macaddr = cam_const_broad;
2150 entry_id = key_index;
2151 } else {
2152 if (mac->opmode == NL80211_IFTYPE_AP) {
2153 entry_id = rtl_cam_get_free_entry(hw,
2154 p_macaddr);
2155 if (entry_id >= TOTAL_CAM_ENTRY) {
2156 pr_err("Can not find free hw security cam entry\n");
2157 return;
2158 }
2159 } else {
2160 entry_id = CAM_PAIRWISE_KEY_POSITION;
2161 }
2162 key_index = PAIRWISE_KEYIDX;
2163 is_pairwise = true;
2164 }
2165 }
2166 if (rtlpriv->sec.key_len[key_index] == 0) {
2167 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2168 "delete one entry, entry_id is %d\n",
2169 entry_id);
2170 if (mac->opmode == NL80211_IFTYPE_AP)
2171 rtl_cam_del_entry(hw, p_macaddr);
2172 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2173 } else {
2174 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2175 "The insert KEY length is %d\n",
2176 rtlpriv->sec.key_len[PAIRWISE_KEYIDX]);
2177 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2178 "The insert KEY is %x %x\n",
2179 rtlpriv->sec.key_buf[0][0],
2180 rtlpriv->sec.key_buf[0][1]);
2181 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2182 "add one entry\n");
2183 if (is_pairwise) {
2184 RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD,
2185 "Pairwise Key content",
2186 rtlpriv->sec.pairwise_key,
2187 rtlpriv->
2188 sec.key_len[PAIRWISE_KEYIDX]);
2189 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2190 "set Pairwise key\n");
2191 rtl_cam_add_one_entry(hw, macaddr, key_index,
2192 entry_id, enc_algo,
2193 CAM_CONFIG_NO_USEDK,
2194 rtlpriv->
2195 sec.key_buf[key_index]);
2196 } else {
2197 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2198 "set group key\n");
2199 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2200 rtl_cam_add_one_entry(hw,
2201 rtlefuse->dev_addr,
2202 PAIRWISE_KEYIDX,
2203 CAM_PAIRWISE_KEY_POSITION,
2204 enc_algo, CAM_CONFIG_NO_USEDK,
2205 rtlpriv->sec.key_buf[entry_id]);
2206 }
2207 rtl_cam_add_one_entry(hw, macaddr, key_index,
2208 entry_id, enc_algo,
2209 CAM_CONFIG_NO_USEDK,
2210 rtlpriv->sec.key_buf
2211 [entry_id]);
2212 }
2213 }
2214 }
2215 }
2216
2217 void rtl92de_suspend(struct ieee80211_hw *hw)
2218 {
2219 struct rtl_priv *rtlpriv = rtl_priv(hw);
2220
2221 rtlpriv->rtlhal.macphyctl_reg = rtl_read_byte(rtlpriv,
2222 REG_MAC_PHY_CTRL_NORMAL);
2223 }
2224
2225 void rtl92de_resume(struct ieee80211_hw *hw)
2226 {
2227 struct rtl_priv *rtlpriv = rtl_priv(hw);
2228
2229 rtl_write_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL,
2230 rtlpriv->rtlhal.macphyctl_reg);
2231 }
Linux with added FPC-III support