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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / nvme / host / pci.c
blob365a2ddbeaa762f84a51106163cc915e2c2919ef
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * NVM Express device driver
4 * Copyright (c) 2011-2014, Intel Corporation.
5 */
6
7 #include <linux/aer.h>
8 #include <linux/async.h>
9 #include <linux/blkdev.h>
10 #include <linux/blk-mq.h>
11 #include <linux/blk-mq-pci.h>
12 #include <linux/dmi.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/io.h>
16 #include <linux/mm.h>
17 #include <linux/module.h>
18 #include <linux/mutex.h>
19 #include <linux/once.h>
20 #include <linux/pci.h>
21 #include <linux/suspend.h>
22 #include <linux/t10-pi.h>
23 #include <linux/types.h>
24 #include <linux/io-64-nonatomic-lo-hi.h>
25 #include <linux/sed-opal.h>
26 #include <linux/pci-p2pdma.h>
27
28 #include "trace.h"
29 #include "nvme.h"
30
31 #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
32 #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
33
34 #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
35
36 /*
37 * These can be higher, but we need to ensure that any command doesn't
38 * require an sg allocation that needs more than a page of data.
39 */
40 #define NVME_MAX_KB_SZ 4096
41 #define NVME_MAX_SEGS 127
42
43 static int use_threaded_interrupts;
44 module_param(use_threaded_interrupts, int, 0);
45
46 static bool use_cmb_sqes = true;
47 module_param(use_cmb_sqes, bool, 0444);
48 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
49
50 static unsigned int max_host_mem_size_mb = 128;
51 module_param(max_host_mem_size_mb, uint, 0444);
52 MODULE_PARM_DESC(max_host_mem_size_mb,
53 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
54
55 static unsigned int sgl_threshold = SZ_32K;
56 module_param(sgl_threshold, uint, 0644);
57 MODULE_PARM_DESC(sgl_threshold,
58 "Use SGLs when average request segment size is larger or equal to "
59 "this size. Use 0 to disable SGLs.");
60
61 static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
62 static const struct kernel_param_ops io_queue_depth_ops = {
63 .set = io_queue_depth_set,
64 .get = param_get_int,
65 };
66
67 static int io_queue_depth = 1024;
68 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
69 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
70
71 static unsigned int write_queues;
72 module_param(write_queues, uint, 0644);
73 MODULE_PARM_DESC(write_queues,
74 "Number of queues to use for writes. If not set, reads and writes "
75 "will share a queue set.");
76
77 static unsigned int poll_queues;
78 module_param(poll_queues, uint, 0644);
79 MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
80
81 struct nvme_dev;
82 struct nvme_queue;
83
84 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
85 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
86
87 /*
88 * Represents an NVM Express device. Each nvme_dev is a PCI function.
89 */
90 struct nvme_dev {
91 struct nvme_queue *queues;
92 struct blk_mq_tag_set tagset;
93 struct blk_mq_tag_set admin_tagset;
94 u32 __iomem *dbs;
95 struct device *dev;
96 struct dma_pool *prp_page_pool;
97 struct dma_pool *prp_small_pool;
98 unsigned online_queues;
99 unsigned max_qid;
100 unsigned io_queues[HCTX_MAX_TYPES];
101 unsigned int num_vecs;
102 int q_depth;
103 int io_sqes;
104 u32 db_stride;
105 void __iomem *bar;
106 unsigned long bar_mapped_size;
107 struct work_struct remove_work;
108 struct mutex shutdown_lock;
109 bool subsystem;
110 u64 cmb_size;
111 bool cmb_use_sqes;
112 u32 cmbsz;
113 u32 cmbloc;
114 struct nvme_ctrl ctrl;
115 u32 last_ps;
116
117 mempool_t *iod_mempool;
118
119 /* shadow doorbell buffer support: */
120 u32 *dbbuf_dbs;
121 dma_addr_t dbbuf_dbs_dma_addr;
122 u32 *dbbuf_eis;
123 dma_addr_t dbbuf_eis_dma_addr;
124
125 /* host memory buffer support: */
126 u64 host_mem_size;
127 u32 nr_host_mem_descs;
128 dma_addr_t host_mem_descs_dma;
129 struct nvme_host_mem_buf_desc *host_mem_descs;
130 void **host_mem_desc_bufs;
131 };
132
133 static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
134 {
135 int n = 0, ret;
136
137 ret = kstrtoint(val, 10, &n);
138 if (ret != 0 || n < 2)
139 return -EINVAL;
140
141 return param_set_int(val, kp);
142 }
143
144 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
145 {
146 return qid * 2 * stride;
147 }
148
149 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
150 {
151 return (qid * 2 + 1) * stride;
152 }
153
154 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
155 {
156 return container_of(ctrl, struct nvme_dev, ctrl);
157 }
158
159 /*
160 * An NVM Express queue. Each device has at least two (one for admin
161 * commands and one for I/O commands).
162 */
163 struct nvme_queue {
164 struct nvme_dev *dev;
165 spinlock_t sq_lock;
166 void *sq_cmds;
167 /* only used for poll queues: */
168 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
169 volatile struct nvme_completion *cqes;
170 struct blk_mq_tags **tags;
171 dma_addr_t sq_dma_addr;
172 dma_addr_t cq_dma_addr;
173 u32 __iomem *q_db;
174 u16 q_depth;
175 u16 cq_vector;
176 u16 sq_tail;
177 u16 last_sq_tail;
178 u16 cq_head;
179 u16 qid;
180 u8 cq_phase;
181 u8 sqes;
182 unsigned long flags;
183 #define NVMEQ_ENABLED 0
184 #define NVMEQ_SQ_CMB 1
185 #define NVMEQ_DELETE_ERROR 2
186 #define NVMEQ_POLLED 3
187 u32 *dbbuf_sq_db;
188 u32 *dbbuf_cq_db;
189 u32 *dbbuf_sq_ei;
190 u32 *dbbuf_cq_ei;
191 struct completion delete_done;
192 };
193
194 /*
195 * The nvme_iod describes the data in an I/O.
196 *
197 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
198 * to the actual struct scatterlist.
199 */
200 struct nvme_iod {
201 struct nvme_request req;
202 struct nvme_queue *nvmeq;
203 bool use_sgl;
204 int aborted;
205 int npages; /* In the PRP list. 0 means small pool in use */
206 int nents; /* Used in scatterlist */
207 dma_addr_t first_dma;
208 unsigned int dma_len; /* length of single DMA segment mapping */
209 dma_addr_t meta_dma;
210 struct scatterlist *sg;
211 };
212
213 static unsigned int max_io_queues(void)
214 {
215 return num_possible_cpus() + write_queues + poll_queues;
216 }
217
218 static unsigned int max_queue_count(void)
219 {
220 /* IO queues + admin queue */
221 return 1 + max_io_queues();
222 }
223
224 static inline unsigned int nvme_dbbuf_size(u32 stride)
225 {
226 return (max_queue_count() * 8 * stride);
227 }
228
229 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
230 {
231 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
232
233 if (dev->dbbuf_dbs)
234 return 0;
235
236 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
237 &dev->dbbuf_dbs_dma_addr,
238 GFP_KERNEL);
239 if (!dev->dbbuf_dbs)
240 return -ENOMEM;
241 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
242 &dev->dbbuf_eis_dma_addr,
243 GFP_KERNEL);
244 if (!dev->dbbuf_eis) {
245 dma_free_coherent(dev->dev, mem_size,
246 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
247 dev->dbbuf_dbs = NULL;
248 return -ENOMEM;
249 }
250
251 return 0;
252 }
253
254 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
255 {
256 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
257
258 if (dev->dbbuf_dbs) {
259 dma_free_coherent(dev->dev, mem_size,
260 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
261 dev->dbbuf_dbs = NULL;
262 }
263 if (dev->dbbuf_eis) {
264 dma_free_coherent(dev->dev, mem_size,
265 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
266 dev->dbbuf_eis = NULL;
267 }
268 }
269
270 static void nvme_dbbuf_init(struct nvme_dev *dev,
271 struct nvme_queue *nvmeq, int qid)
272 {
273 if (!dev->dbbuf_dbs || !qid)
274 return;
275
276 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
277 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
278 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
279 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
280 }
281
282 static void nvme_dbbuf_set(struct nvme_dev *dev)
283 {
284 struct nvme_command c;
285
286 if (!dev->dbbuf_dbs)
287 return;
288
289 memset(&c, 0, sizeof(c));
290 c.dbbuf.opcode = nvme_admin_dbbuf;
291 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
292 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
293
294 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
295 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
296 /* Free memory and continue on */
297 nvme_dbbuf_dma_free(dev);
298 }
299 }
300
301 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
302 {
303 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
304 }
305
306 /* Update dbbuf and return true if an MMIO is required */
307 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
308 volatile u32 *dbbuf_ei)
309 {
310 if (dbbuf_db) {
311 u16 old_value;
312
313 /*
314 * Ensure that the queue is written before updating
315 * the doorbell in memory
316 */
317 wmb();
318
319 old_value = *dbbuf_db;
320 *dbbuf_db = value;
321
322 /*
323 * Ensure that the doorbell is updated before reading the event
324 * index from memory. The controller needs to provide similar
325 * ordering to ensure the envent index is updated before reading
326 * the doorbell.
327 */
328 mb();
329
330 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
331 return false;
332 }
333
334 return true;
335 }
336
337 /*
338 * Will slightly overestimate the number of pages needed. This is OK
339 * as it only leads to a small amount of wasted memory for the lifetime of
340 * the I/O.
341 */
342 static int nvme_npages(unsigned size, struct nvme_dev *dev)
343 {
344 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
345 dev->ctrl.page_size);
346 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
347 }
348
349 /*
350 * Calculates the number of pages needed for the SGL segments. For example a 4k
351 * page can accommodate 256 SGL descriptors.
352 */
353 static int nvme_pci_npages_sgl(unsigned int num_seg)
354 {
355 return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE);
356 }
357
358 static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev,
359 unsigned int size, unsigned int nseg, bool use_sgl)
360 {
361 size_t alloc_size;
362
363 if (use_sgl)
364 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg);
365 else
366 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev);
367
368 return alloc_size + sizeof(struct scatterlist) * nseg;
369 }
370
371 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
372 unsigned int hctx_idx)
373 {
374 struct nvme_dev *dev = data;
375 struct nvme_queue *nvmeq = &dev->queues[0];
376
377 WARN_ON(hctx_idx != 0);
378 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
379 WARN_ON(nvmeq->tags);
380
381 hctx->driver_data = nvmeq;
382 nvmeq->tags = &dev->admin_tagset.tags[0];
383 return 0;
384 }
385
386 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
387 {
388 struct nvme_queue *nvmeq = hctx->driver_data;
389
390 nvmeq->tags = NULL;
391 }
392
393 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
394 unsigned int hctx_idx)
395 {
396 struct nvme_dev *dev = data;
397 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
398
399 if (!nvmeq->tags)
400 nvmeq->tags = &dev->tagset.tags[hctx_idx];
401
402 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
403 hctx->driver_data = nvmeq;
404 return 0;
405 }
406
407 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
408 unsigned int hctx_idx, unsigned int numa_node)
409 {
410 struct nvme_dev *dev = set->driver_data;
411 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
412 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
413 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
414
415 BUG_ON(!nvmeq);
416 iod->nvmeq = nvmeq;
417
418 nvme_req(req)->ctrl = &dev->ctrl;
419 return 0;
420 }
421
422 static int queue_irq_offset(struct nvme_dev *dev)
423 {
424 /* if we have more than 1 vec, admin queue offsets us by 1 */
425 if (dev->num_vecs > 1)
426 return 1;
427
428 return 0;
429 }
430
431 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
432 {
433 struct nvme_dev *dev = set->driver_data;
434 int i, qoff, offset;
435
436 offset = queue_irq_offset(dev);
437 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
438 struct blk_mq_queue_map *map = &set->map[i];
439
440 map->nr_queues = dev->io_queues[i];
441 if (!map->nr_queues) {
442 BUG_ON(i == HCTX_TYPE_DEFAULT);
443 continue;
444 }
445
446 /*
447 * The poll queue(s) doesn't have an IRQ (and hence IRQ
448 * affinity), so use the regular blk-mq cpu mapping
449 */
450 map->queue_offset = qoff;
451 if (i != HCTX_TYPE_POLL && offset)
452 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
453 else
454 blk_mq_map_queues(map);
455 qoff += map->nr_queues;
456 offset += map->nr_queues;
457 }
458
459 return 0;
460 }
461
462 /*
463 * Write sq tail if we are asked to, or if the next command would wrap.
464 */
465 static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
466 {
467 if (!write_sq) {
468 u16 next_tail = nvmeq->sq_tail + 1;
469
470 if (next_tail == nvmeq->q_depth)
471 next_tail = 0;
472 if (next_tail != nvmeq->last_sq_tail)
473 return;
474 }
475
476 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
477 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
478 writel(nvmeq->sq_tail, nvmeq->q_db);
479 nvmeq->last_sq_tail = nvmeq->sq_tail;
480 }
481
482 /**
483 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
484 * @nvmeq: The queue to use
485 * @cmd: The command to send
486 * @write_sq: whether to write to the SQ doorbell
487 */
488 static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
489 bool write_sq)
490 {
491 spin_lock(&nvmeq->sq_lock);
492 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
493 cmd, sizeof(*cmd));
494 if (++nvmeq->sq_tail == nvmeq->q_depth)
495 nvmeq->sq_tail = 0;
496 nvme_write_sq_db(nvmeq, write_sq);
497 spin_unlock(&nvmeq->sq_lock);
498 }
499
500 static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
501 {
502 struct nvme_queue *nvmeq = hctx->driver_data;
503
504 spin_lock(&nvmeq->sq_lock);
505 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
506 nvme_write_sq_db(nvmeq, true);
507 spin_unlock(&nvmeq->sq_lock);
508 }
509
510 static void **nvme_pci_iod_list(struct request *req)
511 {
512 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
513 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
514 }
515
516 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
517 {
518 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
519 int nseg = blk_rq_nr_phys_segments(req);
520 unsigned int avg_seg_size;
521
522 if (nseg == 0)
523 return false;
524
525 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
526
527 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
528 return false;
529 if (!iod->nvmeq->qid)
530 return false;
531 if (!sgl_threshold || avg_seg_size < sgl_threshold)
532 return false;
533 return true;
534 }
535
536 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
537 {
538 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
539 const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1;
540 dma_addr_t dma_addr = iod->first_dma, next_dma_addr;
541 int i;
542
543 if (iod->dma_len) {
544 dma_unmap_page(dev->dev, dma_addr, iod->dma_len,
545 rq_dma_dir(req));
546 return;
547 }
548
549 WARN_ON_ONCE(!iod->nents);
550
551 if (is_pci_p2pdma_page(sg_page(iod->sg)))
552 pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents,
553 rq_dma_dir(req));
554 else
555 dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req));
556
557
558 if (iod->npages == 0)
559 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
560 dma_addr);
561
562 for (i = 0; i < iod->npages; i++) {
563 void *addr = nvme_pci_iod_list(req)[i];
564
565 if (iod->use_sgl) {
566 struct nvme_sgl_desc *sg_list = addr;
567
568 next_dma_addr =
569 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr);
570 } else {
571 __le64 *prp_list = addr;
572
573 next_dma_addr = le64_to_cpu(prp_list[last_prp]);
574 }
575
576 dma_pool_free(dev->prp_page_pool, addr, dma_addr);
577 dma_addr = next_dma_addr;
578 }
579
580 mempool_free(iod->sg, dev->iod_mempool);
581 }
582
583 static void nvme_print_sgl(struct scatterlist *sgl, int nents)
584 {
585 int i;
586 struct scatterlist *sg;
587
588 for_each_sg(sgl, sg, nents, i) {
589 dma_addr_t phys = sg_phys(sg);
590 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
591 "dma_address:%pad dma_length:%d\n",
592 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
593 sg_dma_len(sg));
594 }
595 }
596
597 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
598 struct request *req, struct nvme_rw_command *cmnd)
599 {
600 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
601 struct dma_pool *pool;
602 int length = blk_rq_payload_bytes(req);
603 struct scatterlist *sg = iod->sg;
604 int dma_len = sg_dma_len(sg);
605 u64 dma_addr = sg_dma_address(sg);
606 u32 page_size = dev->ctrl.page_size;
607 int offset = dma_addr & (page_size - 1);
608 __le64 *prp_list;
609 void **list = nvme_pci_iod_list(req);
610 dma_addr_t prp_dma;
611 int nprps, i;
612
613 length -= (page_size - offset);
614 if (length <= 0) {
615 iod->first_dma = 0;
616 goto done;
617 }
618
619 dma_len -= (page_size - offset);
620 if (dma_len) {
621 dma_addr += (page_size - offset);
622 } else {
623 sg = sg_next(sg);
624 dma_addr = sg_dma_address(sg);
625 dma_len = sg_dma_len(sg);
626 }
627
628 if (length <= page_size) {
629 iod->first_dma = dma_addr;
630 goto done;
631 }
632
633 nprps = DIV_ROUND_UP(length, page_size);
634 if (nprps <= (256 / 8)) {
635 pool = dev->prp_small_pool;
636 iod->npages = 0;
637 } else {
638 pool = dev->prp_page_pool;
639 iod->npages = 1;
640 }
641
642 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
643 if (!prp_list) {
644 iod->first_dma = dma_addr;
645 iod->npages = -1;
646 return BLK_STS_RESOURCE;
647 }
648 list[0] = prp_list;
649 iod->first_dma = prp_dma;
650 i = 0;
651 for (;;) {
652 if (i == page_size >> 3) {
653 __le64 *old_prp_list = prp_list;
654 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
655 if (!prp_list)
656 return BLK_STS_RESOURCE;
657 list[iod->npages++] = prp_list;
658 prp_list[0] = old_prp_list[i - 1];
659 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
660 i = 1;
661 }
662 prp_list[i++] = cpu_to_le64(dma_addr);
663 dma_len -= page_size;
664 dma_addr += page_size;
665 length -= page_size;
666 if (length <= 0)
667 break;
668 if (dma_len > 0)
669 continue;
670 if (unlikely(dma_len < 0))
671 goto bad_sgl;
672 sg = sg_next(sg);
673 dma_addr = sg_dma_address(sg);
674 dma_len = sg_dma_len(sg);
675 }
676
677 done:
678 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
679 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
680
681 return BLK_STS_OK;
682
683 bad_sgl:
684 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
685 "Invalid SGL for payload:%d nents:%d\n",
686 blk_rq_payload_bytes(req), iod->nents);
687 return BLK_STS_IOERR;
688 }
689
690 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
691 struct scatterlist *sg)
692 {
693 sge->addr = cpu_to_le64(sg_dma_address(sg));
694 sge->length = cpu_to_le32(sg_dma_len(sg));
695 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
696 }
697
698 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
699 dma_addr_t dma_addr, int entries)
700 {
701 sge->addr = cpu_to_le64(dma_addr);
702 if (entries < SGES_PER_PAGE) {
703 sge->length = cpu_to_le32(entries * sizeof(*sge));
704 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
705 } else {
706 sge->length = cpu_to_le32(PAGE_SIZE);
707 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
708 }
709 }
710
711 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
712 struct request *req, struct nvme_rw_command *cmd, int entries)
713 {
714 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
715 struct dma_pool *pool;
716 struct nvme_sgl_desc *sg_list;
717 struct scatterlist *sg = iod->sg;
718 dma_addr_t sgl_dma;
719 int i = 0;
720
721 /* setting the transfer type as SGL */
722 cmd->flags = NVME_CMD_SGL_METABUF;
723
724 if (entries == 1) {
725 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
726 return BLK_STS_OK;
727 }
728
729 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
730 pool = dev->prp_small_pool;
731 iod->npages = 0;
732 } else {
733 pool = dev->prp_page_pool;
734 iod->npages = 1;
735 }
736
737 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
738 if (!sg_list) {
739 iod->npages = -1;
740 return BLK_STS_RESOURCE;
741 }
742
743 nvme_pci_iod_list(req)[0] = sg_list;
744 iod->first_dma = sgl_dma;
745
746 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
747
748 do {
749 if (i == SGES_PER_PAGE) {
750 struct nvme_sgl_desc *old_sg_desc = sg_list;
751 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
752
753 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
754 if (!sg_list)
755 return BLK_STS_RESOURCE;
756
757 i = 0;
758 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
759 sg_list[i++] = *link;
760 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
761 }
762
763 nvme_pci_sgl_set_data(&sg_list[i++], sg);
764 sg = sg_next(sg);
765 } while (--entries > 0);
766
767 return BLK_STS_OK;
768 }
769
770 static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
771 struct request *req, struct nvme_rw_command *cmnd,
772 struct bio_vec *bv)
773 {
774 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
775 unsigned int offset = bv->bv_offset & (dev->ctrl.page_size - 1);
776 unsigned int first_prp_len = dev->ctrl.page_size - offset;
777
778 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
779 if (dma_mapping_error(dev->dev, iod->first_dma))
780 return BLK_STS_RESOURCE;
781 iod->dma_len = bv->bv_len;
782
783 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
784 if (bv->bv_len > first_prp_len)
785 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
786 return 0;
787 }
788
789 static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
790 struct request *req, struct nvme_rw_command *cmnd,
791 struct bio_vec *bv)
792 {
793 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
794
795 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
796 if (dma_mapping_error(dev->dev, iod->first_dma))
797 return BLK_STS_RESOURCE;
798 iod->dma_len = bv->bv_len;
799
800 cmnd->flags = NVME_CMD_SGL_METABUF;
801 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
802 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
803 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
804 return 0;
805 }
806
807 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
808 struct nvme_command *cmnd)
809 {
810 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
811 blk_status_t ret = BLK_STS_RESOURCE;
812 int nr_mapped;
813
814 if (blk_rq_nr_phys_segments(req) == 1) {
815 struct bio_vec bv = req_bvec(req);
816
817 if (!is_pci_p2pdma_page(bv.bv_page)) {
818 if (bv.bv_offset + bv.bv_len <= dev->ctrl.page_size * 2)
819 return nvme_setup_prp_simple(dev, req,
820 &cmnd->rw, &bv);
821
822 if (iod->nvmeq->qid &&
823 dev->ctrl.sgls & ((1 << 0) | (1 << 1)))
824 return nvme_setup_sgl_simple(dev, req,
825 &cmnd->rw, &bv);
826 }
827 }
828
829 iod->dma_len = 0;
830 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
831 if (!iod->sg)
832 return BLK_STS_RESOURCE;
833 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
834 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
835 if (!iod->nents)
836 goto out;
837
838 if (is_pci_p2pdma_page(sg_page(iod->sg)))
839 nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg,
840 iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN);
841 else
842 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
843 rq_dma_dir(req), DMA_ATTR_NO_WARN);
844 if (!nr_mapped)
845 goto out;
846
847 iod->use_sgl = nvme_pci_use_sgls(dev, req);
848 if (iod->use_sgl)
849 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
850 else
851 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
852 out:
853 if (ret != BLK_STS_OK)
854 nvme_unmap_data(dev, req);
855 return ret;
856 }
857
858 static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
859 struct nvme_command *cmnd)
860 {
861 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
862
863 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
864 rq_dma_dir(req), 0);
865 if (dma_mapping_error(dev->dev, iod->meta_dma))
866 return BLK_STS_IOERR;
867 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
868 return 0;
869 }
870
871 /*
872 * NOTE: ns is NULL when called on the admin queue.
873 */
874 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
875 const struct blk_mq_queue_data *bd)
876 {
877 struct nvme_ns *ns = hctx->queue->queuedata;
878 struct nvme_queue *nvmeq = hctx->driver_data;
879 struct nvme_dev *dev = nvmeq->dev;
880 struct request *req = bd->rq;
881 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
882 struct nvme_command cmnd;
883 blk_status_t ret;
884
885 iod->aborted = 0;
886 iod->npages = -1;
887 iod->nents = 0;
888
889 /*
890 * We should not need to do this, but we're still using this to
891 * ensure we can drain requests on a dying queue.
892 */
893 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
894 return BLK_STS_IOERR;
895
896 ret = nvme_setup_cmd(ns, req, &cmnd);
897 if (ret)
898 return ret;
899
900 if (blk_rq_nr_phys_segments(req)) {
901 ret = nvme_map_data(dev, req, &cmnd);
902 if (ret)
903 goto out_free_cmd;
904 }
905
906 if (blk_integrity_rq(req)) {
907 ret = nvme_map_metadata(dev, req, &cmnd);
908 if (ret)
909 goto out_unmap_data;
910 }
911
912 blk_mq_start_request(req);
913 nvme_submit_cmd(nvmeq, &cmnd, bd->last);
914 return BLK_STS_OK;
915 out_unmap_data:
916 nvme_unmap_data(dev, req);
917 out_free_cmd:
918 nvme_cleanup_cmd(req);
919 return ret;
920 }
921
922 static void nvme_pci_complete_rq(struct request *req)
923 {
924 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
925 struct nvme_dev *dev = iod->nvmeq->dev;
926
927 if (blk_integrity_rq(req))
928 dma_unmap_page(dev->dev, iod->meta_dma,
929 rq_integrity_vec(req)->bv_len, rq_data_dir(req));
930 if (blk_rq_nr_phys_segments(req))
931 nvme_unmap_data(dev, req);
932 nvme_complete_rq(req);
933 }
934
935 /* We read the CQE phase first to check if the rest of the entry is valid */
936 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
937 {
938 return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
939 nvmeq->cq_phase;
940 }
941
942 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
943 {
944 u16 head = nvmeq->cq_head;
945
946 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
947 nvmeq->dbbuf_cq_ei))
948 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
949 }
950
951 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
952 {
953 volatile struct nvme_completion *cqe = &nvmeq->cqes[idx];
954 struct request *req;
955
956 if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
957 dev_warn(nvmeq->dev->ctrl.device,
958 "invalid id %d completed on queue %d\n",
959 cqe->command_id, le16_to_cpu(cqe->sq_id));
960 return;
961 }
962
963 /*
964 * AEN requests are special as they don't time out and can
965 * survive any kind of queue freeze and often don't respond to
966 * aborts. We don't even bother to allocate a struct request
967 * for them but rather special case them here.
968 */
969 if (unlikely(nvme_is_aen_req(nvmeq->qid, cqe->command_id))) {
970 nvme_complete_async_event(&nvmeq->dev->ctrl,
971 cqe->status, &cqe->result);
972 return;
973 }
974
975 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id);
976 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
977 nvme_end_request(req, cqe->status, cqe->result);
978 }
979
980 static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end)
981 {
982 while (start != end) {
983 nvme_handle_cqe(nvmeq, start);
984 if (++start == nvmeq->q_depth)
985 start = 0;
986 }
987 }
988
989 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
990 {
991 if (nvmeq->cq_head == nvmeq->q_depth - 1) {
992 nvmeq->cq_head = 0;
993 nvmeq->cq_phase = !nvmeq->cq_phase;
994 } else {
995 nvmeq->cq_head++;
996 }
997 }
998
999 static inline int nvme_process_cq(struct nvme_queue *nvmeq, u16 *start,
1000 u16 *end, unsigned int tag)
1001 {
1002 int found = 0;
1003
1004 *start = nvmeq->cq_head;
1005 while (nvme_cqe_pending(nvmeq)) {
1006 if (tag == -1U || nvmeq->cqes[nvmeq->cq_head].command_id == tag)
1007 found++;
1008 nvme_update_cq_head(nvmeq);
1009 }
1010 *end = nvmeq->cq_head;
1011
1012 if (*start != *end)
1013 nvme_ring_cq_doorbell(nvmeq);
1014 return found;
1015 }
1016
1017 static irqreturn_t nvme_irq(int irq, void *data)
1018 {
1019 struct nvme_queue *nvmeq = data;
1020 irqreturn_t ret = IRQ_NONE;
1021 u16 start, end;
1022
1023 /*
1024 * The rmb/wmb pair ensures we see all updates from a previous run of
1025 * the irq handler, even if that was on another CPU.
1026 */
1027 rmb();
1028 nvme_process_cq(nvmeq, &start, &end, -1);
1029 wmb();
1030
1031 if (start != end) {
1032 nvme_complete_cqes(nvmeq, start, end);
1033 return IRQ_HANDLED;
1034 }
1035
1036 return ret;
1037 }
1038
1039 static irqreturn_t nvme_irq_check(int irq, void *data)
1040 {
1041 struct nvme_queue *nvmeq = data;
1042 if (nvme_cqe_pending(nvmeq))
1043 return IRQ_WAKE_THREAD;
1044 return IRQ_NONE;
1045 }
1046
1047 /*
1048 * Poll for completions any queue, including those not dedicated to polling.
1049 * Can be called from any context.
1050 */
1051 static int nvme_poll_irqdisable(struct nvme_queue *nvmeq, unsigned int tag)
1052 {
1053 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1054 u16 start, end;
1055 int found;
1056
1057 /*
1058 * For a poll queue we need to protect against the polling thread
1059 * using the CQ lock. For normal interrupt driven threads we have
1060 * to disable the interrupt to avoid racing with it.
1061 */
1062 if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) {
1063 spin_lock(&nvmeq->cq_poll_lock);
1064 found = nvme_process_cq(nvmeq, &start, &end, tag);
1065 spin_unlock(&nvmeq->cq_poll_lock);
1066 } else {
1067 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1068 found = nvme_process_cq(nvmeq, &start, &end, tag);
1069 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1070 }
1071
1072 nvme_complete_cqes(nvmeq, start, end);
1073 return found;
1074 }
1075
1076 static int nvme_poll(struct blk_mq_hw_ctx *hctx)
1077 {
1078 struct nvme_queue *nvmeq = hctx->driver_data;
1079 u16 start, end;
1080 bool found;
1081
1082 if (!nvme_cqe_pending(nvmeq))
1083 return 0;
1084
1085 spin_lock(&nvmeq->cq_poll_lock);
1086 found = nvme_process_cq(nvmeq, &start, &end, -1);
1087 spin_unlock(&nvmeq->cq_poll_lock);
1088
1089 nvme_complete_cqes(nvmeq, start, end);
1090 return found;
1091 }
1092
1093 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
1094 {
1095 struct nvme_dev *dev = to_nvme_dev(ctrl);
1096 struct nvme_queue *nvmeq = &dev->queues[0];
1097 struct nvme_command c;
1098
1099 memset(&c, 0, sizeof(c));
1100 c.common.opcode = nvme_admin_async_event;
1101 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
1102 nvme_submit_cmd(nvmeq, &c, true);
1103 }
1104
1105 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1106 {
1107 struct nvme_command c;
1108
1109 memset(&c, 0, sizeof(c));
1110 c.delete_queue.opcode = opcode;
1111 c.delete_queue.qid = cpu_to_le16(id);
1112
1113 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1114 }
1115
1116 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1117 struct nvme_queue *nvmeq, s16 vector)
1118 {
1119 struct nvme_command c;
1120 int flags = NVME_QUEUE_PHYS_CONTIG;
1121
1122 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
1123 flags |= NVME_CQ_IRQ_ENABLED;
1124
1125 /*
1126 * Note: we (ab)use the fact that the prp fields survive if no data
1127 * is attached to the request.
1128 */
1129 memset(&c, 0, sizeof(c));
1130 c.create_cq.opcode = nvme_admin_create_cq;
1131 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1132 c.create_cq.cqid = cpu_to_le16(qid);
1133 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1134 c.create_cq.cq_flags = cpu_to_le16(flags);
1135 c.create_cq.irq_vector = cpu_to_le16(vector);
1136
1137 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1138 }
1139
1140 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1141 struct nvme_queue *nvmeq)
1142 {
1143 struct nvme_ctrl *ctrl = &dev->ctrl;
1144 struct nvme_command c;
1145 int flags = NVME_QUEUE_PHYS_CONTIG;
1146
1147 /*
1148 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1149 * set. Since URGENT priority is zeroes, it makes all queues
1150 * URGENT.
1151 */
1152 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1153 flags |= NVME_SQ_PRIO_MEDIUM;
1154
1155 /*
1156 * Note: we (ab)use the fact that the prp fields survive if no data
1157 * is attached to the request.
1158 */
1159 memset(&c, 0, sizeof(c));
1160 c.create_sq.opcode = nvme_admin_create_sq;
1161 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1162 c.create_sq.sqid = cpu_to_le16(qid);
1163 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1164 c.create_sq.sq_flags = cpu_to_le16(flags);
1165 c.create_sq.cqid = cpu_to_le16(qid);
1166
1167 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1168 }
1169
1170 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1171 {
1172 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1173 }
1174
1175 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1176 {
1177 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1178 }
1179
1180 static void abort_endio(struct request *req, blk_status_t error)
1181 {
1182 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1183 struct nvme_queue *nvmeq = iod->nvmeq;
1184
1185 dev_warn(nvmeq->dev->ctrl.device,
1186 "Abort status: 0x%x", nvme_req(req)->status);
1187 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
1188 blk_mq_free_request(req);
1189 }
1190
1191 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1192 {
1193
1194 /* If true, indicates loss of adapter communication, possibly by a
1195 * NVMe Subsystem reset.
1196 */
1197 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1198
1199 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1200 switch (dev->ctrl.state) {
1201 case NVME_CTRL_RESETTING:
1202 case NVME_CTRL_CONNECTING:
1203 return false;
1204 default:
1205 break;
1206 }
1207
1208 /* We shouldn't reset unless the controller is on fatal error state
1209 * _or_ if we lost the communication with it.
1210 */
1211 if (!(csts & NVME_CSTS_CFS) && !nssro)
1212 return false;
1213
1214 return true;
1215 }
1216
1217 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1218 {
1219 /* Read a config register to help see what died. */
1220 u16 pci_status;
1221 int result;
1222
1223 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1224 &pci_status);
1225 if (result == PCIBIOS_SUCCESSFUL)
1226 dev_warn(dev->ctrl.device,
1227 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1228 csts, pci_status);
1229 else
1230 dev_warn(dev->ctrl.device,
1231 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1232 csts, result);
1233 }
1234
1235 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1236 {
1237 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1238 struct nvme_queue *nvmeq = iod->nvmeq;
1239 struct nvme_dev *dev = nvmeq->dev;
1240 struct request *abort_req;
1241 struct nvme_command cmd;
1242 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1243
1244 /* If PCI error recovery process is happening, we cannot reset or
1245 * the recovery mechanism will surely fail.
1246 */
1247 mb();
1248 if (pci_channel_offline(to_pci_dev(dev->dev)))
1249 return BLK_EH_RESET_TIMER;
1250
1251 /*
1252 * Reset immediately if the controller is failed
1253 */
1254 if (nvme_should_reset(dev, csts)) {
1255 nvme_warn_reset(dev, csts);
1256 nvme_dev_disable(dev, false);
1257 nvme_reset_ctrl(&dev->ctrl);
1258 return BLK_EH_DONE;
1259 }
1260
1261 /*
1262 * Did we miss an interrupt?
1263 */
1264 if (nvme_poll_irqdisable(nvmeq, req->tag)) {
1265 dev_warn(dev->ctrl.device,
1266 "I/O %d QID %d timeout, completion polled\n",
1267 req->tag, nvmeq->qid);
1268 return BLK_EH_DONE;
1269 }
1270
1271 /*
1272 * Shutdown immediately if controller times out while starting. The
1273 * reset work will see the pci device disabled when it gets the forced
1274 * cancellation error. All outstanding requests are completed on
1275 * shutdown, so we return BLK_EH_DONE.
1276 */
1277 switch (dev->ctrl.state) {
1278 case NVME_CTRL_CONNECTING:
1279 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
1280 /* fall through */
1281 case NVME_CTRL_DELETING:
1282 dev_warn_ratelimited(dev->ctrl.device,
1283 "I/O %d QID %d timeout, disable controller\n",
1284 req->tag, nvmeq->qid);
1285 nvme_dev_disable(dev, true);
1286 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1287 return BLK_EH_DONE;
1288 case NVME_CTRL_RESETTING:
1289 return BLK_EH_RESET_TIMER;
1290 default:
1291 break;
1292 }
1293
1294 /*
1295 * Shutdown the controller immediately and schedule a reset if the
1296 * command was already aborted once before and still hasn't been
1297 * returned to the driver, or if this is the admin queue.
1298 */
1299 if (!nvmeq->qid || iod->aborted) {
1300 dev_warn(dev->ctrl.device,
1301 "I/O %d QID %d timeout, reset controller\n",
1302 req->tag, nvmeq->qid);
1303 nvme_dev_disable(dev, false);
1304 nvme_reset_ctrl(&dev->ctrl);
1305
1306 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1307 return BLK_EH_DONE;
1308 }
1309
1310 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1311 atomic_inc(&dev->ctrl.abort_limit);
1312 return BLK_EH_RESET_TIMER;
1313 }
1314 iod->aborted = 1;
1315
1316 memset(&cmd, 0, sizeof(cmd));
1317 cmd.abort.opcode = nvme_admin_abort_cmd;
1318 cmd.abort.cid = req->tag;
1319 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1320
1321 dev_warn(nvmeq->dev->ctrl.device,
1322 "I/O %d QID %d timeout, aborting\n",
1323 req->tag, nvmeq->qid);
1324
1325 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
1326 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1327 if (IS_ERR(abort_req)) {
1328 atomic_inc(&dev->ctrl.abort_limit);
1329 return BLK_EH_RESET_TIMER;
1330 }
1331
1332 abort_req->timeout = ADMIN_TIMEOUT;
1333 abort_req->end_io_data = NULL;
1334 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
1335
1336 /*
1337 * The aborted req will be completed on receiving the abort req.
1338 * We enable the timer again. If hit twice, it'll cause a device reset,
1339 * as the device then is in a faulty state.
1340 */
1341 return BLK_EH_RESET_TIMER;
1342 }
1343
1344 static void nvme_free_queue(struct nvme_queue *nvmeq)
1345 {
1346 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
1347 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1348 if (!nvmeq->sq_cmds)
1349 return;
1350
1351 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
1352 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
1353 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1354 } else {
1355 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
1356 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1357 }
1358 }
1359
1360 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1361 {
1362 int i;
1363
1364 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1365 dev->ctrl.queue_count--;
1366 nvme_free_queue(&dev->queues[i]);
1367 }
1368 }
1369
1370 /**
1371 * nvme_suspend_queue - put queue into suspended state
1372 * @nvmeq: queue to suspend
1373 */
1374 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1375 {
1376 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
1377 return 1;
1378
1379 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
1380 mb();
1381
1382 nvmeq->dev->online_queues--;
1383 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1384 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
1385 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1386 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
1387 return 0;
1388 }
1389
1390 static void nvme_suspend_io_queues(struct nvme_dev *dev)
1391 {
1392 int i;
1393
1394 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1395 nvme_suspend_queue(&dev->queues[i]);
1396 }
1397
1398 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1399 {
1400 struct nvme_queue *nvmeq = &dev->queues[0];
1401
1402 if (shutdown)
1403 nvme_shutdown_ctrl(&dev->ctrl);
1404 else
1405 nvme_disable_ctrl(&dev->ctrl);
1406
1407 nvme_poll_irqdisable(nvmeq, -1);
1408 }
1409
1410 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1411 int entry_size)
1412 {
1413 int q_depth = dev->q_depth;
1414 unsigned q_size_aligned = roundup(q_depth * entry_size,
1415 dev->ctrl.page_size);
1416
1417 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1418 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1419 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1420 q_depth = div_u64(mem_per_q, entry_size);
1421
1422 /*
1423 * Ensure the reduced q_depth is above some threshold where it
1424 * would be better to map queues in system memory with the
1425 * original depth
1426 */
1427 if (q_depth < 64)
1428 return -ENOMEM;
1429 }
1430
1431 return q_depth;
1432 }
1433
1434 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1435 int qid)
1436 {
1437 struct pci_dev *pdev = to_pci_dev(dev->dev);
1438
1439 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1440 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
1441 if (nvmeq->sq_cmds) {
1442 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1443 nvmeq->sq_cmds);
1444 if (nvmeq->sq_dma_addr) {
1445 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1446 return 0;
1447 }
1448
1449 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1450 }
1451 }
1452
1453 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
1454 &nvmeq->sq_dma_addr, GFP_KERNEL);
1455 if (!nvmeq->sq_cmds)
1456 return -ENOMEM;
1457 return 0;
1458 }
1459
1460 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
1461 {
1462 struct nvme_queue *nvmeq = &dev->queues[qid];
1463
1464 if (dev->ctrl.queue_count > qid)
1465 return 0;
1466
1467 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
1468 nvmeq->q_depth = depth;
1469 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
1470 &nvmeq->cq_dma_addr, GFP_KERNEL);
1471 if (!nvmeq->cqes)
1472 goto free_nvmeq;
1473
1474 if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
1475 goto free_cqdma;
1476
1477 nvmeq->dev = dev;
1478 spin_lock_init(&nvmeq->sq_lock);
1479 spin_lock_init(&nvmeq->cq_poll_lock);
1480 nvmeq->cq_head = 0;
1481 nvmeq->cq_phase = 1;
1482 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1483 nvmeq->qid = qid;
1484 dev->ctrl.queue_count++;
1485
1486 return 0;
1487
1488 free_cqdma:
1489 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1490 nvmeq->cq_dma_addr);
1491 free_nvmeq:
1492 return -ENOMEM;
1493 }
1494
1495 static int queue_request_irq(struct nvme_queue *nvmeq)
1496 {
1497 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1498 int nr = nvmeq->dev->ctrl.instance;
1499
1500 if (use_threaded_interrupts) {
1501 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1502 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1503 } else {
1504 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1505 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1506 }
1507 }
1508
1509 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1510 {
1511 struct nvme_dev *dev = nvmeq->dev;
1512
1513 nvmeq->sq_tail = 0;
1514 nvmeq->last_sq_tail = 0;
1515 nvmeq->cq_head = 0;
1516 nvmeq->cq_phase = 1;
1517 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1518 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
1519 nvme_dbbuf_init(dev, nvmeq, qid);
1520 dev->online_queues++;
1521 wmb(); /* ensure the first interrupt sees the initialization */
1522 }
1523
1524 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
1525 {
1526 struct nvme_dev *dev = nvmeq->dev;
1527 int result;
1528 u16 vector = 0;
1529
1530 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1531
1532 /*
1533 * A queue's vector matches the queue identifier unless the controller
1534 * has only one vector available.
1535 */
1536 if (!polled)
1537 vector = dev->num_vecs == 1 ? 0 : qid;
1538 else
1539 set_bit(NVMEQ_POLLED, &nvmeq->flags);
1540
1541 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
1542 if (result)
1543 return result;
1544
1545 result = adapter_alloc_sq(dev, qid, nvmeq);
1546 if (result < 0)
1547 return result;
1548 if (result)
1549 goto release_cq;
1550
1551 nvmeq->cq_vector = vector;
1552 nvme_init_queue(nvmeq, qid);
1553
1554 if (!polled) {
1555 result = queue_request_irq(nvmeq);
1556 if (result < 0)
1557 goto release_sq;
1558 }
1559
1560 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1561 return result;
1562
1563 release_sq:
1564 dev->online_queues--;
1565 adapter_delete_sq(dev, qid);
1566 release_cq:
1567 adapter_delete_cq(dev, qid);
1568 return result;
1569 }
1570
1571 static const struct blk_mq_ops nvme_mq_admin_ops = {
1572 .queue_rq = nvme_queue_rq,
1573 .complete = nvme_pci_complete_rq,
1574 .init_hctx = nvme_admin_init_hctx,
1575 .exit_hctx = nvme_admin_exit_hctx,
1576 .init_request = nvme_init_request,
1577 .timeout = nvme_timeout,
1578 };
1579
1580 static const struct blk_mq_ops nvme_mq_ops = {
1581 .queue_rq = nvme_queue_rq,
1582 .complete = nvme_pci_complete_rq,
1583 .commit_rqs = nvme_commit_rqs,
1584 .init_hctx = nvme_init_hctx,
1585 .init_request = nvme_init_request,
1586 .map_queues = nvme_pci_map_queues,
1587 .timeout = nvme_timeout,
1588 .poll = nvme_poll,
1589 };
1590
1591 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1592 {
1593 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1594 /*
1595 * If the controller was reset during removal, it's possible
1596 * user requests may be waiting on a stopped queue. Start the
1597 * queue to flush these to completion.
1598 */
1599 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1600 blk_cleanup_queue(dev->ctrl.admin_q);
1601 blk_mq_free_tag_set(&dev->admin_tagset);
1602 }
1603 }
1604
1605 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1606 {
1607 if (!dev->ctrl.admin_q) {
1608 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1609 dev->admin_tagset.nr_hw_queues = 1;
1610
1611 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
1612 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1613 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1614 dev->admin_tagset.cmd_size = sizeof(struct nvme_iod);
1615 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
1616 dev->admin_tagset.driver_data = dev;
1617
1618 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1619 return -ENOMEM;
1620 dev->ctrl.admin_tagset = &dev->admin_tagset;
1621
1622 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1623 if (IS_ERR(dev->ctrl.admin_q)) {
1624 blk_mq_free_tag_set(&dev->admin_tagset);
1625 return -ENOMEM;
1626 }
1627 if (!blk_get_queue(dev->ctrl.admin_q)) {
1628 nvme_dev_remove_admin(dev);
1629 dev->ctrl.admin_q = NULL;
1630 return -ENODEV;
1631 }
1632 } else
1633 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1634
1635 return 0;
1636 }
1637
1638 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1639 {
1640 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1641 }
1642
1643 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1644 {
1645 struct pci_dev *pdev = to_pci_dev(dev->dev);
1646
1647 if (size <= dev->bar_mapped_size)
1648 return 0;
1649 if (size > pci_resource_len(pdev, 0))
1650 return -ENOMEM;
1651 if (dev->bar)
1652 iounmap(dev->bar);
1653 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1654 if (!dev->bar) {
1655 dev->bar_mapped_size = 0;
1656 return -ENOMEM;
1657 }
1658 dev->bar_mapped_size = size;
1659 dev->dbs = dev->bar + NVME_REG_DBS;
1660
1661 return 0;
1662 }
1663
1664 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1665 {
1666 int result;
1667 u32 aqa;
1668 struct nvme_queue *nvmeq;
1669
1670 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1671 if (result < 0)
1672 return result;
1673
1674 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1675 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1676
1677 if (dev->subsystem &&
1678 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1679 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1680
1681 result = nvme_disable_ctrl(&dev->ctrl);
1682 if (result < 0)
1683 return result;
1684
1685 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1686 if (result)
1687 return result;
1688
1689 nvmeq = &dev->queues[0];
1690 aqa = nvmeq->q_depth - 1;
1691 aqa |= aqa << 16;
1692
1693 writel(aqa, dev->bar + NVME_REG_AQA);
1694 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1695 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1696
1697 result = nvme_enable_ctrl(&dev->ctrl);
1698 if (result)
1699 return result;
1700
1701 nvmeq->cq_vector = 0;
1702 nvme_init_queue(nvmeq, 0);
1703 result = queue_request_irq(nvmeq);
1704 if (result) {
1705 dev->online_queues--;
1706 return result;
1707 }
1708
1709 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1710 return result;
1711 }
1712
1713 static int nvme_create_io_queues(struct nvme_dev *dev)
1714 {
1715 unsigned i, max, rw_queues;
1716 int ret = 0;
1717
1718 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1719 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
1720 ret = -ENOMEM;
1721 break;
1722 }
1723 }
1724
1725 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1726 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1727 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1728 dev->io_queues[HCTX_TYPE_READ];
1729 } else {
1730 rw_queues = max;
1731 }
1732
1733 for (i = dev->online_queues; i <= max; i++) {
1734 bool polled = i > rw_queues;
1735
1736 ret = nvme_create_queue(&dev->queues[i], i, polled);
1737 if (ret)
1738 break;
1739 }
1740
1741 /*
1742 * Ignore failing Create SQ/CQ commands, we can continue with less
1743 * than the desired amount of queues, and even a controller without
1744 * I/O queues can still be used to issue admin commands. This might
1745 * be useful to upgrade a buggy firmware for example.
1746 */
1747 return ret >= 0 ? 0 : ret;
1748 }
1749
1750 static ssize_t nvme_cmb_show(struct device *dev,
1751 struct device_attribute *attr,
1752 char *buf)
1753 {
1754 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1755
1756 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
1757 ndev->cmbloc, ndev->cmbsz);
1758 }
1759 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1760
1761 static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
1762 {
1763 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1764
1765 return 1ULL << (12 + 4 * szu);
1766 }
1767
1768 static u32 nvme_cmb_size(struct nvme_dev *dev)
1769 {
1770 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1771 }
1772
1773 static void nvme_map_cmb(struct nvme_dev *dev)
1774 {
1775 u64 size, offset;
1776 resource_size_t bar_size;
1777 struct pci_dev *pdev = to_pci_dev(dev->dev);
1778 int bar;
1779
1780 if (dev->cmb_size)
1781 return;
1782
1783 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1784 if (!dev->cmbsz)
1785 return;
1786 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1787
1788 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1789 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
1790 bar = NVME_CMB_BIR(dev->cmbloc);
1791 bar_size = pci_resource_len(pdev, bar);
1792
1793 if (offset > bar_size)
1794 return;
1795
1796 /*
1797 * Controllers may support a CMB size larger than their BAR,
1798 * for example, due to being behind a bridge. Reduce the CMB to
1799 * the reported size of the BAR
1800 */
1801 if (size > bar_size - offset)
1802 size = bar_size - offset;
1803
1804 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1805 dev_warn(dev->ctrl.device,
1806 "failed to register the CMB\n");
1807 return;
1808 }
1809
1810 dev->cmb_size = size;
1811 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1812
1813 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1814 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1815 pci_p2pmem_publish(pdev, true);
1816
1817 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1818 &dev_attr_cmb.attr, NULL))
1819 dev_warn(dev->ctrl.device,
1820 "failed to add sysfs attribute for CMB\n");
1821 }
1822
1823 static inline void nvme_release_cmb(struct nvme_dev *dev)
1824 {
1825 if (dev->cmb_size) {
1826 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1827 &dev_attr_cmb.attr, NULL);
1828 dev->cmb_size = 0;
1829 }
1830 }
1831
1832 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1833 {
1834 u64 dma_addr = dev->host_mem_descs_dma;
1835 struct nvme_command c;
1836 int ret;
1837
1838 memset(&c, 0, sizeof(c));
1839 c.features.opcode = nvme_admin_set_features;
1840 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1841 c.features.dword11 = cpu_to_le32(bits);
1842 c.features.dword12 = cpu_to_le32(dev->host_mem_size >>
1843 ilog2(dev->ctrl.page_size));
1844 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1845 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1846 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1847
1848 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1849 if (ret) {
1850 dev_warn(dev->ctrl.device,
1851 "failed to set host mem (err %d, flags %#x).\n",
1852 ret, bits);
1853 }
1854 return ret;
1855 }
1856
1857 static void nvme_free_host_mem(struct nvme_dev *dev)
1858 {
1859 int i;
1860
1861 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1862 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1863 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1864
1865 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1866 le64_to_cpu(desc->addr),
1867 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1868 }
1869
1870 kfree(dev->host_mem_desc_bufs);
1871 dev->host_mem_desc_bufs = NULL;
1872 dma_free_coherent(dev->dev,
1873 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1874 dev->host_mem_descs, dev->host_mem_descs_dma);
1875 dev->host_mem_descs = NULL;
1876 dev->nr_host_mem_descs = 0;
1877 }
1878
1879 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1880 u32 chunk_size)
1881 {
1882 struct nvme_host_mem_buf_desc *descs;
1883 u32 max_entries, len;
1884 dma_addr_t descs_dma;
1885 int i = 0;
1886 void **bufs;
1887 u64 size, tmp;
1888
1889 tmp = (preferred + chunk_size - 1);
1890 do_div(tmp, chunk_size);
1891 max_entries = tmp;
1892
1893 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1894 max_entries = dev->ctrl.hmmaxd;
1895
1896 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1897 &descs_dma, GFP_KERNEL);
1898 if (!descs)
1899 goto out;
1900
1901 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1902 if (!bufs)
1903 goto out_free_descs;
1904
1905 for (size = 0; size < preferred && i < max_entries; size += len) {
1906 dma_addr_t dma_addr;
1907
1908 len = min_t(u64, chunk_size, preferred - size);
1909 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1910 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1911 if (!bufs[i])
1912 break;
1913
1914 descs[i].addr = cpu_to_le64(dma_addr);
1915 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1916 i++;
1917 }
1918
1919 if (!size)
1920 goto out_free_bufs;
1921
1922 dev->nr_host_mem_descs = i;
1923 dev->host_mem_size = size;
1924 dev->host_mem_descs = descs;
1925 dev->host_mem_descs_dma = descs_dma;
1926 dev->host_mem_desc_bufs = bufs;
1927 return 0;
1928
1929 out_free_bufs:
1930 while (--i >= 0) {
1931 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1932
1933 dma_free_attrs(dev->dev, size, bufs[i],
1934 le64_to_cpu(descs[i].addr),
1935 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1936 }
1937
1938 kfree(bufs);
1939 out_free_descs:
1940 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1941 descs_dma);
1942 out:
1943 dev->host_mem_descs = NULL;
1944 return -ENOMEM;
1945 }
1946
1947 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1948 {
1949 u32 chunk_size;
1950
1951 /* start big and work our way down */
1952 for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
1953 chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
1954 chunk_size /= 2) {
1955 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
1956 if (!min || dev->host_mem_size >= min)
1957 return 0;
1958 nvme_free_host_mem(dev);
1959 }
1960 }
1961
1962 return -ENOMEM;
1963 }
1964
1965 static int nvme_setup_host_mem(struct nvme_dev *dev)
1966 {
1967 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
1968 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
1969 u64 min = (u64)dev->ctrl.hmmin * 4096;
1970 u32 enable_bits = NVME_HOST_MEM_ENABLE;
1971 int ret;
1972
1973 preferred = min(preferred, max);
1974 if (min > max) {
1975 dev_warn(dev->ctrl.device,
1976 "min host memory (%lld MiB) above limit (%d MiB).\n",
1977 min >> ilog2(SZ_1M), max_host_mem_size_mb);
1978 nvme_free_host_mem(dev);
1979 return 0;
1980 }
1981
1982 /*
1983 * If we already have a buffer allocated check if we can reuse it.
1984 */
1985 if (dev->host_mem_descs) {
1986 if (dev->host_mem_size >= min)
1987 enable_bits |= NVME_HOST_MEM_RETURN;
1988 else
1989 nvme_free_host_mem(dev);
1990 }
1991
1992 if (!dev->host_mem_descs) {
1993 if (nvme_alloc_host_mem(dev, min, preferred)) {
1994 dev_warn(dev->ctrl.device,
1995 "failed to allocate host memory buffer.\n");
1996 return 0; /* controller must work without HMB */
1997 }
1998
1999 dev_info(dev->ctrl.device,
2000 "allocated %lld MiB host memory buffer.\n",
2001 dev->host_mem_size >> ilog2(SZ_1M));
2002 }
2003
2004 ret = nvme_set_host_mem(dev, enable_bits);
2005 if (ret)
2006 nvme_free_host_mem(dev);
2007 return ret;
2008 }
2009
2010 /*
2011 * nirqs is the number of interrupts available for write and read
2012 * queues. The core already reserved an interrupt for the admin queue.
2013 */
2014 static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
2015 {
2016 struct nvme_dev *dev = affd->priv;
2017 unsigned int nr_read_queues;
2018
2019 /*
2020 * If there is no interupt available for queues, ensure that
2021 * the default queue is set to 1. The affinity set size is
2022 * also set to one, but the irq core ignores it for this case.
2023 *
2024 * If only one interrupt is available or 'write_queue' == 0, combine
2025 * write and read queues.
2026 *
2027 * If 'write_queues' > 0, ensure it leaves room for at least one read
2028 * queue.
2029 */
2030 if (!nrirqs) {
2031 nrirqs = 1;
2032 nr_read_queues = 0;
2033 } else if (nrirqs == 1 || !write_queues) {
2034 nr_read_queues = 0;
2035 } else if (write_queues >= nrirqs) {
2036 nr_read_queues = 1;
2037 } else {
2038 nr_read_queues = nrirqs - write_queues;
2039 }
2040
2041 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2042 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2043 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2044 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2045 affd->nr_sets = nr_read_queues ? 2 : 1;
2046 }
2047
2048 static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
2049 {
2050 struct pci_dev *pdev = to_pci_dev(dev->dev);
2051 struct irq_affinity affd = {
2052 .pre_vectors = 1,
2053 .calc_sets = nvme_calc_irq_sets,
2054 .priv = dev,
2055 };
2056 unsigned int irq_queues, this_p_queues;
2057
2058 /*
2059 * Poll queues don't need interrupts, but we need at least one IO
2060 * queue left over for non-polled IO.
2061 */
2062 this_p_queues = poll_queues;
2063 if (this_p_queues >= nr_io_queues) {
2064 this_p_queues = nr_io_queues - 1;
2065 irq_queues = 1;
2066 } else {
2067 irq_queues = nr_io_queues - this_p_queues + 1;
2068 }
2069 dev->io_queues[HCTX_TYPE_POLL] = this_p_queues;
2070
2071 /* Initialize for the single interrupt case */
2072 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2073 dev->io_queues[HCTX_TYPE_READ] = 0;
2074
2075 /*
2076 * Some Apple controllers require all queues to use the
2077 * first vector.
2078 */
2079 if (dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR)
2080 irq_queues = 1;
2081
2082 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2083 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
2084 }
2085
2086 static void nvme_disable_io_queues(struct nvme_dev *dev)
2087 {
2088 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2089 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2090 }
2091
2092 static int nvme_setup_io_queues(struct nvme_dev *dev)
2093 {
2094 struct nvme_queue *adminq = &dev->queues[0];
2095 struct pci_dev *pdev = to_pci_dev(dev->dev);
2096 int result, nr_io_queues;
2097 unsigned long size;
2098
2099 nr_io_queues = max_io_queues();
2100
2101 /*
2102 * If tags are shared with admin queue (Apple bug), then
2103 * make sure we only use one IO queue.
2104 */
2105 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2106 nr_io_queues = 1;
2107
2108 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2109 if (result < 0)
2110 return result;
2111
2112 if (nr_io_queues == 0)
2113 return 0;
2114
2115 clear_bit(NVMEQ_ENABLED, &adminq->flags);
2116
2117 if (dev->cmb_use_sqes) {
2118 result = nvme_cmb_qdepth(dev, nr_io_queues,
2119 sizeof(struct nvme_command));
2120 if (result > 0)
2121 dev->q_depth = result;
2122 else
2123 dev->cmb_use_sqes = false;
2124 }
2125
2126 do {
2127 size = db_bar_size(dev, nr_io_queues);
2128 result = nvme_remap_bar(dev, size);
2129 if (!result)
2130 break;
2131 if (!--nr_io_queues)
2132 return -ENOMEM;
2133 } while (1);
2134 adminq->q_db = dev->dbs;
2135
2136 retry:
2137 /* Deregister the admin queue's interrupt */
2138 pci_free_irq(pdev, 0, adminq);
2139
2140 /*
2141 * If we enable msix early due to not intx, disable it again before
2142 * setting up the full range we need.
2143 */
2144 pci_free_irq_vectors(pdev);
2145
2146 result = nvme_setup_irqs(dev, nr_io_queues);
2147 if (result <= 0)
2148 return -EIO;
2149
2150 dev->num_vecs = result;
2151 result = max(result - 1, 1);
2152 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
2153
2154 /*
2155 * Should investigate if there's a performance win from allocating
2156 * more queues than interrupt vectors; it might allow the submission
2157 * path to scale better, even if the receive path is limited by the
2158 * number of interrupts.
2159 */
2160 result = queue_request_irq(adminq);
2161 if (result)
2162 return result;
2163 set_bit(NVMEQ_ENABLED, &adminq->flags);
2164
2165 result = nvme_create_io_queues(dev);
2166 if (result || dev->online_queues < 2)
2167 return result;
2168
2169 if (dev->online_queues - 1 < dev->max_qid) {
2170 nr_io_queues = dev->online_queues - 1;
2171 nvme_disable_io_queues(dev);
2172 nvme_suspend_io_queues(dev);
2173 goto retry;
2174 }
2175 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2176 dev->io_queues[HCTX_TYPE_DEFAULT],
2177 dev->io_queues[HCTX_TYPE_READ],
2178 dev->io_queues[HCTX_TYPE_POLL]);
2179 return 0;
2180 }
2181
2182 static void nvme_del_queue_end(struct request *req, blk_status_t error)
2183 {
2184 struct nvme_queue *nvmeq = req->end_io_data;
2185
2186 blk_mq_free_request(req);
2187 complete(&nvmeq->delete_done);
2188 }
2189
2190 static void nvme_del_cq_end(struct request *req, blk_status_t error)
2191 {
2192 struct nvme_queue *nvmeq = req->end_io_data;
2193
2194 if (error)
2195 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
2196
2197 nvme_del_queue_end(req, error);
2198 }
2199
2200 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
2201 {
2202 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2203 struct request *req;
2204 struct nvme_command cmd;
2205
2206 memset(&cmd, 0, sizeof(cmd));
2207 cmd.delete_queue.opcode = opcode;
2208 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2209
2210 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
2211 if (IS_ERR(req))
2212 return PTR_ERR(req);
2213
2214 req->timeout = ADMIN_TIMEOUT;
2215 req->end_io_data = nvmeq;
2216
2217 init_completion(&nvmeq->delete_done);
2218 blk_execute_rq_nowait(q, NULL, req, false,
2219 opcode == nvme_admin_delete_cq ?
2220 nvme_del_cq_end : nvme_del_queue_end);
2221 return 0;
2222 }
2223
2224 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
2225 {
2226 int nr_queues = dev->online_queues - 1, sent = 0;
2227 unsigned long timeout;
2228
2229 retry:
2230 timeout = ADMIN_TIMEOUT;
2231 while (nr_queues > 0) {
2232 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2233 break;
2234 nr_queues--;
2235 sent++;
2236 }
2237 while (sent) {
2238 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2239
2240 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
2241 timeout);
2242 if (timeout == 0)
2243 return false;
2244
2245 /* handle any remaining CQEs */
2246 if (opcode == nvme_admin_delete_cq &&
2247 !test_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags))
2248 nvme_poll_irqdisable(nvmeq, -1);
2249
2250 sent--;
2251 if (nr_queues)
2252 goto retry;
2253 }
2254 return true;
2255 }
2256
2257 static void nvme_dev_add(struct nvme_dev *dev)
2258 {
2259 int ret;
2260
2261 if (!dev->ctrl.tagset) {
2262 dev->tagset.ops = &nvme_mq_ops;
2263 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2264 dev->tagset.nr_maps = 2; /* default + read */
2265 if (dev->io_queues[HCTX_TYPE_POLL])
2266 dev->tagset.nr_maps++;
2267 dev->tagset.timeout = NVME_IO_TIMEOUT;
2268 dev->tagset.numa_node = dev_to_node(dev->dev);
2269 dev->tagset.queue_depth =
2270 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
2271 dev->tagset.cmd_size = sizeof(struct nvme_iod);
2272 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2273 dev->tagset.driver_data = dev;
2274
2275 /*
2276 * Some Apple controllers requires tags to be unique
2277 * across admin and IO queue, so reserve the first 32
2278 * tags of the IO queue.
2279 */
2280 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2281 dev->tagset.reserved_tags = NVME_AQ_DEPTH;
2282
2283 ret = blk_mq_alloc_tag_set(&dev->tagset);
2284 if (ret) {
2285 dev_warn(dev->ctrl.device,
2286 "IO queues tagset allocation failed %d\n", ret);
2287 return;
2288 }
2289 dev->ctrl.tagset = &dev->tagset;
2290 } else {
2291 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2292
2293 /* Free previously allocated queues that are no longer usable */
2294 nvme_free_queues(dev, dev->online_queues);
2295 }
2296
2297 nvme_dbbuf_set(dev);
2298 }
2299
2300 static int nvme_pci_enable(struct nvme_dev *dev)
2301 {
2302 int result = -ENOMEM;
2303 struct pci_dev *pdev = to_pci_dev(dev->dev);
2304
2305 if (pci_enable_device_mem(pdev))
2306 return result;
2307
2308 pci_set_master(pdev);
2309
2310 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)))
2311 goto disable;
2312
2313 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
2314 result = -ENODEV;
2315 goto disable;
2316 }
2317
2318 /*
2319 * Some devices and/or platforms don't advertise or work with INTx
2320 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2321 * adjust this later.
2322 */
2323 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2324 if (result < 0)
2325 return result;
2326
2327 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
2328
2329 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,
2330 io_queue_depth);
2331 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
2332 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
2333 dev->dbs = dev->bar + 4096;
2334
2335 /*
2336 * Some Apple controllers require a non-standard SQE size.
2337 * Interestingly they also seem to ignore the CC:IOSQES register
2338 * so we don't bother updating it here.
2339 */
2340 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2341 dev->io_sqes = 7;
2342 else
2343 dev->io_sqes = NVME_NVM_IOSQES;
2344
2345 /*
2346 * Temporary fix for the Apple controller found in the MacBook8,1 and
2347 * some MacBook7,1 to avoid controller resets and data loss.
2348 */
2349 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2350 dev->q_depth = 2;
2351 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2352 "set queue depth=%u to work around controller resets\n",
2353 dev->q_depth);
2354 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2355 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
2356 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
2357 dev->q_depth = 64;
2358 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2359 "set queue depth=%u\n", dev->q_depth);
2360 }
2361
2362 /*
2363 * Controllers with the shared tags quirk need the IO queue to be
2364 * big enough so that we get 32 tags for the admin queue
2365 */
2366 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2367 (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2368 dev->q_depth = NVME_AQ_DEPTH + 2;
2369 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2370 dev->q_depth);
2371 }
2372
2373
2374 nvme_map_cmb(dev);
2375
2376 pci_enable_pcie_error_reporting(pdev);
2377 pci_save_state(pdev);
2378 return 0;
2379
2380 disable:
2381 pci_disable_device(pdev);
2382 return result;
2383 }
2384
2385 static void nvme_dev_unmap(struct nvme_dev *dev)
2386 {
2387 if (dev->bar)
2388 iounmap(dev->bar);
2389 pci_release_mem_regions(to_pci_dev(dev->dev));
2390 }
2391
2392 static void nvme_pci_disable(struct nvme_dev *dev)
2393 {
2394 struct pci_dev *pdev = to_pci_dev(dev->dev);
2395
2396 pci_free_irq_vectors(pdev);
2397
2398 if (pci_is_enabled(pdev)) {
2399 pci_disable_pcie_error_reporting(pdev);
2400 pci_disable_device(pdev);
2401 }
2402 }
2403
2404 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
2405 {
2406 bool dead = true, freeze = false;
2407 struct pci_dev *pdev = to_pci_dev(dev->dev);
2408
2409 mutex_lock(&dev->shutdown_lock);
2410 if (pci_is_enabled(pdev)) {
2411 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2412
2413 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2414 dev->ctrl.state == NVME_CTRL_RESETTING) {
2415 freeze = true;
2416 nvme_start_freeze(&dev->ctrl);
2417 }
2418 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2419 pdev->error_state != pci_channel_io_normal);
2420 }
2421
2422 /*
2423 * Give the controller a chance to complete all entered requests if
2424 * doing a safe shutdown.
2425 */
2426 if (!dead && shutdown && freeze)
2427 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2428
2429 nvme_stop_queues(&dev->ctrl);
2430
2431 if (!dead && dev->ctrl.queue_count > 0) {
2432 nvme_disable_io_queues(dev);
2433 nvme_disable_admin_queue(dev, shutdown);
2434 }
2435 nvme_suspend_io_queues(dev);
2436 nvme_suspend_queue(&dev->queues[0]);
2437 nvme_pci_disable(dev);
2438
2439 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2440 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
2441 blk_mq_tagset_wait_completed_request(&dev->tagset);
2442 blk_mq_tagset_wait_completed_request(&dev->admin_tagset);
2443
2444 /*
2445 * The driver will not be starting up queues again if shutting down so
2446 * must flush all entered requests to their failed completion to avoid
2447 * deadlocking blk-mq hot-cpu notifier.
2448 */
2449 if (shutdown) {
2450 nvme_start_queues(&dev->ctrl);
2451 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
2452 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
2453 }
2454 mutex_unlock(&dev->shutdown_lock);
2455 }
2456
2457 static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2458 {
2459 if (!nvme_wait_reset(&dev->ctrl))
2460 return -EBUSY;
2461 nvme_dev_disable(dev, shutdown);
2462 return 0;
2463 }
2464
2465 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2466 {
2467 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2468 PAGE_SIZE, PAGE_SIZE, 0);
2469 if (!dev->prp_page_pool)
2470 return -ENOMEM;
2471
2472 /* Optimisation for I/Os between 4k and 128k */
2473 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2474 256, 256, 0);
2475 if (!dev->prp_small_pool) {
2476 dma_pool_destroy(dev->prp_page_pool);
2477 return -ENOMEM;
2478 }
2479 return 0;
2480 }
2481
2482 static void nvme_release_prp_pools(struct nvme_dev *dev)
2483 {
2484 dma_pool_destroy(dev->prp_page_pool);
2485 dma_pool_destroy(dev->prp_small_pool);
2486 }
2487
2488 static void nvme_free_tagset(struct nvme_dev *dev)
2489 {
2490 if (dev->tagset.tags)
2491 blk_mq_free_tag_set(&dev->tagset);
2492 dev->ctrl.tagset = NULL;
2493 }
2494
2495 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2496 {
2497 struct nvme_dev *dev = to_nvme_dev(ctrl);
2498
2499 nvme_dbbuf_dma_free(dev);
2500 put_device(dev->dev);
2501 nvme_free_tagset(dev);
2502 if (dev->ctrl.admin_q)
2503 blk_put_queue(dev->ctrl.admin_q);
2504 kfree(dev->queues);
2505 free_opal_dev(dev->ctrl.opal_dev);
2506 mempool_destroy(dev->iod_mempool);
2507 kfree(dev);
2508 }
2509
2510 static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
2511 {
2512 /*
2513 * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2514 * may be holding this pci_dev's device lock.
2515 */
2516 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2517 nvme_get_ctrl(&dev->ctrl);
2518 nvme_dev_disable(dev, false);
2519 nvme_kill_queues(&dev->ctrl);
2520 if (!queue_work(nvme_wq, &dev->remove_work))
2521 nvme_put_ctrl(&dev->ctrl);
2522 }
2523
2524 static void nvme_reset_work(struct work_struct *work)
2525 {
2526 struct nvme_dev *dev =
2527 container_of(work, struct nvme_dev, ctrl.reset_work);
2528 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2529 int result;
2530
2531 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) {
2532 result = -ENODEV;
2533 goto out;
2534 }
2535
2536 /*
2537 * If we're called to reset a live controller first shut it down before
2538 * moving on.
2539 */
2540 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2541 nvme_dev_disable(dev, false);
2542 nvme_sync_queues(&dev->ctrl);
2543
2544 mutex_lock(&dev->shutdown_lock);
2545 result = nvme_pci_enable(dev);
2546 if (result)
2547 goto out_unlock;
2548
2549 result = nvme_pci_configure_admin_queue(dev);
2550 if (result)
2551 goto out_unlock;
2552
2553 result = nvme_alloc_admin_tags(dev);
2554 if (result)
2555 goto out_unlock;
2556
2557 /*
2558 * Limit the max command size to prevent iod->sg allocations going
2559 * over a single page.
2560 */
2561 dev->ctrl.max_hw_sectors = min_t(u32,
2562 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9);
2563 dev->ctrl.max_segments = NVME_MAX_SEGS;
2564
2565 /*
2566 * Don't limit the IOMMU merged segment size.
2567 */
2568 dma_set_max_seg_size(dev->dev, 0xffffffff);
2569
2570 mutex_unlock(&dev->shutdown_lock);
2571
2572 /*
2573 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2574 * initializing procedure here.
2575 */
2576 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2577 dev_warn(dev->ctrl.device,
2578 "failed to mark controller CONNECTING\n");
2579 result = -EBUSY;
2580 goto out;
2581 }
2582
2583 result = nvme_init_identify(&dev->ctrl);
2584 if (result)
2585 goto out;
2586
2587 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2588 if (!dev->ctrl.opal_dev)
2589 dev->ctrl.opal_dev =
2590 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2591 else if (was_suspend)
2592 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2593 } else {
2594 free_opal_dev(dev->ctrl.opal_dev);
2595 dev->ctrl.opal_dev = NULL;
2596 }
2597
2598 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2599 result = nvme_dbbuf_dma_alloc(dev);
2600 if (result)
2601 dev_warn(dev->dev,
2602 "unable to allocate dma for dbbuf\n");
2603 }
2604
2605 if (dev->ctrl.hmpre) {
2606 result = nvme_setup_host_mem(dev);
2607 if (result < 0)
2608 goto out;
2609 }
2610
2611 result = nvme_setup_io_queues(dev);
2612 if (result)
2613 goto out;
2614
2615 /*
2616 * Keep the controller around but remove all namespaces if we don't have
2617 * any working I/O queue.
2618 */
2619 if (dev->online_queues < 2) {
2620 dev_warn(dev->ctrl.device, "IO queues not created\n");
2621 nvme_kill_queues(&dev->ctrl);
2622 nvme_remove_namespaces(&dev->ctrl);
2623 nvme_free_tagset(dev);
2624 } else {
2625 nvme_start_queues(&dev->ctrl);
2626 nvme_wait_freeze(&dev->ctrl);
2627 nvme_dev_add(dev);
2628 nvme_unfreeze(&dev->ctrl);
2629 }
2630
2631 /*
2632 * If only admin queue live, keep it to do further investigation or
2633 * recovery.
2634 */
2635 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2636 dev_warn(dev->ctrl.device,
2637 "failed to mark controller live state\n");
2638 result = -ENODEV;
2639 goto out;
2640 }
2641
2642 nvme_start_ctrl(&dev->ctrl);
2643 return;
2644
2645 out_unlock:
2646 mutex_unlock(&dev->shutdown_lock);
2647 out:
2648 if (result)
2649 dev_warn(dev->ctrl.device,
2650 "Removing after probe failure status: %d\n", result);
2651 nvme_remove_dead_ctrl(dev);
2652 }
2653
2654 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
2655 {
2656 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
2657 struct pci_dev *pdev = to_pci_dev(dev->dev);
2658
2659 if (pci_get_drvdata(pdev))
2660 device_release_driver(&pdev->dev);
2661 nvme_put_ctrl(&dev->ctrl);
2662 }
2663
2664 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2665 {
2666 *val = readl(to_nvme_dev(ctrl)->bar + off);
2667 return 0;
2668 }
2669
2670 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2671 {
2672 writel(val, to_nvme_dev(ctrl)->bar + off);
2673 return 0;
2674 }
2675
2676 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2677 {
2678 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
2679 return 0;
2680 }
2681
2682 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2683 {
2684 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2685
2686 return snprintf(buf, size, "%s", dev_name(&pdev->dev));
2687 }
2688
2689 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2690 .name = "pcie",
2691 .module = THIS_MODULE,
2692 .flags = NVME_F_METADATA_SUPPORTED |
2693 NVME_F_PCI_P2PDMA,
2694 .reg_read32 = nvme_pci_reg_read32,
2695 .reg_write32 = nvme_pci_reg_write32,
2696 .reg_read64 = nvme_pci_reg_read64,
2697 .free_ctrl = nvme_pci_free_ctrl,
2698 .submit_async_event = nvme_pci_submit_async_event,
2699 .get_address = nvme_pci_get_address,
2700 };
2701
2702 static int nvme_dev_map(struct nvme_dev *dev)
2703 {
2704 struct pci_dev *pdev = to_pci_dev(dev->dev);
2705
2706 if (pci_request_mem_regions(pdev, "nvme"))
2707 return -ENODEV;
2708
2709 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
2710 goto release;
2711
2712 return 0;
2713 release:
2714 pci_release_mem_regions(pdev);
2715 return -ENODEV;
2716 }
2717
2718 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
2719 {
2720 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2721 /*
2722 * Several Samsung devices seem to drop off the PCIe bus
2723 * randomly when APST is on and uses the deepest sleep state.
2724 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2725 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2726 * 950 PRO 256GB", but it seems to be restricted to two Dell
2727 * laptops.
2728 */
2729 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2730 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2731 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2732 return NVME_QUIRK_NO_DEEPEST_PS;
2733 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2734 /*
2735 * Samsung SSD 960 EVO drops off the PCIe bus after system
2736 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2737 * within few minutes after bootup on a Coffee Lake board -
2738 * ASUS PRIME Z370-A
2739 */
2740 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
2741 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2742 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
2743 return NVME_QUIRK_NO_APST;
2744 }
2745
2746 return 0;
2747 }
2748
2749 static void nvme_async_probe(void *data, async_cookie_t cookie)
2750 {
2751 struct nvme_dev *dev = data;
2752
2753 flush_work(&dev->ctrl.reset_work);
2754 flush_work(&dev->ctrl.scan_work);
2755 nvme_put_ctrl(&dev->ctrl);
2756 }
2757
2758 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2759 {
2760 int node, result = -ENOMEM;
2761 struct nvme_dev *dev;
2762 unsigned long quirks = id->driver_data;
2763 size_t alloc_size;
2764
2765 node = dev_to_node(&pdev->dev);
2766 if (node == NUMA_NO_NODE)
2767 set_dev_node(&pdev->dev, first_memory_node);
2768
2769 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2770 if (!dev)
2771 return -ENOMEM;
2772
2773 dev->queues = kcalloc_node(max_queue_count(), sizeof(struct nvme_queue),
2774 GFP_KERNEL, node);
2775 if (!dev->queues)
2776 goto free;
2777
2778 dev->dev = get_device(&pdev->dev);
2779 pci_set_drvdata(pdev, dev);
2780
2781 result = nvme_dev_map(dev);
2782 if (result)
2783 goto put_pci;
2784
2785 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2786 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2787 mutex_init(&dev->shutdown_lock);
2788
2789 result = nvme_setup_prp_pools(dev);
2790 if (result)
2791 goto unmap;
2792
2793 quirks |= check_vendor_combination_bug(pdev);
2794
2795 /*
2796 * Double check that our mempool alloc size will cover the biggest
2797 * command we support.
2798 */
2799 alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ,
2800 NVME_MAX_SEGS, true);
2801 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2802
2803 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
2804 mempool_kfree,
2805 (void *) alloc_size,
2806 GFP_KERNEL, node);
2807 if (!dev->iod_mempool) {
2808 result = -ENOMEM;
2809 goto release_pools;
2810 }
2811
2812 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2813 quirks);
2814 if (result)
2815 goto release_mempool;
2816
2817 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2818
2819 nvme_reset_ctrl(&dev->ctrl);
2820 nvme_get_ctrl(&dev->ctrl);
2821 async_schedule(nvme_async_probe, dev);
2822
2823 return 0;
2824
2825 release_mempool:
2826 mempool_destroy(dev->iod_mempool);
2827 release_pools:
2828 nvme_release_prp_pools(dev);
2829 unmap:
2830 nvme_dev_unmap(dev);
2831 put_pci:
2832 put_device(dev->dev);
2833 free:
2834 kfree(dev->queues);
2835 kfree(dev);
2836 return result;
2837 }
2838
2839 static void nvme_reset_prepare(struct pci_dev *pdev)
2840 {
2841 struct nvme_dev *dev = pci_get_drvdata(pdev);
2842
2843 /*
2844 * We don't need to check the return value from waiting for the reset
2845 * state as pci_dev device lock is held, making it impossible to race
2846 * with ->remove().
2847 */
2848 nvme_disable_prepare_reset(dev, false);
2849 nvme_sync_queues(&dev->ctrl);
2850 }
2851
2852 static void nvme_reset_done(struct pci_dev *pdev)
2853 {
2854 struct nvme_dev *dev = pci_get_drvdata(pdev);
2855
2856 if (!nvme_try_sched_reset(&dev->ctrl))
2857 flush_work(&dev->ctrl.reset_work);
2858 }
2859
2860 static void nvme_shutdown(struct pci_dev *pdev)
2861 {
2862 struct nvme_dev *dev = pci_get_drvdata(pdev);
2863 nvme_disable_prepare_reset(dev, true);
2864 }
2865
2866 /*
2867 * The driver's remove may be called on a device in a partially initialized
2868 * state. This function must not have any dependencies on the device state in
2869 * order to proceed.
2870 */
2871 static void nvme_remove(struct pci_dev *pdev)
2872 {
2873 struct nvme_dev *dev = pci_get_drvdata(pdev);
2874
2875 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2876 pci_set_drvdata(pdev, NULL);
2877
2878 if (!pci_device_is_present(pdev)) {
2879 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
2880 nvme_dev_disable(dev, true);
2881 nvme_dev_remove_admin(dev);
2882 }
2883
2884 flush_work(&dev->ctrl.reset_work);
2885 nvme_stop_ctrl(&dev->ctrl);
2886 nvme_remove_namespaces(&dev->ctrl);
2887 nvme_dev_disable(dev, true);
2888 nvme_release_cmb(dev);
2889 nvme_free_host_mem(dev);
2890 nvme_dev_remove_admin(dev);
2891 nvme_free_queues(dev, 0);
2892 nvme_uninit_ctrl(&dev->ctrl);
2893 nvme_release_prp_pools(dev);
2894 nvme_dev_unmap(dev);
2895 nvme_put_ctrl(&dev->ctrl);
2896 }
2897
2898 #ifdef CONFIG_PM_SLEEP
2899 static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
2900 {
2901 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
2902 }
2903
2904 static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
2905 {
2906 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
2907 }
2908
2909 static int nvme_resume(struct device *dev)
2910 {
2911 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
2912 struct nvme_ctrl *ctrl = &ndev->ctrl;
2913
2914 if (ndev->last_ps == U32_MAX ||
2915 nvme_set_power_state(ctrl, ndev->last_ps) != 0)
2916 return nvme_try_sched_reset(&ndev->ctrl);
2917 return 0;
2918 }
2919
2920 static int nvme_suspend(struct device *dev)
2921 {
2922 struct pci_dev *pdev = to_pci_dev(dev);
2923 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2924 struct nvme_ctrl *ctrl = &ndev->ctrl;
2925 int ret = -EBUSY;
2926
2927 ndev->last_ps = U32_MAX;
2928
2929 /*
2930 * The platform does not remove power for a kernel managed suspend so
2931 * use host managed nvme power settings for lowest idle power if
2932 * possible. This should have quicker resume latency than a full device
2933 * shutdown. But if the firmware is involved after the suspend or the
2934 * device does not support any non-default power states, shut down the
2935 * device fully.
2936 *
2937 * If ASPM is not enabled for the device, shut down the device and allow
2938 * the PCI bus layer to put it into D3 in order to take the PCIe link
2939 * down, so as to allow the platform to achieve its minimum low-power
2940 * state (which may not be possible if the link is up).
2941 */
2942 if (pm_suspend_via_firmware() || !ctrl->npss ||
2943 !pcie_aspm_enabled(pdev) ||
2944 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
2945 return nvme_disable_prepare_reset(ndev, true);
2946
2947 nvme_start_freeze(ctrl);
2948 nvme_wait_freeze(ctrl);
2949 nvme_sync_queues(ctrl);
2950
2951 if (ctrl->state != NVME_CTRL_LIVE)
2952 goto unfreeze;
2953
2954 ret = nvme_get_power_state(ctrl, &ndev->last_ps);
2955 if (ret < 0)
2956 goto unfreeze;
2957
2958 /*
2959 * A saved state prevents pci pm from generically controlling the
2960 * device's power. If we're using protocol specific settings, we don't
2961 * want pci interfering.
2962 */
2963 pci_save_state(pdev);
2964
2965 ret = nvme_set_power_state(ctrl, ctrl->npss);
2966 if (ret < 0)
2967 goto unfreeze;
2968
2969 if (ret) {
2970 /* discard the saved state */
2971 pci_load_saved_state(pdev, NULL);
2972
2973 /*
2974 * Clearing npss forces a controller reset on resume. The
2975 * correct value will be rediscovered then.
2976 */
2977 ret = nvme_disable_prepare_reset(ndev, true);
2978 ctrl->npss = 0;
2979 }
2980 unfreeze:
2981 nvme_unfreeze(ctrl);
2982 return ret;
2983 }
2984
2985 static int nvme_simple_suspend(struct device *dev)
2986 {
2987 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
2988 return nvme_disable_prepare_reset(ndev, true);
2989 }
2990
2991 static int nvme_simple_resume(struct device *dev)
2992 {
2993 struct pci_dev *pdev = to_pci_dev(dev);
2994 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2995
2996 return nvme_try_sched_reset(&ndev->ctrl);
2997 }
2998
2999 static const struct dev_pm_ops nvme_dev_pm_ops = {
3000 .suspend = nvme_suspend,
3001 .resume = nvme_resume,
3002 .freeze = nvme_simple_suspend,
3003 .thaw = nvme_simple_resume,
3004 .poweroff = nvme_simple_suspend,
3005 .restore = nvme_simple_resume,
3006 };
3007 #endif /* CONFIG_PM_SLEEP */
3008
3009 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3010 pci_channel_state_t state)
3011 {
3012 struct nvme_dev *dev = pci_get_drvdata(pdev);
3013
3014 /*
3015 * A frozen channel requires a reset. When detected, this method will
3016 * shutdown the controller to quiesce. The controller will be restarted
3017 * after the slot reset through driver's slot_reset callback.
3018 */
3019 switch (state) {
3020 case pci_channel_io_normal:
3021 return PCI_ERS_RESULT_CAN_RECOVER;
3022 case pci_channel_io_frozen:
3023 dev_warn(dev->ctrl.device,
3024 "frozen state error detected, reset controller\n");
3025 nvme_dev_disable(dev, false);
3026 return PCI_ERS_RESULT_NEED_RESET;
3027 case pci_channel_io_perm_failure:
3028 dev_warn(dev->ctrl.device,
3029 "failure state error detected, request disconnect\n");
3030 return PCI_ERS_RESULT_DISCONNECT;
3031 }
3032 return PCI_ERS_RESULT_NEED_RESET;
3033 }
3034
3035 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3036 {
3037 struct nvme_dev *dev = pci_get_drvdata(pdev);
3038
3039 dev_info(dev->ctrl.device, "restart after slot reset\n");
3040 pci_restore_state(pdev);
3041 nvme_reset_ctrl(&dev->ctrl);
3042 return PCI_ERS_RESULT_RECOVERED;
3043 }
3044
3045 static void nvme_error_resume(struct pci_dev *pdev)
3046 {
3047 struct nvme_dev *dev = pci_get_drvdata(pdev);
3048
3049 flush_work(&dev->ctrl.reset_work);
3050 }
3051
3052 static const struct pci_error_handlers nvme_err_handler = {
3053 .error_detected = nvme_error_detected,
3054 .slot_reset = nvme_slot_reset,
3055 .resume = nvme_error_resume,
3056 .reset_prepare = nvme_reset_prepare,
3057 .reset_done = nvme_reset_done,
3058 };
3059
3060 static const struct pci_device_id nvme_id_table[] = {
3061 { PCI_VDEVICE(INTEL, 0x0953),
3062 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3063 NVME_QUIRK_DEALLOCATE_ZEROES, },
3064 { PCI_VDEVICE(INTEL, 0x0a53),
3065 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3066 NVME_QUIRK_DEALLOCATE_ZEROES, },
3067 { PCI_VDEVICE(INTEL, 0x0a54),
3068 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3069 NVME_QUIRK_DEALLOCATE_ZEROES, },
3070 { PCI_VDEVICE(INTEL, 0x0a55),
3071 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3072 NVME_QUIRK_DEALLOCATE_ZEROES, },
3073 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
3074 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3075 NVME_QUIRK_MEDIUM_PRIO_SQ |
3076 NVME_QUIRK_NO_TEMP_THRESH_CHANGE },
3077 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
3078 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3079 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
3080 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
3081 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3082 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
3083 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3084 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
3085 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3086 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
3087 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3088 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
3089 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3090 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
3091 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3092 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
3093 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3094 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
3095 .driver_data = NVME_QUIRK_LIGHTNVM, },
3096 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
3097 .driver_data = NVME_QUIRK_LIGHTNVM, },
3098 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */
3099 .driver_data = NVME_QUIRK_LIGHTNVM, },
3100 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */
3101 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3102 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */
3103 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3104 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3105 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3106 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
3107 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
3108 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3109 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
3110 NVME_QUIRK_128_BYTES_SQES |
3111 NVME_QUIRK_SHARED_TAGS },
3112 { 0, }
3113 };
3114 MODULE_DEVICE_TABLE(pci, nvme_id_table);
3115
3116 static struct pci_driver nvme_driver = {
3117 .name = "nvme",
3118 .id_table = nvme_id_table,
3119 .probe = nvme_probe,
3120 .remove = nvme_remove,
3121 .shutdown = nvme_shutdown,
3122 #ifdef CONFIG_PM_SLEEP
3123 .driver = {
3124 .pm = &nvme_dev_pm_ops,
3125 },
3126 #endif
3127 .sriov_configure = pci_sriov_configure_simple,
3128 .err_handler = &nvme_err_handler,
3129 };
3130
3131 static int __init nvme_init(void)
3132 {
3133 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3134 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3135 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
3136 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
3137
3138 write_queues = min(write_queues, num_possible_cpus());
3139 poll_queues = min(poll_queues, num_possible_cpus());
3140 return pci_register_driver(&nvme_driver);
3141 }
3142
3143 static void __exit nvme_exit(void)
3144 {
3145 pci_unregister_driver(&nvme_driver);
3146 flush_workqueue(nvme_wq);
3147 }
3148
3149 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3150 MODULE_LICENSE("GPL");
3151 MODULE_VERSION("1.0");
3152 module_init(nvme_init);
3153 module_exit(nvme_exit);
Linux with added FPC-III support