drivers/phy/mediatek/phy-mtk-tphy.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2015 MediaTek Inc.
   4  * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
   5  *
   6  */
   7
   8 #include <dt-bindings/phy/phy.h>
   9 #include <linux/clk.h>
  10 #include <linux/delay.h>
  11 #include <linux/io.h>
  12 #include <linux/iopoll.h>
  13 #include <linux/module.h>
  14 #include <linux/of_address.h>
  15 #include <linux/of_device.h>
  16 #include <linux/phy/phy.h>
  17 #include <linux/platform_device.h>
  18
  19 /* version V1 sub-banks offset base address */
  20 /* banks shared by multiple phys */
  21 #define SSUSB_SIFSLV_V1_SPLLC           0x000   /* shared by u3 phys */
  22 #define SSUSB_SIFSLV_V1_U2FREQ          0x100   /* shared by u2 phys */
  23 #define SSUSB_SIFSLV_V1_CHIP            0x300   /* shared by u3 phys */
  24 /* u2 phy bank */
  25 #define SSUSB_SIFSLV_V1_U2PHY_COM       0x000
  26 /* u3/pcie/sata phy banks */
  27 #define SSUSB_SIFSLV_V1_U3PHYD          0x000
  28 #define SSUSB_SIFSLV_V1_U3PHYA          0x200
  29
  30 /* version V2 sub-banks offset base address */
  31 /* u2 phy banks */
  32 #define SSUSB_SIFSLV_V2_MISC            0x000
  33 #define SSUSB_SIFSLV_V2_U2FREQ          0x100
  34 #define SSUSB_SIFSLV_V2_U2PHY_COM       0x300
  35 /* u3/pcie/sata phy banks */
  36 #define SSUSB_SIFSLV_V2_SPLLC           0x000
  37 #define SSUSB_SIFSLV_V2_CHIP            0x100
  38 #define SSUSB_SIFSLV_V2_U3PHYD          0x200
  39 #define SSUSB_SIFSLV_V2_U3PHYA          0x400
  40
  41 #define U3P_USBPHYACR0          0x000
  42 #define PA0_RG_U2PLL_FORCE_ON           BIT(15)
  43 #define PA0_RG_USB20_INTR_EN            BIT(5)
  44
  45 #define U3P_USBPHYACR1          0x004
  46 #define PA1_RG_VRT_SEL                  GENMASK(14, 12)
  47 #define PA1_RG_VRT_SEL_VAL(x)   ((0x7 & (x)) << 12)
  48 #define PA1_RG_TERM_SEL         GENMASK(10, 8)
  49 #define PA1_RG_TERM_SEL_VAL(x)  ((0x7 & (x)) << 8)
  50
  51 #define U3P_USBPHYACR2          0x008
  52 #define PA2_RG_SIF_U2PLL_FORCE_EN       BIT(18)
  53
  54 #define U3P_USBPHYACR5          0x014
  55 #define PA5_RG_U2_HSTX_SRCAL_EN BIT(15)
  56 #define PA5_RG_U2_HSTX_SRCTRL           GENMASK(14, 12)
  57 #define PA5_RG_U2_HSTX_SRCTRL_VAL(x)    ((0x7 & (x)) << 12)
  58 #define PA5_RG_U2_HS_100U_U3_EN BIT(11)
  59
  60 #define U3P_USBPHYACR6          0x018
  61 #define PA6_RG_U2_BC11_SW_EN            BIT(23)
  62 #define PA6_RG_U2_OTG_VBUSCMP_EN        BIT(20)
  63 #define PA6_RG_U2_SQTH          GENMASK(3, 0)
  64 #define PA6_RG_U2_SQTH_VAL(x)   (0xf & (x))
  65
  66 #define U3P_U2PHYACR4           0x020
  67 #define P2C_RG_USB20_GPIO_CTL           BIT(9)
  68 #define P2C_USB20_GPIO_MODE             BIT(8)
  69 #define P2C_U2_GPIO_CTR_MSK     (P2C_RG_USB20_GPIO_CTL | P2C_USB20_GPIO_MODE)
  70
  71 #define U3D_U2PHYDCR0           0x060
  72 #define P2C_RG_SIF_U2PLL_FORCE_ON       BIT(24)
  73
  74 #define U3P_U2PHYDTM0           0x068
  75 #define P2C_FORCE_UART_EN               BIT(26)
  76 #define P2C_FORCE_DATAIN                BIT(23)
  77 #define P2C_FORCE_DM_PULLDOWN           BIT(21)
  78 #define P2C_FORCE_DP_PULLDOWN           BIT(20)
  79 #define P2C_FORCE_XCVRSEL               BIT(19)
  80 #define P2C_FORCE_SUSPENDM              BIT(18)
  81 #define P2C_FORCE_TERMSEL               BIT(17)
  82 #define P2C_RG_DATAIN                   GENMASK(13, 10)
  83 #define P2C_RG_DATAIN_VAL(x)            ((0xf & (x)) << 10)
  84 #define P2C_RG_DMPULLDOWN               BIT(7)
  85 #define P2C_RG_DPPULLDOWN               BIT(6)
  86 #define P2C_RG_XCVRSEL                  GENMASK(5, 4)
  87 #define P2C_RG_XCVRSEL_VAL(x)           ((0x3 & (x)) << 4)
  88 #define P2C_RG_SUSPENDM                 BIT(3)
  89 #define P2C_RG_TERMSEL                  BIT(2)
  90 #define P2C_DTM0_PART_MASK \
  91                 (P2C_FORCE_DATAIN | P2C_FORCE_DM_PULLDOWN | \
  92                 P2C_FORCE_DP_PULLDOWN | P2C_FORCE_XCVRSEL | \
  93                 P2C_FORCE_TERMSEL | P2C_RG_DMPULLDOWN | \
  94                 P2C_RG_DPPULLDOWN | P2C_RG_TERMSEL)
  95
  96 #define U3P_U2PHYDTM1           0x06C
  97 #define P2C_RG_UART_EN                  BIT(16)
  98 #define P2C_FORCE_IDDIG         BIT(9)
  99 #define P2C_RG_VBUSVALID                BIT(5)
 100 #define P2C_RG_SESSEND                  BIT(4)
 101 #define P2C_RG_AVALID                   BIT(2)
 102 #define P2C_RG_IDDIG                    BIT(1)
 103
 104 #define U3P_U2PHYBC12C          0x080
 105 #define P2C_RG_CHGDT_EN         BIT(0)
 106
 107 #define U3P_U3_CHIP_GPIO_CTLD           0x0c
 108 #define P3C_REG_IP_SW_RST               BIT(31)
 109 #define P3C_MCU_BUS_CK_GATE_EN          BIT(30)
 110 #define P3C_FORCE_IP_SW_RST             BIT(29)
 111
 112 #define U3P_U3_CHIP_GPIO_CTLE           0x10
 113 #define P3C_RG_SWRST_U3_PHYD            BIT(25)
 114 #define P3C_RG_SWRST_U3_PHYD_FORCE_EN   BIT(24)
 115
 116 #define U3P_U3_PHYA_REG0        0x000
 117 #define P3A_RG_CLKDRV_OFF               GENMASK(3, 2)
 118 #define P3A_RG_CLKDRV_OFF_VAL(x)        ((0x3 & (x)) << 2)
 119
 120 #define U3P_U3_PHYA_REG1        0x004
 121 #define P3A_RG_CLKDRV_AMP               GENMASK(31, 29)
 122 #define P3A_RG_CLKDRV_AMP_VAL(x)        ((0x7 & (x)) << 29)
 123
 124 #define U3P_U3_PHYA_REG6        0x018
 125 #define P3A_RG_TX_EIDLE_CM              GENMASK(31, 28)
 126 #define P3A_RG_TX_EIDLE_CM_VAL(x)       ((0xf & (x)) << 28)
 127
 128 #define U3P_U3_PHYA_REG9        0x024
 129 #define P3A_RG_RX_DAC_MUX               GENMASK(5, 1)
 130 #define P3A_RG_RX_DAC_MUX_VAL(x)        ((0x1f & (x)) << 1)
 131
 132 #define U3P_U3_PHYA_DA_REG0     0x100
 133 #define P3A_RG_XTAL_EXT_PE2H            GENMASK(17, 16)
 134 #define P3A_RG_XTAL_EXT_PE2H_VAL(x)     ((0x3 & (x)) << 16)
 135 #define P3A_RG_XTAL_EXT_PE1H            GENMASK(13, 12)
 136 #define P3A_RG_XTAL_EXT_PE1H_VAL(x)     ((0x3 & (x)) << 12)
 137 #define P3A_RG_XTAL_EXT_EN_U3           GENMASK(11, 10)
 138 #define P3A_RG_XTAL_EXT_EN_U3_VAL(x)    ((0x3 & (x)) << 10)
 139
 140 #define U3P_U3_PHYA_DA_REG4     0x108
 141 #define P3A_RG_PLL_DIVEN_PE2H           GENMASK(21, 19)
 142 #define P3A_RG_PLL_BC_PE2H              GENMASK(7, 6)
 143 #define P3A_RG_PLL_BC_PE2H_VAL(x)       ((0x3 & (x)) << 6)
 144
 145 #define U3P_U3_PHYA_DA_REG5     0x10c
 146 #define P3A_RG_PLL_BR_PE2H              GENMASK(29, 28)
 147 #define P3A_RG_PLL_BR_PE2H_VAL(x)       ((0x3 & (x)) << 28)
 148 #define P3A_RG_PLL_IC_PE2H              GENMASK(15, 12)
 149 #define P3A_RG_PLL_IC_PE2H_VAL(x)       ((0xf & (x)) << 12)
 150
 151 #define U3P_U3_PHYA_DA_REG6     0x110
 152 #define P3A_RG_PLL_IR_PE2H              GENMASK(19, 16)
 153 #define P3A_RG_PLL_IR_PE2H_VAL(x)       ((0xf & (x)) << 16)
 154
 155 #define U3P_U3_PHYA_DA_REG7     0x114
 156 #define P3A_RG_PLL_BP_PE2H              GENMASK(19, 16)
 157 #define P3A_RG_PLL_BP_PE2H_VAL(x)       ((0xf & (x)) << 16)
 158
 159 #define U3P_U3_PHYA_DA_REG20    0x13c
 160 #define P3A_RG_PLL_DELTA1_PE2H          GENMASK(31, 16)
 161 #define P3A_RG_PLL_DELTA1_PE2H_VAL(x)   ((0xffff & (x)) << 16)
 162
 163 #define U3P_U3_PHYA_DA_REG25    0x148
 164 #define P3A_RG_PLL_DELTA_PE2H           GENMASK(15, 0)
 165 #define P3A_RG_PLL_DELTA_PE2H_VAL(x)    (0xffff & (x))
 166
 167 #define U3P_U3_PHYD_LFPS1               0x00c
 168 #define P3D_RG_FWAKE_TH         GENMASK(21, 16)
 169 #define P3D_RG_FWAKE_TH_VAL(x)  ((0x3f & (x)) << 16)
 170
 171 #define U3P_U3_PHYD_CDR1                0x05c
 172 #define P3D_RG_CDR_BIR_LTD1             GENMASK(28, 24)
 173 #define P3D_RG_CDR_BIR_LTD1_VAL(x)      ((0x1f & (x)) << 24)
 174 #define P3D_RG_CDR_BIR_LTD0             GENMASK(12, 8)
 175 #define P3D_RG_CDR_BIR_LTD0_VAL(x)      ((0x1f & (x)) << 8)
 176
 177 #define U3P_U3_PHYD_RXDET1              0x128
 178 #define P3D_RG_RXDET_STB2_SET           GENMASK(17, 9)
 179 #define P3D_RG_RXDET_STB2_SET_VAL(x)    ((0x1ff & (x)) << 9)
 180
 181 #define U3P_U3_PHYD_RXDET2              0x12c
 182 #define P3D_RG_RXDET_STB2_SET_P3        GENMASK(8, 0)
 183 #define P3D_RG_RXDET_STB2_SET_P3_VAL(x) (0x1ff & (x))
 184
 185 #define U3P_SPLLC_XTALCTL3              0x018
 186 #define XC3_RG_U3_XTAL_RX_PWD           BIT(9)
 187 #define XC3_RG_U3_FRC_XTAL_RX_PWD       BIT(8)
 188
 189 #define U3P_U2FREQ_FMCR0        0x00
 190 #define P2F_RG_MONCLK_SEL       GENMASK(27, 26)
 191 #define P2F_RG_MONCLK_SEL_VAL(x)        ((0x3 & (x)) << 26)
 192 #define P2F_RG_FREQDET_EN       BIT(24)
 193 #define P2F_RG_CYCLECNT         GENMASK(23, 0)
 194 #define P2F_RG_CYCLECNT_VAL(x)  ((P2F_RG_CYCLECNT) & (x))
 195
 196 #define U3P_U2FREQ_VALUE        0x0c
 197
 198 #define U3P_U2FREQ_FMMONR1      0x10
 199 #define P2F_USB_FM_VALID        BIT(0)
 200 #define P2F_RG_FRCK_EN          BIT(8)
 201
 202 #define U3P_REF_CLK             26      /* MHZ */
 203 #define U3P_SLEW_RATE_COEF      28
 204 #define U3P_SR_COEF_DIVISOR     1000
 205 #define U3P_FM_DET_CYCLE_CNT    1024
 206
 207 /* SATA register setting */
 208 #define PHYD_CTRL_SIGNAL_MODE4          0x1c
 209 /* CDR Charge Pump P-path current adjustment */
 210 #define RG_CDR_BICLTD1_GEN1_MSK         GENMASK(23, 20)
 211 #define RG_CDR_BICLTD1_GEN1_VAL(x)      ((0xf & (x)) << 20)
 212 #define RG_CDR_BICLTD0_GEN1_MSK         GENMASK(11, 8)
 213 #define RG_CDR_BICLTD0_GEN1_VAL(x)      ((0xf & (x)) << 8)
 214
 215 #define PHYD_DESIGN_OPTION2             0x24
 216 /* Symbol lock count selection */
 217 #define RG_LOCK_CNT_SEL_MSK             GENMASK(5, 4)
 218 #define RG_LOCK_CNT_SEL_VAL(x)          ((0x3 & (x)) << 4)
 219
 220 #define PHYD_DESIGN_OPTION9     0x40
 221 /* COMWAK GAP width window */
 222 #define RG_TG_MAX_MSK           GENMASK(20, 16)
 223 #define RG_TG_MAX_VAL(x)        ((0x1f & (x)) << 16)
 224 /* COMINIT GAP width window */
 225 #define RG_T2_MAX_MSK           GENMASK(13, 8)
 226 #define RG_T2_MAX_VAL(x)        ((0x3f & (x)) << 8)
 227 /* COMWAK GAP width window */
 228 #define RG_TG_MIN_MSK           GENMASK(7, 5)
 229 #define RG_TG_MIN_VAL(x)        ((0x7 & (x)) << 5)
 230 /* COMINIT GAP width window */
 231 #define RG_T2_MIN_MSK           GENMASK(4, 0)
 232 #define RG_T2_MIN_VAL(x)        (0x1f & (x))
 233
 234 #define ANA_RG_CTRL_SIGNAL1             0x4c
 235 /* TX driver tail current control for 0dB de-empahsis mdoe for Gen1 speed */
 236 #define RG_IDRV_0DB_GEN1_MSK            GENMASK(13, 8)
 237 #define RG_IDRV_0DB_GEN1_VAL(x)         ((0x3f & (x)) << 8)
 238
 239 #define ANA_RG_CTRL_SIGNAL4             0x58
 240 #define RG_CDR_BICLTR_GEN1_MSK          GENMASK(23, 20)
 241 #define RG_CDR_BICLTR_GEN1_VAL(x)       ((0xf & (x)) << 20)
 242 /* Loop filter R1 resistance adjustment for Gen1 speed */
 243 #define RG_CDR_BR_GEN2_MSK              GENMASK(10, 8)
 244 #define RG_CDR_BR_GEN2_VAL(x)           ((0x7 & (x)) << 8)
 245
 246 #define ANA_RG_CTRL_SIGNAL6             0x60
 247 /* I-path capacitance adjustment for Gen1 */
 248 #define RG_CDR_BC_GEN1_MSK              GENMASK(28, 24)
 249 #define RG_CDR_BC_GEN1_VAL(x)           ((0x1f & (x)) << 24)
 250 #define RG_CDR_BIRLTR_GEN1_MSK          GENMASK(4, 0)
 251 #define RG_CDR_BIRLTR_GEN1_VAL(x)       (0x1f & (x))
 252
 253 #define ANA_EQ_EYE_CTRL_SIGNAL1         0x6c
 254 /* RX Gen1 LEQ tuning step */
 255 #define RG_EQ_DLEQ_LFI_GEN1_MSK         GENMASK(11, 8)
 256 #define RG_EQ_DLEQ_LFI_GEN1_VAL(x)      ((0xf & (x)) << 8)
 257
 258 #define ANA_EQ_EYE_CTRL_SIGNAL4         0xd8
 259 #define RG_CDR_BIRLTD0_GEN1_MSK         GENMASK(20, 16)
 260 #define RG_CDR_BIRLTD0_GEN1_VAL(x)      ((0x1f & (x)) << 16)
 261
 262 #define ANA_EQ_EYE_CTRL_SIGNAL5         0xdc
 263 #define RG_CDR_BIRLTD0_GEN3_MSK         GENMASK(4, 0)
 264 #define RG_CDR_BIRLTD0_GEN3_VAL(x)      (0x1f & (x))
 265
 266 enum mtk_phy_version {
 267         MTK_PHY_V1 = 1,
 268         MTK_PHY_V2,
 269 };
 270
 271 struct mtk_phy_pdata {
 272         /* avoid RX sensitivity level degradation only for mt8173 */
 273         bool avoid_rx_sen_degradation;
 274         enum mtk_phy_version version;
 275 };
 276
 277 struct u2phy_banks {
 278         void __iomem *misc;
 279         void __iomem *fmreg;
 280         void __iomem *com;
 281 };
 282
 283 struct u3phy_banks {
 284         void __iomem *spllc;
 285         void __iomem *chip;
 286         void __iomem *phyd; /* include u3phyd_bank2 */
 287         void __iomem *phya; /* include u3phya_da */
 288 };
 289
 290 struct mtk_phy_instance {
 291         struct phy *phy;
 292         void __iomem *port_base;
 293         union {
 294                 struct u2phy_banks u2_banks;
 295                 struct u3phy_banks u3_banks;
 296         };
 297         struct clk *ref_clk;    /* reference clock of anolog phy */
 298         u32 index;
 299         u8 type;
 300         int eye_src;
 301         int eye_vrt;
 302         int eye_term;
 303         bool bc12_en;
 304 };
 305
 306 struct mtk_tphy {
 307         struct device *dev;
 308         void __iomem *sif_base; /* only shared sif */
 309         /* deprecated, use @ref_clk instead in phy instance */
 310         struct clk *u3phya_ref; /* reference clock of usb3 anolog phy */
 311         const struct mtk_phy_pdata *pdata;
 312         struct mtk_phy_instance **phys;
 313         int nphys;
 314         int src_ref_clk; /* MHZ, reference clock for slew rate calibrate */
 315         int src_coef; /* coefficient for slew rate calibrate */
 316 };
 317
 318 static void hs_slew_rate_calibrate(struct mtk_tphy *tphy,
 319         struct mtk_phy_instance *instance)
 320 {
 321         struct u2phy_banks *u2_banks = &instance->u2_banks;
 322         void __iomem *fmreg = u2_banks->fmreg;
 323         void __iomem *com = u2_banks->com;
 324         int calibration_val;
 325         int fm_out;
 326         u32 tmp;
 327
 328         /* use force value */
 329         if (instance->eye_src)
 330                 return;
 331
 332         /* enable USB ring oscillator */
 333         tmp = readl(com + U3P_USBPHYACR5);
 334         tmp |= PA5_RG_U2_HSTX_SRCAL_EN;
 335         writel(tmp, com + U3P_USBPHYACR5);
 336         udelay(1);
 337
 338         /*enable free run clock */
 339         tmp = readl(fmreg + U3P_U2FREQ_FMMONR1);
 340         tmp |= P2F_RG_FRCK_EN;
 341         writel(tmp, fmreg + U3P_U2FREQ_FMMONR1);
 342
 343         /* set cycle count as 1024, and select u2 channel */
 344         tmp = readl(fmreg + U3P_U2FREQ_FMCR0);
 345         tmp &= ~(P2F_RG_CYCLECNT | P2F_RG_MONCLK_SEL);
 346         tmp |= P2F_RG_CYCLECNT_VAL(U3P_FM_DET_CYCLE_CNT);
 347         if (tphy->pdata->version == MTK_PHY_V1)
 348                 tmp |= P2F_RG_MONCLK_SEL_VAL(instance->index >> 1);
 349
 350         writel(tmp, fmreg + U3P_U2FREQ_FMCR0);
 351
 352         /* enable frequency meter */
 353         tmp = readl(fmreg + U3P_U2FREQ_FMCR0);
 354         tmp |= P2F_RG_FREQDET_EN;
 355         writel(tmp, fmreg + U3P_U2FREQ_FMCR0);
 356
 357         /* ignore return value */
 358         readl_poll_timeout(fmreg + U3P_U2FREQ_FMMONR1, tmp,
 359                            (tmp & P2F_USB_FM_VALID), 10, 200);
 360
 361         fm_out = readl(fmreg + U3P_U2FREQ_VALUE);
 362
 363         /* disable frequency meter */
 364         tmp = readl(fmreg + U3P_U2FREQ_FMCR0);
 365         tmp &= ~P2F_RG_FREQDET_EN;
 366         writel(tmp, fmreg + U3P_U2FREQ_FMCR0);
 367
 368         /*disable free run clock */
 369         tmp = readl(fmreg + U3P_U2FREQ_FMMONR1);
 370         tmp &= ~P2F_RG_FRCK_EN;
 371         writel(tmp, fmreg + U3P_U2FREQ_FMMONR1);
 372
 373         if (fm_out) {
 374                 /* ( 1024 / FM_OUT ) x reference clock frequency x coef */
 375                 tmp = tphy->src_ref_clk * tphy->src_coef;
 376                 tmp = (tmp * U3P_FM_DET_CYCLE_CNT) / fm_out;
 377                 calibration_val = DIV_ROUND_CLOSEST(tmp, U3P_SR_COEF_DIVISOR);
 378         } else {
 379                 /* if FM detection fail, set default value */
 380                 calibration_val = 4;
 381         }
 382         dev_dbg(tphy->dev, "phy:%d, fm_out:%d, calib:%d (clk:%d, coef:%d)\n",
 383                 instance->index, fm_out, calibration_val,
 384                 tphy->src_ref_clk, tphy->src_coef);
 385
 386         /* set HS slew rate */
 387         tmp = readl(com + U3P_USBPHYACR5);
 388         tmp &= ~PA5_RG_U2_HSTX_SRCTRL;
 389         tmp |= PA5_RG_U2_HSTX_SRCTRL_VAL(calibration_val);
 390         writel(tmp, com + U3P_USBPHYACR5);
 391
 392         /* disable USB ring oscillator */
 393         tmp = readl(com + U3P_USBPHYACR5);
 394         tmp &= ~PA5_RG_U2_HSTX_SRCAL_EN;
 395         writel(tmp, com + U3P_USBPHYACR5);
 396 }
 397
 398 static void u3_phy_instance_init(struct mtk_tphy *tphy,
 399         struct mtk_phy_instance *instance)
 400 {
 401         struct u3phy_banks *u3_banks = &instance->u3_banks;
 402         u32 tmp;
 403
 404         /* gating PCIe Analog XTAL clock */
 405         tmp = readl(u3_banks->spllc + U3P_SPLLC_XTALCTL3);
 406         tmp |= XC3_RG_U3_XTAL_RX_PWD | XC3_RG_U3_FRC_XTAL_RX_PWD;
 407         writel(tmp, u3_banks->spllc + U3P_SPLLC_XTALCTL3);
 408
 409         /* gating XSQ */
 410         tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG0);
 411         tmp &= ~P3A_RG_XTAL_EXT_EN_U3;
 412         tmp |= P3A_RG_XTAL_EXT_EN_U3_VAL(2);
 413         writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG0);
 414
 415         tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG9);
 416         tmp &= ~P3A_RG_RX_DAC_MUX;
 417         tmp |= P3A_RG_RX_DAC_MUX_VAL(4);
 418         writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG9);
 419
 420         tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG6);
 421         tmp &= ~P3A_RG_TX_EIDLE_CM;
 422         tmp |= P3A_RG_TX_EIDLE_CM_VAL(0xe);
 423         writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG6);
 424
 425         tmp = readl(u3_banks->phyd + U3P_U3_PHYD_CDR1);
 426         tmp &= ~(P3D_RG_CDR_BIR_LTD0 | P3D_RG_CDR_BIR_LTD1);
 427         tmp |= P3D_RG_CDR_BIR_LTD0_VAL(0xc) | P3D_RG_CDR_BIR_LTD1_VAL(0x3);
 428         writel(tmp, u3_banks->phyd + U3P_U3_PHYD_CDR1);
 429
 430         tmp = readl(u3_banks->phyd + U3P_U3_PHYD_LFPS1);
 431         tmp &= ~P3D_RG_FWAKE_TH;
 432         tmp |= P3D_RG_FWAKE_TH_VAL(0x34);
 433         writel(tmp, u3_banks->phyd + U3P_U3_PHYD_LFPS1);
 434
 435         tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET1);
 436         tmp &= ~P3D_RG_RXDET_STB2_SET;
 437         tmp |= P3D_RG_RXDET_STB2_SET_VAL(0x10);
 438         writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET1);
 439
 440         tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET2);
 441         tmp &= ~P3D_RG_RXDET_STB2_SET_P3;
 442         tmp |= P3D_RG_RXDET_STB2_SET_P3_VAL(0x10);
 443         writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET2);
 444
 445         dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
 446 }
 447
 448 static void u2_phy_instance_init(struct mtk_tphy *tphy,
 449         struct mtk_phy_instance *instance)
 450 {
 451         struct u2phy_banks *u2_banks = &instance->u2_banks;
 452         void __iomem *com = u2_banks->com;
 453         u32 index = instance->index;
 454         u32 tmp;
 455
 456         /* switch to USB function, and enable usb pll */
 457         tmp = readl(com + U3P_U2PHYDTM0);
 458         tmp &= ~(P2C_FORCE_UART_EN | P2C_FORCE_SUSPENDM);
 459         tmp |= P2C_RG_XCVRSEL_VAL(1) | P2C_RG_DATAIN_VAL(0);
 460         writel(tmp, com + U3P_U2PHYDTM0);
 461
 462         tmp = readl(com + U3P_U2PHYDTM1);
 463         tmp &= ~P2C_RG_UART_EN;
 464         writel(tmp, com + U3P_U2PHYDTM1);
 465
 466         tmp = readl(com + U3P_USBPHYACR0);
 467         tmp |= PA0_RG_USB20_INTR_EN;
 468         writel(tmp, com + U3P_USBPHYACR0);
 469
 470         /* disable switch 100uA current to SSUSB */
 471         tmp = readl(com + U3P_USBPHYACR5);
 472         tmp &= ~PA5_RG_U2_HS_100U_U3_EN;
 473         writel(tmp, com + U3P_USBPHYACR5);
 474
 475         if (!index) {
 476                 tmp = readl(com + U3P_U2PHYACR4);
 477                 tmp &= ~P2C_U2_GPIO_CTR_MSK;
 478                 writel(tmp, com + U3P_U2PHYACR4);
 479         }
 480
 481         if (tphy->pdata->avoid_rx_sen_degradation) {
 482                 if (!index) {
 483                         tmp = readl(com + U3P_USBPHYACR2);
 484                         tmp |= PA2_RG_SIF_U2PLL_FORCE_EN;
 485                         writel(tmp, com + U3P_USBPHYACR2);
 486
 487                         tmp = readl(com + U3D_U2PHYDCR0);
 488                         tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON;
 489                         writel(tmp, com + U3D_U2PHYDCR0);
 490                 } else {
 491                         tmp = readl(com + U3D_U2PHYDCR0);
 492                         tmp |= P2C_RG_SIF_U2PLL_FORCE_ON;
 493                         writel(tmp, com + U3D_U2PHYDCR0);
 494
 495                         tmp = readl(com + U3P_U2PHYDTM0);
 496                         tmp |= P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM;
 497                         writel(tmp, com + U3P_U2PHYDTM0);
 498                 }
 499         }
 500
 501         tmp = readl(com + U3P_USBPHYACR6);
 502         tmp &= ~PA6_RG_U2_BC11_SW_EN;   /* DP/DM BC1.1 path Disable */
 503         tmp &= ~PA6_RG_U2_SQTH;
 504         tmp |= PA6_RG_U2_SQTH_VAL(2);
 505         writel(tmp, com + U3P_USBPHYACR6);
 506
 507         dev_dbg(tphy->dev, "%s(%d)\n", __func__, index);
 508 }
 509
 510 static void u2_phy_instance_power_on(struct mtk_tphy *tphy,
 511         struct mtk_phy_instance *instance)
 512 {
 513         struct u2phy_banks *u2_banks = &instance->u2_banks;
 514         void __iomem *com = u2_banks->com;
 515         u32 index = instance->index;
 516         u32 tmp;
 517
 518         tmp = readl(com + U3P_U2PHYDTM0);
 519         tmp &= ~(P2C_RG_XCVRSEL | P2C_RG_DATAIN | P2C_DTM0_PART_MASK);
 520         writel(tmp, com + U3P_U2PHYDTM0);
 521
 522         /* OTG Enable */
 523         tmp = readl(com + U3P_USBPHYACR6);
 524         tmp |= PA6_RG_U2_OTG_VBUSCMP_EN;
 525         writel(tmp, com + U3P_USBPHYACR6);
 526
 527         tmp = readl(com + U3P_U2PHYDTM1);
 528         tmp |= P2C_RG_VBUSVALID | P2C_RG_AVALID;
 529         tmp &= ~P2C_RG_SESSEND;
 530         writel(tmp, com + U3P_U2PHYDTM1);
 531
 532         if (tphy->pdata->avoid_rx_sen_degradation && index) {
 533                 tmp = readl(com + U3D_U2PHYDCR0);
 534                 tmp |= P2C_RG_SIF_U2PLL_FORCE_ON;
 535                 writel(tmp, com + U3D_U2PHYDCR0);
 536
 537                 tmp = readl(com + U3P_U2PHYDTM0);
 538                 tmp |= P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM;
 539                 writel(tmp, com + U3P_U2PHYDTM0);
 540         }
 541         dev_dbg(tphy->dev, "%s(%d)\n", __func__, index);
 542 }
 543
 544 static void u2_phy_instance_power_off(struct mtk_tphy *tphy,
 545         struct mtk_phy_instance *instance)
 546 {
 547         struct u2phy_banks *u2_banks = &instance->u2_banks;
 548         void __iomem *com = u2_banks->com;
 549         u32 index = instance->index;
 550         u32 tmp;
 551
 552         tmp = readl(com + U3P_U2PHYDTM0);
 553         tmp &= ~(P2C_RG_XCVRSEL | P2C_RG_DATAIN);
 554         writel(tmp, com + U3P_U2PHYDTM0);
 555
 556         /* OTG Disable */
 557         tmp = readl(com + U3P_USBPHYACR6);
 558         tmp &= ~PA6_RG_U2_OTG_VBUSCMP_EN;
 559         writel(tmp, com + U3P_USBPHYACR6);
 560
 561         tmp = readl(com + U3P_U2PHYDTM1);
 562         tmp &= ~(P2C_RG_VBUSVALID | P2C_RG_AVALID);
 563         tmp |= P2C_RG_SESSEND;
 564         writel(tmp, com + U3P_U2PHYDTM1);
 565
 566         if (tphy->pdata->avoid_rx_sen_degradation && index) {
 567                 tmp = readl(com + U3P_U2PHYDTM0);
 568                 tmp &= ~(P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM);
 569                 writel(tmp, com + U3P_U2PHYDTM0);
 570
 571                 tmp = readl(com + U3D_U2PHYDCR0);
 572                 tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON;
 573                 writel(tmp, com + U3D_U2PHYDCR0);
 574         }
 575
 576         dev_dbg(tphy->dev, "%s(%d)\n", __func__, index);
 577 }
 578
 579 static void u2_phy_instance_exit(struct mtk_tphy *tphy,
 580         struct mtk_phy_instance *instance)
 581 {
 582         struct u2phy_banks *u2_banks = &instance->u2_banks;
 583         void __iomem *com = u2_banks->com;
 584         u32 index = instance->index;
 585         u32 tmp;
 586
 587         if (tphy->pdata->avoid_rx_sen_degradation && index) {
 588                 tmp = readl(com + U3D_U2PHYDCR0);
 589                 tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON;
 590                 writel(tmp, com + U3D_U2PHYDCR0);
 591
 592                 tmp = readl(com + U3P_U2PHYDTM0);
 593                 tmp &= ~P2C_FORCE_SUSPENDM;
 594                 writel(tmp, com + U3P_U2PHYDTM0);
 595         }
 596 }
 597
 598 static void u2_phy_instance_set_mode(struct mtk_tphy *tphy,
 599                                      struct mtk_phy_instance *instance,
 600                                      enum phy_mode mode)
 601 {
 602         struct u2phy_banks *u2_banks = &instance->u2_banks;
 603         u32 tmp;
 604
 605         tmp = readl(u2_banks->com + U3P_U2PHYDTM1);
 606         switch (mode) {
 607         case PHY_MODE_USB_DEVICE:
 608                 tmp |= P2C_FORCE_IDDIG | P2C_RG_IDDIG;
 609                 break;
 610         case PHY_MODE_USB_HOST:
 611                 tmp |= P2C_FORCE_IDDIG;
 612                 tmp &= ~P2C_RG_IDDIG;
 613                 break;
 614         case PHY_MODE_USB_OTG:
 615                 tmp &= ~(P2C_FORCE_IDDIG | P2C_RG_IDDIG);
 616                 break;
 617         default:
 618                 return;
 619         }
 620         writel(tmp, u2_banks->com + U3P_U2PHYDTM1);
 621 }
 622
 623 static void pcie_phy_instance_init(struct mtk_tphy *tphy,
 624         struct mtk_phy_instance *instance)
 625 {
 626         struct u3phy_banks *u3_banks = &instance->u3_banks;
 627         u32 tmp;
 628
 629         if (tphy->pdata->version != MTK_PHY_V1)
 630                 return;
 631
 632         tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG0);
 633         tmp &= ~(P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H);
 634         tmp |= P3A_RG_XTAL_EXT_PE1H_VAL(0x2) | P3A_RG_XTAL_EXT_PE2H_VAL(0x2);
 635         writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG0);
 636
 637         /* ref clk drive */
 638         tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG1);
 639         tmp &= ~P3A_RG_CLKDRV_AMP;
 640         tmp |= P3A_RG_CLKDRV_AMP_VAL(0x4);
 641         writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG1);
 642
 643         tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG0);
 644         tmp &= ~P3A_RG_CLKDRV_OFF;
 645         tmp |= P3A_RG_CLKDRV_OFF_VAL(0x1);
 646         writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0);
 647
 648         /* SSC delta -5000ppm */
 649         tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG20);
 650         tmp &= ~P3A_RG_PLL_DELTA1_PE2H;
 651         tmp |= P3A_RG_PLL_DELTA1_PE2H_VAL(0x3c);
 652         writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG20);
 653
 654         tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG25);
 655         tmp &= ~P3A_RG_PLL_DELTA_PE2H;
 656         tmp |= P3A_RG_PLL_DELTA_PE2H_VAL(0x36);
 657         writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG25);
 658
 659         /* change pll BW 0.6M */
 660         tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG5);
 661         tmp &= ~(P3A_RG_PLL_BR_PE2H | P3A_RG_PLL_IC_PE2H);
 662         tmp |= P3A_RG_PLL_BR_PE2H_VAL(0x1) | P3A_RG_PLL_IC_PE2H_VAL(0x1);
 663         writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG5);
 664
 665         tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG4);
 666         tmp &= ~(P3A_RG_PLL_DIVEN_PE2H | P3A_RG_PLL_BC_PE2H);
 667         tmp |= P3A_RG_PLL_BC_PE2H_VAL(0x3);
 668         writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG4);
 669
 670         tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG6);
 671         tmp &= ~P3A_RG_PLL_IR_PE2H;
 672         tmp |= P3A_RG_PLL_IR_PE2H_VAL(0x2);
 673         writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG6);
 674
 675         tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG7);
 676         tmp &= ~P3A_RG_PLL_BP_PE2H;
 677         tmp |= P3A_RG_PLL_BP_PE2H_VAL(0xa);
 678         writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG7);
 679
 680         /* Tx Detect Rx Timing: 10us -> 5us */
 681         tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET1);
 682         tmp &= ~P3D_RG_RXDET_STB2_SET;
 683         tmp |= P3D_RG_RXDET_STB2_SET_VAL(0x10);
 684         writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET1);
 685
 686         tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET2);
 687         tmp &= ~P3D_RG_RXDET_STB2_SET_P3;
 688         tmp |= P3D_RG_RXDET_STB2_SET_P3_VAL(0x10);
 689         writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET2);
 690
 691         /* wait for PCIe subsys register to active */
 692         usleep_range(2500, 3000);
 693         dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
 694 }
 695
 696 static void pcie_phy_instance_power_on(struct mtk_tphy *tphy,
 697         struct mtk_phy_instance *instance)
 698 {
 699         struct u3phy_banks *bank = &instance->u3_banks;
 700         u32 tmp;
 701
 702         tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLD);
 703         tmp &= ~(P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST);
 704         writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLD);
 705
 706         tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLE);
 707         tmp &= ~(P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD);
 708         writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLE);
 709 }
 710
 711 static void pcie_phy_instance_power_off(struct mtk_tphy *tphy,
 712         struct mtk_phy_instance *instance)
 713
 714 {
 715         struct u3phy_banks *bank = &instance->u3_banks;
 716         u32 tmp;
 717
 718         tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLD);
 719         tmp |= P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST;
 720         writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLD);
 721
 722         tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLE);
 723         tmp |= P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD;
 724         writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLE);
 725 }
 726
 727 static void sata_phy_instance_init(struct mtk_tphy *tphy,
 728         struct mtk_phy_instance *instance)
 729 {
 730         struct u3phy_banks *u3_banks = &instance->u3_banks;
 731         void __iomem *phyd = u3_banks->phyd;
 732         u32 tmp;
 733
 734         /* charge current adjustment */
 735         tmp = readl(phyd + ANA_RG_CTRL_SIGNAL6);
 736         tmp &= ~(RG_CDR_BIRLTR_GEN1_MSK | RG_CDR_BC_GEN1_MSK);
 737         tmp |= RG_CDR_BIRLTR_GEN1_VAL(0x6) | RG_CDR_BC_GEN1_VAL(0x1a);
 738         writel(tmp, phyd + ANA_RG_CTRL_SIGNAL6);
 739
 740         tmp = readl(phyd + ANA_EQ_EYE_CTRL_SIGNAL4);
 741         tmp &= ~RG_CDR_BIRLTD0_GEN1_MSK;
 742         tmp |= RG_CDR_BIRLTD0_GEN1_VAL(0x18);
 743         writel(tmp, phyd + ANA_EQ_EYE_CTRL_SIGNAL4);
 744
 745         tmp = readl(phyd + ANA_EQ_EYE_CTRL_SIGNAL5);
 746         tmp &= ~RG_CDR_BIRLTD0_GEN3_MSK;
 747         tmp |= RG_CDR_BIRLTD0_GEN3_VAL(0x06);
 748         writel(tmp, phyd + ANA_EQ_EYE_CTRL_SIGNAL5);
 749
 750         tmp = readl(phyd + ANA_RG_CTRL_SIGNAL4);
 751         tmp &= ~(RG_CDR_BICLTR_GEN1_MSK | RG_CDR_BR_GEN2_MSK);
 752         tmp |= RG_CDR_BICLTR_GEN1_VAL(0x0c) | RG_CDR_BR_GEN2_VAL(0x07);
 753         writel(tmp, phyd + ANA_RG_CTRL_SIGNAL4);
 754
 755         tmp = readl(phyd + PHYD_CTRL_SIGNAL_MODE4);
 756         tmp &= ~(RG_CDR_BICLTD0_GEN1_MSK | RG_CDR_BICLTD1_GEN1_MSK);
 757         tmp |= RG_CDR_BICLTD0_GEN1_VAL(0x08) | RG_CDR_BICLTD1_GEN1_VAL(0x02);
 758         writel(tmp, phyd + PHYD_CTRL_SIGNAL_MODE4);
 759
 760         tmp = readl(phyd + PHYD_DESIGN_OPTION2);
 761         tmp &= ~RG_LOCK_CNT_SEL_MSK;
 762         tmp |= RG_LOCK_CNT_SEL_VAL(0x02);
 763         writel(tmp, phyd + PHYD_DESIGN_OPTION2);
 764
 765         tmp = readl(phyd + PHYD_DESIGN_OPTION9);
 766         tmp &= ~(RG_T2_MIN_MSK | RG_TG_MIN_MSK |
 767                  RG_T2_MAX_MSK | RG_TG_MAX_MSK);
 768         tmp |= RG_T2_MIN_VAL(0x12) | RG_TG_MIN_VAL(0x04) |
 769                RG_T2_MAX_VAL(0x31) | RG_TG_MAX_VAL(0x0e);
 770         writel(tmp, phyd + PHYD_DESIGN_OPTION9);
 771
 772         tmp = readl(phyd + ANA_RG_CTRL_SIGNAL1);
 773         tmp &= ~RG_IDRV_0DB_GEN1_MSK;
 774         tmp |= RG_IDRV_0DB_GEN1_VAL(0x20);
 775         writel(tmp, phyd + ANA_RG_CTRL_SIGNAL1);
 776
 777         tmp = readl(phyd + ANA_EQ_EYE_CTRL_SIGNAL1);
 778         tmp &= ~RG_EQ_DLEQ_LFI_GEN1_MSK;
 779         tmp |= RG_EQ_DLEQ_LFI_GEN1_VAL(0x03);
 780         writel(tmp, phyd + ANA_EQ_EYE_CTRL_SIGNAL1);
 781
 782         dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
 783 }
 784
 785 static void phy_v1_banks_init(struct mtk_tphy *tphy,
 786                               struct mtk_phy_instance *instance)
 787 {
 788         struct u2phy_banks *u2_banks = &instance->u2_banks;
 789         struct u3phy_banks *u3_banks = &instance->u3_banks;
 790
 791         switch (instance->type) {
 792         case PHY_TYPE_USB2:
 793                 u2_banks->misc = NULL;
 794                 u2_banks->fmreg = tphy->sif_base + SSUSB_SIFSLV_V1_U2FREQ;
 795                 u2_banks->com = instance->port_base + SSUSB_SIFSLV_V1_U2PHY_COM;
 796                 break;
 797         case PHY_TYPE_USB3:
 798         case PHY_TYPE_PCIE:
 799                 u3_banks->spllc = tphy->sif_base + SSUSB_SIFSLV_V1_SPLLC;
 800                 u3_banks->chip = tphy->sif_base + SSUSB_SIFSLV_V1_CHIP;
 801                 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;
 802                 u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA;
 803                 break;
 804         case PHY_TYPE_SATA:
 805                 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;
 806                 break;
 807         default:
 808                 dev_err(tphy->dev, "incompatible PHY type\n");
 809                 return;
 810         }
 811 }
 812
 813 static void phy_v2_banks_init(struct mtk_tphy *tphy,
 814                               struct mtk_phy_instance *instance)
 815 {
 816         struct u2phy_banks *u2_banks = &instance->u2_banks;
 817         struct u3phy_banks *u3_banks = &instance->u3_banks;
 818
 819         switch (instance->type) {
 820         case PHY_TYPE_USB2:
 821                 u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC;
 822                 u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ;
 823                 u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM;
 824                 break;
 825         case PHY_TYPE_USB3:
 826         case PHY_TYPE_PCIE:
 827                 u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC;
 828                 u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP;
 829                 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD;
 830                 u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA;
 831                 break;
 832         default:
 833                 dev_err(tphy->dev, "incompatible PHY type\n");
 834                 return;
 835         }
 836 }
 837
 838 static void phy_parse_property(struct mtk_tphy *tphy,
 839                                 struct mtk_phy_instance *instance)
 840 {
 841         struct device *dev = &instance->phy->dev;
 842
 843         if (instance->type != PHY_TYPE_USB2)
 844                 return;
 845
 846         instance->bc12_en = device_property_read_bool(dev, "mediatek,bc12");
 847         device_property_read_u32(dev, "mediatek,eye-src",
 848                                  &instance->eye_src);
 849         device_property_read_u32(dev, "mediatek,eye-vrt",
 850                                  &instance->eye_vrt);
 851         device_property_read_u32(dev, "mediatek,eye-term",
 852                                  &instance->eye_term);
 853         dev_dbg(dev, "bc12:%d, src:%d, vrt:%d, term:%d\n",
 854                 instance->bc12_en, instance->eye_src,
 855                 instance->eye_vrt, instance->eye_term);
 856 }
 857
 858 static void u2_phy_props_set(struct mtk_tphy *tphy,
 859                              struct mtk_phy_instance *instance)
 860 {
 861         struct u2phy_banks *u2_banks = &instance->u2_banks;
 862         void __iomem *com = u2_banks->com;
 863         u32 tmp;
 864
 865         if (instance->bc12_en) {
 866                 tmp = readl(com + U3P_U2PHYBC12C);
 867                 tmp |= P2C_RG_CHGDT_EN; /* BC1.2 path Enable */
 868                 writel(tmp, com + U3P_U2PHYBC12C);
 869         }
 870
 871         if (instance->eye_src) {
 872                 tmp = readl(com + U3P_USBPHYACR5);
 873                 tmp &= ~PA5_RG_U2_HSTX_SRCTRL;
 874                 tmp |= PA5_RG_U2_HSTX_SRCTRL_VAL(instance->eye_src);
 875                 writel(tmp, com + U3P_USBPHYACR5);
 876         }
 877
 878         if (instance->eye_vrt) {
 879                 tmp = readl(com + U3P_USBPHYACR1);
 880                 tmp &= ~PA1_RG_VRT_SEL;
 881                 tmp |= PA1_RG_VRT_SEL_VAL(instance->eye_vrt);
 882                 writel(tmp, com + U3P_USBPHYACR1);
 883         }
 884
 885         if (instance->eye_term) {
 886                 tmp = readl(com + U3P_USBPHYACR1);
 887                 tmp &= ~PA1_RG_TERM_SEL;
 888                 tmp |= PA1_RG_TERM_SEL_VAL(instance->eye_term);
 889                 writel(tmp, com + U3P_USBPHYACR1);
 890         }
 891 }
 892
 893 static int mtk_phy_init(struct phy *phy)
 894 {
 895         struct mtk_phy_instance *instance = phy_get_drvdata(phy);
 896         struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);
 897         int ret;
 898
 899         ret = clk_prepare_enable(tphy->u3phya_ref);
 900         if (ret) {
 901                 dev_err(tphy->dev, "failed to enable u3phya_ref\n");
 902                 return ret;
 903         }
 904
 905         ret = clk_prepare_enable(instance->ref_clk);
 906         if (ret) {
 907                 dev_err(tphy->dev, "failed to enable ref_clk\n");
 908                 return ret;
 909         }
 910
 911         switch (instance->type) {
 912         case PHY_TYPE_USB2:
 913                 u2_phy_instance_init(tphy, instance);
 914                 u2_phy_props_set(tphy, instance);
 915                 break;
 916         case PHY_TYPE_USB3:
 917                 u3_phy_instance_init(tphy, instance);
 918                 break;
 919         case PHY_TYPE_PCIE:
 920                 pcie_phy_instance_init(tphy, instance);
 921                 break;
 922         case PHY_TYPE_SATA:
 923                 sata_phy_instance_init(tphy, instance);
 924                 break;
 925         default:
 926                 dev_err(tphy->dev, "incompatible PHY type\n");
 927                 return -EINVAL;
 928         }
 929
 930         return 0;
 931 }
 932
 933 static int mtk_phy_power_on(struct phy *phy)
 934 {
 935         struct mtk_phy_instance *instance = phy_get_drvdata(phy);
 936         struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);
 937
 938         if (instance->type == PHY_TYPE_USB2) {
 939                 u2_phy_instance_power_on(tphy, instance);
 940                 hs_slew_rate_calibrate(tphy, instance);
 941         } else if (instance->type == PHY_TYPE_PCIE) {
 942                 pcie_phy_instance_power_on(tphy, instance);
 943         }
 944
 945         return 0;
 946 }
 947
 948 static int mtk_phy_power_off(struct phy *phy)
 949 {
 950         struct mtk_phy_instance *instance = phy_get_drvdata(phy);
 951         struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);
 952
 953         if (instance->type == PHY_TYPE_USB2)
 954                 u2_phy_instance_power_off(tphy, instance);
 955         else if (instance->type == PHY_TYPE_PCIE)
 956                 pcie_phy_instance_power_off(tphy, instance);
 957
 958         return 0;
 959 }
 960
 961 static int mtk_phy_exit(struct phy *phy)
 962 {
 963         struct mtk_phy_instance *instance = phy_get_drvdata(phy);
 964         struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);
 965
 966         if (instance->type == PHY_TYPE_USB2)
 967                 u2_phy_instance_exit(tphy, instance);
 968
 969         clk_disable_unprepare(instance->ref_clk);
 970         clk_disable_unprepare(tphy->u3phya_ref);
 971         return 0;
 972 }
 973
 974 static int mtk_phy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
 975 {
 976         struct mtk_phy_instance *instance = phy_get_drvdata(phy);
 977         struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);
 978
 979         if (instance->type == PHY_TYPE_USB2)
 980                 u2_phy_instance_set_mode(tphy, instance, mode);
 981
 982         return 0;
 983 }
 984
 985 static struct phy *mtk_phy_xlate(struct device *dev,
 986                                         struct of_phandle_args *args)
 987 {
 988         struct mtk_tphy *tphy = dev_get_drvdata(dev);
 989         struct mtk_phy_instance *instance = NULL;
 990         struct device_node *phy_np = args->np;
 991         int index;
 992
 993         if (args->args_count != 1) {
 994                 dev_err(dev, "invalid number of cells in 'phy' property\n");
 995                 return ERR_PTR(-EINVAL);
 996         }
 997
 998         for (index = 0; index < tphy->nphys; index++)
 999                 if (phy_np == tphy->phys[index]->phy->dev.of_node) {
1000                         instance = tphy->phys[index];
1001                         break;
1002                 }
1003
1004         if (!instance) {
1005                 dev_err(dev, "failed to find appropriate phy\n");
1006                 return ERR_PTR(-EINVAL);
1007         }
1008
1009         instance->type = args->args[0];
1010         if (!(instance->type == PHY_TYPE_USB2 ||
1011               instance->type == PHY_TYPE_USB3 ||
1012               instance->type == PHY_TYPE_PCIE ||
1013               instance->type == PHY_TYPE_SATA)) {
1014                 dev_err(dev, "unsupported device type: %d\n", instance->type);
1015                 return ERR_PTR(-EINVAL);
1016         }
1017
1018         if (tphy->pdata->version == MTK_PHY_V1) {
1019                 phy_v1_banks_init(tphy, instance);
1020         } else if (tphy->pdata->version == MTK_PHY_V2) {
1021                 phy_v2_banks_init(tphy, instance);
1022         } else {
1023                 dev_err(dev, "phy version is not supported\n");
1024                 return ERR_PTR(-EINVAL);
1025         }
1026
1027         phy_parse_property(tphy, instance);
1028
1029         return instance->phy;
1030 }
1031
1032 static const struct phy_ops mtk_tphy_ops = {
1033         .init           = mtk_phy_init,
1034         .exit           = mtk_phy_exit,
1035         .power_on       = mtk_phy_power_on,
1036         .power_off      = mtk_phy_power_off,
1037         .set_mode       = mtk_phy_set_mode,
1038         .owner          = THIS_MODULE,
1039 };
1040
1041 static const struct mtk_phy_pdata tphy_v1_pdata = {
1042         .avoid_rx_sen_degradation = false,
1043         .version = MTK_PHY_V1,
1044 };
1045
1046 static const struct mtk_phy_pdata tphy_v2_pdata = {
1047         .avoid_rx_sen_degradation = false,
1048         .version = MTK_PHY_V2,
1049 };
1050
1051 static const struct mtk_phy_pdata mt8173_pdata = {
1052         .avoid_rx_sen_degradation = true,
1053         .version = MTK_PHY_V1,
1054 };
1055
1056 static const struct of_device_id mtk_tphy_id_table[] = {
1057         { .compatible = "mediatek,mt2701-u3phy", .data = &tphy_v1_pdata },
1058         { .compatible = "mediatek,mt2712-u3phy", .data = &tphy_v2_pdata },
1059         { .compatible = "mediatek,mt8173-u3phy", .data = &mt8173_pdata },
1060         { .compatible = "mediatek,generic-tphy-v1", .data = &tphy_v1_pdata },
1061         { .compatible = "mediatek,generic-tphy-v2", .data = &tphy_v2_pdata },
1062         { },
1063 };
1064 MODULE_DEVICE_TABLE(of, mtk_tphy_id_table);
1065
1066 static int mtk_tphy_probe(struct platform_device *pdev)
1067 {
1068         struct device *dev = &pdev->dev;
1069         struct device_node *np = dev->of_node;
1070         struct device_node *child_np;
1071         struct phy_provider *provider;
1072         struct resource *sif_res;
1073         struct mtk_tphy *tphy;
1074         struct resource res;
1075         int port, retval;
1076
1077         tphy = devm_kzalloc(dev, sizeof(*tphy), GFP_KERNEL);
1078         if (!tphy)
1079                 return -ENOMEM;
1080
1081         tphy->pdata = of_device_get_match_data(dev);
1082         if (!tphy->pdata)
1083                 return -EINVAL;
1084
1085         tphy->nphys = of_get_child_count(np);
1086         tphy->phys = devm_kcalloc(dev, tphy->nphys,
1087                                        sizeof(*tphy->phys), GFP_KERNEL);
1088         if (!tphy->phys)
1089                 return -ENOMEM;
1090
1091         tphy->dev = dev;
1092         platform_set_drvdata(pdev, tphy);
1093
1094         sif_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1095         /* SATA phy of V1 needn't it if not shared with PCIe or USB */
1096         if (sif_res && tphy->pdata->version == MTK_PHY_V1) {
1097                 /* get banks shared by multiple phys */
1098                 tphy->sif_base = devm_ioremap_resource(dev, sif_res);
1099                 if (IS_ERR(tphy->sif_base)) {
1100                         dev_err(dev, "failed to remap sif regs\n");
1101                         return PTR_ERR(tphy->sif_base);
1102                 }
1103         }
1104
1105         /* it's deprecated, make it optional for backward compatibility */
1106         tphy->u3phya_ref = devm_clk_get_optional(dev, "u3phya_ref");
1107         if (IS_ERR(tphy->u3phya_ref))
1108                 return PTR_ERR(tphy->u3phya_ref);
1109
1110         tphy->src_ref_clk = U3P_REF_CLK;
1111         tphy->src_coef = U3P_SLEW_RATE_COEF;
1112         /* update parameters of slew rate calibrate if exist */
1113         device_property_read_u32(dev, "mediatek,src-ref-clk-mhz",
1114                 &tphy->src_ref_clk);
1115         device_property_read_u32(dev, "mediatek,src-coef", &tphy->src_coef);
1116
1117         port = 0;
1118         for_each_child_of_node(np, child_np) {
1119                 struct mtk_phy_instance *instance;
1120                 struct phy *phy;
1121
1122                 instance = devm_kzalloc(dev, sizeof(*instance), GFP_KERNEL);
1123                 if (!instance) {
1124                         retval = -ENOMEM;
1125                         goto put_child;
1126                 }
1127
1128                 tphy->phys[port] = instance;
1129
1130                 phy = devm_phy_create(dev, child_np, &mtk_tphy_ops);
1131                 if (IS_ERR(phy)) {
1132                         dev_err(dev, "failed to create phy\n");
1133                         retval = PTR_ERR(phy);
1134                         goto put_child;
1135                 }
1136
1137                 retval = of_address_to_resource(child_np, 0, &res);
1138                 if (retval) {
1139                         dev_err(dev, "failed to get address resource(id-%d)\n",
1140                                 port);
1141                         goto put_child;
1142                 }
1143
1144                 instance->port_base = devm_ioremap_resource(&phy->dev, &res);
1145                 if (IS_ERR(instance->port_base)) {
1146                         dev_err(dev, "failed to remap phy regs\n");
1147                         retval = PTR_ERR(instance->port_base);
1148                         goto put_child;
1149                 }
1150
1151                 instance->phy = phy;
1152                 instance->index = port;
1153                 phy_set_drvdata(phy, instance);
1154                 port++;
1155
1156                 /* if deprecated clock is provided, ignore instance's one */
1157                 if (tphy->u3phya_ref)
1158                         continue;
1159
1160                 instance->ref_clk = devm_clk_get(&phy->dev, "ref");
1161                 if (IS_ERR(instance->ref_clk)) {
1162                         dev_err(dev, "failed to get ref_clk(id-%d)\n", port);
1163                         retval = PTR_ERR(instance->ref_clk);
1164                         goto put_child;
1165                 }
1166         }
1167
1168         provider = devm_of_phy_provider_register(dev, mtk_phy_xlate);
1169
1170         return PTR_ERR_OR_ZERO(provider);
1171 put_child:
1172         of_node_put(child_np);
1173         return retval;
1174 }
1175
1176 static struct platform_driver mtk_tphy_driver = {
1177         .probe          = mtk_tphy_probe,
1178         .driver         = {
1179                 .name   = "mtk-tphy",
1180                 .of_match_table = mtk_tphy_id_table,
1181         },
1182 };
1183
1184 module_platform_driver(mtk_tphy_driver);
1185
1186 MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
1187 MODULE_DESCRIPTION("MediaTek T-PHY driver");
1188 MODULE_LICENSE("GPL v2");