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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / spi / spi-atmel.c
blob013458cabe3c6f05e2b47fa4384d87295ab4206b
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Driver for Atmel AT32 and AT91 SPI Controllers
4 *
5 * Copyright (C) 2006 Atmel Corporation
6 */
7
8 #include <linux/kernel.h>
9 #include <linux/clk.h>
10 #include <linux/module.h>
11 #include <linux/platform_device.h>
12 #include <linux/delay.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/dmaengine.h>
15 #include <linux/err.h>
16 #include <linux/interrupt.h>
17 #include <linux/spi/spi.h>
18 #include <linux/slab.h>
19 #include <linux/platform_data/dma-atmel.h>
20 #include <linux/of.h>
21
22 #include <linux/io.h>
23 #include <linux/gpio/consumer.h>
24 #include <linux/pinctrl/consumer.h>
25 #include <linux/pm_runtime.h>
26 #include <trace/events/spi.h>
27
28 /* SPI register offsets */
29 #define SPI_CR 0x0000
30 #define SPI_MR 0x0004
31 #define SPI_RDR 0x0008
32 #define SPI_TDR 0x000c
33 #define SPI_SR 0x0010
34 #define SPI_IER 0x0014
35 #define SPI_IDR 0x0018
36 #define SPI_IMR 0x001c
37 #define SPI_CSR0 0x0030
38 #define SPI_CSR1 0x0034
39 #define SPI_CSR2 0x0038
40 #define SPI_CSR3 0x003c
41 #define SPI_FMR 0x0040
42 #define SPI_FLR 0x0044
43 #define SPI_VERSION 0x00fc
44 #define SPI_RPR 0x0100
45 #define SPI_RCR 0x0104
46 #define SPI_TPR 0x0108
47 #define SPI_TCR 0x010c
48 #define SPI_RNPR 0x0110
49 #define SPI_RNCR 0x0114
50 #define SPI_TNPR 0x0118
51 #define SPI_TNCR 0x011c
52 #define SPI_PTCR 0x0120
53 #define SPI_PTSR 0x0124
54
55 /* Bitfields in CR */
56 #define SPI_SPIEN_OFFSET 0
57 #define SPI_SPIEN_SIZE 1
58 #define SPI_SPIDIS_OFFSET 1
59 #define SPI_SPIDIS_SIZE 1
60 #define SPI_SWRST_OFFSET 7
61 #define SPI_SWRST_SIZE 1
62 #define SPI_LASTXFER_OFFSET 24
63 #define SPI_LASTXFER_SIZE 1
64 #define SPI_TXFCLR_OFFSET 16
65 #define SPI_TXFCLR_SIZE 1
66 #define SPI_RXFCLR_OFFSET 17
67 #define SPI_RXFCLR_SIZE 1
68 #define SPI_FIFOEN_OFFSET 30
69 #define SPI_FIFOEN_SIZE 1
70 #define SPI_FIFODIS_OFFSET 31
71 #define SPI_FIFODIS_SIZE 1
72
73 /* Bitfields in MR */
74 #define SPI_MSTR_OFFSET 0
75 #define SPI_MSTR_SIZE 1
76 #define SPI_PS_OFFSET 1
77 #define SPI_PS_SIZE 1
78 #define SPI_PCSDEC_OFFSET 2
79 #define SPI_PCSDEC_SIZE 1
80 #define SPI_FDIV_OFFSET 3
81 #define SPI_FDIV_SIZE 1
82 #define SPI_MODFDIS_OFFSET 4
83 #define SPI_MODFDIS_SIZE 1
84 #define SPI_WDRBT_OFFSET 5
85 #define SPI_WDRBT_SIZE 1
86 #define SPI_LLB_OFFSET 7
87 #define SPI_LLB_SIZE 1
88 #define SPI_PCS_OFFSET 16
89 #define SPI_PCS_SIZE 4
90 #define SPI_DLYBCS_OFFSET 24
91 #define SPI_DLYBCS_SIZE 8
92
93 /* Bitfields in RDR */
94 #define SPI_RD_OFFSET 0
95 #define SPI_RD_SIZE 16
96
97 /* Bitfields in TDR */
98 #define SPI_TD_OFFSET 0
99 #define SPI_TD_SIZE 16
100
101 /* Bitfields in SR */
102 #define SPI_RDRF_OFFSET 0
103 #define SPI_RDRF_SIZE 1
104 #define SPI_TDRE_OFFSET 1
105 #define SPI_TDRE_SIZE 1
106 #define SPI_MODF_OFFSET 2
107 #define SPI_MODF_SIZE 1
108 #define SPI_OVRES_OFFSET 3
109 #define SPI_OVRES_SIZE 1
110 #define SPI_ENDRX_OFFSET 4
111 #define SPI_ENDRX_SIZE 1
112 #define SPI_ENDTX_OFFSET 5
113 #define SPI_ENDTX_SIZE 1
114 #define SPI_RXBUFF_OFFSET 6
115 #define SPI_RXBUFF_SIZE 1
116 #define SPI_TXBUFE_OFFSET 7
117 #define SPI_TXBUFE_SIZE 1
118 #define SPI_NSSR_OFFSET 8
119 #define SPI_NSSR_SIZE 1
120 #define SPI_TXEMPTY_OFFSET 9
121 #define SPI_TXEMPTY_SIZE 1
122 #define SPI_SPIENS_OFFSET 16
123 #define SPI_SPIENS_SIZE 1
124 #define SPI_TXFEF_OFFSET 24
125 #define SPI_TXFEF_SIZE 1
126 #define SPI_TXFFF_OFFSET 25
127 #define SPI_TXFFF_SIZE 1
128 #define SPI_TXFTHF_OFFSET 26
129 #define SPI_TXFTHF_SIZE 1
130 #define SPI_RXFEF_OFFSET 27
131 #define SPI_RXFEF_SIZE 1
132 #define SPI_RXFFF_OFFSET 28
133 #define SPI_RXFFF_SIZE 1
134 #define SPI_RXFTHF_OFFSET 29
135 #define SPI_RXFTHF_SIZE 1
136 #define SPI_TXFPTEF_OFFSET 30
137 #define SPI_TXFPTEF_SIZE 1
138 #define SPI_RXFPTEF_OFFSET 31
139 #define SPI_RXFPTEF_SIZE 1
140
141 /* Bitfields in CSR0 */
142 #define SPI_CPOL_OFFSET 0
143 #define SPI_CPOL_SIZE 1
144 #define SPI_NCPHA_OFFSET 1
145 #define SPI_NCPHA_SIZE 1
146 #define SPI_CSAAT_OFFSET 3
147 #define SPI_CSAAT_SIZE 1
148 #define SPI_BITS_OFFSET 4
149 #define SPI_BITS_SIZE 4
150 #define SPI_SCBR_OFFSET 8
151 #define SPI_SCBR_SIZE 8
152 #define SPI_DLYBS_OFFSET 16
153 #define SPI_DLYBS_SIZE 8
154 #define SPI_DLYBCT_OFFSET 24
155 #define SPI_DLYBCT_SIZE 8
156
157 /* Bitfields in RCR */
158 #define SPI_RXCTR_OFFSET 0
159 #define SPI_RXCTR_SIZE 16
160
161 /* Bitfields in TCR */
162 #define SPI_TXCTR_OFFSET 0
163 #define SPI_TXCTR_SIZE 16
164
165 /* Bitfields in RNCR */
166 #define SPI_RXNCR_OFFSET 0
167 #define SPI_RXNCR_SIZE 16
168
169 /* Bitfields in TNCR */
170 #define SPI_TXNCR_OFFSET 0
171 #define SPI_TXNCR_SIZE 16
172
173 /* Bitfields in PTCR */
174 #define SPI_RXTEN_OFFSET 0
175 #define SPI_RXTEN_SIZE 1
176 #define SPI_RXTDIS_OFFSET 1
177 #define SPI_RXTDIS_SIZE 1
178 #define SPI_TXTEN_OFFSET 8
179 #define SPI_TXTEN_SIZE 1
180 #define SPI_TXTDIS_OFFSET 9
181 #define SPI_TXTDIS_SIZE 1
182
183 /* Bitfields in FMR */
184 #define SPI_TXRDYM_OFFSET 0
185 #define SPI_TXRDYM_SIZE 2
186 #define SPI_RXRDYM_OFFSET 4
187 #define SPI_RXRDYM_SIZE 2
188 #define SPI_TXFTHRES_OFFSET 16
189 #define SPI_TXFTHRES_SIZE 6
190 #define SPI_RXFTHRES_OFFSET 24
191 #define SPI_RXFTHRES_SIZE 6
192
193 /* Bitfields in FLR */
194 #define SPI_TXFL_OFFSET 0
195 #define SPI_TXFL_SIZE 6
196 #define SPI_RXFL_OFFSET 16
197 #define SPI_RXFL_SIZE 6
198
199 /* Constants for BITS */
200 #define SPI_BITS_8_BPT 0
201 #define SPI_BITS_9_BPT 1
202 #define SPI_BITS_10_BPT 2
203 #define SPI_BITS_11_BPT 3
204 #define SPI_BITS_12_BPT 4
205 #define SPI_BITS_13_BPT 5
206 #define SPI_BITS_14_BPT 6
207 #define SPI_BITS_15_BPT 7
208 #define SPI_BITS_16_BPT 8
209 #define SPI_ONE_DATA 0
210 #define SPI_TWO_DATA 1
211 #define SPI_FOUR_DATA 2
212
213 /* Bit manipulation macros */
214 #define SPI_BIT(name) \
215 (1 << SPI_##name##_OFFSET)
216 #define SPI_BF(name, value) \
217 (((value) & ((1 << SPI_##name##_SIZE) - 1)) << SPI_##name##_OFFSET)
218 #define SPI_BFEXT(name, value) \
219 (((value) >> SPI_##name##_OFFSET) & ((1 << SPI_##name##_SIZE) - 1))
220 #define SPI_BFINS(name, value, old) \
221 (((old) & ~(((1 << SPI_##name##_SIZE) - 1) << SPI_##name##_OFFSET)) \
222 | SPI_BF(name, value))
223
224 /* Register access macros */
225 #define spi_readl(port, reg) \
226 readl_relaxed((port)->regs + SPI_##reg)
227 #define spi_writel(port, reg, value) \
228 writel_relaxed((value), (port)->regs + SPI_##reg)
229 #define spi_writew(port, reg, value) \
230 writew_relaxed((value), (port)->regs + SPI_##reg)
231
232 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
233 * cache operations; better heuristics consider wordsize and bitrate.
234 */
235 #define DMA_MIN_BYTES 16
236
237 #define SPI_DMA_TIMEOUT (msecs_to_jiffies(1000))
238
239 #define AUTOSUSPEND_TIMEOUT 2000
240
241 struct atmel_spi_caps {
242 bool is_spi2;
243 bool has_wdrbt;
244 bool has_dma_support;
245 bool has_pdc_support;
246 };
247
248 /*
249 * The core SPI transfer engine just talks to a register bank to set up
250 * DMA transfers; transfer queue progress is driven by IRQs. The clock
251 * framework provides the base clock, subdivided for each spi_device.
252 */
253 struct atmel_spi {
254 spinlock_t lock;
255 unsigned long flags;
256
257 phys_addr_t phybase;
258 void __iomem *regs;
259 int irq;
260 struct clk *clk;
261 struct platform_device *pdev;
262 unsigned long spi_clk;
263
264 struct spi_transfer *current_transfer;
265 int current_remaining_bytes;
266 int done_status;
267 dma_addr_t dma_addr_rx_bbuf;
268 dma_addr_t dma_addr_tx_bbuf;
269 void *addr_rx_bbuf;
270 void *addr_tx_bbuf;
271
272 struct completion xfer_completion;
273
274 struct atmel_spi_caps caps;
275
276 bool use_dma;
277 bool use_pdc;
278
279 bool keep_cs;
280
281 u32 fifo_size;
282 u8 native_cs_free;
283 u8 native_cs_for_gpio;
284 };
285
286 /* Controller-specific per-slave state */
287 struct atmel_spi_device {
288 u32 csr;
289 };
290
291 #define SPI_MAX_DMA_XFER 65535 /* true for both PDC and DMA */
292 #define INVALID_DMA_ADDRESS 0xffffffff
293
294 /*
295 * Version 2 of the SPI controller has
296 * - CR.LASTXFER
297 * - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
298 * - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
299 * - SPI_CSRx.CSAAT
300 * - SPI_CSRx.SBCR allows faster clocking
301 */
302 static bool atmel_spi_is_v2(struct atmel_spi *as)
303 {
304 return as->caps.is_spi2;
305 }
306
307 /*
308 * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
309 * they assume that spi slave device state will not change on deselect, so
310 * that automagic deselection is OK. ("NPCSx rises if no data is to be
311 * transmitted") Not so! Workaround uses nCSx pins as GPIOs; or newer
312 * controllers have CSAAT and friends.
313 *
314 * Even controller newer than ar91rm9200, using GPIOs can make sens as
315 * it lets us support active-high chipselects despite the controller's
316 * belief that only active-low devices/systems exists.
317 *
318 * However, at91rm9200 has a second erratum whereby nCS0 doesn't work
319 * right when driven with GPIO. ("Mode Fault does not allow more than one
320 * Master on Chip Select 0.") No workaround exists for that ... so for
321 * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH,
322 * and (c) will trigger that first erratum in some cases.
323 */
324
325 static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
326 {
327 struct atmel_spi_device *asd = spi->controller_state;
328 int chip_select;
329 u32 mr;
330
331 if (spi->cs_gpiod)
332 chip_select = as->native_cs_for_gpio;
333 else
334 chip_select = spi->chip_select;
335
336 if (atmel_spi_is_v2(as)) {
337 spi_writel(as, CSR0 + 4 * chip_select, asd->csr);
338 /* For the low SPI version, there is a issue that PDC transfer
339 * on CS1,2,3 needs SPI_CSR0.BITS config as SPI_CSR1,2,3.BITS
340 */
341 spi_writel(as, CSR0, asd->csr);
342 if (as->caps.has_wdrbt) {
343 spi_writel(as, MR,
344 SPI_BF(PCS, ~(0x01 << chip_select))
345 | SPI_BIT(WDRBT)
346 | SPI_BIT(MODFDIS)
347 | SPI_BIT(MSTR));
348 } else {
349 spi_writel(as, MR,
350 SPI_BF(PCS, ~(0x01 << chip_select))
351 | SPI_BIT(MODFDIS)
352 | SPI_BIT(MSTR));
353 }
354
355 mr = spi_readl(as, MR);
356 if (spi->cs_gpiod)
357 gpiod_set_value(spi->cs_gpiod, 1);
358 } else {
359 u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
360 int i;
361 u32 csr;
362
363 /* Make sure clock polarity is correct */
364 for (i = 0; i < spi->master->num_chipselect; i++) {
365 csr = spi_readl(as, CSR0 + 4 * i);
366 if ((csr ^ cpol) & SPI_BIT(CPOL))
367 spi_writel(as, CSR0 + 4 * i,
368 csr ^ SPI_BIT(CPOL));
369 }
370
371 mr = spi_readl(as, MR);
372 mr = SPI_BFINS(PCS, ~(1 << chip_select), mr);
373 if (spi->cs_gpiod)
374 gpiod_set_value(spi->cs_gpiod, 1);
375 spi_writel(as, MR, mr);
376 }
377
378 dev_dbg(&spi->dev, "activate NPCS, mr %08x\n", mr);
379 }
380
381 static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
382 {
383 int chip_select;
384 u32 mr;
385
386 if (spi->cs_gpiod)
387 chip_select = as->native_cs_for_gpio;
388 else
389 chip_select = spi->chip_select;
390
391 /* only deactivate *this* device; sometimes transfers to
392 * another device may be active when this routine is called.
393 */
394 mr = spi_readl(as, MR);
395 if (~SPI_BFEXT(PCS, mr) & (1 << chip_select)) {
396 mr = SPI_BFINS(PCS, 0xf, mr);
397 spi_writel(as, MR, mr);
398 }
399
400 dev_dbg(&spi->dev, "DEactivate NPCS, mr %08x\n", mr);
401
402 if (!spi->cs_gpiod)
403 spi_writel(as, CR, SPI_BIT(LASTXFER));
404 else
405 gpiod_set_value(spi->cs_gpiod, 0);
406 }
407
408 static void atmel_spi_lock(struct atmel_spi *as) __acquires(&as->lock)
409 {
410 spin_lock_irqsave(&as->lock, as->flags);
411 }
412
413 static void atmel_spi_unlock(struct atmel_spi *as) __releases(&as->lock)
414 {
415 spin_unlock_irqrestore(&as->lock, as->flags);
416 }
417
418 static inline bool atmel_spi_is_vmalloc_xfer(struct spi_transfer *xfer)
419 {
420 return is_vmalloc_addr(xfer->tx_buf) || is_vmalloc_addr(xfer->rx_buf);
421 }
422
423 static inline bool atmel_spi_use_dma(struct atmel_spi *as,
424 struct spi_transfer *xfer)
425 {
426 return as->use_dma && xfer->len >= DMA_MIN_BYTES;
427 }
428
429 static bool atmel_spi_can_dma(struct spi_master *master,
430 struct spi_device *spi,
431 struct spi_transfer *xfer)
432 {
433 struct atmel_spi *as = spi_master_get_devdata(master);
434
435 if (IS_ENABLED(CONFIG_SOC_SAM_V4_V5))
436 return atmel_spi_use_dma(as, xfer) &&
437 !atmel_spi_is_vmalloc_xfer(xfer);
438 else
439 return atmel_spi_use_dma(as, xfer);
440
441 }
442
443 static int atmel_spi_dma_slave_config(struct atmel_spi *as,
444 struct dma_slave_config *slave_config,
445 u8 bits_per_word)
446 {
447 struct spi_master *master = platform_get_drvdata(as->pdev);
448 int err = 0;
449
450 if (bits_per_word > 8) {
451 slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
452 slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
453 } else {
454 slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
455 slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
456 }
457
458 slave_config->dst_addr = (dma_addr_t)as->phybase + SPI_TDR;
459 slave_config->src_addr = (dma_addr_t)as->phybase + SPI_RDR;
460 slave_config->src_maxburst = 1;
461 slave_config->dst_maxburst = 1;
462 slave_config->device_fc = false;
463
464 /*
465 * This driver uses fixed peripheral select mode (PS bit set to '0' in
466 * the Mode Register).
467 * So according to the datasheet, when FIFOs are available (and
468 * enabled), the Transmit FIFO operates in Multiple Data Mode.
469 * In this mode, up to 2 data, not 4, can be written into the Transmit
470 * Data Register in a single access.
471 * However, the first data has to be written into the lowest 16 bits and
472 * the second data into the highest 16 bits of the Transmit
473 * Data Register. For 8bit data (the most frequent case), it would
474 * require to rework tx_buf so each data would actualy fit 16 bits.
475 * So we'd rather write only one data at the time. Hence the transmit
476 * path works the same whether FIFOs are available (and enabled) or not.
477 */
478 slave_config->direction = DMA_MEM_TO_DEV;
479 if (dmaengine_slave_config(master->dma_tx, slave_config)) {
480 dev_err(&as->pdev->dev,
481 "failed to configure tx dma channel\n");
482 err = -EINVAL;
483 }
484
485 /*
486 * This driver configures the spi controller for master mode (MSTR bit
487 * set to '1' in the Mode Register).
488 * So according to the datasheet, when FIFOs are available (and
489 * enabled), the Receive FIFO operates in Single Data Mode.
490 * So the receive path works the same whether FIFOs are available (and
491 * enabled) or not.
492 */
493 slave_config->direction = DMA_DEV_TO_MEM;
494 if (dmaengine_slave_config(master->dma_rx, slave_config)) {
495 dev_err(&as->pdev->dev,
496 "failed to configure rx dma channel\n");
497 err = -EINVAL;
498 }
499
500 return err;
501 }
502
503 static int atmel_spi_configure_dma(struct spi_master *master,
504 struct atmel_spi *as)
505 {
506 struct dma_slave_config slave_config;
507 struct device *dev = &as->pdev->dev;
508 int err;
509
510 dma_cap_mask_t mask;
511 dma_cap_zero(mask);
512 dma_cap_set(DMA_SLAVE, mask);
513
514 master->dma_tx = dma_request_chan(dev, "tx");
515 if (IS_ERR(master->dma_tx)) {
516 err = PTR_ERR(master->dma_tx);
517 if (err != -EPROBE_DEFER)
518 dev_err(dev, "No TX DMA channel, DMA is disabled\n");
519 goto error_clear;
520 }
521
522 master->dma_rx = dma_request_chan(dev, "rx");
523 if (IS_ERR(master->dma_rx)) {
524 err = PTR_ERR(master->dma_rx);
525 /*
526 * No reason to check EPROBE_DEFER here since we have already
527 * requested tx channel.
528 */
529 dev_err(dev, "No RX DMA channel, DMA is disabled\n");
530 goto error;
531 }
532
533 err = atmel_spi_dma_slave_config(as, &slave_config, 8);
534 if (err)
535 goto error;
536
537 dev_info(&as->pdev->dev,
538 "Using %s (tx) and %s (rx) for DMA transfers\n",
539 dma_chan_name(master->dma_tx),
540 dma_chan_name(master->dma_rx));
541
542 return 0;
543 error:
544 if (!IS_ERR(master->dma_rx))
545 dma_release_channel(master->dma_rx);
546 if (!IS_ERR(master->dma_tx))
547 dma_release_channel(master->dma_tx);
548 error_clear:
549 master->dma_tx = master->dma_rx = NULL;
550 return err;
551 }
552
553 static void atmel_spi_stop_dma(struct spi_master *master)
554 {
555 if (master->dma_rx)
556 dmaengine_terminate_all(master->dma_rx);
557 if (master->dma_tx)
558 dmaengine_terminate_all(master->dma_tx);
559 }
560
561 static void atmel_spi_release_dma(struct spi_master *master)
562 {
563 if (master->dma_rx) {
564 dma_release_channel(master->dma_rx);
565 master->dma_rx = NULL;
566 }
567 if (master->dma_tx) {
568 dma_release_channel(master->dma_tx);
569 master->dma_tx = NULL;
570 }
571 }
572
573 /* This function is called by the DMA driver from tasklet context */
574 static void dma_callback(void *data)
575 {
576 struct spi_master *master = data;
577 struct atmel_spi *as = spi_master_get_devdata(master);
578
579 if (is_vmalloc_addr(as->current_transfer->rx_buf) &&
580 IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
581 memcpy(as->current_transfer->rx_buf, as->addr_rx_bbuf,
582 as->current_transfer->len);
583 }
584 complete(&as->xfer_completion);
585 }
586
587 /*
588 * Next transfer using PIO without FIFO.
589 */
590 static void atmel_spi_next_xfer_single(struct spi_master *master,
591 struct spi_transfer *xfer)
592 {
593 struct atmel_spi *as = spi_master_get_devdata(master);
594 unsigned long xfer_pos = xfer->len - as->current_remaining_bytes;
595
596 dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_pio\n");
597
598 /* Make sure data is not remaining in RDR */
599 spi_readl(as, RDR);
600 while (spi_readl(as, SR) & SPI_BIT(RDRF)) {
601 spi_readl(as, RDR);
602 cpu_relax();
603 }
604
605 if (xfer->bits_per_word > 8)
606 spi_writel(as, TDR, *(u16 *)(xfer->tx_buf + xfer_pos));
607 else
608 spi_writel(as, TDR, *(u8 *)(xfer->tx_buf + xfer_pos));
609
610 dev_dbg(master->dev.parent,
611 " start pio xfer %p: len %u tx %p rx %p bitpw %d\n",
612 xfer, xfer->len, xfer->tx_buf, xfer->rx_buf,
613 xfer->bits_per_word);
614
615 /* Enable relevant interrupts */
616 spi_writel(as, IER, SPI_BIT(RDRF) | SPI_BIT(OVRES));
617 }
618
619 /*
620 * Next transfer using PIO with FIFO.
621 */
622 static void atmel_spi_next_xfer_fifo(struct spi_master *master,
623 struct spi_transfer *xfer)
624 {
625 struct atmel_spi *as = spi_master_get_devdata(master);
626 u32 current_remaining_data, num_data;
627 u32 offset = xfer->len - as->current_remaining_bytes;
628 const u16 *words = (const u16 *)((u8 *)xfer->tx_buf + offset);
629 const u8 *bytes = (const u8 *)((u8 *)xfer->tx_buf + offset);
630 u16 td0, td1;
631 u32 fifomr;
632
633 dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_fifo\n");
634
635 /* Compute the number of data to transfer in the current iteration */
636 current_remaining_data = ((xfer->bits_per_word > 8) ?
637 ((u32)as->current_remaining_bytes >> 1) :
638 (u32)as->current_remaining_bytes);
639 num_data = min(current_remaining_data, as->fifo_size);
640
641 /* Flush RX and TX FIFOs */
642 spi_writel(as, CR, SPI_BIT(RXFCLR) | SPI_BIT(TXFCLR));
643 while (spi_readl(as, FLR))
644 cpu_relax();
645
646 /* Set RX FIFO Threshold to the number of data to transfer */
647 fifomr = spi_readl(as, FMR);
648 spi_writel(as, FMR, SPI_BFINS(RXFTHRES, num_data, fifomr));
649
650 /* Clear FIFO flags in the Status Register, especially RXFTHF */
651 (void)spi_readl(as, SR);
652
653 /* Fill TX FIFO */
654 while (num_data >= 2) {
655 if (xfer->bits_per_word > 8) {
656 td0 = *words++;
657 td1 = *words++;
658 } else {
659 td0 = *bytes++;
660 td1 = *bytes++;
661 }
662
663 spi_writel(as, TDR, (td1 << 16) | td0);
664 num_data -= 2;
665 }
666
667 if (num_data) {
668 if (xfer->bits_per_word > 8)
669 td0 = *words++;
670 else
671 td0 = *bytes++;
672
673 spi_writew(as, TDR, td0);
674 num_data--;
675 }
676
677 dev_dbg(master->dev.parent,
678 " start fifo xfer %p: len %u tx %p rx %p bitpw %d\n",
679 xfer, xfer->len, xfer->tx_buf, xfer->rx_buf,
680 xfer->bits_per_word);
681
682 /*
683 * Enable RX FIFO Threshold Flag interrupt to be notified about
684 * transfer completion.
685 */
686 spi_writel(as, IER, SPI_BIT(RXFTHF) | SPI_BIT(OVRES));
687 }
688
689 /*
690 * Next transfer using PIO.
691 */
692 static void atmel_spi_next_xfer_pio(struct spi_master *master,
693 struct spi_transfer *xfer)
694 {
695 struct atmel_spi *as = spi_master_get_devdata(master);
696
697 if (as->fifo_size)
698 atmel_spi_next_xfer_fifo(master, xfer);
699 else
700 atmel_spi_next_xfer_single(master, xfer);
701 }
702
703 /*
704 * Submit next transfer for DMA.
705 */
706 static int atmel_spi_next_xfer_dma_submit(struct spi_master *master,
707 struct spi_transfer *xfer,
708 u32 *plen)
709 {
710 struct atmel_spi *as = spi_master_get_devdata(master);
711 struct dma_chan *rxchan = master->dma_rx;
712 struct dma_chan *txchan = master->dma_tx;
713 struct dma_async_tx_descriptor *rxdesc;
714 struct dma_async_tx_descriptor *txdesc;
715 struct dma_slave_config slave_config;
716 dma_cookie_t cookie;
717
718 dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_dma_submit\n");
719
720 /* Check that the channels are available */
721 if (!rxchan || !txchan)
722 return -ENODEV;
723
724 /* release lock for DMA operations */
725 atmel_spi_unlock(as);
726
727 *plen = xfer->len;
728
729 if (atmel_spi_dma_slave_config(as, &slave_config,
730 xfer->bits_per_word))
731 goto err_exit;
732
733 /* Send both scatterlists */
734 if (atmel_spi_is_vmalloc_xfer(xfer) &&
735 IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
736 rxdesc = dmaengine_prep_slave_single(rxchan,
737 as->dma_addr_rx_bbuf,
738 xfer->len,
739 DMA_DEV_TO_MEM,
740 DMA_PREP_INTERRUPT |
741 DMA_CTRL_ACK);
742 } else {
743 rxdesc = dmaengine_prep_slave_sg(rxchan,
744 xfer->rx_sg.sgl,
745 xfer->rx_sg.nents,
746 DMA_DEV_TO_MEM,
747 DMA_PREP_INTERRUPT |
748 DMA_CTRL_ACK);
749 }
750 if (!rxdesc)
751 goto err_dma;
752
753 if (atmel_spi_is_vmalloc_xfer(xfer) &&
754 IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
755 memcpy(as->addr_tx_bbuf, xfer->tx_buf, xfer->len);
756 txdesc = dmaengine_prep_slave_single(txchan,
757 as->dma_addr_tx_bbuf,
758 xfer->len, DMA_MEM_TO_DEV,
759 DMA_PREP_INTERRUPT |
760 DMA_CTRL_ACK);
761 } else {
762 txdesc = dmaengine_prep_slave_sg(txchan,
763 xfer->tx_sg.sgl,
764 xfer->tx_sg.nents,
765 DMA_MEM_TO_DEV,
766 DMA_PREP_INTERRUPT |
767 DMA_CTRL_ACK);
768 }
769 if (!txdesc)
770 goto err_dma;
771
772 dev_dbg(master->dev.parent,
773 " start dma xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
774 xfer, xfer->len, xfer->tx_buf, (unsigned long long)xfer->tx_dma,
775 xfer->rx_buf, (unsigned long long)xfer->rx_dma);
776
777 /* Enable relevant interrupts */
778 spi_writel(as, IER, SPI_BIT(OVRES));
779
780 /* Put the callback on the RX transfer only, that should finish last */
781 rxdesc->callback = dma_callback;
782 rxdesc->callback_param = master;
783
784 /* Submit and fire RX and TX with TX last so we're ready to read! */
785 cookie = rxdesc->tx_submit(rxdesc);
786 if (dma_submit_error(cookie))
787 goto err_dma;
788 cookie = txdesc->tx_submit(txdesc);
789 if (dma_submit_error(cookie))
790 goto err_dma;
791 rxchan->device->device_issue_pending(rxchan);
792 txchan->device->device_issue_pending(txchan);
793
794 /* take back lock */
795 atmel_spi_lock(as);
796 return 0;
797
798 err_dma:
799 spi_writel(as, IDR, SPI_BIT(OVRES));
800 atmel_spi_stop_dma(master);
801 err_exit:
802 atmel_spi_lock(as);
803 return -ENOMEM;
804 }
805
806 static void atmel_spi_next_xfer_data(struct spi_master *master,
807 struct spi_transfer *xfer,
808 dma_addr_t *tx_dma,
809 dma_addr_t *rx_dma,
810 u32 *plen)
811 {
812 *rx_dma = xfer->rx_dma + xfer->len - *plen;
813 *tx_dma = xfer->tx_dma + xfer->len - *plen;
814 if (*plen > master->max_dma_len)
815 *plen = master->max_dma_len;
816 }
817
818 static int atmel_spi_set_xfer_speed(struct atmel_spi *as,
819 struct spi_device *spi,
820 struct spi_transfer *xfer)
821 {
822 u32 scbr, csr;
823 unsigned long bus_hz;
824 int chip_select;
825
826 if (spi->cs_gpiod)
827 chip_select = as->native_cs_for_gpio;
828 else
829 chip_select = spi->chip_select;
830
831 /* v1 chips start out at half the peripheral bus speed. */
832 bus_hz = as->spi_clk;
833 if (!atmel_spi_is_v2(as))
834 bus_hz /= 2;
835
836 /*
837 * Calculate the lowest divider that satisfies the
838 * constraint, assuming div32/fdiv/mbz == 0.
839 */
840 scbr = DIV_ROUND_UP(bus_hz, xfer->speed_hz);
841
842 /*
843 * If the resulting divider doesn't fit into the
844 * register bitfield, we can't satisfy the constraint.
845 */
846 if (scbr >= (1 << SPI_SCBR_SIZE)) {
847 dev_err(&spi->dev,
848 "setup: %d Hz too slow, scbr %u; min %ld Hz\n",
849 xfer->speed_hz, scbr, bus_hz/255);
850 return -EINVAL;
851 }
852 if (scbr == 0) {
853 dev_err(&spi->dev,
854 "setup: %d Hz too high, scbr %u; max %ld Hz\n",
855 xfer->speed_hz, scbr, bus_hz);
856 return -EINVAL;
857 }
858 csr = spi_readl(as, CSR0 + 4 * chip_select);
859 csr = SPI_BFINS(SCBR, scbr, csr);
860 spi_writel(as, CSR0 + 4 * chip_select, csr);
861
862 return 0;
863 }
864
865 /*
866 * Submit next transfer for PDC.
867 * lock is held, spi irq is blocked
868 */
869 static void atmel_spi_pdc_next_xfer(struct spi_master *master,
870 struct spi_message *msg,
871 struct spi_transfer *xfer)
872 {
873 struct atmel_spi *as = spi_master_get_devdata(master);
874 u32 len;
875 dma_addr_t tx_dma, rx_dma;
876
877 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
878
879 len = as->current_remaining_bytes;
880 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
881 as->current_remaining_bytes -= len;
882
883 spi_writel(as, RPR, rx_dma);
884 spi_writel(as, TPR, tx_dma);
885
886 if (msg->spi->bits_per_word > 8)
887 len >>= 1;
888 spi_writel(as, RCR, len);
889 spi_writel(as, TCR, len);
890
891 dev_dbg(&msg->spi->dev,
892 " start xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
893 xfer, xfer->len, xfer->tx_buf,
894 (unsigned long long)xfer->tx_dma, xfer->rx_buf,
895 (unsigned long long)xfer->rx_dma);
896
897 if (as->current_remaining_bytes) {
898 len = as->current_remaining_bytes;
899 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
900 as->current_remaining_bytes -= len;
901
902 spi_writel(as, RNPR, rx_dma);
903 spi_writel(as, TNPR, tx_dma);
904
905 if (msg->spi->bits_per_word > 8)
906 len >>= 1;
907 spi_writel(as, RNCR, len);
908 spi_writel(as, TNCR, len);
909
910 dev_dbg(&msg->spi->dev,
911 " next xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
912 xfer, xfer->len, xfer->tx_buf,
913 (unsigned long long)xfer->tx_dma, xfer->rx_buf,
914 (unsigned long long)xfer->rx_dma);
915 }
916
917 /* REVISIT: We're waiting for RXBUFF before we start the next
918 * transfer because we need to handle some difficult timing
919 * issues otherwise. If we wait for TXBUFE in one transfer and
920 * then starts waiting for RXBUFF in the next, it's difficult
921 * to tell the difference between the RXBUFF interrupt we're
922 * actually waiting for and the RXBUFF interrupt of the
923 * previous transfer.
924 *
925 * It should be doable, though. Just not now...
926 */
927 spi_writel(as, IER, SPI_BIT(RXBUFF) | SPI_BIT(OVRES));
928 spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
929 }
930
931 /*
932 * For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma:
933 * - The buffer is either valid for CPU access, else NULL
934 * - If the buffer is valid, so is its DMA address
935 *
936 * This driver manages the dma address unless message->is_dma_mapped.
937 */
938 static int
939 atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer)
940 {
941 struct device *dev = &as->pdev->dev;
942
943 xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS;
944 if (xfer->tx_buf) {
945 /* tx_buf is a const void* where we need a void * for the dma
946 * mapping */
947 void *nonconst_tx = (void *)xfer->tx_buf;
948
949 xfer->tx_dma = dma_map_single(dev,
950 nonconst_tx, xfer->len,
951 DMA_TO_DEVICE);
952 if (dma_mapping_error(dev, xfer->tx_dma))
953 return -ENOMEM;
954 }
955 if (xfer->rx_buf) {
956 xfer->rx_dma = dma_map_single(dev,
957 xfer->rx_buf, xfer->len,
958 DMA_FROM_DEVICE);
959 if (dma_mapping_error(dev, xfer->rx_dma)) {
960 if (xfer->tx_buf)
961 dma_unmap_single(dev,
962 xfer->tx_dma, xfer->len,
963 DMA_TO_DEVICE);
964 return -ENOMEM;
965 }
966 }
967 return 0;
968 }
969
970 static void atmel_spi_dma_unmap_xfer(struct spi_master *master,
971 struct spi_transfer *xfer)
972 {
973 if (xfer->tx_dma != INVALID_DMA_ADDRESS)
974 dma_unmap_single(master->dev.parent, xfer->tx_dma,
975 xfer->len, DMA_TO_DEVICE);
976 if (xfer->rx_dma != INVALID_DMA_ADDRESS)
977 dma_unmap_single(master->dev.parent, xfer->rx_dma,
978 xfer->len, DMA_FROM_DEVICE);
979 }
980
981 static void atmel_spi_disable_pdc_transfer(struct atmel_spi *as)
982 {
983 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
984 }
985
986 static void
987 atmel_spi_pump_single_data(struct atmel_spi *as, struct spi_transfer *xfer)
988 {
989 u8 *rxp;
990 u16 *rxp16;
991 unsigned long xfer_pos = xfer->len - as->current_remaining_bytes;
992
993 if (xfer->bits_per_word > 8) {
994 rxp16 = (u16 *)(((u8 *)xfer->rx_buf) + xfer_pos);
995 *rxp16 = spi_readl(as, RDR);
996 } else {
997 rxp = ((u8 *)xfer->rx_buf) + xfer_pos;
998 *rxp = spi_readl(as, RDR);
999 }
1000 if (xfer->bits_per_word > 8) {
1001 if (as->current_remaining_bytes > 2)
1002 as->current_remaining_bytes -= 2;
1003 else
1004 as->current_remaining_bytes = 0;
1005 } else {
1006 as->current_remaining_bytes--;
1007 }
1008 }
1009
1010 static void
1011 atmel_spi_pump_fifo_data(struct atmel_spi *as, struct spi_transfer *xfer)
1012 {
1013 u32 fifolr = spi_readl(as, FLR);
1014 u32 num_bytes, num_data = SPI_BFEXT(RXFL, fifolr);
1015 u32 offset = xfer->len - as->current_remaining_bytes;
1016 u16 *words = (u16 *)((u8 *)xfer->rx_buf + offset);
1017 u8 *bytes = (u8 *)((u8 *)xfer->rx_buf + offset);
1018 u16 rd; /* RD field is the lowest 16 bits of RDR */
1019
1020 /* Update the number of remaining bytes to transfer */
1021 num_bytes = ((xfer->bits_per_word > 8) ?
1022 (num_data << 1) :
1023 num_data);
1024
1025 if (as->current_remaining_bytes > num_bytes)
1026 as->current_remaining_bytes -= num_bytes;
1027 else
1028 as->current_remaining_bytes = 0;
1029
1030 /* Handle odd number of bytes when data are more than 8bit width */
1031 if (xfer->bits_per_word > 8)
1032 as->current_remaining_bytes &= ~0x1;
1033
1034 /* Read data */
1035 while (num_data) {
1036 rd = spi_readl(as, RDR);
1037 if (xfer->bits_per_word > 8)
1038 *words++ = rd;
1039 else
1040 *bytes++ = rd;
1041 num_data--;
1042 }
1043 }
1044
1045 /* Called from IRQ
1046 *
1047 * Must update "current_remaining_bytes" to keep track of data
1048 * to transfer.
1049 */
1050 static void
1051 atmel_spi_pump_pio_data(struct atmel_spi *as, struct spi_transfer *xfer)
1052 {
1053 if (as->fifo_size)
1054 atmel_spi_pump_fifo_data(as, xfer);
1055 else
1056 atmel_spi_pump_single_data(as, xfer);
1057 }
1058
1059 /* Interrupt
1060 *
1061 * No need for locking in this Interrupt handler: done_status is the
1062 * only information modified.
1063 */
1064 static irqreturn_t
1065 atmel_spi_pio_interrupt(int irq, void *dev_id)
1066 {
1067 struct spi_master *master = dev_id;
1068 struct atmel_spi *as = spi_master_get_devdata(master);
1069 u32 status, pending, imr;
1070 struct spi_transfer *xfer;
1071 int ret = IRQ_NONE;
1072
1073 imr = spi_readl(as, IMR);
1074 status = spi_readl(as, SR);
1075 pending = status & imr;
1076
1077 if (pending & SPI_BIT(OVRES)) {
1078 ret = IRQ_HANDLED;
1079 spi_writel(as, IDR, SPI_BIT(OVRES));
1080 dev_warn(master->dev.parent, "overrun\n");
1081
1082 /*
1083 * When we get an overrun, we disregard the current
1084 * transfer. Data will not be copied back from any
1085 * bounce buffer and msg->actual_len will not be
1086 * updated with the last xfer.
1087 *
1088 * We will also not process any remaning transfers in
1089 * the message.
1090 */
1091 as->done_status = -EIO;
1092 smp_wmb();
1093
1094 /* Clear any overrun happening while cleaning up */
1095 spi_readl(as, SR);
1096
1097 complete(&as->xfer_completion);
1098
1099 } else if (pending & (SPI_BIT(RDRF) | SPI_BIT(RXFTHF))) {
1100 atmel_spi_lock(as);
1101
1102 if (as->current_remaining_bytes) {
1103 ret = IRQ_HANDLED;
1104 xfer = as->current_transfer;
1105 atmel_spi_pump_pio_data(as, xfer);
1106 if (!as->current_remaining_bytes)
1107 spi_writel(as, IDR, pending);
1108
1109 complete(&as->xfer_completion);
1110 }
1111
1112 atmel_spi_unlock(as);
1113 } else {
1114 WARN_ONCE(pending, "IRQ not handled, pending = %x\n", pending);
1115 ret = IRQ_HANDLED;
1116 spi_writel(as, IDR, pending);
1117 }
1118
1119 return ret;
1120 }
1121
1122 static irqreturn_t
1123 atmel_spi_pdc_interrupt(int irq, void *dev_id)
1124 {
1125 struct spi_master *master = dev_id;
1126 struct atmel_spi *as = spi_master_get_devdata(master);
1127 u32 status, pending, imr;
1128 int ret = IRQ_NONE;
1129
1130 imr = spi_readl(as, IMR);
1131 status = spi_readl(as, SR);
1132 pending = status & imr;
1133
1134 if (pending & SPI_BIT(OVRES)) {
1135
1136 ret = IRQ_HANDLED;
1137
1138 spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX)
1139 | SPI_BIT(OVRES)));
1140
1141 /* Clear any overrun happening while cleaning up */
1142 spi_readl(as, SR);
1143
1144 as->done_status = -EIO;
1145
1146 complete(&as->xfer_completion);
1147
1148 } else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) {
1149 ret = IRQ_HANDLED;
1150
1151 spi_writel(as, IDR, pending);
1152
1153 complete(&as->xfer_completion);
1154 }
1155
1156 return ret;
1157 }
1158
1159 static int atmel_word_delay_csr(struct spi_device *spi, struct atmel_spi *as)
1160 {
1161 struct spi_delay *delay = &spi->word_delay;
1162 u32 value = delay->value;
1163
1164 switch (delay->unit) {
1165 case SPI_DELAY_UNIT_NSECS:
1166 value /= 1000;
1167 break;
1168 case SPI_DELAY_UNIT_USECS:
1169 break;
1170 default:
1171 return -EINVAL;
1172 }
1173
1174 return (as->spi_clk / 1000000 * value) >> 5;
1175 }
1176
1177 static void initialize_native_cs_for_gpio(struct atmel_spi *as)
1178 {
1179 int i;
1180 struct spi_master *master = platform_get_drvdata(as->pdev);
1181
1182 if (!as->native_cs_free)
1183 return; /* already initialized */
1184
1185 if (!master->cs_gpiods)
1186 return; /* No CS GPIO */
1187
1188 /*
1189 * On the first version of the controller (AT91RM9200), CS0
1190 * can't be used associated with GPIO
1191 */
1192 if (atmel_spi_is_v2(as))
1193 i = 0;
1194 else
1195 i = 1;
1196
1197 for (; i < 4; i++)
1198 if (master->cs_gpiods[i])
1199 as->native_cs_free |= BIT(i);
1200
1201 if (as->native_cs_free)
1202 as->native_cs_for_gpio = ffs(as->native_cs_free);
1203 }
1204
1205 static int atmel_spi_setup(struct spi_device *spi)
1206 {
1207 struct atmel_spi *as;
1208 struct atmel_spi_device *asd;
1209 u32 csr;
1210 unsigned int bits = spi->bits_per_word;
1211 int chip_select;
1212 int word_delay_csr;
1213
1214 as = spi_master_get_devdata(spi->master);
1215
1216 /* see notes above re chipselect */
1217 if (!spi->cs_gpiod && (spi->mode & SPI_CS_HIGH)) {
1218 dev_warn(&spi->dev, "setup: non GPIO CS can't be active-high\n");
1219 return -EINVAL;
1220 }
1221
1222 /* Setup() is called during spi_register_controller(aka
1223 * spi_register_master) but after all membmers of the cs_gpiod
1224 * array have been filled, so we can looked for which native
1225 * CS will be free for using with GPIO
1226 */
1227 initialize_native_cs_for_gpio(as);
1228
1229 if (spi->cs_gpiod && as->native_cs_free) {
1230 dev_err(&spi->dev,
1231 "No native CS available to support this GPIO CS\n");
1232 return -EBUSY;
1233 }
1234
1235 if (spi->cs_gpiod)
1236 chip_select = as->native_cs_for_gpio;
1237 else
1238 chip_select = spi->chip_select;
1239
1240 csr = SPI_BF(BITS, bits - 8);
1241 if (spi->mode & SPI_CPOL)
1242 csr |= SPI_BIT(CPOL);
1243 if (!(spi->mode & SPI_CPHA))
1244 csr |= SPI_BIT(NCPHA);
1245
1246 if (!spi->cs_gpiod)
1247 csr |= SPI_BIT(CSAAT);
1248 csr |= SPI_BF(DLYBS, 0);
1249
1250 word_delay_csr = atmel_word_delay_csr(spi, as);
1251 if (word_delay_csr < 0)
1252 return word_delay_csr;
1253
1254 /* DLYBCT adds delays between words. This is useful for slow devices
1255 * that need a bit of time to setup the next transfer.
1256 */
1257 csr |= SPI_BF(DLYBCT, word_delay_csr);
1258
1259 asd = spi->controller_state;
1260 if (!asd) {
1261 asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL);
1262 if (!asd)
1263 return -ENOMEM;
1264
1265 spi->controller_state = asd;
1266 }
1267
1268 asd->csr = csr;
1269
1270 dev_dbg(&spi->dev,
1271 "setup: bpw %u mode 0x%x -> csr%d %08x\n",
1272 bits, spi->mode, spi->chip_select, csr);
1273
1274 if (!atmel_spi_is_v2(as))
1275 spi_writel(as, CSR0 + 4 * chip_select, csr);
1276
1277 return 0;
1278 }
1279
1280 static int atmel_spi_one_transfer(struct spi_master *master,
1281 struct spi_message *msg,
1282 struct spi_transfer *xfer)
1283 {
1284 struct atmel_spi *as;
1285 struct spi_device *spi = msg->spi;
1286 u8 bits;
1287 u32 len;
1288 struct atmel_spi_device *asd;
1289 int timeout;
1290 int ret;
1291 unsigned long dma_timeout;
1292
1293 as = spi_master_get_devdata(master);
1294
1295 if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) {
1296 dev_dbg(&spi->dev, "missing rx or tx buf\n");
1297 return -EINVAL;
1298 }
1299
1300 asd = spi->controller_state;
1301 bits = (asd->csr >> 4) & 0xf;
1302 if (bits != xfer->bits_per_word - 8) {
1303 dev_dbg(&spi->dev,
1304 "you can't yet change bits_per_word in transfers\n");
1305 return -ENOPROTOOPT;
1306 }
1307
1308 /*
1309 * DMA map early, for performance (empties dcache ASAP) and
1310 * better fault reporting.
1311 */
1312 if ((!msg->is_dma_mapped)
1313 && as->use_pdc) {
1314 if (atmel_spi_dma_map_xfer(as, xfer) < 0)
1315 return -ENOMEM;
1316 }
1317
1318 atmel_spi_set_xfer_speed(as, msg->spi, xfer);
1319
1320 as->done_status = 0;
1321 as->current_transfer = xfer;
1322 as->current_remaining_bytes = xfer->len;
1323 while (as->current_remaining_bytes) {
1324 reinit_completion(&as->xfer_completion);
1325
1326 if (as->use_pdc) {
1327 atmel_spi_pdc_next_xfer(master, msg, xfer);
1328 } else if (atmel_spi_use_dma(as, xfer)) {
1329 len = as->current_remaining_bytes;
1330 ret = atmel_spi_next_xfer_dma_submit(master,
1331 xfer, &len);
1332 if (ret) {
1333 dev_err(&spi->dev,
1334 "unable to use DMA, fallback to PIO\n");
1335 atmel_spi_next_xfer_pio(master, xfer);
1336 } else {
1337 as->current_remaining_bytes -= len;
1338 if (as->current_remaining_bytes < 0)
1339 as->current_remaining_bytes = 0;
1340 }
1341 } else {
1342 atmel_spi_next_xfer_pio(master, xfer);
1343 }
1344
1345 /* interrupts are disabled, so free the lock for schedule */
1346 atmel_spi_unlock(as);
1347 dma_timeout = wait_for_completion_timeout(&as->xfer_completion,
1348 SPI_DMA_TIMEOUT);
1349 atmel_spi_lock(as);
1350 if (WARN_ON(dma_timeout == 0)) {
1351 dev_err(&spi->dev, "spi transfer timeout\n");
1352 as->done_status = -EIO;
1353 }
1354
1355 if (as->done_status)
1356 break;
1357 }
1358
1359 if (as->done_status) {
1360 if (as->use_pdc) {
1361 dev_warn(master->dev.parent,
1362 "overrun (%u/%u remaining)\n",
1363 spi_readl(as, TCR), spi_readl(as, RCR));
1364
1365 /*
1366 * Clean up DMA registers and make sure the data
1367 * registers are empty.
1368 */
1369 spi_writel(as, RNCR, 0);
1370 spi_writel(as, TNCR, 0);
1371 spi_writel(as, RCR, 0);
1372 spi_writel(as, TCR, 0);
1373 for (timeout = 1000; timeout; timeout--)
1374 if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))
1375 break;
1376 if (!timeout)
1377 dev_warn(master->dev.parent,
1378 "timeout waiting for TXEMPTY");
1379 while (spi_readl(as, SR) & SPI_BIT(RDRF))
1380 spi_readl(as, RDR);
1381
1382 /* Clear any overrun happening while cleaning up */
1383 spi_readl(as, SR);
1384
1385 } else if (atmel_spi_use_dma(as, xfer)) {
1386 atmel_spi_stop_dma(master);
1387 }
1388
1389 if (!msg->is_dma_mapped
1390 && as->use_pdc)
1391 atmel_spi_dma_unmap_xfer(master, xfer);
1392
1393 return 0;
1394
1395 } else {
1396 /* only update length if no error */
1397 msg->actual_length += xfer->len;
1398 }
1399
1400 if (!msg->is_dma_mapped
1401 && as->use_pdc)
1402 atmel_spi_dma_unmap_xfer(master, xfer);
1403
1404 spi_transfer_delay_exec(xfer);
1405
1406 if (xfer->cs_change) {
1407 if (list_is_last(&xfer->transfer_list,
1408 &msg->transfers)) {
1409 as->keep_cs = true;
1410 } else {
1411 cs_deactivate(as, msg->spi);
1412 udelay(10);
1413 cs_activate(as, msg->spi);
1414 }
1415 }
1416
1417 return 0;
1418 }
1419
1420 static int atmel_spi_transfer_one_message(struct spi_master *master,
1421 struct spi_message *msg)
1422 {
1423 struct atmel_spi *as;
1424 struct spi_transfer *xfer;
1425 struct spi_device *spi = msg->spi;
1426 int ret = 0;
1427
1428 as = spi_master_get_devdata(master);
1429
1430 dev_dbg(&spi->dev, "new message %p submitted for %s\n",
1431 msg, dev_name(&spi->dev));
1432
1433 atmel_spi_lock(as);
1434 cs_activate(as, spi);
1435
1436 as->keep_cs = false;
1437
1438 msg->status = 0;
1439 msg->actual_length = 0;
1440
1441 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1442 trace_spi_transfer_start(msg, xfer);
1443
1444 ret = atmel_spi_one_transfer(master, msg, xfer);
1445 if (ret)
1446 goto msg_done;
1447
1448 trace_spi_transfer_stop(msg, xfer);
1449 }
1450
1451 if (as->use_pdc)
1452 atmel_spi_disable_pdc_transfer(as);
1453
1454 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1455 dev_dbg(&spi->dev,
1456 " xfer %p: len %u tx %p/%pad rx %p/%pad\n",
1457 xfer, xfer->len,
1458 xfer->tx_buf, &xfer->tx_dma,
1459 xfer->rx_buf, &xfer->rx_dma);
1460 }
1461
1462 msg_done:
1463 if (!as->keep_cs)
1464 cs_deactivate(as, msg->spi);
1465
1466 atmel_spi_unlock(as);
1467
1468 msg->status = as->done_status;
1469 spi_finalize_current_message(spi->master);
1470
1471 return ret;
1472 }
1473
1474 static void atmel_spi_cleanup(struct spi_device *spi)
1475 {
1476 struct atmel_spi_device *asd = spi->controller_state;
1477
1478 if (!asd)
1479 return;
1480
1481 spi->controller_state = NULL;
1482 kfree(asd);
1483 }
1484
1485 static inline unsigned int atmel_get_version(struct atmel_spi *as)
1486 {
1487 return spi_readl(as, VERSION) & 0x00000fff;
1488 }
1489
1490 static void atmel_get_caps(struct atmel_spi *as)
1491 {
1492 unsigned int version;
1493
1494 version = atmel_get_version(as);
1495
1496 as->caps.is_spi2 = version > 0x121;
1497 as->caps.has_wdrbt = version >= 0x210;
1498 as->caps.has_dma_support = version >= 0x212;
1499 as->caps.has_pdc_support = version < 0x212;
1500 }
1501
1502 static void atmel_spi_init(struct atmel_spi *as)
1503 {
1504 spi_writel(as, CR, SPI_BIT(SWRST));
1505 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1506
1507 /* It is recommended to enable FIFOs first thing after reset */
1508 if (as->fifo_size)
1509 spi_writel(as, CR, SPI_BIT(FIFOEN));
1510
1511 if (as->caps.has_wdrbt) {
1512 spi_writel(as, MR, SPI_BIT(WDRBT) | SPI_BIT(MODFDIS)
1513 | SPI_BIT(MSTR));
1514 } else {
1515 spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
1516 }
1517
1518 if (as->use_pdc)
1519 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
1520 spi_writel(as, CR, SPI_BIT(SPIEN));
1521 }
1522
1523 static int atmel_spi_probe(struct platform_device *pdev)
1524 {
1525 struct resource *regs;
1526 int irq;
1527 struct clk *clk;
1528 int ret;
1529 struct spi_master *master;
1530 struct atmel_spi *as;
1531
1532 /* Select default pin state */
1533 pinctrl_pm_select_default_state(&pdev->dev);
1534
1535 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1536 if (!regs)
1537 return -ENXIO;
1538
1539 irq = platform_get_irq(pdev, 0);
1540 if (irq < 0)
1541 return irq;
1542
1543 clk = devm_clk_get(&pdev->dev, "spi_clk");
1544 if (IS_ERR(clk))
1545 return PTR_ERR(clk);
1546
1547 /* setup spi core then atmel-specific driver state */
1548 ret = -ENOMEM;
1549 master = spi_alloc_master(&pdev->dev, sizeof(*as));
1550 if (!master)
1551 goto out_free;
1552
1553 /* the spi->mode bits understood by this driver: */
1554 master->use_gpio_descriptors = true;
1555 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1556 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 16);
1557 master->dev.of_node = pdev->dev.of_node;
1558 master->bus_num = pdev->id;
1559 master->num_chipselect = 4;
1560 master->setup = atmel_spi_setup;
1561 master->flags = (SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX);
1562 master->transfer_one_message = atmel_spi_transfer_one_message;
1563 master->cleanup = atmel_spi_cleanup;
1564 master->auto_runtime_pm = true;
1565 master->max_dma_len = SPI_MAX_DMA_XFER;
1566 master->can_dma = atmel_spi_can_dma;
1567 platform_set_drvdata(pdev, master);
1568
1569 as = spi_master_get_devdata(master);
1570
1571 spin_lock_init(&as->lock);
1572
1573 as->pdev = pdev;
1574 as->regs = devm_ioremap_resource(&pdev->dev, regs);
1575 if (IS_ERR(as->regs)) {
1576 ret = PTR_ERR(as->regs);
1577 goto out_unmap_regs;
1578 }
1579 as->phybase = regs->start;
1580 as->irq = irq;
1581 as->clk = clk;
1582
1583 init_completion(&as->xfer_completion);
1584
1585 atmel_get_caps(as);
1586
1587 as->use_dma = false;
1588 as->use_pdc = false;
1589 if (as->caps.has_dma_support) {
1590 ret = atmel_spi_configure_dma(master, as);
1591 if (ret == 0) {
1592 as->use_dma = true;
1593 } else if (ret == -EPROBE_DEFER) {
1594 return ret;
1595 }
1596 } else if (as->caps.has_pdc_support) {
1597 as->use_pdc = true;
1598 }
1599
1600 if (IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
1601 as->addr_rx_bbuf = dma_alloc_coherent(&pdev->dev,
1602 SPI_MAX_DMA_XFER,
1603 &as->dma_addr_rx_bbuf,
1604 GFP_KERNEL | GFP_DMA);
1605 if (!as->addr_rx_bbuf) {
1606 as->use_dma = false;
1607 } else {
1608 as->addr_tx_bbuf = dma_alloc_coherent(&pdev->dev,
1609 SPI_MAX_DMA_XFER,
1610 &as->dma_addr_tx_bbuf,
1611 GFP_KERNEL | GFP_DMA);
1612 if (!as->addr_tx_bbuf) {
1613 as->use_dma = false;
1614 dma_free_coherent(&pdev->dev, SPI_MAX_DMA_XFER,
1615 as->addr_rx_bbuf,
1616 as->dma_addr_rx_bbuf);
1617 }
1618 }
1619 if (!as->use_dma)
1620 dev_info(master->dev.parent,
1621 " can not allocate dma coherent memory\n");
1622 }
1623
1624 if (as->caps.has_dma_support && !as->use_dma)
1625 dev_info(&pdev->dev, "Atmel SPI Controller using PIO only\n");
1626
1627 if (as->use_pdc) {
1628 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pdc_interrupt,
1629 0, dev_name(&pdev->dev), master);
1630 } else {
1631 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pio_interrupt,
1632 0, dev_name(&pdev->dev), master);
1633 }
1634 if (ret)
1635 goto out_unmap_regs;
1636
1637 /* Initialize the hardware */
1638 ret = clk_prepare_enable(clk);
1639 if (ret)
1640 goto out_free_irq;
1641
1642 as->spi_clk = clk_get_rate(clk);
1643
1644 as->fifo_size = 0;
1645 if (!of_property_read_u32(pdev->dev.of_node, "atmel,fifo-size",
1646 &as->fifo_size)) {
1647 dev_info(&pdev->dev, "Using FIFO (%u data)\n", as->fifo_size);
1648 }
1649
1650 atmel_spi_init(as);
1651
1652 pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT);
1653 pm_runtime_use_autosuspend(&pdev->dev);
1654 pm_runtime_set_active(&pdev->dev);
1655 pm_runtime_enable(&pdev->dev);
1656
1657 ret = devm_spi_register_master(&pdev->dev, master);
1658 if (ret)
1659 goto out_free_dma;
1660
1661 /* go! */
1662 dev_info(&pdev->dev, "Atmel SPI Controller version 0x%x at 0x%08lx (irq %d)\n",
1663 atmel_get_version(as), (unsigned long)regs->start,
1664 irq);
1665
1666 return 0;
1667
1668 out_free_dma:
1669 pm_runtime_disable(&pdev->dev);
1670 pm_runtime_set_suspended(&pdev->dev);
1671
1672 if (as->use_dma)
1673 atmel_spi_release_dma(master);
1674
1675 spi_writel(as, CR, SPI_BIT(SWRST));
1676 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1677 clk_disable_unprepare(clk);
1678 out_free_irq:
1679 out_unmap_regs:
1680 out_free:
1681 spi_master_put(master);
1682 return ret;
1683 }
1684
1685 static int atmel_spi_remove(struct platform_device *pdev)
1686 {
1687 struct spi_master *master = platform_get_drvdata(pdev);
1688 struct atmel_spi *as = spi_master_get_devdata(master);
1689
1690 pm_runtime_get_sync(&pdev->dev);
1691
1692 /* reset the hardware and block queue progress */
1693 if (as->use_dma) {
1694 atmel_spi_stop_dma(master);
1695 atmel_spi_release_dma(master);
1696 if (IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
1697 dma_free_coherent(&pdev->dev, SPI_MAX_DMA_XFER,
1698 as->addr_tx_bbuf,
1699 as->dma_addr_tx_bbuf);
1700 dma_free_coherent(&pdev->dev, SPI_MAX_DMA_XFER,
1701 as->addr_rx_bbuf,
1702 as->dma_addr_rx_bbuf);
1703 }
1704 }
1705
1706 spin_lock_irq(&as->lock);
1707 spi_writel(as, CR, SPI_BIT(SWRST));
1708 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1709 spi_readl(as, SR);
1710 spin_unlock_irq(&as->lock);
1711
1712 clk_disable_unprepare(as->clk);
1713
1714 pm_runtime_put_noidle(&pdev->dev);
1715 pm_runtime_disable(&pdev->dev);
1716
1717 return 0;
1718 }
1719
1720 #ifdef CONFIG_PM
1721 static int atmel_spi_runtime_suspend(struct device *dev)
1722 {
1723 struct spi_master *master = dev_get_drvdata(dev);
1724 struct atmel_spi *as = spi_master_get_devdata(master);
1725
1726 clk_disable_unprepare(as->clk);
1727 pinctrl_pm_select_sleep_state(dev);
1728
1729 return 0;
1730 }
1731
1732 static int atmel_spi_runtime_resume(struct device *dev)
1733 {
1734 struct spi_master *master = dev_get_drvdata(dev);
1735 struct atmel_spi *as = spi_master_get_devdata(master);
1736
1737 pinctrl_pm_select_default_state(dev);
1738
1739 return clk_prepare_enable(as->clk);
1740 }
1741
1742 #ifdef CONFIG_PM_SLEEP
1743 static int atmel_spi_suspend(struct device *dev)
1744 {
1745 struct spi_master *master = dev_get_drvdata(dev);
1746 int ret;
1747
1748 /* Stop the queue running */
1749 ret = spi_master_suspend(master);
1750 if (ret)
1751 return ret;
1752
1753 if (!pm_runtime_suspended(dev))
1754 atmel_spi_runtime_suspend(dev);
1755
1756 return 0;
1757 }
1758
1759 static int atmel_spi_resume(struct device *dev)
1760 {
1761 struct spi_master *master = dev_get_drvdata(dev);
1762 struct atmel_spi *as = spi_master_get_devdata(master);
1763 int ret;
1764
1765 ret = clk_prepare_enable(as->clk);
1766 if (ret)
1767 return ret;
1768
1769 atmel_spi_init(as);
1770
1771 clk_disable_unprepare(as->clk);
1772
1773 if (!pm_runtime_suspended(dev)) {
1774 ret = atmel_spi_runtime_resume(dev);
1775 if (ret)
1776 return ret;
1777 }
1778
1779 /* Start the queue running */
1780 return spi_master_resume(master);
1781 }
1782 #endif
1783
1784 static const struct dev_pm_ops atmel_spi_pm_ops = {
1785 SET_SYSTEM_SLEEP_PM_OPS(atmel_spi_suspend, atmel_spi_resume)
1786 SET_RUNTIME_PM_OPS(atmel_spi_runtime_suspend,
1787 atmel_spi_runtime_resume, NULL)
1788 };
1789 #define ATMEL_SPI_PM_OPS (&atmel_spi_pm_ops)
1790 #else
1791 #define ATMEL_SPI_PM_OPS NULL
1792 #endif
1793
1794 static const struct of_device_id atmel_spi_dt_ids[] = {
1795 { .compatible = "atmel,at91rm9200-spi" },
1796 { /* sentinel */ }
1797 };
1798
1799 MODULE_DEVICE_TABLE(of, atmel_spi_dt_ids);
1800
1801 static struct platform_driver atmel_spi_driver = {
1802 .driver = {
1803 .name = "atmel_spi",
1804 .pm = ATMEL_SPI_PM_OPS,
1805 .of_match_table = atmel_spi_dt_ids,
1806 },
1807 .probe = atmel_spi_probe,
1808 .remove = atmel_spi_remove,
1809 };
1810 module_platform_driver(atmel_spi_driver);
1811
1812 MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver");
1813 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1814 MODULE_LICENSE("GPL");
1815 MODULE_ALIAS("platform:atmel_spi");
Linux with added FPC-III support