1 #ifndef _ASM_IA64_PCI_H
2 #define _ASM_IA64_PCI_H
5 #include <linux/slab.h>
6 #include <linux/spinlock.h>
7 #include <linux/string.h>
8 #include <linux/types.h>
11 #include <asm/scatterlist.h>
12 #include <asm/hw_irq.h>
14 struct pci_vector_struct
{
15 __u16 segment
; /* PCI Segment number */
16 __u16 bus
; /* PCI Bus number */
17 __u32 pci_id
; /* ACPI split 16 bits device, 16 bits function (see section 6.1.1) */
18 __u8 pin
; /* PCI PIN (0 = A, 1 = B, 2 = C, 3 = D) */
19 __u32 irq
; /* IRQ assigned */
23 * Can be used to override the logic in pci_scan_bus for skipping already-configured bus
24 * numbers - to be used for buggy BIOSes or architectures with incomplete PCI setup by the
27 #define pcibios_assign_all_busses() 0
29 #define PCIBIOS_MIN_IO 0x1000
30 #define PCIBIOS_MIN_MEM 0x10000000
32 void pcibios_config_init(void);
37 * PCI_DMA_BUS_IS_PHYS should be set to 1 if there is _necessarily_ a direct
38 * correspondence between device bus addresses and CPU physical addresses.
39 * Platforms with a hardware I/O MMU _must_ turn this off to suppress the
40 * bounce buffer handling code in the block and network device layers.
41 * Platforms with separate bus address spaces _must_ turn this off and provide
42 * a device DMA mapping implementation that takes care of the necessary
43 * address translation.
45 * For now, the ia64 platforms which may have separate/multiple bus address
46 * spaces all have I/O MMUs which support the merging of physically
47 * discontiguous buffers, so we can use that as the sole factor to determine
48 * the setting of PCI_DMA_BUS_IS_PHYS.
50 extern unsigned long ia64_max_iommu_merge_mask
;
51 #define PCI_DMA_BUS_IS_PHYS (ia64_max_iommu_merge_mask == ~0UL)
54 pcibios_penalize_isa_irq (int irq
, int active
)
56 /* We don't do dynamic PCI IRQ allocation */
59 #include <asm-generic/pci-dma-compat.h>
62 static inline void pci_dma_burst_advice(struct pci_dev
*pdev
,
63 enum pci_dma_burst_strategy
*strat
,
64 unsigned long *strategy_parameter
)
66 unsigned long cacheline_size
;
69 pci_read_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, &byte
);
71 cacheline_size
= 1024;
73 cacheline_size
= (int) byte
* 4;
75 *strat
= PCI_DMA_BURST_MULTIPLE
;
76 *strategy_parameter
= cacheline_size
;
81 extern int pci_mmap_page_range (struct pci_dev
*dev
, struct vm_area_struct
*vma
,
82 enum pci_mmap_state mmap_state
, int write_combine
);
83 #define HAVE_PCI_LEGACY
84 extern int pci_mmap_legacy_page_range(struct pci_bus
*bus
,
85 struct vm_area_struct
*vma
,
86 enum pci_mmap_state mmap_state
);
88 #define pci_get_legacy_mem platform_pci_get_legacy_mem
89 #define pci_legacy_read platform_pci_legacy_read
90 #define pci_legacy_write platform_pci_legacy_write
92 struct iospace_resource
{
93 struct list_head list
;
97 struct pci_controller
{
101 int node
; /* nearest node with memory or -1 for global allocation */
107 #define PCI_CONTROLLER(busdev) ((struct pci_controller *) busdev->sysdata)
108 #define pci_domain_nr(busdev) (PCI_CONTROLLER(busdev)->segment)
110 extern struct pci_ops pci_root_ops
;
112 static inline int pci_proc_domain(struct pci_bus
*bus
)
114 return (pci_domain_nr(bus
) != 0);
117 static inline struct resource
*
118 pcibios_select_root(struct pci_dev
*pdev
, struct resource
*res
)
120 struct resource
*root
= NULL
;
122 if (res
->flags
& IORESOURCE_IO
)
123 root
= &ioport_resource
;
124 if (res
->flags
& IORESOURCE_MEM
)
125 root
= &iomem_resource
;
130 #define HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ
131 static inline int pci_get_legacy_ide_irq(struct pci_dev
*dev
, int channel
)
133 return channel
? isa_irq_to_vector(15) : isa_irq_to_vector(14);
136 #ifdef CONFIG_INTEL_IOMMU
137 extern void pci_iommu_alloc(void);
139 #endif /* _ASM_IA64_PCI_H */