arch/powerpc/include/asm/ppc_asm.h

   1 /*
   2  * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
   3  */
   4 #ifndef _ASM_POWERPC_PPC_ASM_H
   5 #define _ASM_POWERPC_PPC_ASM_H
   6
   7 #include <linux/init.h>
   8 #include <linux/stringify.h>
   9 #include <asm/asm-compat.h>
  10 #include <asm/processor.h>
  11 #include <asm/ppc-opcode.h>
  12 #include <asm/firmware.h>
  13
  14 #ifndef __ASSEMBLY__
  15 #error __FILE__ should only be used in assembler files
  16 #else
  17
  18 #define SZL                     (BITS_PER_LONG/8)
  19
  20 /*
  21  * Stuff for accurate CPU time accounting.
  22  * These macros handle transitions between user and system state
  23  * in exception entry and exit and accumulate time to the
  24  * user_time and system_time fields in the paca.
  25  */
  26
  27 #ifndef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
  28 #define ACCOUNT_CPU_USER_ENTRY(ra, rb)
  29 #define ACCOUNT_CPU_USER_EXIT(ra, rb)
  30 #define ACCOUNT_STOLEN_TIME
  31 #else
  32 #define ACCOUNT_CPU_USER_ENTRY(ra, rb)                                  \
  33         MFTB(ra);                       /* get timebase */              \
  34         ld      rb,PACA_STARTTIME_USER(r13);                            \
  35         std     ra,PACA_STARTTIME(r13);                                 \
  36         subf    rb,rb,ra;               /* subtract start value */      \
  37         ld      ra,PACA_USER_TIME(r13);                                 \
  38         add     ra,ra,rb;               /* add on to user time */       \
  39         std     ra,PACA_USER_TIME(r13);                                 \
  40
  41 #define ACCOUNT_CPU_USER_EXIT(ra, rb)                                   \
  42         MFTB(ra);                       /* get timebase */              \
  43         ld      rb,PACA_STARTTIME(r13);                                 \
  44         std     ra,PACA_STARTTIME_USER(r13);                            \
  45         subf    rb,rb,ra;               /* subtract start value */      \
  46         ld      ra,PACA_SYSTEM_TIME(r13);                               \
  47         add     ra,ra,rb;               /* add on to system time */     \
  48         std     ra,PACA_SYSTEM_TIME(r13)
  49
  50 #ifdef CONFIG_PPC_SPLPAR
  51 #define ACCOUNT_STOLEN_TIME                                             \
  52 BEGIN_FW_FTR_SECTION;                                                   \
  53         beq     33f;                                                    \
  54         /* from user - see if there are any DTL entries to process */   \
  55         ld      r10,PACALPPACAPTR(r13); /* get ptr to VPA */            \
  56         ld      r11,PACA_DTL_RIDX(r13); /* get log read index */        \
  57         addi    r10,r10,LPPACA_DTLIDX;                                  \
  58         LDX_BE  r10,0,r10;              /* get log write index */       \
  59         cmpd    cr1,r11,r10;                                            \
  60         beq+    cr1,33f;                                                \
  61         bl      .accumulate_stolen_time;                                \
  62         ld      r12,_MSR(r1);                                           \
  63         andi.   r10,r12,MSR_PR;         /* Restore cr0 (coming from user) */ \
  64 33:                                                                     \
  65 END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
  66
  67 #else  /* CONFIG_PPC_SPLPAR */
  68 #define ACCOUNT_STOLEN_TIME
  69
  70 #endif /* CONFIG_PPC_SPLPAR */
  71
  72 #endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE */
  73
  74 /*
  75  * Macros for storing registers into and loading registers from
  76  * exception frames.
  77  */
  78 #ifdef __powerpc64__
  79 #define SAVE_GPR(n, base)       std     n,GPR0+8*(n)(base)
  80 #define REST_GPR(n, base)       ld      n,GPR0+8*(n)(base)
  81 #define SAVE_NVGPRS(base)       SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)
  82 #define REST_NVGPRS(base)       REST_8GPRS(14, base); REST_10GPRS(22, base)
  83 #else
  84 #define SAVE_GPR(n, base)       stw     n,GPR0+4*(n)(base)
  85 #define REST_GPR(n, base)       lwz     n,GPR0+4*(n)(base)
  86 #define SAVE_NVGPRS(base)       SAVE_GPR(13, base); SAVE_8GPRS(14, base); \
  87                                 SAVE_10GPRS(22, base)
  88 #define REST_NVGPRS(base)       REST_GPR(13, base); REST_8GPRS(14, base); \
  89                                 REST_10GPRS(22, base)
  90 #endif
  91
  92 #define SAVE_2GPRS(n, base)     SAVE_GPR(n, base); SAVE_GPR(n+1, base)
  93 #define SAVE_4GPRS(n, base)     SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
  94 #define SAVE_8GPRS(n, base)     SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
  95 #define SAVE_10GPRS(n, base)    SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
  96 #define REST_2GPRS(n, base)     REST_GPR(n, base); REST_GPR(n+1, base)
  97 #define REST_4GPRS(n, base)     REST_2GPRS(n, base); REST_2GPRS(n+2, base)
  98 #define REST_8GPRS(n, base)     REST_4GPRS(n, base); REST_4GPRS(n+4, base)
  99 #define REST_10GPRS(n, base)    REST_8GPRS(n, base); REST_2GPRS(n+8, base)
 100
 101 #define SAVE_FPR(n, base)       stfd    n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base)
 102 #define SAVE_2FPRS(n, base)     SAVE_FPR(n, base); SAVE_FPR(n+1, base)
 103 #define SAVE_4FPRS(n, base)     SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
 104 #define SAVE_8FPRS(n, base)     SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
 105 #define SAVE_16FPRS(n, base)    SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
 106 #define SAVE_32FPRS(n, base)    SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
 107 #define REST_FPR(n, base)       lfd     n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base)
 108 #define REST_2FPRS(n, base)     REST_FPR(n, base); REST_FPR(n+1, base)
 109 #define REST_4FPRS(n, base)     REST_2FPRS(n, base); REST_2FPRS(n+2, base)
 110 #define REST_8FPRS(n, base)     REST_4FPRS(n, base); REST_4FPRS(n+4, base)
 111 #define REST_16FPRS(n, base)    REST_8FPRS(n, base); REST_8FPRS(n+8, base)
 112 #define REST_32FPRS(n, base)    REST_16FPRS(n, base); REST_16FPRS(n+16, base)
 113
 114 #define SAVE_VR(n,b,base)       li b,THREAD_VR0+(16*(n));  stvx n,base,b
 115 #define SAVE_2VRS(n,b,base)     SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
 116 #define SAVE_4VRS(n,b,base)     SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
 117 #define SAVE_8VRS(n,b,base)     SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
 118 #define SAVE_16VRS(n,b,base)    SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
 119 #define SAVE_32VRS(n,b,base)    SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
 120 #define REST_VR(n,b,base)       li b,THREAD_VR0+(16*(n)); lvx n,base,b
 121 #define REST_2VRS(n,b,base)     REST_VR(n,b,base); REST_VR(n+1,b,base)
 122 #define REST_4VRS(n,b,base)     REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
 123 #define REST_8VRS(n,b,base)     REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
 124 #define REST_16VRS(n,b,base)    REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
 125 #define REST_32VRS(n,b,base)    REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
 126
 127 /* Save/restore FPRs, VRs and VSRs from their checkpointed backups in
 128  * thread_struct:
 129  */
 130 #define SAVE_FPR_TRANSACT(n, base)      stfd n,THREAD_TRANSACT_FPR0+    \
 131                                         8*TS_FPRWIDTH*(n)(base)
 132 #define SAVE_2FPRS_TRANSACT(n, base)    SAVE_FPR_TRANSACT(n, base);     \
 133                                         SAVE_FPR_TRANSACT(n+1, base)
 134 #define SAVE_4FPRS_TRANSACT(n, base)    SAVE_2FPRS_TRANSACT(n, base);   \
 135                                         SAVE_2FPRS_TRANSACT(n+2, base)
 136 #define SAVE_8FPRS_TRANSACT(n, base)    SAVE_4FPRS_TRANSACT(n, base);   \
 137                                         SAVE_4FPRS_TRANSACT(n+4, base)
 138 #define SAVE_16FPRS_TRANSACT(n, base)   SAVE_8FPRS_TRANSACT(n, base);   \
 139                                         SAVE_8FPRS_TRANSACT(n+8, base)
 140 #define SAVE_32FPRS_TRANSACT(n, base)   SAVE_16FPRS_TRANSACT(n, base);  \
 141                                         SAVE_16FPRS_TRANSACT(n+16, base)
 142
 143 #define REST_FPR_TRANSACT(n, base)      lfd     n,THREAD_TRANSACT_FPR0+ \
 144                                         8*TS_FPRWIDTH*(n)(base)
 145 #define REST_2FPRS_TRANSACT(n, base)    REST_FPR_TRANSACT(n, base);     \
 146                                         REST_FPR_TRANSACT(n+1, base)
 147 #define REST_4FPRS_TRANSACT(n, base)    REST_2FPRS_TRANSACT(n, base);   \
 148                                         REST_2FPRS_TRANSACT(n+2, base)
 149 #define REST_8FPRS_TRANSACT(n, base)    REST_4FPRS_TRANSACT(n, base);   \
 150                                         REST_4FPRS_TRANSACT(n+4, base)
 151 #define REST_16FPRS_TRANSACT(n, base)   REST_8FPRS_TRANSACT(n, base);   \
 152                                         REST_8FPRS_TRANSACT(n+8, base)
 153 #define REST_32FPRS_TRANSACT(n, base)   REST_16FPRS_TRANSACT(n, base);  \
 154                                         REST_16FPRS_TRANSACT(n+16, base)
 155
 156
 157 #define SAVE_VR_TRANSACT(n,b,base)      li b,THREAD_TRANSACT_VR0+(16*(n)); \
 158                                         stvx n,b,base
 159 #define SAVE_2VRS_TRANSACT(n,b,base)    SAVE_VR_TRANSACT(n,b,base);     \
 160                                         SAVE_VR_TRANSACT(n+1,b,base)
 161 #define SAVE_4VRS_TRANSACT(n,b,base)    SAVE_2VRS_TRANSACT(n,b,base);   \
 162                                         SAVE_2VRS_TRANSACT(n+2,b,base)
 163 #define SAVE_8VRS_TRANSACT(n,b,base)    SAVE_4VRS_TRANSACT(n,b,base);   \
 164                                         SAVE_4VRS_TRANSACT(n+4,b,base)
 165 #define SAVE_16VRS_TRANSACT(n,b,base)   SAVE_8VRS_TRANSACT(n,b,base);   \
 166                                         SAVE_8VRS_TRANSACT(n+8,b,base)
 167 #define SAVE_32VRS_TRANSACT(n,b,base)   SAVE_16VRS_TRANSACT(n,b,base);  \
 168                                         SAVE_16VRS_TRANSACT(n+16,b,base)
 169
 170 #define REST_VR_TRANSACT(n,b,base)      li b,THREAD_TRANSACT_VR0+(16*(n)); \
 171                                         lvx n,b,base
 172 #define REST_2VRS_TRANSACT(n,b,base)    REST_VR_TRANSACT(n,b,base);     \
 173                                         REST_VR_TRANSACT(n+1,b,base)
 174 #define REST_4VRS_TRANSACT(n,b,base)    REST_2VRS_TRANSACT(n,b,base);   \
 175                                         REST_2VRS_TRANSACT(n+2,b,base)
 176 #define REST_8VRS_TRANSACT(n,b,base)    REST_4VRS_TRANSACT(n,b,base);   \
 177                                         REST_4VRS_TRANSACT(n+4,b,base)
 178 #define REST_16VRS_TRANSACT(n,b,base)   REST_8VRS_TRANSACT(n,b,base);   \
 179                                         REST_8VRS_TRANSACT(n+8,b,base)
 180 #define REST_32VRS_TRANSACT(n,b,base)   REST_16VRS_TRANSACT(n,b,base);  \
 181                                         REST_16VRS_TRANSACT(n+16,b,base)
 182
 183
 184 #define SAVE_VSR_TRANSACT(n,b,base)     li b,THREAD_TRANSACT_VSR0+(16*(n)); \
 185                                         STXVD2X(n,R##base,R##b)
 186 #define SAVE_2VSRS_TRANSACT(n,b,base)   SAVE_VSR_TRANSACT(n,b,base);    \
 187                                         SAVE_VSR_TRANSACT(n+1,b,base)
 188 #define SAVE_4VSRS_TRANSACT(n,b,base)   SAVE_2VSRS_TRANSACT(n,b,base);  \
 189                                         SAVE_2VSRS_TRANSACT(n+2,b,base)
 190 #define SAVE_8VSRS_TRANSACT(n,b,base)   SAVE_4VSRS_TRANSACT(n,b,base);  \
 191                                         SAVE_4VSRS_TRANSACT(n+4,b,base)
 192 #define SAVE_16VSRS_TRANSACT(n,b,base)  SAVE_8VSRS_TRANSACT(n,b,base);  \
 193                                         SAVE_8VSRS_TRANSACT(n+8,b,base)
 194 #define SAVE_32VSRS_TRANSACT(n,b,base)  SAVE_16VSRS_TRANSACT(n,b,base); \
 195                                         SAVE_16VSRS_TRANSACT(n+16,b,base)
 196
 197 #define REST_VSR_TRANSACT(n,b,base)     li b,THREAD_TRANSACT_VSR0+(16*(n)); \
 198                                         LXVD2X(n,R##base,R##b)
 199 #define REST_2VSRS_TRANSACT(n,b,base)   REST_VSR_TRANSACT(n,b,base);    \
 200                                         REST_VSR_TRANSACT(n+1,b,base)
 201 #define REST_4VSRS_TRANSACT(n,b,base)   REST_2VSRS_TRANSACT(n,b,base);  \
 202                                         REST_2VSRS_TRANSACT(n+2,b,base)
 203 #define REST_8VSRS_TRANSACT(n,b,base)   REST_4VSRS_TRANSACT(n,b,base);  \
 204                                         REST_4VSRS_TRANSACT(n+4,b,base)
 205 #define REST_16VSRS_TRANSACT(n,b,base)  REST_8VSRS_TRANSACT(n,b,base);  \
 206                                         REST_8VSRS_TRANSACT(n+8,b,base)
 207 #define REST_32VSRS_TRANSACT(n,b,base)  REST_16VSRS_TRANSACT(n,b,base); \
 208                                         REST_16VSRS_TRANSACT(n+16,b,base)
 209
 210 /* Save the lower 32 VSRs in the thread VSR region */
 211 #define SAVE_VSR(n,b,base)      li b,THREAD_VSR0+(16*(n));  STXVD2X(n,R##base,R##b)
 212 #define SAVE_2VSRS(n,b,base)    SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base)
 213 #define SAVE_4VSRS(n,b,base)    SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base)
 214 #define SAVE_8VSRS(n,b,base)    SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base)
 215 #define SAVE_16VSRS(n,b,base)   SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base)
 216 #define SAVE_32VSRS(n,b,base)   SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base)
 217 #define REST_VSR(n,b,base)      li b,THREAD_VSR0+(16*(n)); LXVD2X(n,R##base,R##b)
 218 #define REST_2VSRS(n,b,base)    REST_VSR(n,b,base); REST_VSR(n+1,b,base)
 219 #define REST_4VSRS(n,b,base)    REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base)
 220 #define REST_8VSRS(n,b,base)    REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base)
 221 #define REST_16VSRS(n,b,base)   REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base)
 222 #define REST_32VSRS(n,b,base)   REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base)
 223
 224 /*
 225  * b = base register for addressing, o = base offset from register of 1st EVR
 226  * n = first EVR, s = scratch
 227  */
 228 #define SAVE_EVR(n,s,b,o)       evmergehi s,s,n; stw s,o+4*(n)(b)
 229 #define SAVE_2EVRS(n,s,b,o)     SAVE_EVR(n,s,b,o); SAVE_EVR(n+1,s,b,o)
 230 #define SAVE_4EVRS(n,s,b,o)     SAVE_2EVRS(n,s,b,o); SAVE_2EVRS(n+2,s,b,o)
 231 #define SAVE_8EVRS(n,s,b,o)     SAVE_4EVRS(n,s,b,o); SAVE_4EVRS(n+4,s,b,o)
 232 #define SAVE_16EVRS(n,s,b,o)    SAVE_8EVRS(n,s,b,o); SAVE_8EVRS(n+8,s,b,o)
 233 #define SAVE_32EVRS(n,s,b,o)    SAVE_16EVRS(n,s,b,o); SAVE_16EVRS(n+16,s,b,o)
 234 #define REST_EVR(n,s,b,o)       lwz s,o+4*(n)(b); evmergelo n,s,n
 235 #define REST_2EVRS(n,s,b,o)     REST_EVR(n,s,b,o); REST_EVR(n+1,s,b,o)
 236 #define REST_4EVRS(n,s,b,o)     REST_2EVRS(n,s,b,o); REST_2EVRS(n+2,s,b,o)
 237 #define REST_8EVRS(n,s,b,o)     REST_4EVRS(n,s,b,o); REST_4EVRS(n+4,s,b,o)
 238 #define REST_16EVRS(n,s,b,o)    REST_8EVRS(n,s,b,o); REST_8EVRS(n+8,s,b,o)
 239 #define REST_32EVRS(n,s,b,o)    REST_16EVRS(n,s,b,o); REST_16EVRS(n+16,s,b,o)
 240
 241 /* Macros to adjust thread priority for hardware multithreading */
 242 #define HMT_VERY_LOW    or      31,31,31        # very low priority
 243 #define HMT_LOW         or      1,1,1
 244 #define HMT_MEDIUM_LOW  or      6,6,6           # medium low priority
 245 #define HMT_MEDIUM      or      2,2,2
 246 #define HMT_MEDIUM_HIGH or      5,5,5           # medium high priority
 247 #define HMT_HIGH        or      3,3,3
 248 #define HMT_EXTRA_HIGH  or      7,7,7           # power7 only
 249
 250 #ifdef CONFIG_PPC64
 251 #define ULONG_SIZE      8
 252 #else
 253 #define ULONG_SIZE      4
 254 #endif
 255 #define __VCPU_GPR(n)   (VCPU_GPRS + (n * ULONG_SIZE))
 256 #define VCPU_GPR(n)     __VCPU_GPR(__REG_##n)
 257
 258 #ifdef __KERNEL__
 259 #ifdef CONFIG_PPC64
 260
 261 #define STACKFRAMESIZE 256
 262 #define __STK_REG(i)   (112 + ((i)-14)*8)
 263 #define STK_REG(i)     __STK_REG(__REG_##i)
 264
 265 #define __STK_PARAM(i)  (48 + ((i)-3)*8)
 266 #define STK_PARAM(i)    __STK_PARAM(__REG_##i)
 267
 268 #define XGLUE(a,b) a##b
 269 #define GLUE(a,b) XGLUE(a,b)
 270
 271 #define _GLOBAL(name) \
 272         .section ".text"; \
 273         .align 2 ; \
 274         .globl name; \
 275         .globl GLUE(.,name); \
 276         .section ".opd","aw"; \
 277 name: \
 278         .quad GLUE(.,name); \
 279         .quad .TOC.@tocbase; \
 280         .quad 0; \
 281         .previous; \
 282         .type GLUE(.,name),@function; \
 283 GLUE(.,name):
 284
 285 #define _INIT_GLOBAL(name) \
 286         __REF; \
 287         .align 2 ; \
 288         .globl name; \
 289         .globl GLUE(.,name); \
 290         .section ".opd","aw"; \
 291 name: \
 292         .quad GLUE(.,name); \
 293         .quad .TOC.@tocbase; \
 294         .quad 0; \
 295         .previous; \
 296         .type GLUE(.,name),@function; \
 297 GLUE(.,name):
 298
 299 #define _KPROBE(name) \
 300         .section ".kprobes.text","a"; \
 301         .align 2 ; \
 302         .globl name; \
 303         .globl GLUE(.,name); \
 304         .section ".opd","aw"; \
 305 name: \
 306         .quad GLUE(.,name); \
 307         .quad .TOC.@tocbase; \
 308         .quad 0; \
 309         .previous; \
 310         .type GLUE(.,name),@function; \
 311 GLUE(.,name):
 312
 313 #define _STATIC(name) \
 314         .section ".text"; \
 315         .align 2 ; \
 316         .section ".opd","aw"; \
 317 name: \
 318         .quad GLUE(.,name); \
 319         .quad .TOC.@tocbase; \
 320         .quad 0; \
 321         .previous; \
 322         .type GLUE(.,name),@function; \
 323 GLUE(.,name):
 324
 325 #define _INIT_STATIC(name) \
 326         __REF; \
 327         .align 2 ; \
 328         .section ".opd","aw"; \
 329 name: \
 330         .quad GLUE(.,name); \
 331         .quad .TOC.@tocbase; \
 332         .quad 0; \
 333         .previous; \
 334         .type GLUE(.,name),@function; \
 335 GLUE(.,name):
 336
 337 #else /* 32-bit */
 338
 339 #define _ENTRY(n)       \
 340         .globl n;       \
 341 n:
 342
 343 #define _GLOBAL(n)      \
 344         .text;          \
 345         .stabs __stringify(n:F-1),N_FUN,0,0,n;\
 346         .globl n;       \
 347 n:
 348
 349 #define _KPROBE(n)      \
 350         .section ".kprobes.text","a";   \
 351         .globl  n;      \
 352 n:
 353
 354 #endif
 355
 356 /*
 357  * LOAD_REG_IMMEDIATE(rn, expr)
 358  *   Loads the value of the constant expression 'expr' into register 'rn'
 359  *   using immediate instructions only.  Use this when it's important not
 360  *   to reference other data (i.e. on ppc64 when the TOC pointer is not
 361  *   valid) and when 'expr' is a constant or absolute address.
 362  *
 363  * LOAD_REG_ADDR(rn, name)
 364  *   Loads the address of label 'name' into register 'rn'.  Use this when
 365  *   you don't particularly need immediate instructions only, but you need
 366  *   the whole address in one register (e.g. it's a structure address and
 367  *   you want to access various offsets within it).  On ppc32 this is
 368  *   identical to LOAD_REG_IMMEDIATE.
 369  *
 370  * LOAD_REG_ADDRBASE(rn, name)
 371  * ADDROFF(name)
 372  *   LOAD_REG_ADDRBASE loads part of the address of label 'name' into
 373  *   register 'rn'.  ADDROFF(name) returns the remainder of the address as
 374  *   a constant expression.  ADDROFF(name) is a signed expression < 16 bits
 375  *   in size, so is suitable for use directly as an offset in load and store
 376  *   instructions.  Use this when loading/storing a single word or less as:
 377  *      LOAD_REG_ADDRBASE(rX, name)
 378  *      ld      rY,ADDROFF(name)(rX)
 379  */
 380 #ifdef __powerpc64__
 381 #ifdef HAVE_AS_ATHIGH
 382 #define __AS_ATHIGH high
 383 #else
 384 #define __AS_ATHIGH h
 385 #endif
 386 #define LOAD_REG_IMMEDIATE(reg,expr)            \
 387         lis     reg,(expr)@highest;             \
 388         ori     reg,reg,(expr)@higher;  \
 389         rldicr  reg,reg,32,31;          \
 390         oris    reg,reg,(expr)@__AS_ATHIGH;     \
 391         ori     reg,reg,(expr)@l;
 392
 393 #define LOAD_REG_ADDR(reg,name)                 \
 394         ld      reg,name@got(r2)
 395
 396 #define LOAD_REG_ADDRBASE(reg,name)     LOAD_REG_ADDR(reg,name)
 397 #define ADDROFF(name)                   0
 398
 399 /* offsets for stack frame layout */
 400 #define LRSAVE  16
 401
 402 #else /* 32-bit */
 403
 404 #define LOAD_REG_IMMEDIATE(reg,expr)            \
 405         lis     reg,(expr)@ha;          \
 406         addi    reg,reg,(expr)@l;
 407
 408 #define LOAD_REG_ADDR(reg,name)         LOAD_REG_IMMEDIATE(reg, name)
 409
 410 #define LOAD_REG_ADDRBASE(reg, name)    lis     reg,name@ha
 411 #define ADDROFF(name)                   name@l
 412
 413 /* offsets for stack frame layout */
 414 #define LRSAVE  4
 415
 416 #endif
 417
 418 /* various errata or part fixups */
 419 #ifdef CONFIG_PPC601_SYNC_FIX
 420 #define SYNC                            \
 421 BEGIN_FTR_SECTION                       \
 422         sync;                           \
 423         isync;                          \
 424 END_FTR_SECTION_IFSET(CPU_FTR_601)
 425 #define SYNC_601                        \
 426 BEGIN_FTR_SECTION                       \
 427         sync;                           \
 428 END_FTR_SECTION_IFSET(CPU_FTR_601)
 429 #define ISYNC_601                       \
 430 BEGIN_FTR_SECTION                       \
 431         isync;                          \
 432 END_FTR_SECTION_IFSET(CPU_FTR_601)
 433 #else
 434 #define SYNC
 435 #define SYNC_601
 436 #define ISYNC_601
 437 #endif
 438
 439 #if defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_FSL_BOOK3E)
 440 #define MFTB(dest)                      \
 441 90:     mfspr dest, SPRN_TBRL;          \
 442 BEGIN_FTR_SECTION_NESTED(96);           \
 443         cmpwi dest,0;                   \
 444         beq-  90b;                      \
 445 END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96)
 446 #elif defined(CONFIG_8xx)
 447 #define MFTB(dest)                      mftb dest
 448 #else
 449 #define MFTB(dest)                      mfspr dest, SPRN_TBRL
 450 #endif
 451
 452 #ifndef CONFIG_SMP
 453 #define TLBSYNC
 454 #else /* CONFIG_SMP */
 455 /* tlbsync is not implemented on 601 */
 456 #define TLBSYNC                         \
 457 BEGIN_FTR_SECTION                       \
 458         tlbsync;                        \
 459         sync;                           \
 460 END_FTR_SECTION_IFCLR(CPU_FTR_601)
 461 #endif
 462
 463 #ifdef CONFIG_PPC64
 464 #define MTOCRF(FXM, RS)                 \
 465         BEGIN_FTR_SECTION_NESTED(848);  \
 466         mtcrf   (FXM), RS;              \
 467         FTR_SECTION_ELSE_NESTED(848);   \
 468         mtocrf (FXM), RS;               \
 469         ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_NOEXECUTE, 848)
 470
 471 /*
 472  * PPR restore macros used in entry_64.S
 473  * Used for P7 or later processors
 474  */
 475 #define HMT_MEDIUM_LOW_HAS_PPR                                          \
 476 BEGIN_FTR_SECTION_NESTED(944)                                           \
 477         HMT_MEDIUM_LOW;                                                 \
 478 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,944)
 479
 480 #define SET_DEFAULT_THREAD_PPR(ra, rb)                                  \
 481 BEGIN_FTR_SECTION_NESTED(945)                                           \
 482         lis     ra,INIT_PPR@highest;    /* default ppr=3 */             \
 483         ld      rb,PACACURRENT(r13);                                    \
 484         sldi    ra,ra,32;       /* 11- 13 bits are used for ppr */      \
 485         std     ra,TASKTHREADPPR(rb);                                   \
 486 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,945)
 487
 488 #endif
 489
 490 /*
 491  * This instruction is not implemented on the PPC 603 or 601; however, on
 492  * the 403GCX and 405GP tlbia IS defined and tlbie is not.
 493  * All of these instructions exist in the 8xx, they have magical powers,
 494  * and they must be used.
 495  */
 496
 497 #if !defined(CONFIG_4xx) && !defined(CONFIG_8xx)
 498 #define tlbia                                   \
 499         li      r4,1024;                        \
 500         mtctr   r4;                             \
 501         lis     r4,KERNELBASE@h;                \
 502 0:      tlbie   r4;                             \
 503         addi    r4,r4,0x1000;                   \
 504         bdnz    0b
 505 #endif
 506
 507
 508 #ifdef CONFIG_IBM440EP_ERR42
 509 #define PPC440EP_ERR42 isync
 510 #else
 511 #define PPC440EP_ERR42
 512 #endif
 513
 514 /* The following stops all load and store data streams associated with stream
 515  * ID (ie. streams created explicitly).  The embedded and server mnemonics for
 516  * dcbt are different so we use machine "power4" here explicitly.
 517  */
 518 #define DCBT_STOP_ALL_STREAM_IDS(scratch)       \
 519 .machine push ;                                 \
 520 .machine "power4" ;                             \
 521        lis     scratch,0x60000000@h;            \
 522        dcbt    r0,scratch,0b01010;              \
 523 .machine pop
 524
 525 /*
 526  * toreal/fromreal/tophys/tovirt macros. 32-bit BookE makes them
 527  * keep the address intact to be compatible with code shared with
 528  * 32-bit classic.
 529  *
 530  * On the other hand, I find it useful to have them behave as expected
 531  * by their name (ie always do the addition) on 64-bit BookE
 532  */
 533 #if defined(CONFIG_BOOKE) && !defined(CONFIG_PPC64)
 534 #define toreal(rd)
 535 #define fromreal(rd)
 536
 537 /*
 538  * We use addis to ensure compatibility with the "classic" ppc versions of
 539  * these macros, which use rs = 0 to get the tophys offset in rd, rather than
 540  * converting the address in r0, and so this version has to do that too
 541  * (i.e. set register rd to 0 when rs == 0).
 542  */
 543 #define tophys(rd,rs)                           \
 544         addis   rd,rs,0
 545
 546 #define tovirt(rd,rs)                           \
 547         addis   rd,rs,0
 548
 549 #elif defined(CONFIG_PPC64)
 550 #define toreal(rd)              /* we can access c000... in real mode */
 551 #define fromreal(rd)
 552
 553 #define tophys(rd,rs)                           \
 554         clrldi  rd,rs,2
 555
 556 #define tovirt(rd,rs)                           \
 557         rotldi  rd,rs,16;                       \
 558         ori     rd,rd,((KERNELBASE>>48)&0xFFFF);\
 559         rotldi  rd,rd,48
 560 #else
 561 /*
 562  * On APUS (Amiga PowerPC cpu upgrade board), we don't know the
 563  * physical base address of RAM at compile time.
 564  */
 565 #define toreal(rd)      tophys(rd,rd)
 566 #define fromreal(rd)    tovirt(rd,rd)
 567
 568 #define tophys(rd,rs)                           \
 569 0:      addis   rd,rs,-PAGE_OFFSET@h;           \
 570         .section ".vtop_fixup","aw";            \
 571         .align  1;                              \
 572         .long   0b;                             \
 573         .previous
 574
 575 #define tovirt(rd,rs)                           \
 576 0:      addis   rd,rs,PAGE_OFFSET@h;            \
 577         .section ".ptov_fixup","aw";            \
 578         .align  1;                              \
 579         .long   0b;                             \
 580         .previous
 581 #endif
 582
 583 #ifdef CONFIG_PPC_BOOK3S_64
 584 #define RFI             rfid
 585 #define MTMSRD(r)       mtmsrd  r
 586 #define MTMSR_EERI(reg) mtmsrd  reg,1
 587 #else
 588 #define FIX_SRR1(ra, rb)
 589 #ifndef CONFIG_40x
 590 #define RFI             rfi
 591 #else
 592 #define RFI             rfi; b .        /* Prevent prefetch past rfi */
 593 #endif
 594 #define MTMSRD(r)       mtmsr   r
 595 #define MTMSR_EERI(reg) mtmsr   reg
 596 #define CLR_TOP32(r)
 597 #endif
 598
 599 #endif /* __KERNEL__ */
 600
 601 /* The boring bits... */
 602
 603 /* Condition Register Bit Fields */
 604
 605 #define cr0     0
 606 #define cr1     1
 607 #define cr2     2
 608 #define cr3     3
 609 #define cr4     4
 610 #define cr5     5
 611 #define cr6     6
 612 #define cr7     7
 613
 614
 615 /*
 616  * General Purpose Registers (GPRs)
 617  *
 618  * The lower case r0-r31 should be used in preference to the upper
 619  * case R0-R31 as they provide more error checking in the assembler.
 620  * Use R0-31 only when really nessesary.
 621  */
 622
 623 #define r0      %r0
 624 #define r1      %r1
 625 #define r2      %r2
 626 #define r3      %r3
 627 #define r4      %r4
 628 #define r5      %r5
 629 #define r6      %r6
 630 #define r7      %r7
 631 #define r8      %r8
 632 #define r9      %r9
 633 #define r10     %r10
 634 #define r11     %r11
 635 #define r12     %r12
 636 #define r13     %r13
 637 #define r14     %r14
 638 #define r15     %r15
 639 #define r16     %r16
 640 #define r17     %r17
 641 #define r18     %r18
 642 #define r19     %r19
 643 #define r20     %r20
 644 #define r21     %r21
 645 #define r22     %r22
 646 #define r23     %r23
 647 #define r24     %r24
 648 #define r25     %r25
 649 #define r26     %r26
 650 #define r27     %r27
 651 #define r28     %r28
 652 #define r29     %r29
 653 #define r30     %r30
 654 #define r31     %r31
 655
 656
 657 /* Floating Point Registers (FPRs) */
 658
 659 #define fr0     0
 660 #define fr1     1
 661 #define fr2     2
 662 #define fr3     3
 663 #define fr4     4
 664 #define fr5     5
 665 #define fr6     6
 666 #define fr7     7
 667 #define fr8     8
 668 #define fr9     9
 669 #define fr10    10
 670 #define fr11    11
 671 #define fr12    12
 672 #define fr13    13
 673 #define fr14    14
 674 #define fr15    15
 675 #define fr16    16
 676 #define fr17    17
 677 #define fr18    18
 678 #define fr19    19
 679 #define fr20    20
 680 #define fr21    21
 681 #define fr22    22
 682 #define fr23    23
 683 #define fr24    24
 684 #define fr25    25
 685 #define fr26    26
 686 #define fr27    27
 687 #define fr28    28
 688 #define fr29    29
 689 #define fr30    30
 690 #define fr31    31
 691
 692 /* AltiVec Registers (VPRs) */
 693
 694 #define vr0     0
 695 #define vr1     1
 696 #define vr2     2
 697 #define vr3     3
 698 #define vr4     4
 699 #define vr5     5
 700 #define vr6     6
 701 #define vr7     7
 702 #define vr8     8
 703 #define vr9     9
 704 #define vr10    10
 705 #define vr11    11
 706 #define vr12    12
 707 #define vr13    13
 708 #define vr14    14
 709 #define vr15    15
 710 #define vr16    16
 711 #define vr17    17
 712 #define vr18    18
 713 #define vr19    19
 714 #define vr20    20
 715 #define vr21    21
 716 #define vr22    22
 717 #define vr23    23
 718 #define vr24    24
 719 #define vr25    25
 720 #define vr26    26
 721 #define vr27    27
 722 #define vr28    28
 723 #define vr29    29
 724 #define vr30    30
 725 #define vr31    31
 726
 727 /* VSX Registers (VSRs) */
 728
 729 #define vsr0    0
 730 #define vsr1    1
 731 #define vsr2    2
 732 #define vsr3    3
 733 #define vsr4    4
 734 #define vsr5    5
 735 #define vsr6    6
 736 #define vsr7    7
 737 #define vsr8    8
 738 #define vsr9    9
 739 #define vsr10   10
 740 #define vsr11   11
 741 #define vsr12   12
 742 #define vsr13   13
 743 #define vsr14   14
 744 #define vsr15   15
 745 #define vsr16   16
 746 #define vsr17   17
 747 #define vsr18   18
 748 #define vsr19   19
 749 #define vsr20   20
 750 #define vsr21   21
 751 #define vsr22   22
 752 #define vsr23   23
 753 #define vsr24   24
 754 #define vsr25   25
 755 #define vsr26   26
 756 #define vsr27   27
 757 #define vsr28   28
 758 #define vsr29   29
 759 #define vsr30   30
 760 #define vsr31   31
 761 #define vsr32   32
 762 #define vsr33   33
 763 #define vsr34   34
 764 #define vsr35   35
 765 #define vsr36   36
 766 #define vsr37   37
 767 #define vsr38   38
 768 #define vsr39   39
 769 #define vsr40   40
 770 #define vsr41   41
 771 #define vsr42   42
 772 #define vsr43   43
 773 #define vsr44   44
 774 #define vsr45   45
 775 #define vsr46   46
 776 #define vsr47   47
 777 #define vsr48   48
 778 #define vsr49   49
 779 #define vsr50   50
 780 #define vsr51   51
 781 #define vsr52   52
 782 #define vsr53   53
 783 #define vsr54   54
 784 #define vsr55   55
 785 #define vsr56   56
 786 #define vsr57   57
 787 #define vsr58   58
 788 #define vsr59   59
 789 #define vsr60   60
 790 #define vsr61   61
 791 #define vsr62   62
 792 #define vsr63   63
 793
 794 /* SPE Registers (EVPRs) */
 795
 796 #define evr0    0
 797 #define evr1    1
 798 #define evr2    2
 799 #define evr3    3
 800 #define evr4    4
 801 #define evr5    5
 802 #define evr6    6
 803 #define evr7    7
 804 #define evr8    8
 805 #define evr9    9
 806 #define evr10   10
 807 #define evr11   11
 808 #define evr12   12
 809 #define evr13   13
 810 #define evr14   14
 811 #define evr15   15
 812 #define evr16   16
 813 #define evr17   17
 814 #define evr18   18
 815 #define evr19   19
 816 #define evr20   20
 817 #define evr21   21
 818 #define evr22   22
 819 #define evr23   23
 820 #define evr24   24
 821 #define evr25   25
 822 #define evr26   26
 823 #define evr27   27
 824 #define evr28   28
 825 #define evr29   29
 826 #define evr30   30
 827 #define evr31   31
 828
 829 /* some stab codes */
 830 #define N_FUN   36
 831 #define N_RSYM  64
 832 #define N_SLINE 68
 833 #define N_SO    100
 834
 835 #endif /*  __ASSEMBLY__ */
 836
 837 #endif /* _ASM_POWERPC_PPC_ASM_H */