2 * Performance event support - powerpc architecture code
4 * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
11 #include <linux/kernel.h>
12 #include <linux/sched.h>
13 #include <linux/perf_event.h>
14 #include <linux/percpu.h>
15 #include <linux/hardirq.h>
16 #include <linux/uaccess.h>
19 #include <asm/machdep.h>
20 #include <asm/firmware.h>
21 #include <asm/ptrace.h>
22 #include <asm/code-patching.h>
24 #define BHRB_MAX_ENTRIES 32
25 #define BHRB_TARGET 0x0000000000000002
26 #define BHRB_PREDICTION 0x0000000000000001
27 #define BHRB_EA 0xFFFFFFFFFFFFFFFCUL
29 struct cpu_hw_events
{
36 struct perf_event
*event
[MAX_HWEVENTS
];
37 u64 events
[MAX_HWEVENTS
];
38 unsigned int flags
[MAX_HWEVENTS
];
39 unsigned long mmcr
[3];
40 struct perf_event
*limited_counter
[MAX_LIMITED_HWCOUNTERS
];
41 u8 limited_hwidx
[MAX_LIMITED_HWCOUNTERS
];
42 u64 alternatives
[MAX_HWEVENTS
][MAX_EVENT_ALTERNATIVES
];
43 unsigned long amasks
[MAX_HWEVENTS
][MAX_EVENT_ALTERNATIVES
];
44 unsigned long avalues
[MAX_HWEVENTS
][MAX_EVENT_ALTERNATIVES
];
46 unsigned int group_flag
;
50 u64 bhrb_filter
; /* BHRB HW branch filter */
53 struct perf_branch_stack bhrb_stack
;
54 struct perf_branch_entry bhrb_entries
[BHRB_MAX_ENTRIES
];
57 DEFINE_PER_CPU(struct cpu_hw_events
, cpu_hw_events
);
59 struct power_pmu
*ppmu
;
62 * Normally, to ignore kernel events we set the FCS (freeze counters
63 * in supervisor mode) bit in MMCR0, but if the kernel runs with the
64 * hypervisor bit set in the MSR, or if we are running on a processor
65 * where the hypervisor bit is forced to 1 (as on Apple G5 processors),
66 * then we need to use the FCHV bit to ignore kernel events.
68 static unsigned int freeze_events_kernel
= MMCR0_FCS
;
71 * 32-bit doesn't have MMCRA but does have an MMCR2,
72 * and a few other names are different.
77 #define MMCR0_PMCjCE MMCR0_PMCnCE
82 #define MMCR0_PMCC_U6 0
84 #define SPRN_MMCRA SPRN_MMCR2
85 #define MMCRA_SAMPLE_ENABLE 0
87 static inline unsigned long perf_ip_adjust(struct pt_regs
*regs
)
91 static inline void perf_get_data_addr(struct pt_regs
*regs
, u64
*addrp
) { }
92 static inline u32
perf_get_misc_flags(struct pt_regs
*regs
)
96 static inline void perf_read_regs(struct pt_regs
*regs
)
100 static inline int perf_intr_is_nmi(struct pt_regs
*regs
)
105 static inline int siar_valid(struct pt_regs
*regs
)
110 static bool is_ebb_event(struct perf_event
*event
) { return false; }
111 static int ebb_event_check(struct perf_event
*event
) { return 0; }
112 static void ebb_event_add(struct perf_event
*event
) { }
113 static void ebb_switch_out(unsigned long mmcr0
) { }
114 static unsigned long ebb_switch_in(bool ebb
, unsigned long mmcr0
)
119 static inline void power_pmu_bhrb_enable(struct perf_event
*event
) {}
120 static inline void power_pmu_bhrb_disable(struct perf_event
*event
) {}
121 void power_pmu_flush_branch_stack(void) {}
122 static inline void power_pmu_bhrb_read(struct cpu_hw_events
*cpuhw
) {}
123 #endif /* CONFIG_PPC32 */
125 static bool regs_use_siar(struct pt_regs
*regs
)
127 return !!regs
->result
;
131 * Things that are specific to 64-bit implementations.
135 static inline unsigned long perf_ip_adjust(struct pt_regs
*regs
)
137 unsigned long mmcra
= regs
->dsisr
;
139 if ((ppmu
->flags
& PPMU_HAS_SSLOT
) && (mmcra
& MMCRA_SAMPLE_ENABLE
)) {
140 unsigned long slot
= (mmcra
& MMCRA_SLOT
) >> MMCRA_SLOT_SHIFT
;
142 return 4 * (slot
- 1);
149 * The user wants a data address recorded.
150 * If we're not doing instruction sampling, give them the SDAR
151 * (sampled data address). If we are doing instruction sampling, then
152 * only give them the SDAR if it corresponds to the instruction
153 * pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC, the
154 * [POWER7P_]MMCRA_SDAR_VALID bit in MMCRA, or the SDAR_VALID bit in SIER.
156 static inline void perf_get_data_addr(struct pt_regs
*regs
, u64
*addrp
)
158 unsigned long mmcra
= regs
->dsisr
;
161 if (ppmu
->flags
& PPMU_HAS_SIER
)
162 sdar_valid
= regs
->dar
& SIER_SDAR_VALID
;
164 unsigned long sdsync
;
166 if (ppmu
->flags
& PPMU_SIAR_VALID
)
167 sdsync
= POWER7P_MMCRA_SDAR_VALID
;
168 else if (ppmu
->flags
& PPMU_ALT_SIPR
)
169 sdsync
= POWER6_MMCRA_SDSYNC
;
171 sdsync
= MMCRA_SDSYNC
;
173 sdar_valid
= mmcra
& sdsync
;
176 if (!(mmcra
& MMCRA_SAMPLE_ENABLE
) || sdar_valid
)
177 *addrp
= mfspr(SPRN_SDAR
);
180 static bool regs_sihv(struct pt_regs
*regs
)
182 unsigned long sihv
= MMCRA_SIHV
;
184 if (ppmu
->flags
& PPMU_HAS_SIER
)
185 return !!(regs
->dar
& SIER_SIHV
);
187 if (ppmu
->flags
& PPMU_ALT_SIPR
)
188 sihv
= POWER6_MMCRA_SIHV
;
190 return !!(regs
->dsisr
& sihv
);
193 static bool regs_sipr(struct pt_regs
*regs
)
195 unsigned long sipr
= MMCRA_SIPR
;
197 if (ppmu
->flags
& PPMU_HAS_SIER
)
198 return !!(regs
->dar
& SIER_SIPR
);
200 if (ppmu
->flags
& PPMU_ALT_SIPR
)
201 sipr
= POWER6_MMCRA_SIPR
;
203 return !!(regs
->dsisr
& sipr
);
206 static inline u32
perf_flags_from_msr(struct pt_regs
*regs
)
208 if (regs
->msr
& MSR_PR
)
209 return PERF_RECORD_MISC_USER
;
210 if ((regs
->msr
& MSR_HV
) && freeze_events_kernel
!= MMCR0_FCHV
)
211 return PERF_RECORD_MISC_HYPERVISOR
;
212 return PERF_RECORD_MISC_KERNEL
;
215 static inline u32
perf_get_misc_flags(struct pt_regs
*regs
)
217 bool use_siar
= regs_use_siar(regs
);
220 return perf_flags_from_msr(regs
);
223 * If we don't have flags in MMCRA, rather than using
224 * the MSR, we intuit the flags from the address in
225 * SIAR which should give slightly more reliable
228 if (ppmu
->flags
& PPMU_NO_SIPR
) {
229 unsigned long siar
= mfspr(SPRN_SIAR
);
230 if (siar
>= PAGE_OFFSET
)
231 return PERF_RECORD_MISC_KERNEL
;
232 return PERF_RECORD_MISC_USER
;
235 /* PR has priority over HV, so order below is important */
237 return PERF_RECORD_MISC_USER
;
239 if (regs_sihv(regs
) && (freeze_events_kernel
!= MMCR0_FCHV
))
240 return PERF_RECORD_MISC_HYPERVISOR
;
242 return PERF_RECORD_MISC_KERNEL
;
246 * Overload regs->dsisr to store MMCRA so we only need to read it once
248 * Overload regs->dar to store SIER if we have it.
249 * Overload regs->result to specify whether we should use the MSR (result
250 * is zero) or the SIAR (result is non zero).
252 static inline void perf_read_regs(struct pt_regs
*regs
)
254 unsigned long mmcra
= mfspr(SPRN_MMCRA
);
255 int marked
= mmcra
& MMCRA_SAMPLE_ENABLE
;
260 if (ppmu
->flags
& PPMU_HAS_SIER
)
261 regs
->dar
= mfspr(SPRN_SIER
);
264 * If this isn't a PMU exception (eg a software event) the SIAR is
265 * not valid. Use pt_regs.
267 * If it is a marked event use the SIAR.
269 * If the PMU doesn't update the SIAR for non marked events use
272 * If the PMU has HV/PR flags then check to see if they
273 * place the exception in userspace. If so, use pt_regs. In
274 * continuous sampling mode the SIAR and the PMU exception are
275 * not synchronised, so they may be many instructions apart.
276 * This can result in confusing backtraces. We still want
277 * hypervisor samples as well as samples in the kernel with
278 * interrupts off hence the userspace check.
280 if (TRAP(regs
) != 0xf00)
284 else if ((ppmu
->flags
& PPMU_NO_CONT_SAMPLING
))
286 else if (!(ppmu
->flags
& PPMU_NO_SIPR
) && regs_sipr(regs
))
291 regs
->result
= use_siar
;
295 * If interrupts were soft-disabled when a PMU interrupt occurs, treat
298 static inline int perf_intr_is_nmi(struct pt_regs
*regs
)
304 * On processors like P7+ that have the SIAR-Valid bit, marked instructions
305 * must be sampled only if the SIAR-valid bit is set.
307 * For unmarked instructions and for processors that don't have the SIAR-Valid
308 * bit, assume that SIAR is valid.
310 static inline int siar_valid(struct pt_regs
*regs
)
312 unsigned long mmcra
= regs
->dsisr
;
313 int marked
= mmcra
& MMCRA_SAMPLE_ENABLE
;
316 if (ppmu
->flags
& PPMU_HAS_SIER
)
317 return regs
->dar
& SIER_SIAR_VALID
;
319 if (ppmu
->flags
& PPMU_SIAR_VALID
)
320 return mmcra
& POWER7P_MMCRA_SIAR_VALID
;
327 /* Reset all possible BHRB entries */
328 static void power_pmu_bhrb_reset(void)
330 asm volatile(PPC_CLRBHRB
);
333 static void power_pmu_bhrb_enable(struct perf_event
*event
)
335 struct cpu_hw_events
*cpuhw
= &__get_cpu_var(cpu_hw_events
);
340 /* Clear BHRB if we changed task context to avoid data leaks */
341 if (event
->ctx
->task
&& cpuhw
->bhrb_context
!= event
->ctx
) {
342 power_pmu_bhrb_reset();
343 cpuhw
->bhrb_context
= event
->ctx
;
348 static void power_pmu_bhrb_disable(struct perf_event
*event
)
350 struct cpu_hw_events
*cpuhw
= &__get_cpu_var(cpu_hw_events
);
356 WARN_ON_ONCE(cpuhw
->bhrb_users
< 0);
358 if (!cpuhw
->disabled
&& !cpuhw
->bhrb_users
) {
359 /* BHRB cannot be turned off when other
360 * events are active on the PMU.
363 /* avoid stale pointer */
364 cpuhw
->bhrb_context
= NULL
;
368 /* Called from ctxsw to prevent one process's branch entries to
369 * mingle with the other process's entries during context switch.
371 void power_pmu_flush_branch_stack(void)
374 power_pmu_bhrb_reset();
376 /* Calculate the to address for a branch */
377 static __u64
power_pmu_bhrb_to(u64 addr
)
383 if (is_kernel_addr(addr
))
384 return branch_target((unsigned int *)addr
);
386 /* Userspace: need copy instruction here then translate it */
388 ret
= __get_user_inatomic(instr
, (unsigned int __user
*)addr
);
395 target
= branch_target(&instr
);
396 if ((!target
) || (instr
& BRANCH_ABSOLUTE
))
399 /* Translate relative branch target from kernel to user address */
400 return target
- (unsigned long)&instr
+ addr
;
403 /* Processing BHRB entries */
404 void power_pmu_bhrb_read(struct cpu_hw_events
*cpuhw
)
408 int r_index
, u_index
, pred
;
412 while (r_index
< ppmu
->bhrb_nr
) {
413 /* Assembly read function */
414 val
= read_bhrb(r_index
++);
416 /* Terminal marker: End of valid BHRB entries */
419 addr
= val
& BHRB_EA
;
420 pred
= val
& BHRB_PREDICTION
;
426 /* Branches are read most recent first (ie. mfbhrb 0 is
427 * the most recent branch).
428 * There are two types of valid entries:
429 * 1) a target entry which is the to address of a
430 * computed goto like a blr,bctr,btar. The next
431 * entry read from the bhrb will be branch
432 * corresponding to this target (ie. the actual
433 * blr/bctr/btar instruction).
434 * 2) a from address which is an actual branch. If a
435 * target entry proceeds this, then this is the
436 * matching branch for that target. If this is not
437 * following a target entry, then this is a branch
438 * where the target is given as an immediate field
439 * in the instruction (ie. an i or b form branch).
440 * In this case we need to read the instruction from
441 * memory to determine the target/to address.
444 if (val
& BHRB_TARGET
) {
445 /* Target branches use two entries
446 * (ie. computed gotos/XL form)
448 cpuhw
->bhrb_entries
[u_index
].to
= addr
;
449 cpuhw
->bhrb_entries
[u_index
].mispred
= pred
;
450 cpuhw
->bhrb_entries
[u_index
].predicted
= ~pred
;
452 /* Get from address in next entry */
453 val
= read_bhrb(r_index
++);
454 addr
= val
& BHRB_EA
;
455 if (val
& BHRB_TARGET
) {
456 /* Shouldn't have two targets in a
457 row.. Reset index and try again */
461 cpuhw
->bhrb_entries
[u_index
].from
= addr
;
463 /* Branches to immediate field
465 cpuhw
->bhrb_entries
[u_index
].from
= addr
;
466 cpuhw
->bhrb_entries
[u_index
].to
=
467 power_pmu_bhrb_to(addr
);
468 cpuhw
->bhrb_entries
[u_index
].mispred
= pred
;
469 cpuhw
->bhrb_entries
[u_index
].predicted
= ~pred
;
475 cpuhw
->bhrb_stack
.nr
= u_index
;
479 static bool is_ebb_event(struct perf_event
*event
)
482 * This could be a per-PMU callback, but we'd rather avoid the cost. We
483 * check that the PMU supports EBB, meaning those that don't can still
484 * use bit 63 of the event code for something else if they wish.
486 return (ppmu
->flags
& PPMU_ARCH_207S
) &&
487 ((event
->attr
.config
>> PERF_EVENT_CONFIG_EBB_SHIFT
) & 1);
490 static int ebb_event_check(struct perf_event
*event
)
492 struct perf_event
*leader
= event
->group_leader
;
494 /* Event and group leader must agree on EBB */
495 if (is_ebb_event(leader
) != is_ebb_event(event
))
498 if (is_ebb_event(event
)) {
499 if (!(event
->attach_state
& PERF_ATTACH_TASK
))
502 if (!leader
->attr
.pinned
|| !leader
->attr
.exclusive
)
505 if (event
->attr
.inherit
|| event
->attr
.sample_period
||
506 event
->attr
.enable_on_exec
|| event
->attr
.freq
)
513 static void ebb_event_add(struct perf_event
*event
)
515 if (!is_ebb_event(event
) || current
->thread
.used_ebb
)
519 * IFF this is the first time we've added an EBB event, set
520 * PMXE in the user MMCR0 so we can detect when it's cleared by
521 * userspace. We need this so that we can context switch while
522 * userspace is in the EBB handler (where PMXE is 0).
524 current
->thread
.used_ebb
= 1;
525 current
->thread
.mmcr0
|= MMCR0_PMXE
;
528 static void ebb_switch_out(unsigned long mmcr0
)
530 if (!(mmcr0
& MMCR0_EBE
))
533 current
->thread
.siar
= mfspr(SPRN_SIAR
);
534 current
->thread
.sier
= mfspr(SPRN_SIER
);
535 current
->thread
.sdar
= mfspr(SPRN_SDAR
);
536 current
->thread
.mmcr0
= mmcr0
& MMCR0_USER_MASK
;
537 current
->thread
.mmcr2
= mfspr(SPRN_MMCR2
) & MMCR2_USER_MASK
;
540 static unsigned long ebb_switch_in(bool ebb
, unsigned long mmcr0
)
545 /* Enable EBB and read/write to all 6 PMCs for userspace */
546 mmcr0
|= MMCR0_EBE
| MMCR0_PMCC_U6
;
548 /* Add any bits from the user reg, FC or PMAO */
549 mmcr0
|= current
->thread
.mmcr0
;
551 /* Be careful not to set PMXE if userspace had it cleared */
552 if (!(current
->thread
.mmcr0
& MMCR0_PMXE
))
553 mmcr0
&= ~MMCR0_PMXE
;
555 mtspr(SPRN_SIAR
, current
->thread
.siar
);
556 mtspr(SPRN_SIER
, current
->thread
.sier
);
557 mtspr(SPRN_SDAR
, current
->thread
.sdar
);
558 mtspr(SPRN_MMCR2
, current
->thread
.mmcr2
);
562 #endif /* CONFIG_PPC64 */
564 static void perf_event_interrupt(struct pt_regs
*regs
);
566 void perf_event_print_debug(void)
571 * Read one performance monitor counter (PMC).
573 static unsigned long read_pmc(int idx
)
579 val
= mfspr(SPRN_PMC1
);
582 val
= mfspr(SPRN_PMC2
);
585 val
= mfspr(SPRN_PMC3
);
588 val
= mfspr(SPRN_PMC4
);
591 val
= mfspr(SPRN_PMC5
);
594 val
= mfspr(SPRN_PMC6
);
598 val
= mfspr(SPRN_PMC7
);
601 val
= mfspr(SPRN_PMC8
);
603 #endif /* CONFIG_PPC64 */
605 printk(KERN_ERR
"oops trying to read PMC%d\n", idx
);
614 static void write_pmc(int idx
, unsigned long val
)
618 mtspr(SPRN_PMC1
, val
);
621 mtspr(SPRN_PMC2
, val
);
624 mtspr(SPRN_PMC3
, val
);
627 mtspr(SPRN_PMC4
, val
);
630 mtspr(SPRN_PMC5
, val
);
633 mtspr(SPRN_PMC6
, val
);
637 mtspr(SPRN_PMC7
, val
);
640 mtspr(SPRN_PMC8
, val
);
642 #endif /* CONFIG_PPC64 */
644 printk(KERN_ERR
"oops trying to write PMC%d\n", idx
);
649 * Check if a set of events can all go on the PMU at once.
650 * If they can't, this will look at alternative codes for the events
651 * and see if any combination of alternative codes is feasible.
652 * The feasible set is returned in event_id[].
654 static int power_check_constraints(struct cpu_hw_events
*cpuhw
,
655 u64 event_id
[], unsigned int cflags
[],
658 unsigned long mask
, value
, nv
;
659 unsigned long smasks
[MAX_HWEVENTS
], svalues
[MAX_HWEVENTS
];
660 int n_alt
[MAX_HWEVENTS
], choice
[MAX_HWEVENTS
];
662 unsigned long addf
= ppmu
->add_fields
;
663 unsigned long tadd
= ppmu
->test_adder
;
665 if (n_ev
> ppmu
->n_counter
)
668 /* First see if the events will go on as-is */
669 for (i
= 0; i
< n_ev
; ++i
) {
670 if ((cflags
[i
] & PPMU_LIMITED_PMC_REQD
)
671 && !ppmu
->limited_pmc_event(event_id
[i
])) {
672 ppmu
->get_alternatives(event_id
[i
], cflags
[i
],
673 cpuhw
->alternatives
[i
]);
674 event_id
[i
] = cpuhw
->alternatives
[i
][0];
676 if (ppmu
->get_constraint(event_id
[i
], &cpuhw
->amasks
[i
][0],
677 &cpuhw
->avalues
[i
][0]))
681 for (i
= 0; i
< n_ev
; ++i
) {
682 nv
= (value
| cpuhw
->avalues
[i
][0]) +
683 (value
& cpuhw
->avalues
[i
][0] & addf
);
684 if ((((nv
+ tadd
) ^ value
) & mask
) != 0 ||
685 (((nv
+ tadd
) ^ cpuhw
->avalues
[i
][0]) &
686 cpuhw
->amasks
[i
][0]) != 0)
689 mask
|= cpuhw
->amasks
[i
][0];
692 return 0; /* all OK */
694 /* doesn't work, gather alternatives... */
695 if (!ppmu
->get_alternatives
)
697 for (i
= 0; i
< n_ev
; ++i
) {
699 n_alt
[i
] = ppmu
->get_alternatives(event_id
[i
], cflags
[i
],
700 cpuhw
->alternatives
[i
]);
701 for (j
= 1; j
< n_alt
[i
]; ++j
)
702 ppmu
->get_constraint(cpuhw
->alternatives
[i
][j
],
703 &cpuhw
->amasks
[i
][j
],
704 &cpuhw
->avalues
[i
][j
]);
707 /* enumerate all possibilities and see if any will work */
710 value
= mask
= nv
= 0;
713 /* we're backtracking, restore context */
719 * See if any alternative k for event_id i,
720 * where k > j, will satisfy the constraints.
722 while (++j
< n_alt
[i
]) {
723 nv
= (value
| cpuhw
->avalues
[i
][j
]) +
724 (value
& cpuhw
->avalues
[i
][j
] & addf
);
725 if ((((nv
+ tadd
) ^ value
) & mask
) == 0 &&
726 (((nv
+ tadd
) ^ cpuhw
->avalues
[i
][j
])
727 & cpuhw
->amasks
[i
][j
]) == 0)
732 * No feasible alternative, backtrack
733 * to event_id i-1 and continue enumerating its
734 * alternatives from where we got up to.
740 * Found a feasible alternative for event_id i,
741 * remember where we got up to with this event_id,
742 * go on to the next event_id, and start with
743 * the first alternative for it.
749 mask
|= cpuhw
->amasks
[i
][j
];
755 /* OK, we have a feasible combination, tell the caller the solution */
756 for (i
= 0; i
< n_ev
; ++i
)
757 event_id
[i
] = cpuhw
->alternatives
[i
][choice
[i
]];
762 * Check if newly-added events have consistent settings for
763 * exclude_{user,kernel,hv} with each other and any previously
766 static int check_excludes(struct perf_event
**ctrs
, unsigned int cflags
[],
767 int n_prev
, int n_new
)
769 int eu
= 0, ek
= 0, eh
= 0;
771 struct perf_event
*event
;
778 for (i
= 0; i
< n
; ++i
) {
779 if (cflags
[i
] & PPMU_LIMITED_PMC_OK
) {
780 cflags
[i
] &= ~PPMU_LIMITED_PMC_REQD
;
785 eu
= event
->attr
.exclude_user
;
786 ek
= event
->attr
.exclude_kernel
;
787 eh
= event
->attr
.exclude_hv
;
789 } else if (event
->attr
.exclude_user
!= eu
||
790 event
->attr
.exclude_kernel
!= ek
||
791 event
->attr
.exclude_hv
!= eh
) {
797 for (i
= 0; i
< n
; ++i
)
798 if (cflags
[i
] & PPMU_LIMITED_PMC_OK
)
799 cflags
[i
] |= PPMU_LIMITED_PMC_REQD
;
804 static u64
check_and_compute_delta(u64 prev
, u64 val
)
806 u64 delta
= (val
- prev
) & 0xfffffffful
;
809 * POWER7 can roll back counter values, if the new value is smaller
810 * than the previous value it will cause the delta and the counter to
811 * have bogus values unless we rolled a counter over. If a coutner is
812 * rolled back, it will be smaller, but within 256, which is the maximum
813 * number of events to rollback at once. If we dectect a rollback
814 * return 0. This can lead to a small lack of precision in the
817 if (prev
> val
&& (prev
- val
) < 256)
823 static void power_pmu_read(struct perf_event
*event
)
825 s64 val
, delta
, prev
;
827 if (event
->hw
.state
& PERF_HES_STOPPED
)
833 if (is_ebb_event(event
)) {
834 val
= read_pmc(event
->hw
.idx
);
835 local64_set(&event
->hw
.prev_count
, val
);
840 * Performance monitor interrupts come even when interrupts
841 * are soft-disabled, as long as interrupts are hard-enabled.
842 * Therefore we treat them like NMIs.
845 prev
= local64_read(&event
->hw
.prev_count
);
847 val
= read_pmc(event
->hw
.idx
);
848 delta
= check_and_compute_delta(prev
, val
);
851 } while (local64_cmpxchg(&event
->hw
.prev_count
, prev
, val
) != prev
);
853 local64_add(delta
, &event
->count
);
856 * A number of places program the PMC with (0x80000000 - period_left).
857 * We never want period_left to be less than 1 because we will program
858 * the PMC with a value >= 0x800000000 and an edge detected PMC will
859 * roll around to 0 before taking an exception. We have seen this
862 * To fix this, clamp the minimum value of period_left to 1.
865 prev
= local64_read(&event
->hw
.period_left
);
869 } while (local64_cmpxchg(&event
->hw
.period_left
, prev
, val
) != prev
);
873 * On some machines, PMC5 and PMC6 can't be written, don't respect
874 * the freeze conditions, and don't generate interrupts. This tells
875 * us if `event' is using such a PMC.
877 static int is_limited_pmc(int pmcnum
)
879 return (ppmu
->flags
& PPMU_LIMITED_PMC5_6
)
880 && (pmcnum
== 5 || pmcnum
== 6);
883 static void freeze_limited_counters(struct cpu_hw_events
*cpuhw
,
884 unsigned long pmc5
, unsigned long pmc6
)
886 struct perf_event
*event
;
887 u64 val
, prev
, delta
;
890 for (i
= 0; i
< cpuhw
->n_limited
; ++i
) {
891 event
= cpuhw
->limited_counter
[i
];
894 val
= (event
->hw
.idx
== 5) ? pmc5
: pmc6
;
895 prev
= local64_read(&event
->hw
.prev_count
);
897 delta
= check_and_compute_delta(prev
, val
);
899 local64_add(delta
, &event
->count
);
903 static void thaw_limited_counters(struct cpu_hw_events
*cpuhw
,
904 unsigned long pmc5
, unsigned long pmc6
)
906 struct perf_event
*event
;
910 for (i
= 0; i
< cpuhw
->n_limited
; ++i
) {
911 event
= cpuhw
->limited_counter
[i
];
912 event
->hw
.idx
= cpuhw
->limited_hwidx
[i
];
913 val
= (event
->hw
.idx
== 5) ? pmc5
: pmc6
;
914 prev
= local64_read(&event
->hw
.prev_count
);
915 if (check_and_compute_delta(prev
, val
))
916 local64_set(&event
->hw
.prev_count
, val
);
917 perf_event_update_userpage(event
);
922 * Since limited events don't respect the freeze conditions, we
923 * have to read them immediately after freezing or unfreezing the
924 * other events. We try to keep the values from the limited
925 * events as consistent as possible by keeping the delay (in
926 * cycles and instructions) between freezing/unfreezing and reading
927 * the limited events as small and consistent as possible.
928 * Therefore, if any limited events are in use, we read them
929 * both, and always in the same order, to minimize variability,
930 * and do it inside the same asm that writes MMCR0.
932 static void write_mmcr0(struct cpu_hw_events
*cpuhw
, unsigned long mmcr0
)
934 unsigned long pmc5
, pmc6
;
936 if (!cpuhw
->n_limited
) {
937 mtspr(SPRN_MMCR0
, mmcr0
);
942 * Write MMCR0, then read PMC5 and PMC6 immediately.
943 * To ensure we don't get a performance monitor interrupt
944 * between writing MMCR0 and freezing/thawing the limited
945 * events, we first write MMCR0 with the event overflow
946 * interrupt enable bits turned off.
948 asm volatile("mtspr %3,%2; mfspr %0,%4; mfspr %1,%5"
949 : "=&r" (pmc5
), "=&r" (pmc6
)
950 : "r" (mmcr0
& ~(MMCR0_PMC1CE
| MMCR0_PMCjCE
)),
952 "i" (SPRN_PMC5
), "i" (SPRN_PMC6
));
954 if (mmcr0
& MMCR0_FC
)
955 freeze_limited_counters(cpuhw
, pmc5
, pmc6
);
957 thaw_limited_counters(cpuhw
, pmc5
, pmc6
);
960 * Write the full MMCR0 including the event overflow interrupt
961 * enable bits, if necessary.
963 if (mmcr0
& (MMCR0_PMC1CE
| MMCR0_PMCjCE
))
964 mtspr(SPRN_MMCR0
, mmcr0
);
968 * Disable all events to prevent PMU interrupts and to allow
969 * events to be added or removed.
971 static void power_pmu_disable(struct pmu
*pmu
)
973 struct cpu_hw_events
*cpuhw
;
974 unsigned long flags
, mmcr0
, val
;
978 local_irq_save(flags
);
979 cpuhw
= &__get_cpu_var(cpu_hw_events
);
981 if (!cpuhw
->disabled
) {
983 * Check if we ever enabled the PMU on this cpu.
985 if (!cpuhw
->pmcs_enabled
) {
987 cpuhw
->pmcs_enabled
= 1;
991 * Set the 'freeze counters' bit, clear EBE/PMCC/PMAO/FC56.
993 val
= mmcr0
= mfspr(SPRN_MMCR0
);
995 val
&= ~(MMCR0_EBE
| MMCR0_PMCC
| MMCR0_PMAO
| MMCR0_FC56
);
998 * The barrier is to make sure the mtspr has been
999 * executed and the PMU has frozen the events etc.
1002 write_mmcr0(cpuhw
, val
);
1006 * Disable instruction sampling if it was enabled
1008 if (cpuhw
->mmcr
[2] & MMCRA_SAMPLE_ENABLE
) {
1010 cpuhw
->mmcr
[2] & ~MMCRA_SAMPLE_ENABLE
);
1014 cpuhw
->disabled
= 1;
1017 ebb_switch_out(mmcr0
);
1020 local_irq_restore(flags
);
1024 * Re-enable all events if disable == 0.
1025 * If we were previously disabled and events were added, then
1026 * put the new config on the PMU.
1028 static void power_pmu_enable(struct pmu
*pmu
)
1030 struct perf_event
*event
;
1031 struct cpu_hw_events
*cpuhw
;
1032 unsigned long flags
;
1034 unsigned long val
, mmcr0
;
1036 unsigned int hwc_index
[MAX_HWEVENTS
];
1043 local_irq_save(flags
);
1045 cpuhw
= &__get_cpu_var(cpu_hw_events
);
1046 if (!cpuhw
->disabled
)
1049 if (cpuhw
->n_events
== 0) {
1050 ppc_set_pmu_inuse(0);
1054 cpuhw
->disabled
= 0;
1057 * EBB requires an exclusive group and all events must have the EBB
1058 * flag set, or not set, so we can just check a single event. Also we
1059 * know we have at least one event.
1061 ebb
= is_ebb_event(cpuhw
->event
[0]);
1064 * If we didn't change anything, or only removed events,
1065 * no need to recalculate MMCR* settings and reset the PMCs.
1066 * Just reenable the PMU with the current MMCR* settings
1067 * (possibly updated for removal of events).
1069 if (!cpuhw
->n_added
) {
1070 mtspr(SPRN_MMCRA
, cpuhw
->mmcr
[2] & ~MMCRA_SAMPLE_ENABLE
);
1071 mtspr(SPRN_MMCR1
, cpuhw
->mmcr
[1]);
1076 * Compute MMCR* values for the new set of events
1078 if (ppmu
->compute_mmcr(cpuhw
->events
, cpuhw
->n_events
, hwc_index
,
1080 /* shouldn't ever get here */
1081 printk(KERN_ERR
"oops compute_mmcr failed\n");
1086 * Add in MMCR0 freeze bits corresponding to the
1087 * attr.exclude_* bits for the first event.
1088 * We have already checked that all events have the
1089 * same values for these bits as the first event.
1091 event
= cpuhw
->event
[0];
1092 if (event
->attr
.exclude_user
)
1093 cpuhw
->mmcr
[0] |= MMCR0_FCP
;
1094 if (event
->attr
.exclude_kernel
)
1095 cpuhw
->mmcr
[0] |= freeze_events_kernel
;
1096 if (event
->attr
.exclude_hv
)
1097 cpuhw
->mmcr
[0] |= MMCR0_FCHV
;
1100 * Write the new configuration to MMCR* with the freeze
1101 * bit set and set the hardware events to their initial values.
1102 * Then unfreeze the events.
1104 ppc_set_pmu_inuse(1);
1105 mtspr(SPRN_MMCRA
, cpuhw
->mmcr
[2] & ~MMCRA_SAMPLE_ENABLE
);
1106 mtspr(SPRN_MMCR1
, cpuhw
->mmcr
[1]);
1107 mtspr(SPRN_MMCR0
, (cpuhw
->mmcr
[0] & ~(MMCR0_PMC1CE
| MMCR0_PMCjCE
))
1111 * Read off any pre-existing events that need to move
1114 for (i
= 0; i
< cpuhw
->n_events
; ++i
) {
1115 event
= cpuhw
->event
[i
];
1116 if (event
->hw
.idx
&& event
->hw
.idx
!= hwc_index
[i
] + 1) {
1117 power_pmu_read(event
);
1118 write_pmc(event
->hw
.idx
, 0);
1124 * Initialize the PMCs for all the new and moved events.
1126 cpuhw
->n_limited
= n_lim
= 0;
1127 for (i
= 0; i
< cpuhw
->n_events
; ++i
) {
1128 event
= cpuhw
->event
[i
];
1131 idx
= hwc_index
[i
] + 1;
1132 if (is_limited_pmc(idx
)) {
1133 cpuhw
->limited_counter
[n_lim
] = event
;
1134 cpuhw
->limited_hwidx
[n_lim
] = idx
;
1140 val
= local64_read(&event
->hw
.prev_count
);
1143 if (event
->hw
.sample_period
) {
1144 left
= local64_read(&event
->hw
.period_left
);
1145 if (left
< 0x80000000L
)
1146 val
= 0x80000000L
- left
;
1148 local64_set(&event
->hw
.prev_count
, val
);
1151 event
->hw
.idx
= idx
;
1152 if (event
->hw
.state
& PERF_HES_STOPPED
)
1154 write_pmc(idx
, val
);
1156 perf_event_update_userpage(event
);
1158 cpuhw
->n_limited
= n_lim
;
1159 cpuhw
->mmcr
[0] |= MMCR0_PMXE
| MMCR0_FCECE
;
1162 mmcr0
= ebb_switch_in(ebb
, cpuhw
->mmcr
[0]);
1165 write_mmcr0(cpuhw
, mmcr0
);
1167 if (ppmu
->flags
& PPMU_ARCH_207S
)
1168 mtspr(SPRN_MMCR2
, 0);
1171 * Enable instruction sampling if necessary
1173 if (cpuhw
->mmcr
[2] & MMCRA_SAMPLE_ENABLE
) {
1175 mtspr(SPRN_MMCRA
, cpuhw
->mmcr
[2]);
1179 if (cpuhw
->bhrb_users
)
1180 ppmu
->config_bhrb(cpuhw
->bhrb_filter
);
1182 local_irq_restore(flags
);
1185 static int collect_events(struct perf_event
*group
, int max_count
,
1186 struct perf_event
*ctrs
[], u64
*events
,
1187 unsigned int *flags
)
1190 struct perf_event
*event
;
1192 if (!is_software_event(group
)) {
1196 flags
[n
] = group
->hw
.event_base
;
1197 events
[n
++] = group
->hw
.config
;
1199 list_for_each_entry(event
, &group
->sibling_list
, group_entry
) {
1200 if (!is_software_event(event
) &&
1201 event
->state
!= PERF_EVENT_STATE_OFF
) {
1205 flags
[n
] = event
->hw
.event_base
;
1206 events
[n
++] = event
->hw
.config
;
1213 * Add a event to the PMU.
1214 * If all events are not already frozen, then we disable and
1215 * re-enable the PMU in order to get hw_perf_enable to do the
1216 * actual work of reconfiguring the PMU.
1218 static int power_pmu_add(struct perf_event
*event
, int ef_flags
)
1220 struct cpu_hw_events
*cpuhw
;
1221 unsigned long flags
;
1225 local_irq_save(flags
);
1226 perf_pmu_disable(event
->pmu
);
1229 * Add the event to the list (if there is room)
1230 * and check whether the total set is still feasible.
1232 cpuhw
= &__get_cpu_var(cpu_hw_events
);
1233 n0
= cpuhw
->n_events
;
1234 if (n0
>= ppmu
->n_counter
)
1236 cpuhw
->event
[n0
] = event
;
1237 cpuhw
->events
[n0
] = event
->hw
.config
;
1238 cpuhw
->flags
[n0
] = event
->hw
.event_base
;
1241 * This event may have been disabled/stopped in record_and_restart()
1242 * because we exceeded the ->event_limit. If re-starting the event,
1243 * clear the ->hw.state (STOPPED and UPTODATE flags), so the user
1244 * notification is re-enabled.
1246 if (!(ef_flags
& PERF_EF_START
))
1247 event
->hw
.state
= PERF_HES_STOPPED
| PERF_HES_UPTODATE
;
1249 event
->hw
.state
= 0;
1252 * If group events scheduling transaction was started,
1253 * skip the schedulability test here, it will be performed
1254 * at commit time(->commit_txn) as a whole
1256 if (cpuhw
->group_flag
& PERF_EVENT_TXN
)
1259 if (check_excludes(cpuhw
->event
, cpuhw
->flags
, n0
, 1))
1261 if (power_check_constraints(cpuhw
, cpuhw
->events
, cpuhw
->flags
, n0
+ 1))
1263 event
->hw
.config
= cpuhw
->events
[n0
];
1266 ebb_event_add(event
);
1273 if (has_branch_stack(event
)) {
1274 power_pmu_bhrb_enable(event
);
1275 cpuhw
->bhrb_filter
= ppmu
->bhrb_filter_map(
1276 event
->attr
.branch_sample_type
);
1279 perf_pmu_enable(event
->pmu
);
1280 local_irq_restore(flags
);
1285 * Remove a event from the PMU.
1287 static void power_pmu_del(struct perf_event
*event
, int ef_flags
)
1289 struct cpu_hw_events
*cpuhw
;
1291 unsigned long flags
;
1293 local_irq_save(flags
);
1294 perf_pmu_disable(event
->pmu
);
1296 power_pmu_read(event
);
1298 cpuhw
= &__get_cpu_var(cpu_hw_events
);
1299 for (i
= 0; i
< cpuhw
->n_events
; ++i
) {
1300 if (event
== cpuhw
->event
[i
]) {
1301 while (++i
< cpuhw
->n_events
) {
1302 cpuhw
->event
[i
-1] = cpuhw
->event
[i
];
1303 cpuhw
->events
[i
-1] = cpuhw
->events
[i
];
1304 cpuhw
->flags
[i
-1] = cpuhw
->flags
[i
];
1307 ppmu
->disable_pmc(event
->hw
.idx
- 1, cpuhw
->mmcr
);
1308 if (event
->hw
.idx
) {
1309 write_pmc(event
->hw
.idx
, 0);
1312 perf_event_update_userpage(event
);
1316 for (i
= 0; i
< cpuhw
->n_limited
; ++i
)
1317 if (event
== cpuhw
->limited_counter
[i
])
1319 if (i
< cpuhw
->n_limited
) {
1320 while (++i
< cpuhw
->n_limited
) {
1321 cpuhw
->limited_counter
[i
-1] = cpuhw
->limited_counter
[i
];
1322 cpuhw
->limited_hwidx
[i
-1] = cpuhw
->limited_hwidx
[i
];
1326 if (cpuhw
->n_events
== 0) {
1327 /* disable exceptions if no events are running */
1328 cpuhw
->mmcr
[0] &= ~(MMCR0_PMXE
| MMCR0_FCECE
);
1331 if (has_branch_stack(event
))
1332 power_pmu_bhrb_disable(event
);
1334 perf_pmu_enable(event
->pmu
);
1335 local_irq_restore(flags
);
1339 * POWER-PMU does not support disabling individual counters, hence
1340 * program their cycle counter to their max value and ignore the interrupts.
1343 static void power_pmu_start(struct perf_event
*event
, int ef_flags
)
1345 unsigned long flags
;
1349 if (!event
->hw
.idx
|| !event
->hw
.sample_period
)
1352 if (!(event
->hw
.state
& PERF_HES_STOPPED
))
1355 if (ef_flags
& PERF_EF_RELOAD
)
1356 WARN_ON_ONCE(!(event
->hw
.state
& PERF_HES_UPTODATE
));
1358 local_irq_save(flags
);
1359 perf_pmu_disable(event
->pmu
);
1361 event
->hw
.state
= 0;
1362 left
= local64_read(&event
->hw
.period_left
);
1365 if (left
< 0x80000000L
)
1366 val
= 0x80000000L
- left
;
1368 write_pmc(event
->hw
.idx
, val
);
1370 perf_event_update_userpage(event
);
1371 perf_pmu_enable(event
->pmu
);
1372 local_irq_restore(flags
);
1375 static void power_pmu_stop(struct perf_event
*event
, int ef_flags
)
1377 unsigned long flags
;
1379 if (!event
->hw
.idx
|| !event
->hw
.sample_period
)
1382 if (event
->hw
.state
& PERF_HES_STOPPED
)
1385 local_irq_save(flags
);
1386 perf_pmu_disable(event
->pmu
);
1388 power_pmu_read(event
);
1389 event
->hw
.state
|= PERF_HES_STOPPED
| PERF_HES_UPTODATE
;
1390 write_pmc(event
->hw
.idx
, 0);
1392 perf_event_update_userpage(event
);
1393 perf_pmu_enable(event
->pmu
);
1394 local_irq_restore(flags
);
1398 * Start group events scheduling transaction
1399 * Set the flag to make pmu::enable() not perform the
1400 * schedulability test, it will be performed at commit time
1402 void power_pmu_start_txn(struct pmu
*pmu
)
1404 struct cpu_hw_events
*cpuhw
= &__get_cpu_var(cpu_hw_events
);
1406 perf_pmu_disable(pmu
);
1407 cpuhw
->group_flag
|= PERF_EVENT_TXN
;
1408 cpuhw
->n_txn_start
= cpuhw
->n_events
;
1412 * Stop group events scheduling transaction
1413 * Clear the flag and pmu::enable() will perform the
1414 * schedulability test.
1416 void power_pmu_cancel_txn(struct pmu
*pmu
)
1418 struct cpu_hw_events
*cpuhw
= &__get_cpu_var(cpu_hw_events
);
1420 cpuhw
->group_flag
&= ~PERF_EVENT_TXN
;
1421 perf_pmu_enable(pmu
);
1425 * Commit group events scheduling transaction
1426 * Perform the group schedulability test as a whole
1427 * Return 0 if success
1429 int power_pmu_commit_txn(struct pmu
*pmu
)
1431 struct cpu_hw_events
*cpuhw
;
1436 cpuhw
= &__get_cpu_var(cpu_hw_events
);
1437 n
= cpuhw
->n_events
;
1438 if (check_excludes(cpuhw
->event
, cpuhw
->flags
, 0, n
))
1440 i
= power_check_constraints(cpuhw
, cpuhw
->events
, cpuhw
->flags
, n
);
1444 for (i
= cpuhw
->n_txn_start
; i
< n
; ++i
)
1445 cpuhw
->event
[i
]->hw
.config
= cpuhw
->events
[i
];
1447 cpuhw
->group_flag
&= ~PERF_EVENT_TXN
;
1448 perf_pmu_enable(pmu
);
1453 * Return 1 if we might be able to put event on a limited PMC,
1455 * A event can only go on a limited PMC if it counts something
1456 * that a limited PMC can count, doesn't require interrupts, and
1457 * doesn't exclude any processor mode.
1459 static int can_go_on_limited_pmc(struct perf_event
*event
, u64 ev
,
1463 u64 alt
[MAX_EVENT_ALTERNATIVES
];
1465 if (event
->attr
.exclude_user
1466 || event
->attr
.exclude_kernel
1467 || event
->attr
.exclude_hv
1468 || event
->attr
.sample_period
)
1471 if (ppmu
->limited_pmc_event(ev
))
1475 * The requested event_id isn't on a limited PMC already;
1476 * see if any alternative code goes on a limited PMC.
1478 if (!ppmu
->get_alternatives
)
1481 flags
|= PPMU_LIMITED_PMC_OK
| PPMU_LIMITED_PMC_REQD
;
1482 n
= ppmu
->get_alternatives(ev
, flags
, alt
);
1488 * Find an alternative event_id that goes on a normal PMC, if possible,
1489 * and return the event_id code, or 0 if there is no such alternative.
1490 * (Note: event_id code 0 is "don't count" on all machines.)
1492 static u64
normal_pmc_alternative(u64 ev
, unsigned long flags
)
1494 u64 alt
[MAX_EVENT_ALTERNATIVES
];
1497 flags
&= ~(PPMU_LIMITED_PMC_OK
| PPMU_LIMITED_PMC_REQD
);
1498 n
= ppmu
->get_alternatives(ev
, flags
, alt
);
1504 /* Number of perf_events counting hardware events */
1505 static atomic_t num_events
;
1506 /* Used to avoid races in calling reserve/release_pmc_hardware */
1507 static DEFINE_MUTEX(pmc_reserve_mutex
);
1510 * Release the PMU if this is the last perf_event.
1512 static void hw_perf_event_destroy(struct perf_event
*event
)
1514 if (!atomic_add_unless(&num_events
, -1, 1)) {
1515 mutex_lock(&pmc_reserve_mutex
);
1516 if (atomic_dec_return(&num_events
) == 0)
1517 release_pmc_hardware();
1518 mutex_unlock(&pmc_reserve_mutex
);
1523 * Translate a generic cache event_id config to a raw event_id code.
1525 static int hw_perf_cache_event(u64 config
, u64
*eventp
)
1527 unsigned long type
, op
, result
;
1530 if (!ppmu
->cache_events
)
1534 type
= config
& 0xff;
1535 op
= (config
>> 8) & 0xff;
1536 result
= (config
>> 16) & 0xff;
1538 if (type
>= PERF_COUNT_HW_CACHE_MAX
||
1539 op
>= PERF_COUNT_HW_CACHE_OP_MAX
||
1540 result
>= PERF_COUNT_HW_CACHE_RESULT_MAX
)
1543 ev
= (*ppmu
->cache_events
)[type
][op
][result
];
1552 static int power_pmu_event_init(struct perf_event
*event
)
1555 unsigned long flags
;
1556 struct perf_event
*ctrs
[MAX_HWEVENTS
];
1557 u64 events
[MAX_HWEVENTS
];
1558 unsigned int cflags
[MAX_HWEVENTS
];
1561 struct cpu_hw_events
*cpuhw
;
1566 if (has_branch_stack(event
)) {
1567 /* PMU has BHRB enabled */
1568 if (!(ppmu
->flags
& PPMU_ARCH_207S
))
1572 switch (event
->attr
.type
) {
1573 case PERF_TYPE_HARDWARE
:
1574 ev
= event
->attr
.config
;
1575 if (ev
>= ppmu
->n_generic
|| ppmu
->generic_events
[ev
] == 0)
1577 ev
= ppmu
->generic_events
[ev
];
1579 case PERF_TYPE_HW_CACHE
:
1580 err
= hw_perf_cache_event(event
->attr
.config
, &ev
);
1585 ev
= event
->attr
.config
;
1591 event
->hw
.config_base
= ev
;
1595 * If we are not running on a hypervisor, force the
1596 * exclude_hv bit to 0 so that we don't care what
1597 * the user set it to.
1599 if (!firmware_has_feature(FW_FEATURE_LPAR
))
1600 event
->attr
.exclude_hv
= 0;
1603 * If this is a per-task event, then we can use
1604 * PM_RUN_* events interchangeably with their non RUN_*
1605 * equivalents, e.g. PM_RUN_CYC instead of PM_CYC.
1606 * XXX we should check if the task is an idle task.
1609 if (event
->attach_state
& PERF_ATTACH_TASK
)
1610 flags
|= PPMU_ONLY_COUNT_RUN
;
1613 * If this machine has limited events, check whether this
1614 * event_id could go on a limited event.
1616 if (ppmu
->flags
& PPMU_LIMITED_PMC5_6
) {
1617 if (can_go_on_limited_pmc(event
, ev
, flags
)) {
1618 flags
|= PPMU_LIMITED_PMC_OK
;
1619 } else if (ppmu
->limited_pmc_event(ev
)) {
1621 * The requested event_id is on a limited PMC,
1622 * but we can't use a limited PMC; see if any
1623 * alternative goes on a normal PMC.
1625 ev
= normal_pmc_alternative(ev
, flags
);
1631 /* Extra checks for EBB */
1632 err
= ebb_event_check(event
);
1637 * If this is in a group, check if it can go on with all the
1638 * other hardware events in the group. We assume the event
1639 * hasn't been linked into its leader's sibling list at this point.
1642 if (event
->group_leader
!= event
) {
1643 n
= collect_events(event
->group_leader
, ppmu
->n_counter
- 1,
1644 ctrs
, events
, cflags
);
1651 if (check_excludes(ctrs
, cflags
, n
, 1))
1654 cpuhw
= &get_cpu_var(cpu_hw_events
);
1655 err
= power_check_constraints(cpuhw
, events
, cflags
, n
+ 1);
1657 if (has_branch_stack(event
)) {
1658 cpuhw
->bhrb_filter
= ppmu
->bhrb_filter_map(
1659 event
->attr
.branch_sample_type
);
1661 if(cpuhw
->bhrb_filter
== -1)
1665 put_cpu_var(cpu_hw_events
);
1669 event
->hw
.config
= events
[n
];
1670 event
->hw
.event_base
= cflags
[n
];
1671 event
->hw
.last_period
= event
->hw
.sample_period
;
1672 local64_set(&event
->hw
.period_left
, event
->hw
.last_period
);
1675 * For EBB events we just context switch the PMC value, we don't do any
1676 * of the sample_period logic. We use hw.prev_count for this.
1678 if (is_ebb_event(event
))
1679 local64_set(&event
->hw
.prev_count
, 0);
1682 * See if we need to reserve the PMU.
1683 * If no events are currently in use, then we have to take a
1684 * mutex to ensure that we don't race with another task doing
1685 * reserve_pmc_hardware or release_pmc_hardware.
1688 if (!atomic_inc_not_zero(&num_events
)) {
1689 mutex_lock(&pmc_reserve_mutex
);
1690 if (atomic_read(&num_events
) == 0 &&
1691 reserve_pmc_hardware(perf_event_interrupt
))
1694 atomic_inc(&num_events
);
1695 mutex_unlock(&pmc_reserve_mutex
);
1697 event
->destroy
= hw_perf_event_destroy
;
1702 static int power_pmu_event_idx(struct perf_event
*event
)
1704 return event
->hw
.idx
;
1707 ssize_t
power_events_sysfs_show(struct device
*dev
,
1708 struct device_attribute
*attr
, char *page
)
1710 struct perf_pmu_events_attr
*pmu_attr
;
1712 pmu_attr
= container_of(attr
, struct perf_pmu_events_attr
, attr
);
1714 return sprintf(page
, "event=0x%02llx\n", pmu_attr
->id
);
1717 struct pmu power_pmu
= {
1718 .pmu_enable
= power_pmu_enable
,
1719 .pmu_disable
= power_pmu_disable
,
1720 .event_init
= power_pmu_event_init
,
1721 .add
= power_pmu_add
,
1722 .del
= power_pmu_del
,
1723 .start
= power_pmu_start
,
1724 .stop
= power_pmu_stop
,
1725 .read
= power_pmu_read
,
1726 .start_txn
= power_pmu_start_txn
,
1727 .cancel_txn
= power_pmu_cancel_txn
,
1728 .commit_txn
= power_pmu_commit_txn
,
1729 .event_idx
= power_pmu_event_idx
,
1730 .flush_branch_stack
= power_pmu_flush_branch_stack
,
1734 * A counter has overflowed; update its count and record
1735 * things if requested. Note that interrupts are hard-disabled
1736 * here so there is no possibility of being interrupted.
1738 static void record_and_restart(struct perf_event
*event
, unsigned long val
,
1739 struct pt_regs
*regs
)
1741 u64 period
= event
->hw
.sample_period
;
1742 s64 prev
, delta
, left
;
1745 if (event
->hw
.state
& PERF_HES_STOPPED
) {
1746 write_pmc(event
->hw
.idx
, 0);
1750 /* we don't have to worry about interrupts here */
1751 prev
= local64_read(&event
->hw
.prev_count
);
1752 delta
= check_and_compute_delta(prev
, val
);
1753 local64_add(delta
, &event
->count
);
1756 * See if the total period for this event has expired,
1757 * and update for the next period.
1760 left
= local64_read(&event
->hw
.period_left
) - delta
;
1768 record
= siar_valid(regs
);
1769 event
->hw
.last_period
= event
->hw
.sample_period
;
1771 if (left
< 0x80000000LL
)
1772 val
= 0x80000000LL
- left
;
1775 write_pmc(event
->hw
.idx
, val
);
1776 local64_set(&event
->hw
.prev_count
, val
);
1777 local64_set(&event
->hw
.period_left
, left
);
1778 perf_event_update_userpage(event
);
1781 * Finally record data if requested.
1784 struct perf_sample_data data
;
1786 perf_sample_data_init(&data
, ~0ULL, event
->hw
.last_period
);
1788 if (event
->attr
.sample_type
& PERF_SAMPLE_ADDR
)
1789 perf_get_data_addr(regs
, &data
.addr
);
1791 if (event
->attr
.sample_type
& PERF_SAMPLE_BRANCH_STACK
) {
1792 struct cpu_hw_events
*cpuhw
;
1793 cpuhw
= &__get_cpu_var(cpu_hw_events
);
1794 power_pmu_bhrb_read(cpuhw
);
1795 data
.br_stack
= &cpuhw
->bhrb_stack
;
1798 if (perf_event_overflow(event
, &data
, regs
))
1799 power_pmu_stop(event
, 0);
1804 * Called from generic code to get the misc flags (i.e. processor mode)
1807 unsigned long perf_misc_flags(struct pt_regs
*regs
)
1809 u32 flags
= perf_get_misc_flags(regs
);
1813 return user_mode(regs
) ? PERF_RECORD_MISC_USER
:
1814 PERF_RECORD_MISC_KERNEL
;
1818 * Called from generic code to get the instruction pointer
1821 unsigned long perf_instruction_pointer(struct pt_regs
*regs
)
1823 bool use_siar
= regs_use_siar(regs
);
1825 if (use_siar
&& siar_valid(regs
))
1826 return mfspr(SPRN_SIAR
) + perf_ip_adjust(regs
);
1828 return 0; // no valid instruction pointer
1833 static bool pmc_overflow_power7(unsigned long val
)
1836 * Events on POWER7 can roll back if a speculative event doesn't
1837 * eventually complete. Unfortunately in some rare cases they will
1838 * raise a performance monitor exception. We need to catch this to
1839 * ensure we reset the PMC. In all cases the PMC will be 256 or less
1840 * cycles from overflow.
1842 * We only do this if the first pass fails to find any overflowing
1843 * PMCs because a user might set a period of less than 256 and we
1844 * don't want to mistakenly reset them.
1846 if ((0x80000000 - val
) <= 256)
1852 static bool pmc_overflow(unsigned long val
)
1861 * Performance monitor interrupt stuff
1863 static void perf_event_interrupt(struct pt_regs
*regs
)
1866 struct cpu_hw_events
*cpuhw
= &__get_cpu_var(cpu_hw_events
);
1867 struct perf_event
*event
;
1868 unsigned long val
[8];
1872 if (cpuhw
->n_limited
)
1873 freeze_limited_counters(cpuhw
, mfspr(SPRN_PMC5
),
1876 perf_read_regs(regs
);
1878 nmi
= perf_intr_is_nmi(regs
);
1884 /* Read all the PMCs since we'll need them a bunch of times */
1885 for (i
= 0; i
< ppmu
->n_counter
; ++i
)
1886 val
[i
] = read_pmc(i
+ 1);
1888 /* Try to find what caused the IRQ */
1890 for (i
= 0; i
< ppmu
->n_counter
; ++i
) {
1891 if (!pmc_overflow(val
[i
]))
1893 if (is_limited_pmc(i
+ 1))
1894 continue; /* these won't generate IRQs */
1896 * We've found one that's overflowed. For active
1897 * counters we need to log this. For inactive
1898 * counters, we need to reset it anyway
1902 for (j
= 0; j
< cpuhw
->n_events
; ++j
) {
1903 event
= cpuhw
->event
[j
];
1904 if (event
->hw
.idx
== (i
+ 1)) {
1906 record_and_restart(event
, val
[i
], regs
);
1911 /* reset non active counters that have overflowed */
1912 write_pmc(i
+ 1, 0);
1914 if (!found
&& pvr_version_is(PVR_POWER7
)) {
1915 /* check active counters for special buggy p7 overflow */
1916 for (i
= 0; i
< cpuhw
->n_events
; ++i
) {
1917 event
= cpuhw
->event
[i
];
1918 if (!event
->hw
.idx
|| is_limited_pmc(event
->hw
.idx
))
1920 if (pmc_overflow_power7(val
[event
->hw
.idx
- 1])) {
1921 /* event has overflowed in a buggy way*/
1923 record_and_restart(event
,
1924 val
[event
->hw
.idx
- 1],
1929 if (!found
&& !nmi
&& printk_ratelimit())
1930 printk(KERN_WARNING
"Can't find PMC that caused IRQ\n");
1933 * Reset MMCR0 to its normal value. This will set PMXE and
1934 * clear FC (freeze counters) and PMAO (perf mon alert occurred)
1935 * and thus allow interrupts to occur again.
1936 * XXX might want to use MSR.PM to keep the events frozen until
1937 * we get back out of this interrupt.
1939 write_mmcr0(cpuhw
, cpuhw
->mmcr
[0]);
1947 static void power_pmu_setup(int cpu
)
1949 struct cpu_hw_events
*cpuhw
= &per_cpu(cpu_hw_events
, cpu
);
1953 memset(cpuhw
, 0, sizeof(*cpuhw
));
1954 cpuhw
->mmcr
[0] = MMCR0_FC
;
1958 power_pmu_notifier(struct notifier_block
*self
, unsigned long action
, void *hcpu
)
1960 unsigned int cpu
= (long)hcpu
;
1962 switch (action
& ~CPU_TASKS_FROZEN
) {
1963 case CPU_UP_PREPARE
:
1964 power_pmu_setup(cpu
);
1974 int register_power_pmu(struct power_pmu
*pmu
)
1977 return -EBUSY
; /* something's already registered */
1980 pr_info("%s performance monitor hardware support registered\n",
1983 power_pmu
.attr_groups
= ppmu
->attr_groups
;
1987 * Use FCHV to ignore kernel events if MSR.HV is set.
1989 if (mfmsr() & MSR_HV
)
1990 freeze_events_kernel
= MMCR0_FCHV
;
1991 #endif /* CONFIG_PPC64 */
1993 perf_pmu_register(&power_pmu
, "cpu", PERF_TYPE_RAW
);
1994 perf_cpu_notifier(power_pmu_notifier
);