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x86/efi: Enforce CONFIG_RELOCATABLE for EFI boot stub
[linux/fpc-iii.git] / arch / sparc / mm / init_64.c
blobb26015f49c0dfb3dd2a22c0c0e04724047e72a34
1 /*
2 * arch/sparc64/mm/init.c
3 *
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7
8 #include <linux/module.h>
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/string.h>
12 #include <linux/init.h>
13 #include <linux/bootmem.h>
14 #include <linux/mm.h>
15 #include <linux/hugetlb.h>
16 #include <linux/initrd.h>
17 #include <linux/swap.h>
18 #include <linux/pagemap.h>
19 #include <linux/poison.h>
20 #include <linux/fs.h>
21 #include <linux/seq_file.h>
22 #include <linux/kprobes.h>
23 #include <linux/cache.h>
24 #include <linux/sort.h>
25 #include <linux/percpu.h>
26 #include <linux/memblock.h>
27 #include <linux/mmzone.h>
28 #include <linux/gfp.h>
29
30 #include <asm/head.h>
31 #include <asm/page.h>
32 #include <asm/pgalloc.h>
33 #include <asm/pgtable.h>
34 #include <asm/oplib.h>
35 #include <asm/iommu.h>
36 #include <asm/io.h>
37 #include <asm/uaccess.h>
38 #include <asm/mmu_context.h>
39 #include <asm/tlbflush.h>
40 #include <asm/dma.h>
41 #include <asm/starfire.h>
42 #include <asm/tlb.h>
43 #include <asm/spitfire.h>
44 #include <asm/sections.h>
45 #include <asm/tsb.h>
46 #include <asm/hypervisor.h>
47 #include <asm/prom.h>
48 #include <asm/mdesc.h>
49 #include <asm/cpudata.h>
50 #include <asm/irq.h>
51
52 #include "init_64.h"
53
54 unsigned long kern_linear_pte_xor[4] __read_mostly;
55
56 /* A bitmap, two bits for every 256MB of physical memory. These two
57 * bits determine what page size we use for kernel linear
58 * translations. They form an index into kern_linear_pte_xor[]. The
59 * value in the indexed slot is XOR'd with the TLB miss virtual
60 * address to form the resulting TTE. The mapping is:
61 *
62 * 0 ==> 4MB
63 * 1 ==> 256MB
64 * 2 ==> 2GB
65 * 3 ==> 16GB
66 *
67 * All sun4v chips support 256MB pages. Only SPARC-T4 and later
68 * support 2GB pages, and hopefully future cpus will support the 16GB
69 * pages as well. For slots 2 and 3, we encode a 256MB TTE xor there
70 * if these larger page sizes are not supported by the cpu.
71 *
72 * It would be nice to determine this from the machine description
73 * 'cpu' properties, but we need to have this table setup before the
74 * MDESC is initialized.
75 */
76 unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)];
77
78 #ifndef CONFIG_DEBUG_PAGEALLOC
79 /* A special kernel TSB for 4MB, 256MB, 2GB and 16GB linear mappings.
80 * Space is allocated for this right after the trap table in
81 * arch/sparc64/kernel/head.S
82 */
83 extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
84 #endif
85
86 static unsigned long cpu_pgsz_mask;
87
88 #define MAX_BANKS 32
89
90 static struct linux_prom64_registers pavail[MAX_BANKS];
91 static int pavail_ents;
92
93 static int cmp_p64(const void *a, const void *b)
94 {
95 const struct linux_prom64_registers *x = a, *y = b;
96
97 if (x->phys_addr > y->phys_addr)
98 return 1;
99 if (x->phys_addr < y->phys_addr)
100 return -1;
101 return 0;
102 }
103
104 static void __init read_obp_memory(const char *property,
105 struct linux_prom64_registers *regs,
106 int *num_ents)
107 {
108 phandle node = prom_finddevice("/memory");
109 int prop_size = prom_getproplen(node, property);
110 int ents, ret, i;
111
112 ents = prop_size / sizeof(struct linux_prom64_registers);
113 if (ents > MAX_BANKS) {
114 prom_printf("The machine has more %s property entries than "
115 "this kernel can support (%d).\n",
116 property, MAX_BANKS);
117 prom_halt();
118 }
119
120 ret = prom_getproperty(node, property, (char *) regs, prop_size);
121 if (ret == -1) {
122 prom_printf("Couldn't get %s property from /memory.\n",
123 property);
124 prom_halt();
125 }
126
127 /* Sanitize what we got from the firmware, by page aligning
128 * everything.
129 */
130 for (i = 0; i < ents; i++) {
131 unsigned long base, size;
132
133 base = regs[i].phys_addr;
134 size = regs[i].reg_size;
135
136 size &= PAGE_MASK;
137 if (base & ~PAGE_MASK) {
138 unsigned long new_base = PAGE_ALIGN(base);
139
140 size -= new_base - base;
141 if ((long) size < 0L)
142 size = 0UL;
143 base = new_base;
144 }
145 if (size == 0UL) {
146 /* If it is empty, simply get rid of it.
147 * This simplifies the logic of the other
148 * functions that process these arrays.
149 */
150 memmove(&regs[i], &regs[i + 1],
151 (ents - i - 1) * sizeof(regs[0]));
152 i--;
153 ents--;
154 continue;
155 }
156 regs[i].phys_addr = base;
157 regs[i].reg_size = size;
158 }
159
160 *num_ents = ents;
161
162 sort(regs, ents, sizeof(struct linux_prom64_registers),
163 cmp_p64, NULL);
164 }
165
166 unsigned long sparc64_valid_addr_bitmap[VALID_ADDR_BITMAP_BYTES /
167 sizeof(unsigned long)];
168 EXPORT_SYMBOL(sparc64_valid_addr_bitmap);
169
170 /* Kernel physical address base and size in bytes. */
171 unsigned long kern_base __read_mostly;
172 unsigned long kern_size __read_mostly;
173
174 /* Initial ramdisk setup */
175 extern unsigned long sparc_ramdisk_image64;
176 extern unsigned int sparc_ramdisk_image;
177 extern unsigned int sparc_ramdisk_size;
178
179 struct page *mem_map_zero __read_mostly;
180 EXPORT_SYMBOL(mem_map_zero);
181
182 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
183
184 unsigned long sparc64_kern_pri_context __read_mostly;
185 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
186 unsigned long sparc64_kern_sec_context __read_mostly;
187
188 int num_kernel_image_mappings;
189
190 #ifdef CONFIG_DEBUG_DCFLUSH
191 atomic_t dcpage_flushes = ATOMIC_INIT(0);
192 #ifdef CONFIG_SMP
193 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
194 #endif
195 #endif
196
197 inline void flush_dcache_page_impl(struct page *page)
198 {
199 BUG_ON(tlb_type == hypervisor);
200 #ifdef CONFIG_DEBUG_DCFLUSH
201 atomic_inc(&dcpage_flushes);
202 #endif
203
204 #ifdef DCACHE_ALIASING_POSSIBLE
205 __flush_dcache_page(page_address(page),
206 ((tlb_type == spitfire) &&
207 page_mapping(page) != NULL));
208 #else
209 if (page_mapping(page) != NULL &&
210 tlb_type == spitfire)
211 __flush_icache_page(__pa(page_address(page)));
212 #endif
213 }
214
215 #define PG_dcache_dirty PG_arch_1
216 #define PG_dcache_cpu_shift 32UL
217 #define PG_dcache_cpu_mask \
218 ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
219
220 #define dcache_dirty_cpu(page) \
221 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
222
223 static inline void set_dcache_dirty(struct page *page, int this_cpu)
224 {
225 unsigned long mask = this_cpu;
226 unsigned long non_cpu_bits;
227
228 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
229 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
230
231 __asm__ __volatile__("1:\n\t"
232 "ldx [%2], %%g7\n\t"
233 "and %%g7, %1, %%g1\n\t"
234 "or %%g1, %0, %%g1\n\t"
235 "casx [%2], %%g7, %%g1\n\t"
236 "cmp %%g7, %%g1\n\t"
237 "bne,pn %%xcc, 1b\n\t"
238 " nop"
239 : /* no outputs */
240 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
241 : "g1", "g7");
242 }
243
244 static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
245 {
246 unsigned long mask = (1UL << PG_dcache_dirty);
247
248 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
249 "1:\n\t"
250 "ldx [%2], %%g7\n\t"
251 "srlx %%g7, %4, %%g1\n\t"
252 "and %%g1, %3, %%g1\n\t"
253 "cmp %%g1, %0\n\t"
254 "bne,pn %%icc, 2f\n\t"
255 " andn %%g7, %1, %%g1\n\t"
256 "casx [%2], %%g7, %%g1\n\t"
257 "cmp %%g7, %%g1\n\t"
258 "bne,pn %%xcc, 1b\n\t"
259 " nop\n"
260 "2:"
261 : /* no outputs */
262 : "r" (cpu), "r" (mask), "r" (&page->flags),
263 "i" (PG_dcache_cpu_mask),
264 "i" (PG_dcache_cpu_shift)
265 : "g1", "g7");
266 }
267
268 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
269 {
270 unsigned long tsb_addr = (unsigned long) ent;
271
272 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
273 tsb_addr = __pa(tsb_addr);
274
275 __tsb_insert(tsb_addr, tag, pte);
276 }
277
278 unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
279
280 static void flush_dcache(unsigned long pfn)
281 {
282 struct page *page;
283
284 page = pfn_to_page(pfn);
285 if (page) {
286 unsigned long pg_flags;
287
288 pg_flags = page->flags;
289 if (pg_flags & (1UL << PG_dcache_dirty)) {
290 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
291 PG_dcache_cpu_mask);
292 int this_cpu = get_cpu();
293
294 /* This is just to optimize away some function calls
295 * in the SMP case.
296 */
297 if (cpu == this_cpu)
298 flush_dcache_page_impl(page);
299 else
300 smp_flush_dcache_page_impl(page, cpu);
301
302 clear_dcache_dirty_cpu(page, cpu);
303
304 put_cpu();
305 }
306 }
307 }
308
309 /* mm->context.lock must be held */
310 static void __update_mmu_tsb_insert(struct mm_struct *mm, unsigned long tsb_index,
311 unsigned long tsb_hash_shift, unsigned long address,
312 unsigned long tte)
313 {
314 struct tsb *tsb = mm->context.tsb_block[tsb_index].tsb;
315 unsigned long tag;
316
317 if (unlikely(!tsb))
318 return;
319
320 tsb += ((address >> tsb_hash_shift) &
321 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
322 tag = (address >> 22UL);
323 tsb_insert(tsb, tag, tte);
324 }
325
326 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
327 static inline bool is_hugetlb_pte(pte_t pte)
328 {
329 if ((tlb_type == hypervisor &&
330 (pte_val(pte) & _PAGE_SZALL_4V) == _PAGE_SZHUGE_4V) ||
331 (tlb_type != hypervisor &&
332 (pte_val(pte) & _PAGE_SZALL_4U) == _PAGE_SZHUGE_4U))
333 return true;
334 return false;
335 }
336 #endif
337
338 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
339 {
340 struct mm_struct *mm;
341 unsigned long flags;
342 pte_t pte = *ptep;
343
344 if (tlb_type != hypervisor) {
345 unsigned long pfn = pte_pfn(pte);
346
347 if (pfn_valid(pfn))
348 flush_dcache(pfn);
349 }
350
351 mm = vma->vm_mm;
352
353 /* Don't insert a non-valid PTE into the TSB, we'll deadlock. */
354 if (!pte_accessible(mm, pte))
355 return;
356
357 spin_lock_irqsave(&mm->context.lock, flags);
358
359 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
360 if (mm->context.huge_pte_count && is_hugetlb_pte(pte))
361 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, HPAGE_SHIFT,
362 address, pte_val(pte));
363 else
364 #endif
365 __update_mmu_tsb_insert(mm, MM_TSB_BASE, PAGE_SHIFT,
366 address, pte_val(pte));
367
368 spin_unlock_irqrestore(&mm->context.lock, flags);
369 }
370
371 void flush_dcache_page(struct page *page)
372 {
373 struct address_space *mapping;
374 int this_cpu;
375
376 if (tlb_type == hypervisor)
377 return;
378
379 /* Do not bother with the expensive D-cache flush if it
380 * is merely the zero page. The 'bigcore' testcase in GDB
381 * causes this case to run millions of times.
382 */
383 if (page == ZERO_PAGE(0))
384 return;
385
386 this_cpu = get_cpu();
387
388 mapping = page_mapping(page);
389 if (mapping && !mapping_mapped(mapping)) {
390 int dirty = test_bit(PG_dcache_dirty, &page->flags);
391 if (dirty) {
392 int dirty_cpu = dcache_dirty_cpu(page);
393
394 if (dirty_cpu == this_cpu)
395 goto out;
396 smp_flush_dcache_page_impl(page, dirty_cpu);
397 }
398 set_dcache_dirty(page, this_cpu);
399 } else {
400 /* We could delay the flush for the !page_mapping
401 * case too. But that case is for exec env/arg
402 * pages and those are %99 certainly going to get
403 * faulted into the tlb (and thus flushed) anyways.
404 */
405 flush_dcache_page_impl(page);
406 }
407
408 out:
409 put_cpu();
410 }
411 EXPORT_SYMBOL(flush_dcache_page);
412
413 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
414 {
415 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
416 if (tlb_type == spitfire) {
417 unsigned long kaddr;
418
419 /* This code only runs on Spitfire cpus so this is
420 * why we can assume _PAGE_PADDR_4U.
421 */
422 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
423 unsigned long paddr, mask = _PAGE_PADDR_4U;
424
425 if (kaddr >= PAGE_OFFSET)
426 paddr = kaddr & mask;
427 else {
428 pgd_t *pgdp = pgd_offset_k(kaddr);
429 pud_t *pudp = pud_offset(pgdp, kaddr);
430 pmd_t *pmdp = pmd_offset(pudp, kaddr);
431 pte_t *ptep = pte_offset_kernel(pmdp, kaddr);
432
433 paddr = pte_val(*ptep) & mask;
434 }
435 __flush_icache_page(paddr);
436 }
437 }
438 }
439 EXPORT_SYMBOL(flush_icache_range);
440
441 void mmu_info(struct seq_file *m)
442 {
443 static const char *pgsz_strings[] = {
444 "8K", "64K", "512K", "4MB", "32MB",
445 "256MB", "2GB", "16GB",
446 };
447 int i, printed;
448
449 if (tlb_type == cheetah)
450 seq_printf(m, "MMU Type\t: Cheetah\n");
451 else if (tlb_type == cheetah_plus)
452 seq_printf(m, "MMU Type\t: Cheetah+\n");
453 else if (tlb_type == spitfire)
454 seq_printf(m, "MMU Type\t: Spitfire\n");
455 else if (tlb_type == hypervisor)
456 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
457 else
458 seq_printf(m, "MMU Type\t: ???\n");
459
460 seq_printf(m, "MMU PGSZs\t: ");
461 printed = 0;
462 for (i = 0; i < ARRAY_SIZE(pgsz_strings); i++) {
463 if (cpu_pgsz_mask & (1UL << i)) {
464 seq_printf(m, "%s%s",
465 printed ? "," : "", pgsz_strings[i]);
466 printed++;
467 }
468 }
469 seq_putc(m, '\n');
470
471 #ifdef CONFIG_DEBUG_DCFLUSH
472 seq_printf(m, "DCPageFlushes\t: %d\n",
473 atomic_read(&dcpage_flushes));
474 #ifdef CONFIG_SMP
475 seq_printf(m, "DCPageFlushesXC\t: %d\n",
476 atomic_read(&dcpage_flushes_xcall));
477 #endif /* CONFIG_SMP */
478 #endif /* CONFIG_DEBUG_DCFLUSH */
479 }
480
481 struct linux_prom_translation prom_trans[512] __read_mostly;
482 unsigned int prom_trans_ents __read_mostly;
483
484 unsigned long kern_locked_tte_data;
485
486 /* The obp translations are saved based on 8k pagesize, since obp can
487 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
488 * HI_OBP_ADDRESS range are handled in ktlb.S.
489 */
490 static inline int in_obp_range(unsigned long vaddr)
491 {
492 return (vaddr >= LOW_OBP_ADDRESS &&
493 vaddr < HI_OBP_ADDRESS);
494 }
495
496 static int cmp_ptrans(const void *a, const void *b)
497 {
498 const struct linux_prom_translation *x = a, *y = b;
499
500 if (x->virt > y->virt)
501 return 1;
502 if (x->virt < y->virt)
503 return -1;
504 return 0;
505 }
506
507 /* Read OBP translations property into 'prom_trans[]'. */
508 static void __init read_obp_translations(void)
509 {
510 int n, node, ents, first, last, i;
511
512 node = prom_finddevice("/virtual-memory");
513 n = prom_getproplen(node, "translations");
514 if (unlikely(n == 0 || n == -1)) {
515 prom_printf("prom_mappings: Couldn't get size.\n");
516 prom_halt();
517 }
518 if (unlikely(n > sizeof(prom_trans))) {
519 prom_printf("prom_mappings: Size %d is too big.\n", n);
520 prom_halt();
521 }
522
523 if ((n = prom_getproperty(node, "translations",
524 (char *)&prom_trans[0],
525 sizeof(prom_trans))) == -1) {
526 prom_printf("prom_mappings: Couldn't get property.\n");
527 prom_halt();
528 }
529
530 n = n / sizeof(struct linux_prom_translation);
531
532 ents = n;
533
534 sort(prom_trans, ents, sizeof(struct linux_prom_translation),
535 cmp_ptrans, NULL);
536
537 /* Now kick out all the non-OBP entries. */
538 for (i = 0; i < ents; i++) {
539 if (in_obp_range(prom_trans[i].virt))
540 break;
541 }
542 first = i;
543 for (; i < ents; i++) {
544 if (!in_obp_range(prom_trans[i].virt))
545 break;
546 }
547 last = i;
548
549 for (i = 0; i < (last - first); i++) {
550 struct linux_prom_translation *src = &prom_trans[i + first];
551 struct linux_prom_translation *dest = &prom_trans[i];
552
553 *dest = *src;
554 }
555 for (; i < ents; i++) {
556 struct linux_prom_translation *dest = &prom_trans[i];
557 dest->virt = dest->size = dest->data = 0x0UL;
558 }
559
560 prom_trans_ents = last - first;
561
562 if (tlb_type == spitfire) {
563 /* Clear diag TTE bits. */
564 for (i = 0; i < prom_trans_ents; i++)
565 prom_trans[i].data &= ~0x0003fe0000000000UL;
566 }
567
568 /* Force execute bit on. */
569 for (i = 0; i < prom_trans_ents; i++)
570 prom_trans[i].data |= (tlb_type == hypervisor ?
571 _PAGE_EXEC_4V : _PAGE_EXEC_4U);
572 }
573
574 static void __init hypervisor_tlb_lock(unsigned long vaddr,
575 unsigned long pte,
576 unsigned long mmu)
577 {
578 unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);
579
580 if (ret != 0) {
581 prom_printf("hypervisor_tlb_lock[%lx:%x:%lx:%lx]: "
582 "errors with %lx\n", vaddr, 0, pte, mmu, ret);
583 prom_halt();
584 }
585 }
586
587 static unsigned long kern_large_tte(unsigned long paddr);
588
589 static void __init remap_kernel(void)
590 {
591 unsigned long phys_page, tte_vaddr, tte_data;
592 int i, tlb_ent = sparc64_highest_locked_tlbent();
593
594 tte_vaddr = (unsigned long) KERNBASE;
595 phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
596 tte_data = kern_large_tte(phys_page);
597
598 kern_locked_tte_data = tte_data;
599
600 /* Now lock us into the TLBs via Hypervisor or OBP. */
601 if (tlb_type == hypervisor) {
602 for (i = 0; i < num_kernel_image_mappings; i++) {
603 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
604 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
605 tte_vaddr += 0x400000;
606 tte_data += 0x400000;
607 }
608 } else {
609 for (i = 0; i < num_kernel_image_mappings; i++) {
610 prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr);
611 prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr);
612 tte_vaddr += 0x400000;
613 tte_data += 0x400000;
614 }
615 sparc64_highest_unlocked_tlb_ent = tlb_ent - i;
616 }
617 if (tlb_type == cheetah_plus) {
618 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
619 CTX_CHEETAH_PLUS_NUC);
620 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
621 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
622 }
623 }
624
625
626 static void __init inherit_prom_mappings(void)
627 {
628 /* Now fixup OBP's idea about where we really are mapped. */
629 printk("Remapping the kernel... ");
630 remap_kernel();
631 printk("done.\n");
632 }
633
634 void prom_world(int enter)
635 {
636 if (!enter)
637 set_fs(get_fs());
638
639 __asm__ __volatile__("flushw");
640 }
641
642 void __flush_dcache_range(unsigned long start, unsigned long end)
643 {
644 unsigned long va;
645
646 if (tlb_type == spitfire) {
647 int n = 0;
648
649 for (va = start; va < end; va += 32) {
650 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
651 if (++n >= 512)
652 break;
653 }
654 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
655 start = __pa(start);
656 end = __pa(end);
657 for (va = start; va < end; va += 32)
658 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
659 "membar #Sync"
660 : /* no outputs */
661 : "r" (va),
662 "i" (ASI_DCACHE_INVALIDATE));
663 }
664 }
665 EXPORT_SYMBOL(__flush_dcache_range);
666
667 /* get_new_mmu_context() uses "cache + 1". */
668 DEFINE_SPINLOCK(ctx_alloc_lock);
669 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
670 #define MAX_CTX_NR (1UL << CTX_NR_BITS)
671 #define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR)
672 DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
673
674 /* Caller does TLB context flushing on local CPU if necessary.
675 * The caller also ensures that CTX_VALID(mm->context) is false.
676 *
677 * We must be careful about boundary cases so that we never
678 * let the user have CTX 0 (nucleus) or we ever use a CTX
679 * version of zero (and thus NO_CONTEXT would not be caught
680 * by version mis-match tests in mmu_context.h).
681 *
682 * Always invoked with interrupts disabled.
683 */
684 void get_new_mmu_context(struct mm_struct *mm)
685 {
686 unsigned long ctx, new_ctx;
687 unsigned long orig_pgsz_bits;
688 int new_version;
689
690 spin_lock(&ctx_alloc_lock);
691 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
692 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
693 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
694 new_version = 0;
695 if (new_ctx >= (1 << CTX_NR_BITS)) {
696 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
697 if (new_ctx >= ctx) {
698 int i;
699 new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
700 CTX_FIRST_VERSION;
701 if (new_ctx == 1)
702 new_ctx = CTX_FIRST_VERSION;
703
704 /* Don't call memset, for 16 entries that's just
705 * plain silly...
706 */
707 mmu_context_bmap[0] = 3;
708 mmu_context_bmap[1] = 0;
709 mmu_context_bmap[2] = 0;
710 mmu_context_bmap[3] = 0;
711 for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
712 mmu_context_bmap[i + 0] = 0;
713 mmu_context_bmap[i + 1] = 0;
714 mmu_context_bmap[i + 2] = 0;
715 mmu_context_bmap[i + 3] = 0;
716 }
717 new_version = 1;
718 goto out;
719 }
720 }
721 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
722 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
723 out:
724 tlb_context_cache = new_ctx;
725 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
726 spin_unlock(&ctx_alloc_lock);
727
728 if (unlikely(new_version))
729 smp_new_mmu_context_version();
730 }
731
732 static int numa_enabled = 1;
733 static int numa_debug;
734
735 static int __init early_numa(char *p)
736 {
737 if (!p)
738 return 0;
739
740 if (strstr(p, "off"))
741 numa_enabled = 0;
742
743 if (strstr(p, "debug"))
744 numa_debug = 1;
745
746 return 0;
747 }
748 early_param("numa", early_numa);
749
750 #define numadbg(f, a...) \
751 do { if (numa_debug) \
752 printk(KERN_INFO f, ## a); \
753 } while (0)
754
755 static void __init find_ramdisk(unsigned long phys_base)
756 {
757 #ifdef CONFIG_BLK_DEV_INITRD
758 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
759 unsigned long ramdisk_image;
760
761 /* Older versions of the bootloader only supported a
762 * 32-bit physical address for the ramdisk image
763 * location, stored at sparc_ramdisk_image. Newer
764 * SILO versions set sparc_ramdisk_image to zero and
765 * provide a full 64-bit physical address at
766 * sparc_ramdisk_image64.
767 */
768 ramdisk_image = sparc_ramdisk_image;
769 if (!ramdisk_image)
770 ramdisk_image = sparc_ramdisk_image64;
771
772 /* Another bootloader quirk. The bootloader normalizes
773 * the physical address to KERNBASE, so we have to
774 * factor that back out and add in the lowest valid
775 * physical page address to get the true physical address.
776 */
777 ramdisk_image -= KERNBASE;
778 ramdisk_image += phys_base;
779
780 numadbg("Found ramdisk at physical address 0x%lx, size %u\n",
781 ramdisk_image, sparc_ramdisk_size);
782
783 initrd_start = ramdisk_image;
784 initrd_end = ramdisk_image + sparc_ramdisk_size;
785
786 memblock_reserve(initrd_start, sparc_ramdisk_size);
787
788 initrd_start += PAGE_OFFSET;
789 initrd_end += PAGE_OFFSET;
790 }
791 #endif
792 }
793
794 struct node_mem_mask {
795 unsigned long mask;
796 unsigned long val;
797 };
798 static struct node_mem_mask node_masks[MAX_NUMNODES];
799 static int num_node_masks;
800
801 int numa_cpu_lookup_table[NR_CPUS];
802 cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES];
803
804 #ifdef CONFIG_NEED_MULTIPLE_NODES
805
806 struct mdesc_mblock {
807 u64 base;
808 u64 size;
809 u64 offset; /* RA-to-PA */
810 };
811 static struct mdesc_mblock *mblocks;
812 static int num_mblocks;
813
814 static unsigned long ra_to_pa(unsigned long addr)
815 {
816 int i;
817
818 for (i = 0; i < num_mblocks; i++) {
819 struct mdesc_mblock *m = &mblocks[i];
820
821 if (addr >= m->base &&
822 addr < (m->base + m->size)) {
823 addr += m->offset;
824 break;
825 }
826 }
827 return addr;
828 }
829
830 static int find_node(unsigned long addr)
831 {
832 int i;
833
834 addr = ra_to_pa(addr);
835 for (i = 0; i < num_node_masks; i++) {
836 struct node_mem_mask *p = &node_masks[i];
837
838 if ((addr & p->mask) == p->val)
839 return i;
840 }
841 return -1;
842 }
843
844 static u64 memblock_nid_range(u64 start, u64 end, int *nid)
845 {
846 *nid = find_node(start);
847 start += PAGE_SIZE;
848 while (start < end) {
849 int n = find_node(start);
850
851 if (n != *nid)
852 break;
853 start += PAGE_SIZE;
854 }
855
856 if (start > end)
857 start = end;
858
859 return start;
860 }
861 #endif
862
863 /* This must be invoked after performing all of the necessary
864 * memblock_set_node() calls for 'nid'. We need to be able to get
865 * correct data from get_pfn_range_for_nid().
866 */
867 static void __init allocate_node_data(int nid)
868 {
869 struct pglist_data *p;
870 unsigned long start_pfn, end_pfn;
871 #ifdef CONFIG_NEED_MULTIPLE_NODES
872 unsigned long paddr;
873
874 paddr = memblock_alloc_try_nid(sizeof(struct pglist_data), SMP_CACHE_BYTES, nid);
875 if (!paddr) {
876 prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid);
877 prom_halt();
878 }
879 NODE_DATA(nid) = __va(paddr);
880 memset(NODE_DATA(nid), 0, sizeof(struct pglist_data));
881
882 NODE_DATA(nid)->node_id = nid;
883 #endif
884
885 p = NODE_DATA(nid);
886
887 get_pfn_range_for_nid(nid, &start_pfn, &end_pfn);
888 p->node_start_pfn = start_pfn;
889 p->node_spanned_pages = end_pfn - start_pfn;
890 }
891
892 static void init_node_masks_nonnuma(void)
893 {
894 int i;
895
896 numadbg("Initializing tables for non-numa.\n");
897
898 node_masks[0].mask = node_masks[0].val = 0;
899 num_node_masks = 1;
900
901 for (i = 0; i < NR_CPUS; i++)
902 numa_cpu_lookup_table[i] = 0;
903
904 cpumask_setall(&numa_cpumask_lookup_table[0]);
905 }
906
907 #ifdef CONFIG_NEED_MULTIPLE_NODES
908 struct pglist_data *node_data[MAX_NUMNODES];
909
910 EXPORT_SYMBOL(numa_cpu_lookup_table);
911 EXPORT_SYMBOL(numa_cpumask_lookup_table);
912 EXPORT_SYMBOL(node_data);
913
914 struct mdesc_mlgroup {
915 u64 node;
916 u64 latency;
917 u64 match;
918 u64 mask;
919 };
920 static struct mdesc_mlgroup *mlgroups;
921 static int num_mlgroups;
922
923 static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio,
924 u32 cfg_handle)
925 {
926 u64 arc;
927
928 mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) {
929 u64 target = mdesc_arc_target(md, arc);
930 const u64 *val;
931
932 val = mdesc_get_property(md, target,
933 "cfg-handle", NULL);
934 if (val && *val == cfg_handle)
935 return 0;
936 }
937 return -ENODEV;
938 }
939
940 static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp,
941 u32 cfg_handle)
942 {
943 u64 arc, candidate, best_latency = ~(u64)0;
944
945 candidate = MDESC_NODE_NULL;
946 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
947 u64 target = mdesc_arc_target(md, arc);
948 const char *name = mdesc_node_name(md, target);
949 const u64 *val;
950
951 if (strcmp(name, "pio-latency-group"))
952 continue;
953
954 val = mdesc_get_property(md, target, "latency", NULL);
955 if (!val)
956 continue;
957
958 if (*val < best_latency) {
959 candidate = target;
960 best_latency = *val;
961 }
962 }
963
964 if (candidate == MDESC_NODE_NULL)
965 return -ENODEV;
966
967 return scan_pio_for_cfg_handle(md, candidate, cfg_handle);
968 }
969
970 int of_node_to_nid(struct device_node *dp)
971 {
972 const struct linux_prom64_registers *regs;
973 struct mdesc_handle *md;
974 u32 cfg_handle;
975 int count, nid;
976 u64 grp;
977
978 /* This is the right thing to do on currently supported
979 * SUN4U NUMA platforms as well, as the PCI controller does
980 * not sit behind any particular memory controller.
981 */
982 if (!mlgroups)
983 return -1;
984
985 regs = of_get_property(dp, "reg", NULL);
986 if (!regs)
987 return -1;
988
989 cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff;
990
991 md = mdesc_grab();
992
993 count = 0;
994 nid = -1;
995 mdesc_for_each_node_by_name(md, grp, "group") {
996 if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) {
997 nid = count;
998 break;
999 }
1000 count++;
1001 }
1002
1003 mdesc_release(md);
1004
1005 return nid;
1006 }
1007
1008 static void __init add_node_ranges(void)
1009 {
1010 struct memblock_region *reg;
1011
1012 for_each_memblock(memory, reg) {
1013 unsigned long size = reg->size;
1014 unsigned long start, end;
1015
1016 start = reg->base;
1017 end = start + size;
1018 while (start < end) {
1019 unsigned long this_end;
1020 int nid;
1021
1022 this_end = memblock_nid_range(start, end, &nid);
1023
1024 numadbg("Setting memblock NUMA node nid[%d] "
1025 "start[%lx] end[%lx]\n",
1026 nid, start, this_end);
1027
1028 memblock_set_node(start, this_end - start, nid);
1029 start = this_end;
1030 }
1031 }
1032 }
1033
1034 static int __init grab_mlgroups(struct mdesc_handle *md)
1035 {
1036 unsigned long paddr;
1037 int count = 0;
1038 u64 node;
1039
1040 mdesc_for_each_node_by_name(md, node, "memory-latency-group")
1041 count++;
1042 if (!count)
1043 return -ENOENT;
1044
1045 paddr = memblock_alloc(count * sizeof(struct mdesc_mlgroup),
1046 SMP_CACHE_BYTES);
1047 if (!paddr)
1048 return -ENOMEM;
1049
1050 mlgroups = __va(paddr);
1051 num_mlgroups = count;
1052
1053 count = 0;
1054 mdesc_for_each_node_by_name(md, node, "memory-latency-group") {
1055 struct mdesc_mlgroup *m = &mlgroups[count++];
1056 const u64 *val;
1057
1058 m->node = node;
1059
1060 val = mdesc_get_property(md, node, "latency", NULL);
1061 m->latency = *val;
1062 val = mdesc_get_property(md, node, "address-match", NULL);
1063 m->match = *val;
1064 val = mdesc_get_property(md, node, "address-mask", NULL);
1065 m->mask = *val;
1066
1067 numadbg("MLGROUP[%d]: node[%llx] latency[%llx] "
1068 "match[%llx] mask[%llx]\n",
1069 count - 1, m->node, m->latency, m->match, m->mask);
1070 }
1071
1072 return 0;
1073 }
1074
1075 static int __init grab_mblocks(struct mdesc_handle *md)
1076 {
1077 unsigned long paddr;
1078 int count = 0;
1079 u64 node;
1080
1081 mdesc_for_each_node_by_name(md, node, "mblock")
1082 count++;
1083 if (!count)
1084 return -ENOENT;
1085
1086 paddr = memblock_alloc(count * sizeof(struct mdesc_mblock),
1087 SMP_CACHE_BYTES);
1088 if (!paddr)
1089 return -ENOMEM;
1090
1091 mblocks = __va(paddr);
1092 num_mblocks = count;
1093
1094 count = 0;
1095 mdesc_for_each_node_by_name(md, node, "mblock") {
1096 struct mdesc_mblock *m = &mblocks[count++];
1097 const u64 *val;
1098
1099 val = mdesc_get_property(md, node, "base", NULL);
1100 m->base = *val;
1101 val = mdesc_get_property(md, node, "size", NULL);
1102 m->size = *val;
1103 val = mdesc_get_property(md, node,
1104 "address-congruence-offset", NULL);
1105
1106 /* The address-congruence-offset property is optional.
1107 * Explicity zero it be identifty this.
1108 */
1109 if (val)
1110 m->offset = *val;
1111 else
1112 m->offset = 0UL;
1113
1114 numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n",
1115 count - 1, m->base, m->size, m->offset);
1116 }
1117
1118 return 0;
1119 }
1120
1121 static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md,
1122 u64 grp, cpumask_t *mask)
1123 {
1124 u64 arc;
1125
1126 cpumask_clear(mask);
1127
1128 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) {
1129 u64 target = mdesc_arc_target(md, arc);
1130 const char *name = mdesc_node_name(md, target);
1131 const u64 *id;
1132
1133 if (strcmp(name, "cpu"))
1134 continue;
1135 id = mdesc_get_property(md, target, "id", NULL);
1136 if (*id < nr_cpu_ids)
1137 cpumask_set_cpu(*id, mask);
1138 }
1139 }
1140
1141 static struct mdesc_mlgroup * __init find_mlgroup(u64 node)
1142 {
1143 int i;
1144
1145 for (i = 0; i < num_mlgroups; i++) {
1146 struct mdesc_mlgroup *m = &mlgroups[i];
1147 if (m->node == node)
1148 return m;
1149 }
1150 return NULL;
1151 }
1152
1153 static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp,
1154 int index)
1155 {
1156 struct mdesc_mlgroup *candidate = NULL;
1157 u64 arc, best_latency = ~(u64)0;
1158 struct node_mem_mask *n;
1159
1160 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1161 u64 target = mdesc_arc_target(md, arc);
1162 struct mdesc_mlgroup *m = find_mlgroup(target);
1163 if (!m)
1164 continue;
1165 if (m->latency < best_latency) {
1166 candidate = m;
1167 best_latency = m->latency;
1168 }
1169 }
1170 if (!candidate)
1171 return -ENOENT;
1172
1173 if (num_node_masks != index) {
1174 printk(KERN_ERR "Inconsistent NUMA state, "
1175 "index[%d] != num_node_masks[%d]\n",
1176 index, num_node_masks);
1177 return -EINVAL;
1178 }
1179
1180 n = &node_masks[num_node_masks++];
1181
1182 n->mask = candidate->mask;
1183 n->val = candidate->match;
1184
1185 numadbg("NUMA NODE[%d]: mask[%lx] val[%lx] (latency[%llx])\n",
1186 index, n->mask, n->val, candidate->latency);
1187
1188 return 0;
1189 }
1190
1191 static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp,
1192 int index)
1193 {
1194 cpumask_t mask;
1195 int cpu;
1196
1197 numa_parse_mdesc_group_cpus(md, grp, &mask);
1198
1199 for_each_cpu(cpu, &mask)
1200 numa_cpu_lookup_table[cpu] = index;
1201 cpumask_copy(&numa_cpumask_lookup_table[index], &mask);
1202
1203 if (numa_debug) {
1204 printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index);
1205 for_each_cpu(cpu, &mask)
1206 printk("%d ", cpu);
1207 printk("]\n");
1208 }
1209
1210 return numa_attach_mlgroup(md, grp, index);
1211 }
1212
1213 static int __init numa_parse_mdesc(void)
1214 {
1215 struct mdesc_handle *md = mdesc_grab();
1216 int i, err, count;
1217 u64 node;
1218
1219 node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups");
1220 if (node == MDESC_NODE_NULL) {
1221 mdesc_release(md);
1222 return -ENOENT;
1223 }
1224
1225 err = grab_mblocks(md);
1226 if (err < 0)
1227 goto out;
1228
1229 err = grab_mlgroups(md);
1230 if (err < 0)
1231 goto out;
1232
1233 count = 0;
1234 mdesc_for_each_node_by_name(md, node, "group") {
1235 err = numa_parse_mdesc_group(md, node, count);
1236 if (err < 0)
1237 break;
1238 count++;
1239 }
1240
1241 add_node_ranges();
1242
1243 for (i = 0; i < num_node_masks; i++) {
1244 allocate_node_data(i);
1245 node_set_online(i);
1246 }
1247
1248 err = 0;
1249 out:
1250 mdesc_release(md);
1251 return err;
1252 }
1253
1254 static int __init numa_parse_jbus(void)
1255 {
1256 unsigned long cpu, index;
1257
1258 /* NUMA node id is encoded in bits 36 and higher, and there is
1259 * a 1-to-1 mapping from CPU ID to NUMA node ID.
1260 */
1261 index = 0;
1262 for_each_present_cpu(cpu) {
1263 numa_cpu_lookup_table[cpu] = index;
1264 cpumask_copy(&numa_cpumask_lookup_table[index], cpumask_of(cpu));
1265 node_masks[index].mask = ~((1UL << 36UL) - 1UL);
1266 node_masks[index].val = cpu << 36UL;
1267
1268 index++;
1269 }
1270 num_node_masks = index;
1271
1272 add_node_ranges();
1273
1274 for (index = 0; index < num_node_masks; index++) {
1275 allocate_node_data(index);
1276 node_set_online(index);
1277 }
1278
1279 return 0;
1280 }
1281
1282 static int __init numa_parse_sun4u(void)
1283 {
1284 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1285 unsigned long ver;
1286
1287 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
1288 if ((ver >> 32UL) == __JALAPENO_ID ||
1289 (ver >> 32UL) == __SERRANO_ID)
1290 return numa_parse_jbus();
1291 }
1292 return -1;
1293 }
1294
1295 static int __init bootmem_init_numa(void)
1296 {
1297 int err = -1;
1298
1299 numadbg("bootmem_init_numa()\n");
1300
1301 if (numa_enabled) {
1302 if (tlb_type == hypervisor)
1303 err = numa_parse_mdesc();
1304 else
1305 err = numa_parse_sun4u();
1306 }
1307 return err;
1308 }
1309
1310 #else
1311
1312 static int bootmem_init_numa(void)
1313 {
1314 return -1;
1315 }
1316
1317 #endif
1318
1319 static void __init bootmem_init_nonnuma(void)
1320 {
1321 unsigned long top_of_ram = memblock_end_of_DRAM();
1322 unsigned long total_ram = memblock_phys_mem_size();
1323
1324 numadbg("bootmem_init_nonnuma()\n");
1325
1326 printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n",
1327 top_of_ram, total_ram);
1328 printk(KERN_INFO "Memory hole size: %ldMB\n",
1329 (top_of_ram - total_ram) >> 20);
1330
1331 init_node_masks_nonnuma();
1332 memblock_set_node(0, (phys_addr_t)ULLONG_MAX, 0);
1333 allocate_node_data(0);
1334 node_set_online(0);
1335 }
1336
1337 static unsigned long __init bootmem_init(unsigned long phys_base)
1338 {
1339 unsigned long end_pfn;
1340
1341 end_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT;
1342 max_pfn = max_low_pfn = end_pfn;
1343 min_low_pfn = (phys_base >> PAGE_SHIFT);
1344
1345 if (bootmem_init_numa() < 0)
1346 bootmem_init_nonnuma();
1347
1348 /* Dump memblock with node info. */
1349 memblock_dump_all();
1350
1351 /* XXX cpu notifier XXX */
1352
1353 sparse_memory_present_with_active_regions(MAX_NUMNODES);
1354 sparse_init();
1355
1356 return end_pfn;
1357 }
1358
1359 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1360 static int pall_ents __initdata;
1361
1362 #ifdef CONFIG_DEBUG_PAGEALLOC
1363 static unsigned long __ref kernel_map_range(unsigned long pstart,
1364 unsigned long pend, pgprot_t prot)
1365 {
1366 unsigned long vstart = PAGE_OFFSET + pstart;
1367 unsigned long vend = PAGE_OFFSET + pend;
1368 unsigned long alloc_bytes = 0UL;
1369
1370 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1371 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1372 vstart, vend);
1373 prom_halt();
1374 }
1375
1376 while (vstart < vend) {
1377 unsigned long this_end, paddr = __pa(vstart);
1378 pgd_t *pgd = pgd_offset_k(vstart);
1379 pud_t *pud;
1380 pmd_t *pmd;
1381 pte_t *pte;
1382
1383 pud = pud_offset(pgd, vstart);
1384 if (pud_none(*pud)) {
1385 pmd_t *new;
1386
1387 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1388 alloc_bytes += PAGE_SIZE;
1389 pud_populate(&init_mm, pud, new);
1390 }
1391
1392 pmd = pmd_offset(pud, vstart);
1393 if (!pmd_present(*pmd)) {
1394 pte_t *new;
1395
1396 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1397 alloc_bytes += PAGE_SIZE;
1398 pmd_populate_kernel(&init_mm, pmd, new);
1399 }
1400
1401 pte = pte_offset_kernel(pmd, vstart);
1402 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1403 if (this_end > vend)
1404 this_end = vend;
1405
1406 while (vstart < this_end) {
1407 pte_val(*pte) = (paddr | pgprot_val(prot));
1408
1409 vstart += PAGE_SIZE;
1410 paddr += PAGE_SIZE;
1411 pte++;
1412 }
1413 }
1414
1415 return alloc_bytes;
1416 }
1417
1418 extern unsigned int kvmap_linear_patch[1];
1419 #endif /* CONFIG_DEBUG_PAGEALLOC */
1420
1421 static void __init kpte_set_val(unsigned long index, unsigned long val)
1422 {
1423 unsigned long *ptr = kpte_linear_bitmap;
1424
1425 val <<= ((index % (BITS_PER_LONG / 2)) * 2);
1426 ptr += (index / (BITS_PER_LONG / 2));
1427
1428 *ptr |= val;
1429 }
1430
1431 static const unsigned long kpte_shift_min = 28; /* 256MB */
1432 static const unsigned long kpte_shift_max = 34; /* 16GB */
1433 static const unsigned long kpte_shift_incr = 3;
1434
1435 static unsigned long kpte_mark_using_shift(unsigned long start, unsigned long end,
1436 unsigned long shift)
1437 {
1438 unsigned long size = (1UL << shift);
1439 unsigned long mask = (size - 1UL);
1440 unsigned long remains = end - start;
1441 unsigned long val;
1442
1443 if (remains < size || (start & mask))
1444 return start;
1445
1446 /* VAL maps:
1447 *
1448 * shift 28 --> kern_linear_pte_xor index 1
1449 * shift 31 --> kern_linear_pte_xor index 2
1450 * shift 34 --> kern_linear_pte_xor index 3
1451 */
1452 val = ((shift - kpte_shift_min) / kpte_shift_incr) + 1;
1453
1454 remains &= ~mask;
1455 if (shift != kpte_shift_max)
1456 remains = size;
1457
1458 while (remains) {
1459 unsigned long index = start >> kpte_shift_min;
1460
1461 kpte_set_val(index, val);
1462
1463 start += 1UL << kpte_shift_min;
1464 remains -= 1UL << kpte_shift_min;
1465 }
1466
1467 return start;
1468 }
1469
1470 static void __init mark_kpte_bitmap(unsigned long start, unsigned long end)
1471 {
1472 unsigned long smallest_size, smallest_mask;
1473 unsigned long s;
1474
1475 smallest_size = (1UL << kpte_shift_min);
1476 smallest_mask = (smallest_size - 1UL);
1477
1478 while (start < end) {
1479 unsigned long orig_start = start;
1480
1481 for (s = kpte_shift_max; s >= kpte_shift_min; s -= kpte_shift_incr) {
1482 start = kpte_mark_using_shift(start, end, s);
1483
1484 if (start != orig_start)
1485 break;
1486 }
1487
1488 if (start == orig_start)
1489 start = (start + smallest_size) & ~smallest_mask;
1490 }
1491 }
1492
1493 static void __init init_kpte_bitmap(void)
1494 {
1495 unsigned long i;
1496
1497 for (i = 0; i < pall_ents; i++) {
1498 unsigned long phys_start, phys_end;
1499
1500 phys_start = pall[i].phys_addr;
1501 phys_end = phys_start + pall[i].reg_size;
1502
1503 mark_kpte_bitmap(phys_start, phys_end);
1504 }
1505 }
1506
1507 static void __init kernel_physical_mapping_init(void)
1508 {
1509 #ifdef CONFIG_DEBUG_PAGEALLOC
1510 unsigned long i, mem_alloced = 0UL;
1511
1512 for (i = 0; i < pall_ents; i++) {
1513 unsigned long phys_start, phys_end;
1514
1515 phys_start = pall[i].phys_addr;
1516 phys_end = phys_start + pall[i].reg_size;
1517
1518 mem_alloced += kernel_map_range(phys_start, phys_end,
1519 PAGE_KERNEL);
1520 }
1521
1522 printk("Allocated %ld bytes for kernel page tables.\n",
1523 mem_alloced);
1524
1525 kvmap_linear_patch[0] = 0x01000000; /* nop */
1526 flushi(&kvmap_linear_patch[0]);
1527
1528 __flush_tlb_all();
1529 #endif
1530 }
1531
1532 #ifdef CONFIG_DEBUG_PAGEALLOC
1533 void kernel_map_pages(struct page *page, int numpages, int enable)
1534 {
1535 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1536 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1537
1538 kernel_map_range(phys_start, phys_end,
1539 (enable ? PAGE_KERNEL : __pgprot(0)));
1540
1541 flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1542 PAGE_OFFSET + phys_end);
1543
1544 /* we should perform an IPI and flush all tlbs,
1545 * but that can deadlock->flush only current cpu.
1546 */
1547 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1548 PAGE_OFFSET + phys_end);
1549 }
1550 #endif
1551
1552 unsigned long __init find_ecache_flush_span(unsigned long size)
1553 {
1554 int i;
1555
1556 for (i = 0; i < pavail_ents; i++) {
1557 if (pavail[i].reg_size >= size)
1558 return pavail[i].phys_addr;
1559 }
1560
1561 return ~0UL;
1562 }
1563
1564 static void __init tsb_phys_patch(void)
1565 {
1566 struct tsb_ldquad_phys_patch_entry *pquad;
1567 struct tsb_phys_patch_entry *p;
1568
1569 pquad = &__tsb_ldquad_phys_patch;
1570 while (pquad < &__tsb_ldquad_phys_patch_end) {
1571 unsigned long addr = pquad->addr;
1572
1573 if (tlb_type == hypervisor)
1574 *(unsigned int *) addr = pquad->sun4v_insn;
1575 else
1576 *(unsigned int *) addr = pquad->sun4u_insn;
1577 wmb();
1578 __asm__ __volatile__("flush %0"
1579 : /* no outputs */
1580 : "r" (addr));
1581
1582 pquad++;
1583 }
1584
1585 p = &__tsb_phys_patch;
1586 while (p < &__tsb_phys_patch_end) {
1587 unsigned long addr = p->addr;
1588
1589 *(unsigned int *) addr = p->insn;
1590 wmb();
1591 __asm__ __volatile__("flush %0"
1592 : /* no outputs */
1593 : "r" (addr));
1594
1595 p++;
1596 }
1597 }
1598
1599 /* Don't mark as init, we give this to the Hypervisor. */
1600 #ifndef CONFIG_DEBUG_PAGEALLOC
1601 #define NUM_KTSB_DESCR 2
1602 #else
1603 #define NUM_KTSB_DESCR 1
1604 #endif
1605 static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
1606 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
1607
1608 static void patch_one_ktsb_phys(unsigned int *start, unsigned int *end, unsigned long pa)
1609 {
1610 pa >>= KTSB_PHYS_SHIFT;
1611
1612 while (start < end) {
1613 unsigned int *ia = (unsigned int *)(unsigned long)*start;
1614
1615 ia[0] = (ia[0] & ~0x3fffff) | (pa >> 10);
1616 __asm__ __volatile__("flush %0" : : "r" (ia));
1617
1618 ia[1] = (ia[1] & ~0x3ff) | (pa & 0x3ff);
1619 __asm__ __volatile__("flush %0" : : "r" (ia + 1));
1620
1621 start++;
1622 }
1623 }
1624
1625 static void ktsb_phys_patch(void)
1626 {
1627 extern unsigned int __swapper_tsb_phys_patch;
1628 extern unsigned int __swapper_tsb_phys_patch_end;
1629 unsigned long ktsb_pa;
1630
1631 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1632 patch_one_ktsb_phys(&__swapper_tsb_phys_patch,
1633 &__swapper_tsb_phys_patch_end, ktsb_pa);
1634 #ifndef CONFIG_DEBUG_PAGEALLOC
1635 {
1636 extern unsigned int __swapper_4m_tsb_phys_patch;
1637 extern unsigned int __swapper_4m_tsb_phys_patch_end;
1638 ktsb_pa = (kern_base +
1639 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1640 patch_one_ktsb_phys(&__swapper_4m_tsb_phys_patch,
1641 &__swapper_4m_tsb_phys_patch_end, ktsb_pa);
1642 }
1643 #endif
1644 }
1645
1646 static void __init sun4v_ktsb_init(void)
1647 {
1648 unsigned long ktsb_pa;
1649
1650 /* First KTSB for PAGE_SIZE mappings. */
1651 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1652
1653 switch (PAGE_SIZE) {
1654 case 8 * 1024:
1655 default:
1656 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1657 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1658 break;
1659
1660 case 64 * 1024:
1661 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1662 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1663 break;
1664
1665 case 512 * 1024:
1666 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1667 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1668 break;
1669
1670 case 4 * 1024 * 1024:
1671 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1672 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1673 break;
1674 }
1675
1676 ktsb_descr[0].assoc = 1;
1677 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1678 ktsb_descr[0].ctx_idx = 0;
1679 ktsb_descr[0].tsb_base = ktsb_pa;
1680 ktsb_descr[0].resv = 0;
1681
1682 #ifndef CONFIG_DEBUG_PAGEALLOC
1683 /* Second KTSB for 4MB/256MB/2GB/16GB mappings. */
1684 ktsb_pa = (kern_base +
1685 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1686
1687 ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
1688 ktsb_descr[1].pgsz_mask = ((HV_PGSZ_MASK_4MB |
1689 HV_PGSZ_MASK_256MB |
1690 HV_PGSZ_MASK_2GB |
1691 HV_PGSZ_MASK_16GB) &
1692 cpu_pgsz_mask);
1693 ktsb_descr[1].assoc = 1;
1694 ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
1695 ktsb_descr[1].ctx_idx = 0;
1696 ktsb_descr[1].tsb_base = ktsb_pa;
1697 ktsb_descr[1].resv = 0;
1698 #endif
1699 }
1700
1701 void sun4v_ktsb_register(void)
1702 {
1703 unsigned long pa, ret;
1704
1705 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1706
1707 ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
1708 if (ret != 0) {
1709 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
1710 "errors with %lx\n", pa, ret);
1711 prom_halt();
1712 }
1713 }
1714
1715 static void __init sun4u_linear_pte_xor_finalize(void)
1716 {
1717 #ifndef CONFIG_DEBUG_PAGEALLOC
1718 /* This is where we would add Panther support for
1719 * 32MB and 256MB pages.
1720 */
1721 #endif
1722 }
1723
1724 static void __init sun4v_linear_pte_xor_finalize(void)
1725 {
1726 #ifndef CONFIG_DEBUG_PAGEALLOC
1727 if (cpu_pgsz_mask & HV_PGSZ_MASK_256MB) {
1728 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
1729 0xfffff80000000000UL;
1730 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1731 _PAGE_P_4V | _PAGE_W_4V);
1732 } else {
1733 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
1734 }
1735
1736 if (cpu_pgsz_mask & HV_PGSZ_MASK_2GB) {
1737 kern_linear_pte_xor[2] = (_PAGE_VALID | _PAGE_SZ2GB_4V) ^
1738 0xfffff80000000000UL;
1739 kern_linear_pte_xor[2] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1740 _PAGE_P_4V | _PAGE_W_4V);
1741 } else {
1742 kern_linear_pte_xor[2] = kern_linear_pte_xor[1];
1743 }
1744
1745 if (cpu_pgsz_mask & HV_PGSZ_MASK_16GB) {
1746 kern_linear_pte_xor[3] = (_PAGE_VALID | _PAGE_SZ16GB_4V) ^
1747 0xfffff80000000000UL;
1748 kern_linear_pte_xor[3] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1749 _PAGE_P_4V | _PAGE_W_4V);
1750 } else {
1751 kern_linear_pte_xor[3] = kern_linear_pte_xor[2];
1752 }
1753 #endif
1754 }
1755
1756 /* paging_init() sets up the page tables */
1757
1758 static unsigned long last_valid_pfn;
1759 pgd_t swapper_pg_dir[2048];
1760
1761 static void sun4u_pgprot_init(void);
1762 static void sun4v_pgprot_init(void);
1763
1764 void __init paging_init(void)
1765 {
1766 unsigned long end_pfn, shift, phys_base;
1767 unsigned long real_end, i;
1768 int node;
1769
1770 /* These build time checkes make sure that the dcache_dirty_cpu()
1771 * page->flags usage will work.
1772 *
1773 * When a page gets marked as dcache-dirty, we store the
1774 * cpu number starting at bit 32 in the page->flags. Also,
1775 * functions like clear_dcache_dirty_cpu use the cpu mask
1776 * in 13-bit signed-immediate instruction fields.
1777 */
1778
1779 /*
1780 * Page flags must not reach into upper 32 bits that are used
1781 * for the cpu number
1782 */
1783 BUILD_BUG_ON(NR_PAGEFLAGS > 32);
1784
1785 /*
1786 * The bit fields placed in the high range must not reach below
1787 * the 32 bit boundary. Otherwise we cannot place the cpu field
1788 * at the 32 bit boundary.
1789 */
1790 BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
1791 ilog2(roundup_pow_of_two(NR_CPUS)) > 32);
1792
1793 BUILD_BUG_ON(NR_CPUS > 4096);
1794
1795 kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1796 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1797
1798 /* Invalidate both kernel TSBs. */
1799 memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
1800 #ifndef CONFIG_DEBUG_PAGEALLOC
1801 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
1802 #endif
1803
1804 if (tlb_type == hypervisor)
1805 sun4v_pgprot_init();
1806 else
1807 sun4u_pgprot_init();
1808
1809 if (tlb_type == cheetah_plus ||
1810 tlb_type == hypervisor) {
1811 tsb_phys_patch();
1812 ktsb_phys_patch();
1813 }
1814
1815 if (tlb_type == hypervisor)
1816 sun4v_patch_tlb_handlers();
1817
1818 /* Find available physical memory...
1819 *
1820 * Read it twice in order to work around a bug in openfirmware.
1821 * The call to grab this table itself can cause openfirmware to
1822 * allocate memory, which in turn can take away some space from
1823 * the list of available memory. Reading it twice makes sure
1824 * we really do get the final value.
1825 */
1826 read_obp_translations();
1827 read_obp_memory("reg", &pall[0], &pall_ents);
1828 read_obp_memory("available", &pavail[0], &pavail_ents);
1829 read_obp_memory("available", &pavail[0], &pavail_ents);
1830
1831 phys_base = 0xffffffffffffffffUL;
1832 for (i = 0; i < pavail_ents; i++) {
1833 phys_base = min(phys_base, pavail[i].phys_addr);
1834 memblock_add(pavail[i].phys_addr, pavail[i].reg_size);
1835 }
1836
1837 memblock_reserve(kern_base, kern_size);
1838
1839 find_ramdisk(phys_base);
1840
1841 memblock_enforce_memory_limit(cmdline_memory_size);
1842
1843 memblock_allow_resize();
1844 memblock_dump_all();
1845
1846 set_bit(0, mmu_context_bmap);
1847
1848 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1849
1850 real_end = (unsigned long)_end;
1851 num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << 22);
1852 printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
1853 num_kernel_image_mappings);
1854
1855 /* Set kernel pgd to upper alias so physical page computations
1856 * work.
1857 */
1858 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1859
1860 memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1861
1862 /* Now can init the kernel/bad page tables. */
1863 pud_set(pud_offset(&swapper_pg_dir[0], 0),
1864 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1865
1866 inherit_prom_mappings();
1867
1868 init_kpte_bitmap();
1869
1870 /* Ok, we can use our TLB miss and window trap handlers safely. */
1871 setup_tba();
1872
1873 __flush_tlb_all();
1874
1875 prom_build_devicetree();
1876 of_populate_present_mask();
1877 #ifndef CONFIG_SMP
1878 of_fill_in_cpu_data();
1879 #endif
1880
1881 if (tlb_type == hypervisor) {
1882 sun4v_mdesc_init();
1883 mdesc_populate_present_mask(cpu_all_mask);
1884 #ifndef CONFIG_SMP
1885 mdesc_fill_in_cpu_data(cpu_all_mask);
1886 #endif
1887 mdesc_get_page_sizes(cpu_all_mask, &cpu_pgsz_mask);
1888
1889 sun4v_linear_pte_xor_finalize();
1890
1891 sun4v_ktsb_init();
1892 sun4v_ktsb_register();
1893 } else {
1894 unsigned long impl, ver;
1895
1896 cpu_pgsz_mask = (HV_PGSZ_MASK_8K | HV_PGSZ_MASK_64K |
1897 HV_PGSZ_MASK_512K | HV_PGSZ_MASK_4MB);
1898
1899 __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
1900 impl = ((ver >> 32) & 0xffff);
1901 if (impl == PANTHER_IMPL)
1902 cpu_pgsz_mask |= (HV_PGSZ_MASK_32MB |
1903 HV_PGSZ_MASK_256MB);
1904
1905 sun4u_linear_pte_xor_finalize();
1906 }
1907
1908 /* Flush the TLBs and the 4M TSB so that the updated linear
1909 * pte XOR settings are realized for all mappings.
1910 */
1911 __flush_tlb_all();
1912 #ifndef CONFIG_DEBUG_PAGEALLOC
1913 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
1914 #endif
1915 __flush_tlb_all();
1916
1917 /* Setup bootmem... */
1918 last_valid_pfn = end_pfn = bootmem_init(phys_base);
1919
1920 /* Once the OF device tree and MDESC have been setup, we know
1921 * the list of possible cpus. Therefore we can allocate the
1922 * IRQ stacks.
1923 */
1924 for_each_possible_cpu(i) {
1925 node = cpu_to_node(i);
1926
1927 softirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
1928 THREAD_SIZE,
1929 THREAD_SIZE, 0);
1930 hardirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
1931 THREAD_SIZE,
1932 THREAD_SIZE, 0);
1933 }
1934
1935 kernel_physical_mapping_init();
1936
1937 {
1938 unsigned long max_zone_pfns[MAX_NR_ZONES];
1939
1940 memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
1941
1942 max_zone_pfns[ZONE_NORMAL] = end_pfn;
1943
1944 free_area_init_nodes(max_zone_pfns);
1945 }
1946
1947 printk("Booting Linux...\n");
1948 }
1949
1950 int page_in_phys_avail(unsigned long paddr)
1951 {
1952 int i;
1953
1954 paddr &= PAGE_MASK;
1955
1956 for (i = 0; i < pavail_ents; i++) {
1957 unsigned long start, end;
1958
1959 start = pavail[i].phys_addr;
1960 end = start + pavail[i].reg_size;
1961
1962 if (paddr >= start && paddr < end)
1963 return 1;
1964 }
1965 if (paddr >= kern_base && paddr < (kern_base + kern_size))
1966 return 1;
1967 #ifdef CONFIG_BLK_DEV_INITRD
1968 if (paddr >= __pa(initrd_start) &&
1969 paddr < __pa(PAGE_ALIGN(initrd_end)))
1970 return 1;
1971 #endif
1972
1973 return 0;
1974 }
1975
1976 static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
1977 static int pavail_rescan_ents __initdata;
1978
1979 /* Certain OBP calls, such as fetching "available" properties, can
1980 * claim physical memory. So, along with initializing the valid
1981 * address bitmap, what we do here is refetch the physical available
1982 * memory list again, and make sure it provides at least as much
1983 * memory as 'pavail' does.
1984 */
1985 static void __init setup_valid_addr_bitmap_from_pavail(unsigned long *bitmap)
1986 {
1987 int i;
1988
1989 read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
1990
1991 for (i = 0; i < pavail_ents; i++) {
1992 unsigned long old_start, old_end;
1993
1994 old_start = pavail[i].phys_addr;
1995 old_end = old_start + pavail[i].reg_size;
1996 while (old_start < old_end) {
1997 int n;
1998
1999 for (n = 0; n < pavail_rescan_ents; n++) {
2000 unsigned long new_start, new_end;
2001
2002 new_start = pavail_rescan[n].phys_addr;
2003 new_end = new_start +
2004 pavail_rescan[n].reg_size;
2005
2006 if (new_start <= old_start &&
2007 new_end >= (old_start + PAGE_SIZE)) {
2008 set_bit(old_start >> 22, bitmap);
2009 goto do_next_page;
2010 }
2011 }
2012
2013 prom_printf("mem_init: Lost memory in pavail\n");
2014 prom_printf("mem_init: OLD start[%lx] size[%lx]\n",
2015 pavail[i].phys_addr,
2016 pavail[i].reg_size);
2017 prom_printf("mem_init: NEW start[%lx] size[%lx]\n",
2018 pavail_rescan[i].phys_addr,
2019 pavail_rescan[i].reg_size);
2020 prom_printf("mem_init: Cannot continue, aborting.\n");
2021 prom_halt();
2022
2023 do_next_page:
2024 old_start += PAGE_SIZE;
2025 }
2026 }
2027 }
2028
2029 static void __init patch_tlb_miss_handler_bitmap(void)
2030 {
2031 extern unsigned int valid_addr_bitmap_insn[];
2032 extern unsigned int valid_addr_bitmap_patch[];
2033
2034 valid_addr_bitmap_insn[1] = valid_addr_bitmap_patch[1];
2035 mb();
2036 valid_addr_bitmap_insn[0] = valid_addr_bitmap_patch[0];
2037 flushi(&valid_addr_bitmap_insn[0]);
2038 }
2039
2040 static void __init register_page_bootmem_info(void)
2041 {
2042 #ifdef CONFIG_NEED_MULTIPLE_NODES
2043 int i;
2044
2045 for_each_online_node(i)
2046 if (NODE_DATA(i)->node_spanned_pages)
2047 register_page_bootmem_info_node(NODE_DATA(i));
2048 #endif
2049 }
2050 void __init mem_init(void)
2051 {
2052 unsigned long addr, last;
2053
2054 addr = PAGE_OFFSET + kern_base;
2055 last = PAGE_ALIGN(kern_size) + addr;
2056 while (addr < last) {
2057 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
2058 addr += PAGE_SIZE;
2059 }
2060
2061 setup_valid_addr_bitmap_from_pavail(sparc64_valid_addr_bitmap);
2062 patch_tlb_miss_handler_bitmap();
2063
2064 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
2065
2066 register_page_bootmem_info();
2067 free_all_bootmem();
2068
2069 /*
2070 * Set up the zero page, mark it reserved, so that page count
2071 * is not manipulated when freeing the page from user ptes.
2072 */
2073 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
2074 if (mem_map_zero == NULL) {
2075 prom_printf("paging_init: Cannot alloc zero page.\n");
2076 prom_halt();
2077 }
2078 mark_page_reserved(mem_map_zero);
2079
2080 mem_init_print_info(NULL);
2081
2082 if (tlb_type == cheetah || tlb_type == cheetah_plus)
2083 cheetah_ecache_flush_init();
2084 }
2085
2086 void free_initmem(void)
2087 {
2088 unsigned long addr, initend;
2089 int do_free = 1;
2090
2091 /* If the physical memory maps were trimmed by kernel command
2092 * line options, don't even try freeing this initmem stuff up.
2093 * The kernel image could have been in the trimmed out region
2094 * and if so the freeing below will free invalid page structs.
2095 */
2096 if (cmdline_memory_size)
2097 do_free = 0;
2098
2099 /*
2100 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
2101 */
2102 addr = PAGE_ALIGN((unsigned long)(__init_begin));
2103 initend = (unsigned long)(__init_end) & PAGE_MASK;
2104 for (; addr < initend; addr += PAGE_SIZE) {
2105 unsigned long page;
2106
2107 page = (addr +
2108 ((unsigned long) __va(kern_base)) -
2109 ((unsigned long) KERNBASE));
2110 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
2111
2112 if (do_free)
2113 free_reserved_page(virt_to_page(page));
2114 }
2115 }
2116
2117 #ifdef CONFIG_BLK_DEV_INITRD
2118 void free_initrd_mem(unsigned long start, unsigned long end)
2119 {
2120 free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM,
2121 "initrd");
2122 }
2123 #endif
2124
2125 #define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
2126 #define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
2127 #define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
2128 #define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
2129 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
2130 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
2131
2132 pgprot_t PAGE_KERNEL __read_mostly;
2133 EXPORT_SYMBOL(PAGE_KERNEL);
2134
2135 pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
2136 pgprot_t PAGE_COPY __read_mostly;
2137
2138 pgprot_t PAGE_SHARED __read_mostly;
2139 EXPORT_SYMBOL(PAGE_SHARED);
2140
2141 unsigned long pg_iobits __read_mostly;
2142
2143 unsigned long _PAGE_IE __read_mostly;
2144 EXPORT_SYMBOL(_PAGE_IE);
2145
2146 unsigned long _PAGE_E __read_mostly;
2147 EXPORT_SYMBOL(_PAGE_E);
2148
2149 unsigned long _PAGE_CACHE __read_mostly;
2150 EXPORT_SYMBOL(_PAGE_CACHE);
2151
2152 #ifdef CONFIG_SPARSEMEM_VMEMMAP
2153 unsigned long vmemmap_table[VMEMMAP_SIZE];
2154
2155 static long __meminitdata addr_start, addr_end;
2156 static int __meminitdata node_start;
2157
2158 int __meminit vmemmap_populate(unsigned long vstart, unsigned long vend,
2159 int node)
2160 {
2161 unsigned long phys_start = (vstart - VMEMMAP_BASE);
2162 unsigned long phys_end = (vend - VMEMMAP_BASE);
2163 unsigned long addr = phys_start & VMEMMAP_CHUNK_MASK;
2164 unsigned long end = VMEMMAP_ALIGN(phys_end);
2165 unsigned long pte_base;
2166
2167 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2168 _PAGE_CP_4U | _PAGE_CV_4U |
2169 _PAGE_P_4U | _PAGE_W_4U);
2170 if (tlb_type == hypervisor)
2171 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2172 _PAGE_CP_4V | _PAGE_CV_4V |
2173 _PAGE_P_4V | _PAGE_W_4V);
2174
2175 for (; addr < end; addr += VMEMMAP_CHUNK) {
2176 unsigned long *vmem_pp =
2177 vmemmap_table + (addr >> VMEMMAP_CHUNK_SHIFT);
2178 void *block;
2179
2180 if (!(*vmem_pp & _PAGE_VALID)) {
2181 block = vmemmap_alloc_block(1UL << 22, node);
2182 if (!block)
2183 return -ENOMEM;
2184
2185 *vmem_pp = pte_base | __pa(block);
2186
2187 /* check to see if we have contiguous blocks */
2188 if (addr_end != addr || node_start != node) {
2189 if (addr_start)
2190 printk(KERN_DEBUG " [%lx-%lx] on node %d\n",
2191 addr_start, addr_end-1, node_start);
2192 addr_start = addr;
2193 node_start = node;
2194 }
2195 addr_end = addr + VMEMMAP_CHUNK;
2196 }
2197 }
2198 return 0;
2199 }
2200
2201 void __meminit vmemmap_populate_print_last(void)
2202 {
2203 if (addr_start) {
2204 printk(KERN_DEBUG " [%lx-%lx] on node %d\n",
2205 addr_start, addr_end-1, node_start);
2206 addr_start = 0;
2207 addr_end = 0;
2208 node_start = 0;
2209 }
2210 }
2211
2212 void vmemmap_free(unsigned long start, unsigned long end)
2213 {
2214 }
2215
2216 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
2217
2218 static void prot_init_common(unsigned long page_none,
2219 unsigned long page_shared,
2220 unsigned long page_copy,
2221 unsigned long page_readonly,
2222 unsigned long page_exec_bit)
2223 {
2224 PAGE_COPY = __pgprot(page_copy);
2225 PAGE_SHARED = __pgprot(page_shared);
2226
2227 protection_map[0x0] = __pgprot(page_none);
2228 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
2229 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
2230 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
2231 protection_map[0x4] = __pgprot(page_readonly);
2232 protection_map[0x5] = __pgprot(page_readonly);
2233 protection_map[0x6] = __pgprot(page_copy);
2234 protection_map[0x7] = __pgprot(page_copy);
2235 protection_map[0x8] = __pgprot(page_none);
2236 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
2237 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
2238 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
2239 protection_map[0xc] = __pgprot(page_readonly);
2240 protection_map[0xd] = __pgprot(page_readonly);
2241 protection_map[0xe] = __pgprot(page_shared);
2242 protection_map[0xf] = __pgprot(page_shared);
2243 }
2244
2245 static void __init sun4u_pgprot_init(void)
2246 {
2247 unsigned long page_none, page_shared, page_copy, page_readonly;
2248 unsigned long page_exec_bit;
2249 int i;
2250
2251 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2252 _PAGE_CACHE_4U | _PAGE_P_4U |
2253 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2254 _PAGE_EXEC_4U);
2255 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2256 _PAGE_CACHE_4U | _PAGE_P_4U |
2257 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2258 _PAGE_EXEC_4U | _PAGE_L_4U);
2259
2260 _PAGE_IE = _PAGE_IE_4U;
2261 _PAGE_E = _PAGE_E_4U;
2262 _PAGE_CACHE = _PAGE_CACHE_4U;
2263
2264 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
2265 __ACCESS_BITS_4U | _PAGE_E_4U);
2266
2267 #ifdef CONFIG_DEBUG_PAGEALLOC
2268 kern_linear_pte_xor[0] = _PAGE_VALID ^ 0xfffff80000000000UL;
2269 #else
2270 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
2271 0xfffff80000000000UL;
2272 #endif
2273 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
2274 _PAGE_P_4U | _PAGE_W_4U);
2275
2276 for (i = 1; i < 4; i++)
2277 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2278
2279 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
2280 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
2281 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
2282
2283
2284 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
2285 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2286 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
2287 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2288 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2289 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2290 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2291
2292 page_exec_bit = _PAGE_EXEC_4U;
2293
2294 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2295 page_exec_bit);
2296 }
2297
2298 static void __init sun4v_pgprot_init(void)
2299 {
2300 unsigned long page_none, page_shared, page_copy, page_readonly;
2301 unsigned long page_exec_bit;
2302 int i;
2303
2304 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
2305 _PAGE_CACHE_4V | _PAGE_P_4V |
2306 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
2307 _PAGE_EXEC_4V);
2308 PAGE_KERNEL_LOCKED = PAGE_KERNEL;
2309
2310 _PAGE_IE = _PAGE_IE_4V;
2311 _PAGE_E = _PAGE_E_4V;
2312 _PAGE_CACHE = _PAGE_CACHE_4V;
2313
2314 #ifdef CONFIG_DEBUG_PAGEALLOC
2315 kern_linear_pte_xor[0] = _PAGE_VALID ^ 0xfffff80000000000UL;
2316 #else
2317 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
2318 0xfffff80000000000UL;
2319 #endif
2320 kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V |
2321 _PAGE_P_4V | _PAGE_W_4V);
2322
2323 for (i = 1; i < 4; i++)
2324 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2325
2326 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
2327 __ACCESS_BITS_4V | _PAGE_E_4V);
2328
2329 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
2330 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
2331 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
2332 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
2333
2334 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V;
2335 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2336 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
2337 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2338 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2339 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2340 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2341
2342 page_exec_bit = _PAGE_EXEC_4V;
2343
2344 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2345 page_exec_bit);
2346 }
2347
2348 unsigned long pte_sz_bits(unsigned long sz)
2349 {
2350 if (tlb_type == hypervisor) {
2351 switch (sz) {
2352 case 8 * 1024:
2353 default:
2354 return _PAGE_SZ8K_4V;
2355 case 64 * 1024:
2356 return _PAGE_SZ64K_4V;
2357 case 512 * 1024:
2358 return _PAGE_SZ512K_4V;
2359 case 4 * 1024 * 1024:
2360 return _PAGE_SZ4MB_4V;
2361 }
2362 } else {
2363 switch (sz) {
2364 case 8 * 1024:
2365 default:
2366 return _PAGE_SZ8K_4U;
2367 case 64 * 1024:
2368 return _PAGE_SZ64K_4U;
2369 case 512 * 1024:
2370 return _PAGE_SZ512K_4U;
2371 case 4 * 1024 * 1024:
2372 return _PAGE_SZ4MB_4U;
2373 }
2374 }
2375 }
2376
2377 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
2378 {
2379 pte_t pte;
2380
2381 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot));
2382 pte_val(pte) |= (((unsigned long)space) << 32);
2383 pte_val(pte) |= pte_sz_bits(page_size);
2384
2385 return pte;
2386 }
2387
2388 static unsigned long kern_large_tte(unsigned long paddr)
2389 {
2390 unsigned long val;
2391
2392 val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2393 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
2394 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
2395 if (tlb_type == hypervisor)
2396 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2397 _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V |
2398 _PAGE_EXEC_4V | _PAGE_W_4V);
2399
2400 return val | paddr;
2401 }
2402
2403 /* If not locked, zap it. */
2404 void __flush_tlb_all(void)
2405 {
2406 unsigned long pstate;
2407 int i;
2408
2409 __asm__ __volatile__("flushw\n\t"
2410 "rdpr %%pstate, %0\n\t"
2411 "wrpr %0, %1, %%pstate"
2412 : "=r" (pstate)
2413 : "i" (PSTATE_IE));
2414 if (tlb_type == hypervisor) {
2415 sun4v_mmu_demap_all();
2416 } else if (tlb_type == spitfire) {
2417 for (i = 0; i < 64; i++) {
2418 /* Spitfire Errata #32 workaround */
2419 /* NOTE: Always runs on spitfire, so no
2420 * cheetah+ page size encodings.
2421 */
2422 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2423 "flush %%g6"
2424 : /* No outputs */
2425 : "r" (0),
2426 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2427
2428 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
2429 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2430 "membar #Sync"
2431 : /* no outputs */
2432 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
2433 spitfire_put_dtlb_data(i, 0x0UL);
2434 }
2435
2436 /* Spitfire Errata #32 workaround */
2437 /* NOTE: Always runs on spitfire, so no
2438 * cheetah+ page size encodings.
2439 */
2440 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2441 "flush %%g6"
2442 : /* No outputs */
2443 : "r" (0),
2444 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2445
2446 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
2447 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2448 "membar #Sync"
2449 : /* no outputs */
2450 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
2451 spitfire_put_itlb_data(i, 0x0UL);
2452 }
2453 }
2454 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
2455 cheetah_flush_dtlb_all();
2456 cheetah_flush_itlb_all();
2457 }
2458 __asm__ __volatile__("wrpr %0, 0, %%pstate"
2459 : : "r" (pstate));
2460 }
2461
2462 static pte_t *get_from_cache(struct mm_struct *mm)
2463 {
2464 struct page *page;
2465 pte_t *ret;
2466
2467 spin_lock(&mm->page_table_lock);
2468 page = mm->context.pgtable_page;
2469 ret = NULL;
2470 if (page) {
2471 void *p = page_address(page);
2472
2473 mm->context.pgtable_page = NULL;
2474
2475 ret = (pte_t *) (p + (PAGE_SIZE / 2));
2476 }
2477 spin_unlock(&mm->page_table_lock);
2478
2479 return ret;
2480 }
2481
2482 static struct page *__alloc_for_cache(struct mm_struct *mm)
2483 {
2484 struct page *page = alloc_page(GFP_KERNEL | __GFP_NOTRACK |
2485 __GFP_REPEAT | __GFP_ZERO);
2486
2487 if (page) {
2488 spin_lock(&mm->page_table_lock);
2489 if (!mm->context.pgtable_page) {
2490 atomic_set(&page->_count, 2);
2491 mm->context.pgtable_page = page;
2492 }
2493 spin_unlock(&mm->page_table_lock);
2494 }
2495 return page;
2496 }
2497
2498 pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
2499 unsigned long address)
2500 {
2501 struct page *page;
2502 pte_t *pte;
2503
2504 pte = get_from_cache(mm);
2505 if (pte)
2506 return pte;
2507
2508 page = __alloc_for_cache(mm);
2509 if (page)
2510 pte = (pte_t *) page_address(page);
2511
2512 return pte;
2513 }
2514
2515 pgtable_t pte_alloc_one(struct mm_struct *mm,
2516 unsigned long address)
2517 {
2518 struct page *page;
2519 pte_t *pte;
2520
2521 pte = get_from_cache(mm);
2522 if (pte)
2523 return pte;
2524
2525 page = __alloc_for_cache(mm);
2526 if (page) {
2527 pgtable_page_ctor(page);
2528 pte = (pte_t *) page_address(page);
2529 }
2530
2531 return pte;
2532 }
2533
2534 void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
2535 {
2536 struct page *page = virt_to_page(pte);
2537 if (put_page_testzero(page))
2538 free_hot_cold_page(page, 0);
2539 }
2540
2541 static void __pte_free(pgtable_t pte)
2542 {
2543 struct page *page = virt_to_page(pte);
2544 if (put_page_testzero(page)) {
2545 pgtable_page_dtor(page);
2546 free_hot_cold_page(page, 0);
2547 }
2548 }
2549
2550 void pte_free(struct mm_struct *mm, pgtable_t pte)
2551 {
2552 __pte_free(pte);
2553 }
2554
2555 void pgtable_free(void *table, bool is_page)
2556 {
2557 if (is_page)
2558 __pte_free(table);
2559 else
2560 kmem_cache_free(pgtable_cache, table);
2561 }
2562
2563 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
2564 static pmd_t pmd_set_protbits(pmd_t pmd, pgprot_t pgprot, bool for_modify)
2565 {
2566 if (pgprot_val(pgprot) & _PAGE_VALID)
2567 pmd_val(pmd) |= PMD_HUGE_PRESENT;
2568 if (tlb_type == hypervisor) {
2569 if (pgprot_val(pgprot) & _PAGE_WRITE_4V)
2570 pmd_val(pmd) |= PMD_HUGE_WRITE;
2571 if (pgprot_val(pgprot) & _PAGE_EXEC_4V)
2572 pmd_val(pmd) |= PMD_HUGE_EXEC;
2573
2574 if (!for_modify) {
2575 if (pgprot_val(pgprot) & _PAGE_ACCESSED_4V)
2576 pmd_val(pmd) |= PMD_HUGE_ACCESSED;
2577 if (pgprot_val(pgprot) & _PAGE_MODIFIED_4V)
2578 pmd_val(pmd) |= PMD_HUGE_DIRTY;
2579 }
2580 } else {
2581 if (pgprot_val(pgprot) & _PAGE_WRITE_4U)
2582 pmd_val(pmd) |= PMD_HUGE_WRITE;
2583 if (pgprot_val(pgprot) & _PAGE_EXEC_4U)
2584 pmd_val(pmd) |= PMD_HUGE_EXEC;
2585
2586 if (!for_modify) {
2587 if (pgprot_val(pgprot) & _PAGE_ACCESSED_4U)
2588 pmd_val(pmd) |= PMD_HUGE_ACCESSED;
2589 if (pgprot_val(pgprot) & _PAGE_MODIFIED_4U)
2590 pmd_val(pmd) |= PMD_HUGE_DIRTY;
2591 }
2592 }
2593
2594 return pmd;
2595 }
2596
2597 pmd_t pfn_pmd(unsigned long page_nr, pgprot_t pgprot)
2598 {
2599 pmd_t pmd;
2600
2601 pmd_val(pmd) = (page_nr << ((PAGE_SHIFT - PMD_PADDR_SHIFT)));
2602 pmd_val(pmd) |= PMD_ISHUGE;
2603 pmd = pmd_set_protbits(pmd, pgprot, false);
2604 return pmd;
2605 }
2606
2607 pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
2608 {
2609 pmd_val(pmd) &= ~(PMD_HUGE_PRESENT |
2610 PMD_HUGE_WRITE |
2611 PMD_HUGE_EXEC);
2612 pmd = pmd_set_protbits(pmd, newprot, true);
2613 return pmd;
2614 }
2615
2616 pgprot_t pmd_pgprot(pmd_t entry)
2617 {
2618 unsigned long pte = 0;
2619
2620 if (pmd_val(entry) & PMD_HUGE_PRESENT)
2621 pte |= _PAGE_VALID;
2622
2623 if (tlb_type == hypervisor) {
2624 if (pmd_val(entry) & PMD_HUGE_PRESENT)
2625 pte |= _PAGE_PRESENT_4V;
2626 if (pmd_val(entry) & PMD_HUGE_EXEC)
2627 pte |= _PAGE_EXEC_4V;
2628 if (pmd_val(entry) & PMD_HUGE_WRITE)
2629 pte |= _PAGE_W_4V;
2630 if (pmd_val(entry) & PMD_HUGE_ACCESSED)
2631 pte |= _PAGE_ACCESSED_4V;
2632 if (pmd_val(entry) & PMD_HUGE_DIRTY)
2633 pte |= _PAGE_MODIFIED_4V;
2634 pte |= _PAGE_CP_4V|_PAGE_CV_4V;
2635 } else {
2636 if (pmd_val(entry) & PMD_HUGE_PRESENT)
2637 pte |= _PAGE_PRESENT_4U;
2638 if (pmd_val(entry) & PMD_HUGE_EXEC)
2639 pte |= _PAGE_EXEC_4U;
2640 if (pmd_val(entry) & PMD_HUGE_WRITE)
2641 pte |= _PAGE_W_4U;
2642 if (pmd_val(entry) & PMD_HUGE_ACCESSED)
2643 pte |= _PAGE_ACCESSED_4U;
2644 if (pmd_val(entry) & PMD_HUGE_DIRTY)
2645 pte |= _PAGE_MODIFIED_4U;
2646 pte |= _PAGE_CP_4U|_PAGE_CV_4U;
2647 }
2648
2649 return __pgprot(pte);
2650 }
2651
2652 void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
2653 pmd_t *pmd)
2654 {
2655 unsigned long pte, flags;
2656 struct mm_struct *mm;
2657 pmd_t entry = *pmd;
2658 pgprot_t prot;
2659
2660 if (!pmd_large(entry) || !pmd_young(entry))
2661 return;
2662
2663 pte = (pmd_val(entry) & ~PMD_HUGE_PROTBITS);
2664 pte <<= PMD_PADDR_SHIFT;
2665 pte |= _PAGE_VALID;
2666
2667 prot = pmd_pgprot(entry);
2668
2669 if (tlb_type == hypervisor)
2670 pgprot_val(prot) |= _PAGE_SZHUGE_4V;
2671 else
2672 pgprot_val(prot) |= _PAGE_SZHUGE_4U;
2673
2674 pte |= pgprot_val(prot);
2675
2676 mm = vma->vm_mm;
2677
2678 spin_lock_irqsave(&mm->context.lock, flags);
2679
2680 if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL)
2681 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, HPAGE_SHIFT,
2682 addr, pte);
2683
2684 spin_unlock_irqrestore(&mm->context.lock, flags);
2685 }
2686 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
2687
2688 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
2689 static void context_reload(void *__data)
2690 {
2691 struct mm_struct *mm = __data;
2692
2693 if (mm == current->mm)
2694 load_secondary_context(mm);
2695 }
2696
2697 void hugetlb_setup(struct pt_regs *regs)
2698 {
2699 struct mm_struct *mm = current->mm;
2700 struct tsb_config *tp;
2701
2702 if (in_atomic() || !mm) {
2703 const struct exception_table_entry *entry;
2704
2705 entry = search_exception_tables(regs->tpc);
2706 if (entry) {
2707 regs->tpc = entry->fixup;
2708 regs->tnpc = regs->tpc + 4;
2709 return;
2710 }
2711 pr_alert("Unexpected HugeTLB setup in atomic context.\n");
2712 die_if_kernel("HugeTSB in atomic", regs);
2713 }
2714
2715 tp = &mm->context.tsb_block[MM_TSB_HUGE];
2716 if (likely(tp->tsb == NULL))
2717 tsb_grow(mm, MM_TSB_HUGE, 0);
2718
2719 tsb_context_switch(mm);
2720 smp_tsb_sync(mm);
2721
2722 /* On UltraSPARC-III+ and later, configure the second half of
2723 * the Data-TLB for huge pages.
2724 */
2725 if (tlb_type == cheetah_plus) {
2726 unsigned long ctx;
2727
2728 spin_lock(&ctx_alloc_lock);
2729 ctx = mm->context.sparc64_ctx_val;
2730 ctx &= ~CTX_PGSZ_MASK;
2731 ctx |= CTX_PGSZ_BASE << CTX_PGSZ0_SHIFT;
2732 ctx |= CTX_PGSZ_HUGE << CTX_PGSZ1_SHIFT;
2733
2734 if (ctx != mm->context.sparc64_ctx_val) {
2735 /* When changing the page size fields, we
2736 * must perform a context flush so that no
2737 * stale entries match. This flush must
2738 * occur with the original context register
2739 * settings.
2740 */
2741 do_flush_tlb_mm(mm);
2742
2743 /* Reload the context register of all processors
2744 * also executing in this address space.
2745 */
2746 mm->context.sparc64_ctx_val = ctx;
2747 on_each_cpu(context_reload, mm, 0);
2748 }
2749 spin_unlock(&ctx_alloc_lock);
2750 }
2751 }
2752 #endif
2753
2754 #ifdef CONFIG_SMP
2755 #define do_flush_tlb_kernel_range smp_flush_tlb_kernel_range
2756 #else
2757 #define do_flush_tlb_kernel_range __flush_tlb_kernel_range
2758 #endif
2759
2760 void flush_tlb_kernel_range(unsigned long start, unsigned long end)
2761 {
2762 if (start < HI_OBP_ADDRESS && end > LOW_OBP_ADDRESS) {
2763 if (start < LOW_OBP_ADDRESS) {
2764 flush_tsb_kernel_range(start, LOW_OBP_ADDRESS);
2765 do_flush_tlb_kernel_range(start, LOW_OBP_ADDRESS);
2766 }
2767 if (end > HI_OBP_ADDRESS) {
2768 flush_tsb_kernel_range(end, HI_OBP_ADDRESS);
2769 do_flush_tlb_kernel_range(end, HI_OBP_ADDRESS);
2770 }
2771 } else {
2772 flush_tsb_kernel_range(start, end);
2773 do_flush_tlb_kernel_range(start, end);
2774 }
2775 }
Linux with added FPC-III support