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Merge tag 'for-linus-20190706' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / iio / adc / ti-ads1015.c
bloba550b132cfb7347ada13ecd210a034f865463690
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * ADS1015 - Texas Instruments Analog-to-Digital Converter
4 *
5 * Copyright (c) 2016, Intel Corporation.
6 *
7 * IIO driver for ADS1015 ADC 7-bit I2C slave address:
8 * * 0x48 - ADDR connected to Ground
9 * * 0x49 - ADDR connected to Vdd
10 * * 0x4A - ADDR connected to SDA
11 * * 0x4B - ADDR connected to SCL
12 */
13
14 #include <linux/module.h>
15 #include <linux/of_device.h>
16 #include <linux/init.h>
17 #include <linux/irq.h>
18 #include <linux/i2c.h>
19 #include <linux/regmap.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/mutex.h>
22 #include <linux/delay.h>
23
24 #include <linux/platform_data/ads1015.h>
25
26 #include <linux/iio/iio.h>
27 #include <linux/iio/types.h>
28 #include <linux/iio/sysfs.h>
29 #include <linux/iio/events.h>
30 #include <linux/iio/buffer.h>
31 #include <linux/iio/triggered_buffer.h>
32 #include <linux/iio/trigger_consumer.h>
33
34 #define ADS1015_DRV_NAME "ads1015"
35
36 #define ADS1015_CONV_REG 0x00
37 #define ADS1015_CFG_REG 0x01
38 #define ADS1015_LO_THRESH_REG 0x02
39 #define ADS1015_HI_THRESH_REG 0x03
40
41 #define ADS1015_CFG_COMP_QUE_SHIFT 0
42 #define ADS1015_CFG_COMP_LAT_SHIFT 2
43 #define ADS1015_CFG_COMP_POL_SHIFT 3
44 #define ADS1015_CFG_COMP_MODE_SHIFT 4
45 #define ADS1015_CFG_DR_SHIFT 5
46 #define ADS1015_CFG_MOD_SHIFT 8
47 #define ADS1015_CFG_PGA_SHIFT 9
48 #define ADS1015_CFG_MUX_SHIFT 12
49
50 #define ADS1015_CFG_COMP_QUE_MASK GENMASK(1, 0)
51 #define ADS1015_CFG_COMP_LAT_MASK BIT(2)
52 #define ADS1015_CFG_COMP_POL_MASK BIT(3)
53 #define ADS1015_CFG_COMP_MODE_MASK BIT(4)
54 #define ADS1015_CFG_DR_MASK GENMASK(7, 5)
55 #define ADS1015_CFG_MOD_MASK BIT(8)
56 #define ADS1015_CFG_PGA_MASK GENMASK(11, 9)
57 #define ADS1015_CFG_MUX_MASK GENMASK(14, 12)
58
59 /* Comparator queue and disable field */
60 #define ADS1015_CFG_COMP_DISABLE 3
61
62 /* Comparator polarity field */
63 #define ADS1015_CFG_COMP_POL_LOW 0
64 #define ADS1015_CFG_COMP_POL_HIGH 1
65
66 /* Comparator mode field */
67 #define ADS1015_CFG_COMP_MODE_TRAD 0
68 #define ADS1015_CFG_COMP_MODE_WINDOW 1
69
70 /* device operating modes */
71 #define ADS1015_CONTINUOUS 0
72 #define ADS1015_SINGLESHOT 1
73
74 #define ADS1015_SLEEP_DELAY_MS 2000
75 #define ADS1015_DEFAULT_PGA 2
76 #define ADS1015_DEFAULT_DATA_RATE 4
77 #define ADS1015_DEFAULT_CHAN 0
78
79 enum chip_ids {
80 ADS1015,
81 ADS1115,
82 };
83
84 enum ads1015_channels {
85 ADS1015_AIN0_AIN1 = 0,
86 ADS1015_AIN0_AIN3,
87 ADS1015_AIN1_AIN3,
88 ADS1015_AIN2_AIN3,
89 ADS1015_AIN0,
90 ADS1015_AIN1,
91 ADS1015_AIN2,
92 ADS1015_AIN3,
93 ADS1015_TIMESTAMP,
94 };
95
96 static const unsigned int ads1015_data_rate[] = {
97 128, 250, 490, 920, 1600, 2400, 3300, 3300
98 };
99
100 static const unsigned int ads1115_data_rate[] = {
101 8, 16, 32, 64, 128, 250, 475, 860
102 };
103
104 /*
105 * Translation from PGA bits to full-scale positive and negative input voltage
106 * range in mV
107 */
108 static int ads1015_fullscale_range[] = {
109 6144, 4096, 2048, 1024, 512, 256, 256, 256
110 };
111
112 /*
113 * Translation from COMP_QUE field value to the number of successive readings
114 * exceed the threshold values before an interrupt is generated
115 */
116 static const int ads1015_comp_queue[] = { 1, 2, 4 };
117
118 static const struct iio_event_spec ads1015_events[] = {
119 {
120 .type = IIO_EV_TYPE_THRESH,
121 .dir = IIO_EV_DIR_RISING,
122 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
123 BIT(IIO_EV_INFO_ENABLE),
124 }, {
125 .type = IIO_EV_TYPE_THRESH,
126 .dir = IIO_EV_DIR_FALLING,
127 .mask_separate = BIT(IIO_EV_INFO_VALUE),
128 }, {
129 .type = IIO_EV_TYPE_THRESH,
130 .dir = IIO_EV_DIR_EITHER,
131 .mask_separate = BIT(IIO_EV_INFO_ENABLE) |
132 BIT(IIO_EV_INFO_PERIOD),
133 },
134 };
135
136 #define ADS1015_V_CHAN(_chan, _addr) { \
137 .type = IIO_VOLTAGE, \
138 .indexed = 1, \
139 .address = _addr, \
140 .channel = _chan, \
141 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
142 BIT(IIO_CHAN_INFO_SCALE) | \
143 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
144 .scan_index = _addr, \
145 .scan_type = { \
146 .sign = 's', \
147 .realbits = 12, \
148 .storagebits = 16, \
149 .shift = 4, \
150 .endianness = IIO_CPU, \
151 }, \
152 .event_spec = ads1015_events, \
153 .num_event_specs = ARRAY_SIZE(ads1015_events), \
154 .datasheet_name = "AIN"#_chan, \
155 }
156
157 #define ADS1015_V_DIFF_CHAN(_chan, _chan2, _addr) { \
158 .type = IIO_VOLTAGE, \
159 .differential = 1, \
160 .indexed = 1, \
161 .address = _addr, \
162 .channel = _chan, \
163 .channel2 = _chan2, \
164 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
165 BIT(IIO_CHAN_INFO_SCALE) | \
166 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
167 .scan_index = _addr, \
168 .scan_type = { \
169 .sign = 's', \
170 .realbits = 12, \
171 .storagebits = 16, \
172 .shift = 4, \
173 .endianness = IIO_CPU, \
174 }, \
175 .event_spec = ads1015_events, \
176 .num_event_specs = ARRAY_SIZE(ads1015_events), \
177 .datasheet_name = "AIN"#_chan"-AIN"#_chan2, \
178 }
179
180 #define ADS1115_V_CHAN(_chan, _addr) { \
181 .type = IIO_VOLTAGE, \
182 .indexed = 1, \
183 .address = _addr, \
184 .channel = _chan, \
185 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
186 BIT(IIO_CHAN_INFO_SCALE) | \
187 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
188 .scan_index = _addr, \
189 .scan_type = { \
190 .sign = 's', \
191 .realbits = 16, \
192 .storagebits = 16, \
193 .endianness = IIO_CPU, \
194 }, \
195 .event_spec = ads1015_events, \
196 .num_event_specs = ARRAY_SIZE(ads1015_events), \
197 .datasheet_name = "AIN"#_chan, \
198 }
199
200 #define ADS1115_V_DIFF_CHAN(_chan, _chan2, _addr) { \
201 .type = IIO_VOLTAGE, \
202 .differential = 1, \
203 .indexed = 1, \
204 .address = _addr, \
205 .channel = _chan, \
206 .channel2 = _chan2, \
207 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
208 BIT(IIO_CHAN_INFO_SCALE) | \
209 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
210 .scan_index = _addr, \
211 .scan_type = { \
212 .sign = 's', \
213 .realbits = 16, \
214 .storagebits = 16, \
215 .endianness = IIO_CPU, \
216 }, \
217 .event_spec = ads1015_events, \
218 .num_event_specs = ARRAY_SIZE(ads1015_events), \
219 .datasheet_name = "AIN"#_chan"-AIN"#_chan2, \
220 }
221
222 struct ads1015_thresh_data {
223 unsigned int comp_queue;
224 int high_thresh;
225 int low_thresh;
226 };
227
228 struct ads1015_data {
229 struct regmap *regmap;
230 /*
231 * Protects ADC ops, e.g: concurrent sysfs/buffered
232 * data reads, configuration updates
233 */
234 struct mutex lock;
235 struct ads1015_channel_data channel_data[ADS1015_CHANNELS];
236
237 unsigned int event_channel;
238 unsigned int comp_mode;
239 struct ads1015_thresh_data thresh_data[ADS1015_CHANNELS];
240
241 unsigned int *data_rate;
242 /*
243 * Set to true when the ADC is switched to the continuous-conversion
244 * mode and exits from a power-down state. This flag is used to avoid
245 * getting the stale result from the conversion register.
246 */
247 bool conv_invalid;
248 };
249
250 static bool ads1015_event_channel_enabled(struct ads1015_data *data)
251 {
252 return (data->event_channel != ADS1015_CHANNELS);
253 }
254
255 static void ads1015_event_channel_enable(struct ads1015_data *data, int chan,
256 int comp_mode)
257 {
258 WARN_ON(ads1015_event_channel_enabled(data));
259
260 data->event_channel = chan;
261 data->comp_mode = comp_mode;
262 }
263
264 static void ads1015_event_channel_disable(struct ads1015_data *data, int chan)
265 {
266 data->event_channel = ADS1015_CHANNELS;
267 }
268
269 static bool ads1015_is_writeable_reg(struct device *dev, unsigned int reg)
270 {
271 switch (reg) {
272 case ADS1015_CFG_REG:
273 case ADS1015_LO_THRESH_REG:
274 case ADS1015_HI_THRESH_REG:
275 return true;
276 default:
277 return false;
278 }
279 }
280
281 static const struct regmap_config ads1015_regmap_config = {
282 .reg_bits = 8,
283 .val_bits = 16,
284 .max_register = ADS1015_HI_THRESH_REG,
285 .writeable_reg = ads1015_is_writeable_reg,
286 };
287
288 static const struct iio_chan_spec ads1015_channels[] = {
289 ADS1015_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1),
290 ADS1015_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3),
291 ADS1015_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3),
292 ADS1015_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3),
293 ADS1015_V_CHAN(0, ADS1015_AIN0),
294 ADS1015_V_CHAN(1, ADS1015_AIN1),
295 ADS1015_V_CHAN(2, ADS1015_AIN2),
296 ADS1015_V_CHAN(3, ADS1015_AIN3),
297 IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP),
298 };
299
300 static const struct iio_chan_spec ads1115_channels[] = {
301 ADS1115_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1),
302 ADS1115_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3),
303 ADS1115_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3),
304 ADS1115_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3),
305 ADS1115_V_CHAN(0, ADS1015_AIN0),
306 ADS1115_V_CHAN(1, ADS1015_AIN1),
307 ADS1115_V_CHAN(2, ADS1015_AIN2),
308 ADS1115_V_CHAN(3, ADS1015_AIN3),
309 IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP),
310 };
311
312 static int ads1015_set_power_state(struct ads1015_data *data, bool on)
313 {
314 int ret;
315 struct device *dev = regmap_get_device(data->regmap);
316
317 if (on) {
318 ret = pm_runtime_get_sync(dev);
319 if (ret < 0)
320 pm_runtime_put_noidle(dev);
321 } else {
322 pm_runtime_mark_last_busy(dev);
323 ret = pm_runtime_put_autosuspend(dev);
324 }
325
326 return ret < 0 ? ret : 0;
327 }
328
329 static
330 int ads1015_get_adc_result(struct ads1015_data *data, int chan, int *val)
331 {
332 int ret, pga, dr, dr_old, conv_time;
333 unsigned int old, mask, cfg;
334
335 if (chan < 0 || chan >= ADS1015_CHANNELS)
336 return -EINVAL;
337
338 ret = regmap_read(data->regmap, ADS1015_CFG_REG, &old);
339 if (ret)
340 return ret;
341
342 pga = data->channel_data[chan].pga;
343 dr = data->channel_data[chan].data_rate;
344 mask = ADS1015_CFG_MUX_MASK | ADS1015_CFG_PGA_MASK |
345 ADS1015_CFG_DR_MASK;
346 cfg = chan << ADS1015_CFG_MUX_SHIFT | pga << ADS1015_CFG_PGA_SHIFT |
347 dr << ADS1015_CFG_DR_SHIFT;
348
349 if (ads1015_event_channel_enabled(data)) {
350 mask |= ADS1015_CFG_COMP_QUE_MASK | ADS1015_CFG_COMP_MODE_MASK;
351 cfg |= data->thresh_data[chan].comp_queue <<
352 ADS1015_CFG_COMP_QUE_SHIFT |
353 data->comp_mode <<
354 ADS1015_CFG_COMP_MODE_SHIFT;
355 }
356
357 cfg = (old & ~mask) | (cfg & mask);
358 if (old != cfg) {
359 ret = regmap_write(data->regmap, ADS1015_CFG_REG, cfg);
360 if (ret)
361 return ret;
362 data->conv_invalid = true;
363 }
364 if (data->conv_invalid) {
365 dr_old = (old & ADS1015_CFG_DR_MASK) >> ADS1015_CFG_DR_SHIFT;
366 conv_time = DIV_ROUND_UP(USEC_PER_SEC, data->data_rate[dr_old]);
367 conv_time += DIV_ROUND_UP(USEC_PER_SEC, data->data_rate[dr]);
368 conv_time += conv_time / 10; /* 10% internal clock inaccuracy */
369 usleep_range(conv_time, conv_time + 1);
370 data->conv_invalid = false;
371 }
372
373 return regmap_read(data->regmap, ADS1015_CONV_REG, val);
374 }
375
376 static irqreturn_t ads1015_trigger_handler(int irq, void *p)
377 {
378 struct iio_poll_func *pf = p;
379 struct iio_dev *indio_dev = pf->indio_dev;
380 struct ads1015_data *data = iio_priv(indio_dev);
381 s16 buf[8]; /* 1x s16 ADC val + 3x s16 padding + 4x s16 timestamp */
382 int chan, ret, res;
383
384 memset(buf, 0, sizeof(buf));
385
386 mutex_lock(&data->lock);
387 chan = find_first_bit(indio_dev->active_scan_mask,
388 indio_dev->masklength);
389 ret = ads1015_get_adc_result(data, chan, &res);
390 if (ret < 0) {
391 mutex_unlock(&data->lock);
392 goto err;
393 }
394
395 buf[0] = res;
396 mutex_unlock(&data->lock);
397
398 iio_push_to_buffers_with_timestamp(indio_dev, buf,
399 iio_get_time_ns(indio_dev));
400
401 err:
402 iio_trigger_notify_done(indio_dev->trig);
403
404 return IRQ_HANDLED;
405 }
406
407 static int ads1015_set_scale(struct ads1015_data *data,
408 struct iio_chan_spec const *chan,
409 int scale, int uscale)
410 {
411 int i;
412 int fullscale = div_s64((scale * 1000000LL + uscale) <<
413 (chan->scan_type.realbits - 1), 1000000);
414
415 for (i = 0; i < ARRAY_SIZE(ads1015_fullscale_range); i++) {
416 if (ads1015_fullscale_range[i] == fullscale) {
417 data->channel_data[chan->address].pga = i;
418 return 0;
419 }
420 }
421
422 return -EINVAL;
423 }
424
425 static int ads1015_set_data_rate(struct ads1015_data *data, int chan, int rate)
426 {
427 int i;
428
429 for (i = 0; i < ARRAY_SIZE(ads1015_data_rate); i++) {
430 if (data->data_rate[i] == rate) {
431 data->channel_data[chan].data_rate = i;
432 return 0;
433 }
434 }
435
436 return -EINVAL;
437 }
438
439 static int ads1015_read_raw(struct iio_dev *indio_dev,
440 struct iio_chan_spec const *chan, int *val,
441 int *val2, long mask)
442 {
443 int ret, idx;
444 struct ads1015_data *data = iio_priv(indio_dev);
445
446 mutex_lock(&data->lock);
447 switch (mask) {
448 case IIO_CHAN_INFO_RAW: {
449 int shift = chan->scan_type.shift;
450
451 ret = iio_device_claim_direct_mode(indio_dev);
452 if (ret)
453 break;
454
455 if (ads1015_event_channel_enabled(data) &&
456 data->event_channel != chan->address) {
457 ret = -EBUSY;
458 goto release_direct;
459 }
460
461 ret = ads1015_set_power_state(data, true);
462 if (ret < 0)
463 goto release_direct;
464
465 ret = ads1015_get_adc_result(data, chan->address, val);
466 if (ret < 0) {
467 ads1015_set_power_state(data, false);
468 goto release_direct;
469 }
470
471 *val = sign_extend32(*val >> shift, 15 - shift);
472
473 ret = ads1015_set_power_state(data, false);
474 if (ret < 0)
475 goto release_direct;
476
477 ret = IIO_VAL_INT;
478 release_direct:
479 iio_device_release_direct_mode(indio_dev);
480 break;
481 }
482 case IIO_CHAN_INFO_SCALE:
483 idx = data->channel_data[chan->address].pga;
484 *val = ads1015_fullscale_range[idx];
485 *val2 = chan->scan_type.realbits - 1;
486 ret = IIO_VAL_FRACTIONAL_LOG2;
487 break;
488 case IIO_CHAN_INFO_SAMP_FREQ:
489 idx = data->channel_data[chan->address].data_rate;
490 *val = data->data_rate[idx];
491 ret = IIO_VAL_INT;
492 break;
493 default:
494 ret = -EINVAL;
495 break;
496 }
497 mutex_unlock(&data->lock);
498
499 return ret;
500 }
501
502 static int ads1015_write_raw(struct iio_dev *indio_dev,
503 struct iio_chan_spec const *chan, int val,
504 int val2, long mask)
505 {
506 struct ads1015_data *data = iio_priv(indio_dev);
507 int ret;
508
509 mutex_lock(&data->lock);
510 switch (mask) {
511 case IIO_CHAN_INFO_SCALE:
512 ret = ads1015_set_scale(data, chan, val, val2);
513 break;
514 case IIO_CHAN_INFO_SAMP_FREQ:
515 ret = ads1015_set_data_rate(data, chan->address, val);
516 break;
517 default:
518 ret = -EINVAL;
519 break;
520 }
521 mutex_unlock(&data->lock);
522
523 return ret;
524 }
525
526 static int ads1015_read_event(struct iio_dev *indio_dev,
527 const struct iio_chan_spec *chan, enum iio_event_type type,
528 enum iio_event_direction dir, enum iio_event_info info, int *val,
529 int *val2)
530 {
531 struct ads1015_data *data = iio_priv(indio_dev);
532 int ret;
533 unsigned int comp_queue;
534 int period;
535 int dr;
536
537 mutex_lock(&data->lock);
538
539 switch (info) {
540 case IIO_EV_INFO_VALUE:
541 *val = (dir == IIO_EV_DIR_RISING) ?
542 data->thresh_data[chan->address].high_thresh :
543 data->thresh_data[chan->address].low_thresh;
544 ret = IIO_VAL_INT;
545 break;
546 case IIO_EV_INFO_PERIOD:
547 dr = data->channel_data[chan->address].data_rate;
548 comp_queue = data->thresh_data[chan->address].comp_queue;
549 period = ads1015_comp_queue[comp_queue] *
550 USEC_PER_SEC / data->data_rate[dr];
551
552 *val = period / USEC_PER_SEC;
553 *val2 = period % USEC_PER_SEC;
554 ret = IIO_VAL_INT_PLUS_MICRO;
555 break;
556 default:
557 ret = -EINVAL;
558 break;
559 }
560
561 mutex_unlock(&data->lock);
562
563 return ret;
564 }
565
566 static int ads1015_write_event(struct iio_dev *indio_dev,
567 const struct iio_chan_spec *chan, enum iio_event_type type,
568 enum iio_event_direction dir, enum iio_event_info info, int val,
569 int val2)
570 {
571 struct ads1015_data *data = iio_priv(indio_dev);
572 int realbits = chan->scan_type.realbits;
573 int ret = 0;
574 long long period;
575 int i;
576 int dr;
577
578 mutex_lock(&data->lock);
579
580 switch (info) {
581 case IIO_EV_INFO_VALUE:
582 if (val >= 1 << (realbits - 1) || val < -1 << (realbits - 1)) {
583 ret = -EINVAL;
584 break;
585 }
586 if (dir == IIO_EV_DIR_RISING)
587 data->thresh_data[chan->address].high_thresh = val;
588 else
589 data->thresh_data[chan->address].low_thresh = val;
590 break;
591 case IIO_EV_INFO_PERIOD:
592 dr = data->channel_data[chan->address].data_rate;
593 period = val * USEC_PER_SEC + val2;
594
595 for (i = 0; i < ARRAY_SIZE(ads1015_comp_queue) - 1; i++) {
596 if (period <= ads1015_comp_queue[i] *
597 USEC_PER_SEC / data->data_rate[dr])
598 break;
599 }
600 data->thresh_data[chan->address].comp_queue = i;
601 break;
602 default:
603 ret = -EINVAL;
604 break;
605 }
606
607 mutex_unlock(&data->lock);
608
609 return ret;
610 }
611
612 static int ads1015_read_event_config(struct iio_dev *indio_dev,
613 const struct iio_chan_spec *chan, enum iio_event_type type,
614 enum iio_event_direction dir)
615 {
616 struct ads1015_data *data = iio_priv(indio_dev);
617 int ret = 0;
618
619 mutex_lock(&data->lock);
620 if (data->event_channel == chan->address) {
621 switch (dir) {
622 case IIO_EV_DIR_RISING:
623 ret = 1;
624 break;
625 case IIO_EV_DIR_EITHER:
626 ret = (data->comp_mode == ADS1015_CFG_COMP_MODE_WINDOW);
627 break;
628 default:
629 ret = -EINVAL;
630 break;
631 }
632 }
633 mutex_unlock(&data->lock);
634
635 return ret;
636 }
637
638 static int ads1015_enable_event_config(struct ads1015_data *data,
639 const struct iio_chan_spec *chan, int comp_mode)
640 {
641 int low_thresh = data->thresh_data[chan->address].low_thresh;
642 int high_thresh = data->thresh_data[chan->address].high_thresh;
643 int ret;
644 unsigned int val;
645
646 if (ads1015_event_channel_enabled(data)) {
647 if (data->event_channel != chan->address ||
648 (data->comp_mode == ADS1015_CFG_COMP_MODE_TRAD &&
649 comp_mode == ADS1015_CFG_COMP_MODE_WINDOW))
650 return -EBUSY;
651
652 return 0;
653 }
654
655 if (comp_mode == ADS1015_CFG_COMP_MODE_TRAD) {
656 low_thresh = max(-1 << (chan->scan_type.realbits - 1),
657 high_thresh - 1);
658 }
659 ret = regmap_write(data->regmap, ADS1015_LO_THRESH_REG,
660 low_thresh << chan->scan_type.shift);
661 if (ret)
662 return ret;
663
664 ret = regmap_write(data->regmap, ADS1015_HI_THRESH_REG,
665 high_thresh << chan->scan_type.shift);
666 if (ret)
667 return ret;
668
669 ret = ads1015_set_power_state(data, true);
670 if (ret < 0)
671 return ret;
672
673 ads1015_event_channel_enable(data, chan->address, comp_mode);
674
675 ret = ads1015_get_adc_result(data, chan->address, &val);
676 if (ret) {
677 ads1015_event_channel_disable(data, chan->address);
678 ads1015_set_power_state(data, false);
679 }
680
681 return ret;
682 }
683
684 static int ads1015_disable_event_config(struct ads1015_data *data,
685 const struct iio_chan_spec *chan, int comp_mode)
686 {
687 int ret;
688
689 if (!ads1015_event_channel_enabled(data))
690 return 0;
691
692 if (data->event_channel != chan->address)
693 return 0;
694
695 if (data->comp_mode == ADS1015_CFG_COMP_MODE_TRAD &&
696 comp_mode == ADS1015_CFG_COMP_MODE_WINDOW)
697 return 0;
698
699 ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG,
700 ADS1015_CFG_COMP_QUE_MASK,
701 ADS1015_CFG_COMP_DISABLE <<
702 ADS1015_CFG_COMP_QUE_SHIFT);
703 if (ret)
704 return ret;
705
706 ads1015_event_channel_disable(data, chan->address);
707
708 return ads1015_set_power_state(data, false);
709 }
710
711 static int ads1015_write_event_config(struct iio_dev *indio_dev,
712 const struct iio_chan_spec *chan, enum iio_event_type type,
713 enum iio_event_direction dir, int state)
714 {
715 struct ads1015_data *data = iio_priv(indio_dev);
716 int ret;
717 int comp_mode = (dir == IIO_EV_DIR_EITHER) ?
718 ADS1015_CFG_COMP_MODE_WINDOW : ADS1015_CFG_COMP_MODE_TRAD;
719
720 mutex_lock(&data->lock);
721
722 /* Prevent from enabling both buffer and event at a time */
723 ret = iio_device_claim_direct_mode(indio_dev);
724 if (ret) {
725 mutex_unlock(&data->lock);
726 return ret;
727 }
728
729 if (state)
730 ret = ads1015_enable_event_config(data, chan, comp_mode);
731 else
732 ret = ads1015_disable_event_config(data, chan, comp_mode);
733
734 iio_device_release_direct_mode(indio_dev);
735 mutex_unlock(&data->lock);
736
737 return ret;
738 }
739
740 static irqreturn_t ads1015_event_handler(int irq, void *priv)
741 {
742 struct iio_dev *indio_dev = priv;
743 struct ads1015_data *data = iio_priv(indio_dev);
744 int val;
745 int ret;
746
747 /* Clear the latched ALERT/RDY pin */
748 ret = regmap_read(data->regmap, ADS1015_CONV_REG, &val);
749 if (ret)
750 return IRQ_HANDLED;
751
752 if (ads1015_event_channel_enabled(data)) {
753 enum iio_event_direction dir;
754 u64 code;
755
756 dir = data->comp_mode == ADS1015_CFG_COMP_MODE_TRAD ?
757 IIO_EV_DIR_RISING : IIO_EV_DIR_EITHER;
758 code = IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, data->event_channel,
759 IIO_EV_TYPE_THRESH, dir);
760 iio_push_event(indio_dev, code, iio_get_time_ns(indio_dev));
761 }
762
763 return IRQ_HANDLED;
764 }
765
766 static int ads1015_buffer_preenable(struct iio_dev *indio_dev)
767 {
768 struct ads1015_data *data = iio_priv(indio_dev);
769
770 /* Prevent from enabling both buffer and event at a time */
771 if (ads1015_event_channel_enabled(data))
772 return -EBUSY;
773
774 return ads1015_set_power_state(iio_priv(indio_dev), true);
775 }
776
777 static int ads1015_buffer_postdisable(struct iio_dev *indio_dev)
778 {
779 return ads1015_set_power_state(iio_priv(indio_dev), false);
780 }
781
782 static const struct iio_buffer_setup_ops ads1015_buffer_setup_ops = {
783 .preenable = ads1015_buffer_preenable,
784 .postenable = iio_triggered_buffer_postenable,
785 .predisable = iio_triggered_buffer_predisable,
786 .postdisable = ads1015_buffer_postdisable,
787 .validate_scan_mask = &iio_validate_scan_mask_onehot,
788 };
789
790 static IIO_CONST_ATTR_NAMED(ads1015_scale_available, scale_available,
791 "3 2 1 0.5 0.25 0.125");
792 static IIO_CONST_ATTR_NAMED(ads1115_scale_available, scale_available,
793 "0.1875 0.125 0.0625 0.03125 0.015625 0.007813");
794
795 static IIO_CONST_ATTR_NAMED(ads1015_sampling_frequency_available,
796 sampling_frequency_available, "128 250 490 920 1600 2400 3300");
797 static IIO_CONST_ATTR_NAMED(ads1115_sampling_frequency_available,
798 sampling_frequency_available, "8 16 32 64 128 250 475 860");
799
800 static struct attribute *ads1015_attributes[] = {
801 &iio_const_attr_ads1015_scale_available.dev_attr.attr,
802 &iio_const_attr_ads1015_sampling_frequency_available.dev_attr.attr,
803 NULL,
804 };
805
806 static const struct attribute_group ads1015_attribute_group = {
807 .attrs = ads1015_attributes,
808 };
809
810 static struct attribute *ads1115_attributes[] = {
811 &iio_const_attr_ads1115_scale_available.dev_attr.attr,
812 &iio_const_attr_ads1115_sampling_frequency_available.dev_attr.attr,
813 NULL,
814 };
815
816 static const struct attribute_group ads1115_attribute_group = {
817 .attrs = ads1115_attributes,
818 };
819
820 static const struct iio_info ads1015_info = {
821 .read_raw = ads1015_read_raw,
822 .write_raw = ads1015_write_raw,
823 .read_event_value = ads1015_read_event,
824 .write_event_value = ads1015_write_event,
825 .read_event_config = ads1015_read_event_config,
826 .write_event_config = ads1015_write_event_config,
827 .attrs = &ads1015_attribute_group,
828 };
829
830 static const struct iio_info ads1115_info = {
831 .read_raw = ads1015_read_raw,
832 .write_raw = ads1015_write_raw,
833 .read_event_value = ads1015_read_event,
834 .write_event_value = ads1015_write_event,
835 .read_event_config = ads1015_read_event_config,
836 .write_event_config = ads1015_write_event_config,
837 .attrs = &ads1115_attribute_group,
838 };
839
840 #ifdef CONFIG_OF
841 static int ads1015_get_channels_config_of(struct i2c_client *client)
842 {
843 struct iio_dev *indio_dev = i2c_get_clientdata(client);
844 struct ads1015_data *data = iio_priv(indio_dev);
845 struct device_node *node;
846
847 if (!client->dev.of_node ||
848 !of_get_next_child(client->dev.of_node, NULL))
849 return -EINVAL;
850
851 for_each_child_of_node(client->dev.of_node, node) {
852 u32 pval;
853 unsigned int channel;
854 unsigned int pga = ADS1015_DEFAULT_PGA;
855 unsigned int data_rate = ADS1015_DEFAULT_DATA_RATE;
856
857 if (of_property_read_u32(node, "reg", &pval)) {
858 dev_err(&client->dev, "invalid reg on %pOF\n",
859 node);
860 continue;
861 }
862
863 channel = pval;
864 if (channel >= ADS1015_CHANNELS) {
865 dev_err(&client->dev,
866 "invalid channel index %d on %pOF\n",
867 channel, node);
868 continue;
869 }
870
871 if (!of_property_read_u32(node, "ti,gain", &pval)) {
872 pga = pval;
873 if (pga > 6) {
874 dev_err(&client->dev, "invalid gain on %pOF\n",
875 node);
876 of_node_put(node);
877 return -EINVAL;
878 }
879 }
880
881 if (!of_property_read_u32(node, "ti,datarate", &pval)) {
882 data_rate = pval;
883 if (data_rate > 7) {
884 dev_err(&client->dev,
885 "invalid data_rate on %pOF\n",
886 node);
887 of_node_put(node);
888 return -EINVAL;
889 }
890 }
891
892 data->channel_data[channel].pga = pga;
893 data->channel_data[channel].data_rate = data_rate;
894 }
895
896 return 0;
897 }
898 #endif
899
900 static void ads1015_get_channels_config(struct i2c_client *client)
901 {
902 unsigned int k;
903
904 struct iio_dev *indio_dev = i2c_get_clientdata(client);
905 struct ads1015_data *data = iio_priv(indio_dev);
906 struct ads1015_platform_data *pdata = dev_get_platdata(&client->dev);
907
908 /* prefer platform data */
909 if (pdata) {
910 memcpy(data->channel_data, pdata->channel_data,
911 sizeof(data->channel_data));
912 return;
913 }
914
915 #ifdef CONFIG_OF
916 if (!ads1015_get_channels_config_of(client))
917 return;
918 #endif
919 /* fallback on default configuration */
920 for (k = 0; k < ADS1015_CHANNELS; ++k) {
921 data->channel_data[k].pga = ADS1015_DEFAULT_PGA;
922 data->channel_data[k].data_rate = ADS1015_DEFAULT_DATA_RATE;
923 }
924 }
925
926 static int ads1015_set_conv_mode(struct ads1015_data *data, int mode)
927 {
928 return regmap_update_bits(data->regmap, ADS1015_CFG_REG,
929 ADS1015_CFG_MOD_MASK,
930 mode << ADS1015_CFG_MOD_SHIFT);
931 }
932
933 static int ads1015_probe(struct i2c_client *client,
934 const struct i2c_device_id *id)
935 {
936 struct iio_dev *indio_dev;
937 struct ads1015_data *data;
938 int ret;
939 enum chip_ids chip;
940 int i;
941
942 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
943 if (!indio_dev)
944 return -ENOMEM;
945
946 data = iio_priv(indio_dev);
947 i2c_set_clientdata(client, indio_dev);
948
949 mutex_init(&data->lock);
950
951 indio_dev->dev.parent = &client->dev;
952 indio_dev->dev.of_node = client->dev.of_node;
953 indio_dev->name = ADS1015_DRV_NAME;
954 indio_dev->modes = INDIO_DIRECT_MODE;
955
956 if (client->dev.of_node)
957 chip = (enum chip_ids)of_device_get_match_data(&client->dev);
958 else
959 chip = id->driver_data;
960 switch (chip) {
961 case ADS1015:
962 indio_dev->channels = ads1015_channels;
963 indio_dev->num_channels = ARRAY_SIZE(ads1015_channels);
964 indio_dev->info = &ads1015_info;
965 data->data_rate = (unsigned int *) &ads1015_data_rate;
966 break;
967 case ADS1115:
968 indio_dev->channels = ads1115_channels;
969 indio_dev->num_channels = ARRAY_SIZE(ads1115_channels);
970 indio_dev->info = &ads1115_info;
971 data->data_rate = (unsigned int *) &ads1115_data_rate;
972 break;
973 }
974
975 data->event_channel = ADS1015_CHANNELS;
976 /*
977 * Set default lower and upper threshold to min and max value
978 * respectively.
979 */
980 for (i = 0; i < ADS1015_CHANNELS; i++) {
981 int realbits = indio_dev->channels[i].scan_type.realbits;
982
983 data->thresh_data[i].low_thresh = -1 << (realbits - 1);
984 data->thresh_data[i].high_thresh = (1 << (realbits - 1)) - 1;
985 }
986
987 /* we need to keep this ABI the same as used by hwmon ADS1015 driver */
988 ads1015_get_channels_config(client);
989
990 data->regmap = devm_regmap_init_i2c(client, &ads1015_regmap_config);
991 if (IS_ERR(data->regmap)) {
992 dev_err(&client->dev, "Failed to allocate register map\n");
993 return PTR_ERR(data->regmap);
994 }
995
996 ret = devm_iio_triggered_buffer_setup(&client->dev, indio_dev, NULL,
997 ads1015_trigger_handler,
998 &ads1015_buffer_setup_ops);
999 if (ret < 0) {
1000 dev_err(&client->dev, "iio triggered buffer setup failed\n");
1001 return ret;
1002 }
1003
1004 if (client->irq) {
1005 unsigned long irq_trig =
1006 irqd_get_trigger_type(irq_get_irq_data(client->irq));
1007 unsigned int cfg_comp_mask = ADS1015_CFG_COMP_QUE_MASK |
1008 ADS1015_CFG_COMP_LAT_MASK | ADS1015_CFG_COMP_POL_MASK;
1009 unsigned int cfg_comp =
1010 ADS1015_CFG_COMP_DISABLE << ADS1015_CFG_COMP_QUE_SHIFT |
1011 1 << ADS1015_CFG_COMP_LAT_SHIFT;
1012
1013 switch (irq_trig) {
1014 case IRQF_TRIGGER_LOW:
1015 cfg_comp |= ADS1015_CFG_COMP_POL_LOW <<
1016 ADS1015_CFG_COMP_POL_SHIFT;
1017 break;
1018 case IRQF_TRIGGER_HIGH:
1019 cfg_comp |= ADS1015_CFG_COMP_POL_HIGH <<
1020 ADS1015_CFG_COMP_POL_SHIFT;
1021 break;
1022 default:
1023 return -EINVAL;
1024 }
1025
1026 ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG,
1027 cfg_comp_mask, cfg_comp);
1028 if (ret)
1029 return ret;
1030
1031 ret = devm_request_threaded_irq(&client->dev, client->irq,
1032 NULL, ads1015_event_handler,
1033 irq_trig | IRQF_ONESHOT,
1034 client->name, indio_dev);
1035 if (ret)
1036 return ret;
1037 }
1038
1039 ret = ads1015_set_conv_mode(data, ADS1015_CONTINUOUS);
1040 if (ret)
1041 return ret;
1042
1043 data->conv_invalid = true;
1044
1045 ret = pm_runtime_set_active(&client->dev);
1046 if (ret)
1047 return ret;
1048 pm_runtime_set_autosuspend_delay(&client->dev, ADS1015_SLEEP_DELAY_MS);
1049 pm_runtime_use_autosuspend(&client->dev);
1050 pm_runtime_enable(&client->dev);
1051
1052 ret = iio_device_register(indio_dev);
1053 if (ret < 0) {
1054 dev_err(&client->dev, "Failed to register IIO device\n");
1055 return ret;
1056 }
1057
1058 return 0;
1059 }
1060
1061 static int ads1015_remove(struct i2c_client *client)
1062 {
1063 struct iio_dev *indio_dev = i2c_get_clientdata(client);
1064 struct ads1015_data *data = iio_priv(indio_dev);
1065
1066 iio_device_unregister(indio_dev);
1067
1068 pm_runtime_disable(&client->dev);
1069 pm_runtime_set_suspended(&client->dev);
1070 pm_runtime_put_noidle(&client->dev);
1071
1072 /* power down single shot mode */
1073 return ads1015_set_conv_mode(data, ADS1015_SINGLESHOT);
1074 }
1075
1076 #ifdef CONFIG_PM
1077 static int ads1015_runtime_suspend(struct device *dev)
1078 {
1079 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1080 struct ads1015_data *data = iio_priv(indio_dev);
1081
1082 return ads1015_set_conv_mode(data, ADS1015_SINGLESHOT);
1083 }
1084
1085 static int ads1015_runtime_resume(struct device *dev)
1086 {
1087 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1088 struct ads1015_data *data = iio_priv(indio_dev);
1089 int ret;
1090
1091 ret = ads1015_set_conv_mode(data, ADS1015_CONTINUOUS);
1092 if (!ret)
1093 data->conv_invalid = true;
1094
1095 return ret;
1096 }
1097 #endif
1098
1099 static const struct dev_pm_ops ads1015_pm_ops = {
1100 SET_RUNTIME_PM_OPS(ads1015_runtime_suspend,
1101 ads1015_runtime_resume, NULL)
1102 };
1103
1104 static const struct i2c_device_id ads1015_id[] = {
1105 {"ads1015", ADS1015},
1106 {"ads1115", ADS1115},
1107 {}
1108 };
1109 MODULE_DEVICE_TABLE(i2c, ads1015_id);
1110
1111 static const struct of_device_id ads1015_of_match[] = {
1112 {
1113 .compatible = "ti,ads1015",
1114 .data = (void *)ADS1015
1115 },
1116 {
1117 .compatible = "ti,ads1115",
1118 .data = (void *)ADS1115
1119 },
1120 {}
1121 };
1122 MODULE_DEVICE_TABLE(of, ads1015_of_match);
1123
1124 static struct i2c_driver ads1015_driver = {
1125 .driver = {
1126 .name = ADS1015_DRV_NAME,
1127 .of_match_table = ads1015_of_match,
1128 .pm = &ads1015_pm_ops,
1129 },
1130 .probe = ads1015_probe,
1131 .remove = ads1015_remove,
1132 .id_table = ads1015_id,
1133 };
1134
1135 module_i2c_driver(ads1015_driver);
1136
1137 MODULE_AUTHOR("Daniel Baluta <daniel.baluta@intel.com>");
1138 MODULE_DESCRIPTION("Texas Instruments ADS1015 ADC driver");
1139 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support