drivers/net/ethernet/cadence/macb_ptp.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /**
   3  * 1588 PTP support for Cadence GEM device.
   4  *
   5  * Copyright (C) 2017 Cadence Design Systems - http://www.cadence.com
   6  *
   7  * Authors: Rafal Ozieblo <rafalo@cadence.com>
   8  *          Bartosz Folta <bfolta@cadence.com>
   9  */
  10 #include <linux/kernel.h>
  11 #include <linux/types.h>
  12 #include <linux/clk.h>
  13 #include <linux/device.h>
  14 #include <linux/etherdevice.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/time64.h>
  17 #include <linux/ptp_classify.h>
  18 #include <linux/if_ether.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/net_tstamp.h>
  21 #include <linux/circ_buf.h>
  22 #include <linux/spinlock.h>
  23
  24 #include "macb.h"
  25
  26 #define  GEM_PTP_TIMER_NAME "gem-ptp-timer"
  27
  28 static struct macb_dma_desc_ptp *macb_ptp_desc(struct macb *bp,
  29                                                struct macb_dma_desc *desc)
  30 {
  31         if (bp->hw_dma_cap == HW_DMA_CAP_PTP)
  32                 return (struct macb_dma_desc_ptp *)
  33                                 ((u8 *)desc + sizeof(struct macb_dma_desc));
  34         if (bp->hw_dma_cap == HW_DMA_CAP_64B_PTP)
  35                 return (struct macb_dma_desc_ptp *)
  36                                 ((u8 *)desc + sizeof(struct macb_dma_desc)
  37                                 + sizeof(struct macb_dma_desc_64));
  38         return NULL;
  39 }
  40
  41 static int gem_tsu_get_time(struct ptp_clock_info *ptp, struct timespec64 *ts)
  42 {
  43         struct macb *bp = container_of(ptp, struct macb, ptp_clock_info);
  44         unsigned long flags;
  45         long first, second;
  46         u32 secl, sech;
  47
  48         spin_lock_irqsave(&bp->tsu_clk_lock, flags);
  49         first = gem_readl(bp, TN);
  50         secl = gem_readl(bp, TSL);
  51         sech = gem_readl(bp, TSH);
  52         second = gem_readl(bp, TN);
  53
  54         /* test for nsec rollover */
  55         if (first > second) {
  56                 /* if so, use later read & re-read seconds
  57                  * (assume all done within 1s)
  58                  */
  59                 ts->tv_nsec = gem_readl(bp, TN);
  60                 secl = gem_readl(bp, TSL);
  61                 sech = gem_readl(bp, TSH);
  62         } else {
  63                 ts->tv_nsec = first;
  64         }
  65
  66         spin_unlock_irqrestore(&bp->tsu_clk_lock, flags);
  67         ts->tv_sec = (((u64)sech << GEM_TSL_SIZE) | secl)
  68                         & TSU_SEC_MAX_VAL;
  69         return 0;
  70 }
  71
  72 static int gem_tsu_set_time(struct ptp_clock_info *ptp,
  73                             const struct timespec64 *ts)
  74 {
  75         struct macb *bp = container_of(ptp, struct macb, ptp_clock_info);
  76         unsigned long flags;
  77         u32 ns, sech, secl;
  78
  79         secl = (u32)ts->tv_sec;
  80         sech = (ts->tv_sec >> GEM_TSL_SIZE) & ((1 << GEM_TSH_SIZE) - 1);
  81         ns = ts->tv_nsec;
  82
  83         spin_lock_irqsave(&bp->tsu_clk_lock, flags);
  84
  85         /* TSH doesn't latch the time and no atomicity! */
  86         gem_writel(bp, TN, 0); /* clear to avoid overflow */
  87         gem_writel(bp, TSH, sech);
  88         /* write lower bits 2nd, for synchronized secs update */
  89         gem_writel(bp, TSL, secl);
  90         gem_writel(bp, TN, ns);
  91
  92         spin_unlock_irqrestore(&bp->tsu_clk_lock, flags);
  93
  94         return 0;
  95 }
  96
  97 static int gem_tsu_incr_set(struct macb *bp, struct tsu_incr *incr_spec)
  98 {
  99         unsigned long flags;
 100
 101         /* tsu_timer_incr register must be written after
 102          * the tsu_timer_incr_sub_ns register and the write operation
 103          * will cause the value written to the tsu_timer_incr_sub_ns register
 104          * to take effect.
 105          */
 106         spin_lock_irqsave(&bp->tsu_clk_lock, flags);
 107         gem_writel(bp, TISUBN, GEM_BF(SUBNSINCR, incr_spec->sub_ns));
 108         gem_writel(bp, TI, GEM_BF(NSINCR, incr_spec->ns));
 109         spin_unlock_irqrestore(&bp->tsu_clk_lock, flags);
 110
 111         return 0;
 112 }
 113
 114 static int gem_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
 115 {
 116         struct macb *bp = container_of(ptp, struct macb, ptp_clock_info);
 117         struct tsu_incr incr_spec;
 118         bool neg_adj = false;
 119         u32 word;
 120         u64 adj;
 121
 122         if (scaled_ppm < 0) {
 123                 neg_adj = true;
 124                 scaled_ppm = -scaled_ppm;
 125         }
 126
 127         /* Adjustment is relative to base frequency */
 128         incr_spec.sub_ns = bp->tsu_incr.sub_ns;
 129         incr_spec.ns = bp->tsu_incr.ns;
 130
 131         /* scaling: unused(8bit) | ns(8bit) | fractions(16bit) */
 132         word = ((u64)incr_spec.ns << GEM_SUBNSINCR_SIZE) + incr_spec.sub_ns;
 133         adj = (u64)scaled_ppm * word;
 134         /* Divide with rounding, equivalent to floating dividing:
 135          * (temp / USEC_PER_SEC) + 0.5
 136          */
 137         adj += (USEC_PER_SEC >> 1);
 138         adj >>= GEM_SUBNSINCR_SIZE; /* remove fractions */
 139         adj = div_u64(adj, USEC_PER_SEC);
 140         adj = neg_adj ? (word - adj) : (word + adj);
 141
 142         incr_spec.ns = (adj >> GEM_SUBNSINCR_SIZE)
 143                         & ((1 << GEM_NSINCR_SIZE) - 1);
 144         incr_spec.sub_ns = adj & ((1 << GEM_SUBNSINCR_SIZE) - 1);
 145         gem_tsu_incr_set(bp, &incr_spec);
 146         return 0;
 147 }
 148
 149 static int gem_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
 150 {
 151         struct macb *bp = container_of(ptp, struct macb, ptp_clock_info);
 152         struct timespec64 now, then = ns_to_timespec64(delta);
 153         u32 adj, sign = 0;
 154
 155         if (delta < 0) {
 156                 sign = 1;
 157                 delta = -delta;
 158         }
 159
 160         if (delta > TSU_NSEC_MAX_VAL) {
 161                 gem_tsu_get_time(&bp->ptp_clock_info, &now);
 162                 now = timespec64_add(now, then);
 163
 164                 gem_tsu_set_time(&bp->ptp_clock_info,
 165                                  (const struct timespec64 *)&now);
 166         } else {
 167                 adj = (sign << GEM_ADDSUB_OFFSET) | delta;
 168
 169                 gem_writel(bp, TA, adj);
 170         }
 171
 172         return 0;
 173 }
 174
 175 static int gem_ptp_enable(struct ptp_clock_info *ptp,
 176                           struct ptp_clock_request *rq, int on)
 177 {
 178         return -EOPNOTSUPP;
 179 }
 180
 181 static const struct ptp_clock_info gem_ptp_caps_template = {
 182         .owner          = THIS_MODULE,
 183         .name           = GEM_PTP_TIMER_NAME,
 184         .max_adj        = 0,
 185         .n_alarm        = 0,
 186         .n_ext_ts       = 0,
 187         .n_per_out      = 0,
 188         .n_pins         = 0,
 189         .pps            = 1,
 190         .adjfine        = gem_ptp_adjfine,
 191         .adjtime        = gem_ptp_adjtime,
 192         .gettime64      = gem_tsu_get_time,
 193         .settime64      = gem_tsu_set_time,
 194         .enable         = gem_ptp_enable,
 195 };
 196
 197 static void gem_ptp_init_timer(struct macb *bp)
 198 {
 199         u32 rem = 0;
 200         u64 adj;
 201
 202         bp->tsu_incr.ns = div_u64_rem(NSEC_PER_SEC, bp->tsu_rate, &rem);
 203         if (rem) {
 204                 adj = rem;
 205                 adj <<= GEM_SUBNSINCR_SIZE;
 206                 bp->tsu_incr.sub_ns = div_u64(adj, bp->tsu_rate);
 207         } else {
 208                 bp->tsu_incr.sub_ns = 0;
 209         }
 210 }
 211
 212 static void gem_ptp_init_tsu(struct macb *bp)
 213 {
 214         struct timespec64 ts;
 215
 216         /* 1. get current system time */
 217         ts = ns_to_timespec64(ktime_to_ns(ktime_get_real()));
 218
 219         /* 2. set ptp timer */
 220         gem_tsu_set_time(&bp->ptp_clock_info, &ts);
 221
 222         /* 3. set PTP timer increment value to BASE_INCREMENT */
 223         gem_tsu_incr_set(bp, &bp->tsu_incr);
 224
 225         gem_writel(bp, TA, 0);
 226 }
 227
 228 static void gem_ptp_clear_timer(struct macb *bp)
 229 {
 230         bp->tsu_incr.sub_ns = 0;
 231         bp->tsu_incr.ns = 0;
 232
 233         gem_writel(bp, TISUBN, GEM_BF(SUBNSINCR, 0));
 234         gem_writel(bp, TI, GEM_BF(NSINCR, 0));
 235         gem_writel(bp, TA, 0);
 236 }
 237
 238 static int gem_hw_timestamp(struct macb *bp, u32 dma_desc_ts_1,
 239                             u32 dma_desc_ts_2, struct timespec64 *ts)
 240 {
 241         struct timespec64 tsu;
 242
 243         ts->tv_sec = (GEM_BFEXT(DMA_SECH, dma_desc_ts_2) << GEM_DMA_SECL_SIZE) |
 244                         GEM_BFEXT(DMA_SECL, dma_desc_ts_1);
 245         ts->tv_nsec = GEM_BFEXT(DMA_NSEC, dma_desc_ts_1);
 246
 247         /* TSU overlapping workaround
 248          * The timestamp only contains lower few bits of seconds,
 249          * so add value from 1588 timer
 250          */
 251         gem_tsu_get_time(&bp->ptp_clock_info, &tsu);
 252
 253         /* If the top bit is set in the timestamp,
 254          * but not in 1588 timer, it has rolled over,
 255          * so subtract max size
 256          */
 257         if ((ts->tv_sec & (GEM_DMA_SEC_TOP >> 1)) &&
 258             !(tsu.tv_sec & (GEM_DMA_SEC_TOP >> 1)))
 259                 ts->tv_sec -= GEM_DMA_SEC_TOP;
 260
 261         ts->tv_sec += ((~GEM_DMA_SEC_MASK) & tsu.tv_sec);
 262
 263         return 0;
 264 }
 265
 266 void gem_ptp_rxstamp(struct macb *bp, struct sk_buff *skb,
 267                      struct macb_dma_desc *desc)
 268 {
 269         struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
 270         struct macb_dma_desc_ptp *desc_ptp;
 271         struct timespec64 ts;
 272
 273         if (GEM_BFEXT(DMA_RXVALID, desc->addr)) {
 274                 desc_ptp = macb_ptp_desc(bp, desc);
 275                 gem_hw_timestamp(bp, desc_ptp->ts_1, desc_ptp->ts_2, &ts);
 276                 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps));
 277                 shhwtstamps->hwtstamp = ktime_set(ts.tv_sec, ts.tv_nsec);
 278         }
 279 }
 280
 281 static void gem_tstamp_tx(struct macb *bp, struct sk_buff *skb,
 282                           struct macb_dma_desc_ptp *desc_ptp)
 283 {
 284         struct skb_shared_hwtstamps shhwtstamps;
 285         struct timespec64 ts;
 286
 287         gem_hw_timestamp(bp, desc_ptp->ts_1, desc_ptp->ts_2, &ts);
 288         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
 289         shhwtstamps.hwtstamp = ktime_set(ts.tv_sec, ts.tv_nsec);
 290         skb_tstamp_tx(skb, &shhwtstamps);
 291 }
 292
 293 int gem_ptp_txstamp(struct macb_queue *queue, struct sk_buff *skb,
 294                     struct macb_dma_desc *desc)
 295 {
 296         unsigned long tail = READ_ONCE(queue->tx_ts_tail);
 297         unsigned long head = queue->tx_ts_head;
 298         struct macb_dma_desc_ptp *desc_ptp;
 299         struct gem_tx_ts *tx_timestamp;
 300
 301         if (!GEM_BFEXT(DMA_TXVALID, desc->ctrl))
 302                 return -EINVAL;
 303
 304         if (CIRC_SPACE(head, tail, PTP_TS_BUFFER_SIZE) == 0)
 305                 return -ENOMEM;
 306
 307         skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
 308         desc_ptp = macb_ptp_desc(queue->bp, desc);
 309         tx_timestamp = &queue->tx_timestamps[head];
 310         tx_timestamp->skb = skb;
 311         /* ensure ts_1/ts_2 is loaded after ctrl (TX_USED check) */
 312         dma_rmb();
 313         tx_timestamp->desc_ptp.ts_1 = desc_ptp->ts_1;
 314         tx_timestamp->desc_ptp.ts_2 = desc_ptp->ts_2;
 315         /* move head */
 316         smp_store_release(&queue->tx_ts_head,
 317                           (head + 1) & (PTP_TS_BUFFER_SIZE - 1));
 318
 319         schedule_work(&queue->tx_ts_task);
 320         return 0;
 321 }
 322
 323 static void gem_tx_timestamp_flush(struct work_struct *work)
 324 {
 325         struct macb_queue *queue =
 326                         container_of(work, struct macb_queue, tx_ts_task);
 327         unsigned long head, tail;
 328         struct gem_tx_ts *tx_ts;
 329
 330         /* take current head */
 331         head = smp_load_acquire(&queue->tx_ts_head);
 332         tail = queue->tx_ts_tail;
 333
 334         while (CIRC_CNT(head, tail, PTP_TS_BUFFER_SIZE)) {
 335                 tx_ts = &queue->tx_timestamps[tail];
 336                 gem_tstamp_tx(queue->bp, tx_ts->skb, &tx_ts->desc_ptp);
 337                 /* cleanup */
 338                 dev_kfree_skb_any(tx_ts->skb);
 339                 /* remove old tail */
 340                 smp_store_release(&queue->tx_ts_tail,
 341                                   (tail + 1) & (PTP_TS_BUFFER_SIZE - 1));
 342                 tail = queue->tx_ts_tail;
 343         }
 344 }
 345
 346 void gem_ptp_init(struct net_device *dev)
 347 {
 348         struct macb *bp = netdev_priv(dev);
 349         struct macb_queue *queue;
 350         unsigned int q;
 351
 352         bp->ptp_clock_info = gem_ptp_caps_template;
 353
 354         /* nominal frequency and maximum adjustment in ppb */
 355         bp->tsu_rate = bp->ptp_info->get_tsu_rate(bp);
 356         bp->ptp_clock_info.max_adj = bp->ptp_info->get_ptp_max_adj();
 357         gem_ptp_init_timer(bp);
 358         bp->ptp_clock = ptp_clock_register(&bp->ptp_clock_info, &dev->dev);
 359         if (IS_ERR(bp->ptp_clock)) {
 360                 pr_err("ptp clock register failed: %ld\n",
 361                         PTR_ERR(bp->ptp_clock));
 362                 bp->ptp_clock = NULL;
 363                 return;
 364         } else if (bp->ptp_clock == NULL) {
 365                 pr_err("ptp clock register failed\n");
 366                 return;
 367         }
 368
 369         spin_lock_init(&bp->tsu_clk_lock);
 370         for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
 371                 queue->tx_ts_head = 0;
 372                 queue->tx_ts_tail = 0;
 373                 INIT_WORK(&queue->tx_ts_task, gem_tx_timestamp_flush);
 374         }
 375
 376         gem_ptp_init_tsu(bp);
 377
 378         dev_info(&bp->pdev->dev, "%s ptp clock registered.\n",
 379                  GEM_PTP_TIMER_NAME);
 380 }
 381
 382 void gem_ptp_remove(struct net_device *ndev)
 383 {
 384         struct macb *bp = netdev_priv(ndev);
 385
 386         if (bp->ptp_clock)
 387                 ptp_clock_unregister(bp->ptp_clock);
 388
 389         gem_ptp_clear_timer(bp);
 390
 391         dev_info(&bp->pdev->dev, "%s ptp clock unregistered.\n",
 392                  GEM_PTP_TIMER_NAME);
 393 }
 394
 395 static int gem_ptp_set_ts_mode(struct macb *bp,
 396                                enum macb_bd_control tx_bd_control,
 397                                enum macb_bd_control rx_bd_control)
 398 {
 399         gem_writel(bp, TXBDCTRL, GEM_BF(TXTSMODE, tx_bd_control));
 400         gem_writel(bp, RXBDCTRL, GEM_BF(RXTSMODE, rx_bd_control));
 401
 402         return 0;
 403 }
 404
 405 int gem_get_hwtst(struct net_device *dev, struct ifreq *rq)
 406 {
 407         struct hwtstamp_config *tstamp_config;
 408         struct macb *bp = netdev_priv(dev);
 409
 410         tstamp_config = &bp->tstamp_config;
 411         if ((bp->hw_dma_cap & HW_DMA_CAP_PTP) == 0)
 412                 return -EOPNOTSUPP;
 413
 414         if (copy_to_user(rq->ifr_data, tstamp_config, sizeof(*tstamp_config)))
 415                 return -EFAULT;
 416         else
 417                 return 0;
 418 }
 419
 420 static int gem_ptp_set_one_step_sync(struct macb *bp, u8 enable)
 421 {
 422         u32 reg_val;
 423
 424         reg_val = macb_readl(bp, NCR);
 425
 426         if (enable)
 427                 macb_writel(bp, NCR, reg_val | MACB_BIT(OSSMODE));
 428         else
 429                 macb_writel(bp, NCR, reg_val & ~MACB_BIT(OSSMODE));
 430
 431         return 0;
 432 }
 433
 434 int gem_set_hwtst(struct net_device *dev, struct ifreq *ifr, int cmd)
 435 {
 436         enum macb_bd_control tx_bd_control = TSTAMP_DISABLED;
 437         enum macb_bd_control rx_bd_control = TSTAMP_DISABLED;
 438         struct hwtstamp_config *tstamp_config;
 439         struct macb *bp = netdev_priv(dev);
 440         u32 regval;
 441
 442         tstamp_config = &bp->tstamp_config;
 443         if ((bp->hw_dma_cap & HW_DMA_CAP_PTP) == 0)
 444                 return -EOPNOTSUPP;
 445
 446         if (copy_from_user(tstamp_config, ifr->ifr_data,
 447                            sizeof(*tstamp_config)))
 448                 return -EFAULT;
 449
 450         /* reserved for future extensions */
 451         if (tstamp_config->flags)
 452                 return -EINVAL;
 453
 454         switch (tstamp_config->tx_type) {
 455         case HWTSTAMP_TX_OFF:
 456                 break;
 457         case HWTSTAMP_TX_ONESTEP_SYNC:
 458                 if (gem_ptp_set_one_step_sync(bp, 1) != 0)
 459                         return -ERANGE;
 460                 /* fall through */
 461         case HWTSTAMP_TX_ON:
 462                 tx_bd_control = TSTAMP_ALL_FRAMES;
 463                 break;
 464         default:
 465                 return -ERANGE;
 466         }
 467
 468         switch (tstamp_config->rx_filter) {
 469         case HWTSTAMP_FILTER_NONE:
 470                 break;
 471         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 472                 break;
 473         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 474                 break;
 475         case HWTSTAMP_FILTER_PTP_V2_EVENT:
 476         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
 477         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
 478         case HWTSTAMP_FILTER_PTP_V2_SYNC:
 479         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
 480         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
 481         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
 482         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
 483         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
 484                 rx_bd_control =  TSTAMP_ALL_PTP_FRAMES;
 485                 tstamp_config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
 486                 regval = macb_readl(bp, NCR);
 487                 macb_writel(bp, NCR, (regval | MACB_BIT(SRTSM)));
 488                 break;
 489         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
 490         case HWTSTAMP_FILTER_ALL:
 491                 rx_bd_control = TSTAMP_ALL_FRAMES;
 492                 tstamp_config->rx_filter = HWTSTAMP_FILTER_ALL;
 493                 break;
 494         default:
 495                 tstamp_config->rx_filter = HWTSTAMP_FILTER_NONE;
 496                 return -ERANGE;
 497         }
 498
 499         if (gem_ptp_set_ts_mode(bp, tx_bd_control, rx_bd_control) != 0)
 500                 return -ERANGE;
 501
 502         if (copy_to_user(ifr->ifr_data, tstamp_config, sizeof(*tstamp_config)))
 503                 return -EFAULT;
 504         else
 505                 return 0;
 506 }
 507