?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
ALSA: usb-audio: Fix an out-of-bound read in create_composite_quirks
[linux/fpc-iii.git] / drivers / clk / tegra / clk-pll.c
blob66d1fc7dff5817a38a2e7b4000bf770a76df50d6
1 /*
2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17 #include <linux/slab.h>
18 #include <linux/io.h>
19 #include <linux/delay.h>
20 #include <linux/err.h>
21 #include <linux/clk.h>
22 #include <linux/clk-provider.h>
23
24 #include "clk.h"
25
26 #define PLL_BASE_BYPASS BIT(31)
27 #define PLL_BASE_ENABLE BIT(30)
28 #define PLL_BASE_REF_ENABLE BIT(29)
29 #define PLL_BASE_OVERRIDE BIT(28)
30
31 #define PLL_BASE_DIVP_SHIFT 20
32 #define PLL_BASE_DIVP_WIDTH 3
33 #define PLL_BASE_DIVN_SHIFT 8
34 #define PLL_BASE_DIVN_WIDTH 10
35 #define PLL_BASE_DIVM_SHIFT 0
36 #define PLL_BASE_DIVM_WIDTH 5
37 #define PLLU_POST_DIVP_MASK 0x1
38
39 #define PLL_MISC_DCCON_SHIFT 20
40 #define PLL_MISC_CPCON_SHIFT 8
41 #define PLL_MISC_CPCON_WIDTH 4
42 #define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1)
43 #define PLL_MISC_LFCON_SHIFT 4
44 #define PLL_MISC_LFCON_WIDTH 4
45 #define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1)
46 #define PLL_MISC_VCOCON_SHIFT 0
47 #define PLL_MISC_VCOCON_WIDTH 4
48 #define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1)
49
50 #define OUT_OF_TABLE_CPCON 8
51
52 #define PMC_PLLP_WB0_OVERRIDE 0xf8
53 #define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE BIT(12)
54 #define PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE BIT(11)
55
56 #define PLL_POST_LOCK_DELAY 50
57
58 #define PLLDU_LFCON_SET_DIVN 600
59
60 #define PLLE_BASE_DIVCML_SHIFT 24
61 #define PLLE_BASE_DIVCML_MASK 0xf
62 #define PLLE_BASE_DIVP_SHIFT 16
63 #define PLLE_BASE_DIVP_WIDTH 6
64 #define PLLE_BASE_DIVN_SHIFT 8
65 #define PLLE_BASE_DIVN_WIDTH 8
66 #define PLLE_BASE_DIVM_SHIFT 0
67 #define PLLE_BASE_DIVM_WIDTH 8
68 #define PLLE_BASE_ENABLE BIT(31)
69
70 #define PLLE_MISC_SETUP_BASE_SHIFT 16
71 #define PLLE_MISC_SETUP_BASE_MASK (0xffff << PLLE_MISC_SETUP_BASE_SHIFT)
72 #define PLLE_MISC_LOCK_ENABLE BIT(9)
73 #define PLLE_MISC_READY BIT(15)
74 #define PLLE_MISC_SETUP_EX_SHIFT 2
75 #define PLLE_MISC_SETUP_EX_MASK (3 << PLLE_MISC_SETUP_EX_SHIFT)
76 #define PLLE_MISC_SETUP_MASK (PLLE_MISC_SETUP_BASE_MASK | \
77 PLLE_MISC_SETUP_EX_MASK)
78 #define PLLE_MISC_SETUP_VALUE (7 << PLLE_MISC_SETUP_BASE_SHIFT)
79
80 #define PLLE_SS_CTRL 0x68
81 #define PLLE_SS_CNTL_BYPASS_SS BIT(10)
82 #define PLLE_SS_CNTL_INTERP_RESET BIT(11)
83 #define PLLE_SS_CNTL_SSC_BYP BIT(12)
84 #define PLLE_SS_CNTL_CENTER BIT(14)
85 #define PLLE_SS_CNTL_INVERT BIT(15)
86 #define PLLE_SS_DISABLE (PLLE_SS_CNTL_BYPASS_SS | PLLE_SS_CNTL_INTERP_RESET |\
87 PLLE_SS_CNTL_SSC_BYP)
88 #define PLLE_SS_MAX_MASK 0x1ff
89 #define PLLE_SS_MAX_VAL_TEGRA114 0x25
90 #define PLLE_SS_MAX_VAL_TEGRA210 0x21
91 #define PLLE_SS_INC_MASK (0xff << 16)
92 #define PLLE_SS_INC_VAL (0x1 << 16)
93 #define PLLE_SS_INCINTRV_MASK (0x3f << 24)
94 #define PLLE_SS_INCINTRV_VAL_TEGRA114 (0x20 << 24)
95 #define PLLE_SS_INCINTRV_VAL_TEGRA210 (0x23 << 24)
96 #define PLLE_SS_COEFFICIENTS_MASK \
97 (PLLE_SS_MAX_MASK | PLLE_SS_INC_MASK | PLLE_SS_INCINTRV_MASK)
98 #define PLLE_SS_COEFFICIENTS_VAL_TEGRA114 \
99 (PLLE_SS_MAX_VAL_TEGRA114 | PLLE_SS_INC_VAL |\
100 PLLE_SS_INCINTRV_VAL_TEGRA114)
101 #define PLLE_SS_COEFFICIENTS_VAL_TEGRA210 \
102 (PLLE_SS_MAX_VAL_TEGRA210 | PLLE_SS_INC_VAL |\
103 PLLE_SS_INCINTRV_VAL_TEGRA210)
104
105 #define PLLE_AUX_PLLP_SEL BIT(2)
106 #define PLLE_AUX_USE_LOCKDET BIT(3)
107 #define PLLE_AUX_ENABLE_SWCTL BIT(4)
108 #define PLLE_AUX_SS_SWCTL BIT(6)
109 #define PLLE_AUX_SEQ_ENABLE BIT(24)
110 #define PLLE_AUX_SEQ_START_STATE BIT(25)
111 #define PLLE_AUX_PLLRE_SEL BIT(28)
112 #define PLLE_AUX_SS_SEQ_INCLUDE BIT(31)
113
114 #define XUSBIO_PLL_CFG0 0x51c
115 #define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0)
116 #define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL BIT(2)
117 #define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET BIT(6)
118 #define XUSBIO_PLL_CFG0_SEQ_ENABLE BIT(24)
119 #define XUSBIO_PLL_CFG0_SEQ_START_STATE BIT(25)
120
121 #define SATA_PLL_CFG0 0x490
122 #define SATA_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0)
123 #define SATA_PLL_CFG0_PADPLL_USE_LOCKDET BIT(2)
124 #define SATA_PLL_CFG0_SEQ_ENABLE BIT(24)
125 #define SATA_PLL_CFG0_SEQ_START_STATE BIT(25)
126
127 #define PLLE_MISC_PLLE_PTS BIT(8)
128 #define PLLE_MISC_IDDQ_SW_VALUE BIT(13)
129 #define PLLE_MISC_IDDQ_SW_CTRL BIT(14)
130 #define PLLE_MISC_VREG_BG_CTRL_SHIFT 4
131 #define PLLE_MISC_VREG_BG_CTRL_MASK (3 << PLLE_MISC_VREG_BG_CTRL_SHIFT)
132 #define PLLE_MISC_VREG_CTRL_SHIFT 2
133 #define PLLE_MISC_VREG_CTRL_MASK (2 << PLLE_MISC_VREG_CTRL_SHIFT)
134
135 #define PLLCX_MISC_STROBE BIT(31)
136 #define PLLCX_MISC_RESET BIT(30)
137 #define PLLCX_MISC_SDM_DIV_SHIFT 28
138 #define PLLCX_MISC_SDM_DIV_MASK (0x3 << PLLCX_MISC_SDM_DIV_SHIFT)
139 #define PLLCX_MISC_FILT_DIV_SHIFT 26
140 #define PLLCX_MISC_FILT_DIV_MASK (0x3 << PLLCX_MISC_FILT_DIV_SHIFT)
141 #define PLLCX_MISC_ALPHA_SHIFT 18
142 #define PLLCX_MISC_DIV_LOW_RANGE \
143 ((0x1 << PLLCX_MISC_SDM_DIV_SHIFT) | \
144 (0x1 << PLLCX_MISC_FILT_DIV_SHIFT))
145 #define PLLCX_MISC_DIV_HIGH_RANGE \
146 ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | \
147 (0x2 << PLLCX_MISC_FILT_DIV_SHIFT))
148 #define PLLCX_MISC_COEF_LOW_RANGE \
149 ((0x14 << PLLCX_MISC_KA_SHIFT) | (0x38 << PLLCX_MISC_KB_SHIFT))
150 #define PLLCX_MISC_KA_SHIFT 2
151 #define PLLCX_MISC_KB_SHIFT 9
152 #define PLLCX_MISC_DEFAULT (PLLCX_MISC_COEF_LOW_RANGE | \
153 (0x19 << PLLCX_MISC_ALPHA_SHIFT) | \
154 PLLCX_MISC_DIV_LOW_RANGE | \
155 PLLCX_MISC_RESET)
156 #define PLLCX_MISC1_DEFAULT 0x000d2308
157 #define PLLCX_MISC2_DEFAULT 0x30211200
158 #define PLLCX_MISC3_DEFAULT 0x200
159
160 #define PMC_SATA_PWRGT 0x1ac
161 #define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5)
162 #define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4)
163
164 #define PLLSS_MISC_KCP 0
165 #define PLLSS_MISC_KVCO 0
166 #define PLLSS_MISC_SETUP 0
167 #define PLLSS_EN_SDM 0
168 #define PLLSS_EN_SSC 0
169 #define PLLSS_EN_DITHER2 0
170 #define PLLSS_EN_DITHER 1
171 #define PLLSS_SDM_RESET 0
172 #define PLLSS_CLAMP 0
173 #define PLLSS_SDM_SSC_MAX 0
174 #define PLLSS_SDM_SSC_MIN 0
175 #define PLLSS_SDM_SSC_STEP 0
176 #define PLLSS_SDM_DIN 0
177 #define PLLSS_MISC_DEFAULT ((PLLSS_MISC_KCP << 25) | \
178 (PLLSS_MISC_KVCO << 24) | \
179 PLLSS_MISC_SETUP)
180 #define PLLSS_CFG_DEFAULT ((PLLSS_EN_SDM << 31) | \
181 (PLLSS_EN_SSC << 30) | \
182 (PLLSS_EN_DITHER2 << 29) | \
183 (PLLSS_EN_DITHER << 28) | \
184 (PLLSS_SDM_RESET) << 27 | \
185 (PLLSS_CLAMP << 22))
186 #define PLLSS_CTRL1_DEFAULT \
187 ((PLLSS_SDM_SSC_MAX << 16) | PLLSS_SDM_SSC_MIN)
188 #define PLLSS_CTRL2_DEFAULT \
189 ((PLLSS_SDM_SSC_STEP << 16) | PLLSS_SDM_DIN)
190 #define PLLSS_LOCK_OVERRIDE BIT(24)
191 #define PLLSS_REF_SRC_SEL_SHIFT 25
192 #define PLLSS_REF_SRC_SEL_MASK (3 << PLLSS_REF_SRC_SEL_SHIFT)
193
194 #define UTMIP_PLL_CFG1 0x484
195 #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
196 #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
197 #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
198 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
199 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15)
200 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
201 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17)
202
203 #define UTMIP_PLL_CFG2 0x488
204 #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6)
205 #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
206 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
207 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP BIT(1)
208 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
209 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP BIT(3)
210 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
211 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP BIT(5)
212 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN BIT(24)
213 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP BIT(25)
214 #define UTMIP_PLL_CFG2_PHY_XTAL_CLOCKEN BIT(30)
215
216 #define UTMIPLL_HW_PWRDN_CFG0 0x52c
217 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0)
218 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1)
219 #define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
220 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL BIT(4)
221 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5)
222 #define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
223 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
224 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE BIT(25)
225
226 #define PLLU_HW_PWRDN_CFG0 0x530
227 #define PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL BIT(0)
228 #define PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
229 #define PLLU_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
230 #define PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT BIT(7)
231 #define PLLU_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
232 #define PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE BIT(28)
233
234 #define XUSB_PLL_CFG0 0x534
235 #define XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY 0x3ff
236 #define XUSB_PLL_CFG0_PLLU_LOCK_DLY (0x3ff << 14)
237
238 #define PLLU_BASE_CLKENABLE_USB BIT(21)
239 #define PLLU_BASE_OVERRIDE BIT(24)
240
241 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
242 #define pll_readl_base(p) pll_readl(p->params->base_reg, p)
243 #define pll_readl_misc(p) pll_readl(p->params->misc_reg, p)
244 #define pll_override_readl(offset, p) readl_relaxed(p->pmc + offset)
245 #define pll_readl_sdm_din(p) pll_readl(p->params->sdm_din_reg, p)
246 #define pll_readl_sdm_ctrl(p) pll_readl(p->params->sdm_ctrl_reg, p)
247
248 #define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset)
249 #define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p)
250 #define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p)
251 #define pll_override_writel(val, offset, p) writel(val, p->pmc + offset)
252 #define pll_writel_sdm_din(val, p) pll_writel(val, p->params->sdm_din_reg, p)
253 #define pll_writel_sdm_ctrl(val, p) pll_writel(val, p->params->sdm_ctrl_reg, p)
254
255 #define mask(w) ((1 << (w)) - 1)
256 #define divm_mask(p) mask(p->params->div_nmp->divm_width)
257 #define divn_mask(p) mask(p->params->div_nmp->divn_width)
258 #define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\
259 mask(p->params->div_nmp->divp_width))
260 #define sdm_din_mask(p) p->params->sdm_din_mask
261 #define sdm_en_mask(p) p->params->sdm_ctrl_en_mask
262
263 #define divm_shift(p) (p)->params->div_nmp->divm_shift
264 #define divn_shift(p) (p)->params->div_nmp->divn_shift
265 #define divp_shift(p) (p)->params->div_nmp->divp_shift
266
267 #define divm_mask_shifted(p) (divm_mask(p) << divm_shift(p))
268 #define divn_mask_shifted(p) (divn_mask(p) << divn_shift(p))
269 #define divp_mask_shifted(p) (divp_mask(p) << divp_shift(p))
270
271 #define divm_max(p) (divm_mask(p))
272 #define divn_max(p) (divn_mask(p))
273 #define divp_max(p) (1 << (divp_mask(p)))
274
275 #define sdin_din_to_data(din) ((u16)((din) ? : 0xFFFFU))
276 #define sdin_data_to_din(dat) (((dat) == 0xFFFFU) ? 0 : (s16)dat)
277
278 static struct div_nmp default_nmp = {
279 .divn_shift = PLL_BASE_DIVN_SHIFT,
280 .divn_width = PLL_BASE_DIVN_WIDTH,
281 .divm_shift = PLL_BASE_DIVM_SHIFT,
282 .divm_width = PLL_BASE_DIVM_WIDTH,
283 .divp_shift = PLL_BASE_DIVP_SHIFT,
284 .divp_width = PLL_BASE_DIVP_WIDTH,
285 };
286
287 static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
288 {
289 u32 val;
290
291 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK))
292 return;
293
294 if (!(pll->params->flags & TEGRA_PLL_HAS_LOCK_ENABLE))
295 return;
296
297 val = pll_readl_misc(pll);
298 val |= BIT(pll->params->lock_enable_bit_idx);
299 pll_writel_misc(val, pll);
300 }
301
302 static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll)
303 {
304 int i;
305 u32 val, lock_mask;
306 void __iomem *lock_addr;
307
308 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) {
309 udelay(pll->params->lock_delay);
310 return 0;
311 }
312
313 lock_addr = pll->clk_base;
314 if (pll->params->flags & TEGRA_PLL_LOCK_MISC)
315 lock_addr += pll->params->misc_reg;
316 else
317 lock_addr += pll->params->base_reg;
318
319 lock_mask = pll->params->lock_mask;
320
321 for (i = 0; i < pll->params->lock_delay; i++) {
322 val = readl_relaxed(lock_addr);
323 if ((val & lock_mask) == lock_mask) {
324 udelay(PLL_POST_LOCK_DELAY);
325 return 0;
326 }
327 udelay(2); /* timeout = 2 * lock time */
328 }
329
330 pr_err("%s: Timed out waiting for pll %s lock\n", __func__,
331 clk_hw_get_name(&pll->hw));
332
333 return -1;
334 }
335
336 int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll)
337 {
338 return clk_pll_wait_for_lock(pll);
339 }
340
341 static int clk_pll_is_enabled(struct clk_hw *hw)
342 {
343 struct tegra_clk_pll *pll = to_clk_pll(hw);
344 u32 val;
345
346 if (pll->params->flags & TEGRA_PLLM) {
347 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
348 if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)
349 return val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE ? 1 : 0;
350 }
351
352 val = pll_readl_base(pll);
353
354 return val & PLL_BASE_ENABLE ? 1 : 0;
355 }
356
357 static void _clk_pll_enable(struct clk_hw *hw)
358 {
359 struct tegra_clk_pll *pll = to_clk_pll(hw);
360 u32 val;
361
362 if (pll->params->iddq_reg) {
363 val = pll_readl(pll->params->iddq_reg, pll);
364 val &= ~BIT(pll->params->iddq_bit_idx);
365 pll_writel(val, pll->params->iddq_reg, pll);
366 udelay(2);
367 }
368
369 if (pll->params->reset_reg) {
370 val = pll_readl(pll->params->reset_reg, pll);
371 val &= ~BIT(pll->params->reset_bit_idx);
372 pll_writel(val, pll->params->reset_reg, pll);
373 }
374
375 clk_pll_enable_lock(pll);
376
377 val = pll_readl_base(pll);
378 if (pll->params->flags & TEGRA_PLL_BYPASS)
379 val &= ~PLL_BASE_BYPASS;
380 val |= PLL_BASE_ENABLE;
381 pll_writel_base(val, pll);
382
383 if (pll->params->flags & TEGRA_PLLM) {
384 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
385 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
386 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
387 }
388 }
389
390 static void _clk_pll_disable(struct clk_hw *hw)
391 {
392 struct tegra_clk_pll *pll = to_clk_pll(hw);
393 u32 val;
394
395 val = pll_readl_base(pll);
396 if (pll->params->flags & TEGRA_PLL_BYPASS)
397 val &= ~PLL_BASE_BYPASS;
398 val &= ~PLL_BASE_ENABLE;
399 pll_writel_base(val, pll);
400
401 if (pll->params->flags & TEGRA_PLLM) {
402 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
403 val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
404 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
405 }
406
407 if (pll->params->reset_reg) {
408 val = pll_readl(pll->params->reset_reg, pll);
409 val |= BIT(pll->params->reset_bit_idx);
410 pll_writel(val, pll->params->reset_reg, pll);
411 }
412
413 if (pll->params->iddq_reg) {
414 val = pll_readl(pll->params->iddq_reg, pll);
415 val |= BIT(pll->params->iddq_bit_idx);
416 pll_writel(val, pll->params->iddq_reg, pll);
417 udelay(2);
418 }
419 }
420
421 static int clk_pll_enable(struct clk_hw *hw)
422 {
423 struct tegra_clk_pll *pll = to_clk_pll(hw);
424 unsigned long flags = 0;
425 int ret;
426
427 if (pll->lock)
428 spin_lock_irqsave(pll->lock, flags);
429
430 _clk_pll_enable(hw);
431
432 ret = clk_pll_wait_for_lock(pll);
433
434 if (pll->lock)
435 spin_unlock_irqrestore(pll->lock, flags);
436
437 return ret;
438 }
439
440 static void clk_pll_disable(struct clk_hw *hw)
441 {
442 struct tegra_clk_pll *pll = to_clk_pll(hw);
443 unsigned long flags = 0;
444
445 if (pll->lock)
446 spin_lock_irqsave(pll->lock, flags);
447
448 _clk_pll_disable(hw);
449
450 if (pll->lock)
451 spin_unlock_irqrestore(pll->lock, flags);
452 }
453
454 static int _p_div_to_hw(struct clk_hw *hw, u8 p_div)
455 {
456 struct tegra_clk_pll *pll = to_clk_pll(hw);
457 const struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
458
459 if (p_tohw) {
460 while (p_tohw->pdiv) {
461 if (p_div <= p_tohw->pdiv)
462 return p_tohw->hw_val;
463 p_tohw++;
464 }
465 return -EINVAL;
466 }
467 return -EINVAL;
468 }
469
470 int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div)
471 {
472 return _p_div_to_hw(&pll->hw, p_div);
473 }
474
475 static int _hw_to_p_div(struct clk_hw *hw, u8 p_div_hw)
476 {
477 struct tegra_clk_pll *pll = to_clk_pll(hw);
478 const struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
479
480 if (p_tohw) {
481 while (p_tohw->pdiv) {
482 if (p_div_hw == p_tohw->hw_val)
483 return p_tohw->pdiv;
484 p_tohw++;
485 }
486 return -EINVAL;
487 }
488
489 return 1 << p_div_hw;
490 }
491
492 static int _get_table_rate(struct clk_hw *hw,
493 struct tegra_clk_pll_freq_table *cfg,
494 unsigned long rate, unsigned long parent_rate)
495 {
496 struct tegra_clk_pll *pll = to_clk_pll(hw);
497 struct tegra_clk_pll_freq_table *sel;
498 int p;
499
500 for (sel = pll->params->freq_table; sel->input_rate != 0; sel++)
501 if (sel->input_rate == parent_rate &&
502 sel->output_rate == rate)
503 break;
504
505 if (sel->input_rate == 0)
506 return -EINVAL;
507
508 if (pll->params->pdiv_tohw) {
509 p = _p_div_to_hw(hw, sel->p);
510 if (p < 0)
511 return p;
512 } else {
513 p = ilog2(sel->p);
514 }
515
516 cfg->input_rate = sel->input_rate;
517 cfg->output_rate = sel->output_rate;
518 cfg->m = sel->m;
519 cfg->n = sel->n;
520 cfg->p = p;
521 cfg->cpcon = sel->cpcon;
522 cfg->sdm_data = sel->sdm_data;
523
524 return 0;
525 }
526
527 static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
528 unsigned long rate, unsigned long parent_rate)
529 {
530 struct tegra_clk_pll *pll = to_clk_pll(hw);
531 unsigned long cfreq;
532 u32 p_div = 0;
533 int ret;
534
535 switch (parent_rate) {
536 case 12000000:
537 case 26000000:
538 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
539 break;
540 case 13000000:
541 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
542 break;
543 case 16800000:
544 case 19200000:
545 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
546 break;
547 case 9600000:
548 case 28800000:
549 /*
550 * PLL_P_OUT1 rate is not listed in PLLA table
551 */
552 cfreq = parent_rate / (parent_rate / 1000000);
553 break;
554 default:
555 pr_err("%s Unexpected reference rate %lu\n",
556 __func__, parent_rate);
557 BUG();
558 }
559
560 /* Raise VCO to guarantee 0.5% accuracy */
561 for (cfg->output_rate = rate; cfg->output_rate < 200 * cfreq;
562 cfg->output_rate <<= 1)
563 p_div++;
564
565 cfg->m = parent_rate / cfreq;
566 cfg->n = cfg->output_rate / cfreq;
567 cfg->cpcon = OUT_OF_TABLE_CPCON;
568
569 if (cfg->m > divm_max(pll) || cfg->n > divn_max(pll) ||
570 (1 << p_div) > divp_max(pll)
571 || cfg->output_rate > pll->params->vco_max) {
572 return -EINVAL;
573 }
574
575 cfg->output_rate >>= p_div;
576
577 if (pll->params->pdiv_tohw) {
578 ret = _p_div_to_hw(hw, 1 << p_div);
579 if (ret < 0)
580 return ret;
581 else
582 cfg->p = ret;
583 } else
584 cfg->p = p_div;
585
586 return 0;
587 }
588
589 /*
590 * SDM (Sigma Delta Modulator) divisor is 16-bit 2's complement signed number
591 * within (-2^12 ... 2^12-1) range. Represented in PLL data structure as
592 * unsigned 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used
593 * to indicate that SDM is disabled.
594 *
595 * Effective ndiv value when SDM is enabled: ndiv + 1/2 + sdm_din/2^13
596 */
597 static void clk_pll_set_sdm_data(struct clk_hw *hw,
598 struct tegra_clk_pll_freq_table *cfg)
599 {
600 struct tegra_clk_pll *pll = to_clk_pll(hw);
601 u32 val;
602 bool enabled;
603
604 if (!pll->params->sdm_din_reg)
605 return;
606
607 if (cfg->sdm_data) {
608 val = pll_readl_sdm_din(pll) & (~sdm_din_mask(pll));
609 val |= sdin_data_to_din(cfg->sdm_data) & sdm_din_mask(pll);
610 pll_writel_sdm_din(val, pll);
611 }
612
613 val = pll_readl_sdm_ctrl(pll);
614 enabled = (val & sdm_en_mask(pll));
615
616 if (cfg->sdm_data == 0 && enabled)
617 val &= ~pll->params->sdm_ctrl_en_mask;
618
619 if (cfg->sdm_data != 0 && !enabled)
620 val |= pll->params->sdm_ctrl_en_mask;
621
622 pll_writel_sdm_ctrl(val, pll);
623 }
624
625 static void _update_pll_mnp(struct tegra_clk_pll *pll,
626 struct tegra_clk_pll_freq_table *cfg)
627 {
628 u32 val;
629 struct tegra_clk_pll_params *params = pll->params;
630 struct div_nmp *div_nmp = params->div_nmp;
631
632 if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
633 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
634 PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
635 val = pll_override_readl(params->pmc_divp_reg, pll);
636 val &= ~(divp_mask(pll) << div_nmp->override_divp_shift);
637 val |= cfg->p << div_nmp->override_divp_shift;
638 pll_override_writel(val, params->pmc_divp_reg, pll);
639
640 val = pll_override_readl(params->pmc_divnm_reg, pll);
641 val &= ~(divm_mask(pll) << div_nmp->override_divm_shift) |
642 ~(divn_mask(pll) << div_nmp->override_divn_shift);
643 val |= (cfg->m << div_nmp->override_divm_shift) |
644 (cfg->n << div_nmp->override_divn_shift);
645 pll_override_writel(val, params->pmc_divnm_reg, pll);
646 } else {
647 val = pll_readl_base(pll);
648
649 val &= ~(divm_mask_shifted(pll) | divn_mask_shifted(pll) |
650 divp_mask_shifted(pll));
651
652 val |= (cfg->m << divm_shift(pll)) |
653 (cfg->n << divn_shift(pll)) |
654 (cfg->p << divp_shift(pll));
655
656 pll_writel_base(val, pll);
657
658 clk_pll_set_sdm_data(&pll->hw, cfg);
659 }
660 }
661
662 static void _get_pll_mnp(struct tegra_clk_pll *pll,
663 struct tegra_clk_pll_freq_table *cfg)
664 {
665 u32 val;
666 struct tegra_clk_pll_params *params = pll->params;
667 struct div_nmp *div_nmp = params->div_nmp;
668
669 if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
670 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
671 PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
672 val = pll_override_readl(params->pmc_divp_reg, pll);
673 cfg->p = (val >> div_nmp->override_divp_shift) & divp_mask(pll);
674
675 val = pll_override_readl(params->pmc_divnm_reg, pll);
676 cfg->m = (val >> div_nmp->override_divm_shift) & divm_mask(pll);
677 cfg->n = (val >> div_nmp->override_divn_shift) & divn_mask(pll);
678 } else {
679 val = pll_readl_base(pll);
680
681 cfg->m = (val >> div_nmp->divm_shift) & divm_mask(pll);
682 cfg->n = (val >> div_nmp->divn_shift) & divn_mask(pll);
683 cfg->p = (val >> div_nmp->divp_shift) & divp_mask(pll);
684
685 if (pll->params->sdm_din_reg) {
686 if (sdm_en_mask(pll) & pll_readl_sdm_ctrl(pll)) {
687 val = pll_readl_sdm_din(pll);
688 val &= sdm_din_mask(pll);
689 cfg->sdm_data = sdin_din_to_data(val);
690 }
691 }
692 }
693 }
694
695 static void _update_pll_cpcon(struct tegra_clk_pll *pll,
696 struct tegra_clk_pll_freq_table *cfg,
697 unsigned long rate)
698 {
699 u32 val;
700
701 val = pll_readl_misc(pll);
702
703 val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT);
704 val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT;
705
706 if (pll->params->flags & TEGRA_PLL_SET_LFCON) {
707 val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT);
708 if (cfg->n >= PLLDU_LFCON_SET_DIVN)
709 val |= 1 << PLL_MISC_LFCON_SHIFT;
710 } else if (pll->params->flags & TEGRA_PLL_SET_DCCON) {
711 val &= ~(1 << PLL_MISC_DCCON_SHIFT);
712 if (rate >= (pll->params->vco_max >> 1))
713 val |= 1 << PLL_MISC_DCCON_SHIFT;
714 }
715
716 pll_writel_misc(val, pll);
717 }
718
719 static void pll_clk_start_ss(struct tegra_clk_pll *pll)
720 {
721 if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
722 u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
723
724 val |= pll->params->ssc_ctrl_en_mask;
725 pll_writel(val, pll->params->ssc_ctrl_reg, pll);
726 }
727 }
728
729 static void pll_clk_stop_ss(struct tegra_clk_pll *pll)
730 {
731 if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
732 u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
733
734 val &= ~pll->params->ssc_ctrl_en_mask;
735 pll_writel(val, pll->params->ssc_ctrl_reg, pll);
736 }
737 }
738
739 static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
740 unsigned long rate)
741 {
742 struct tegra_clk_pll *pll = to_clk_pll(hw);
743 struct tegra_clk_pll_freq_table old_cfg;
744 int state, ret = 0;
745
746 state = clk_pll_is_enabled(hw);
747
748 _get_pll_mnp(pll, &old_cfg);
749
750 if (state && pll->params->defaults_set && pll->params->dyn_ramp &&
751 (cfg->m == old_cfg.m) && (cfg->p == old_cfg.p)) {
752 ret = pll->params->dyn_ramp(pll, cfg);
753 if (!ret)
754 return 0;
755 }
756
757 if (state) {
758 pll_clk_stop_ss(pll);
759 _clk_pll_disable(hw);
760 }
761
762 if (!pll->params->defaults_set && pll->params->set_defaults)
763 pll->params->set_defaults(pll);
764
765 _update_pll_mnp(pll, cfg);
766
767 if (pll->params->flags & TEGRA_PLL_HAS_CPCON)
768 _update_pll_cpcon(pll, cfg, rate);
769
770 if (state) {
771 _clk_pll_enable(hw);
772 ret = clk_pll_wait_for_lock(pll);
773 pll_clk_start_ss(pll);
774 }
775
776 return ret;
777 }
778
779 static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
780 unsigned long parent_rate)
781 {
782 struct tegra_clk_pll *pll = to_clk_pll(hw);
783 struct tegra_clk_pll_freq_table cfg, old_cfg;
784 unsigned long flags = 0;
785 int ret = 0;
786
787 if (pll->params->flags & TEGRA_PLL_FIXED) {
788 if (rate != pll->params->fixed_rate) {
789 pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
790 __func__, clk_hw_get_name(hw),
791 pll->params->fixed_rate, rate);
792 return -EINVAL;
793 }
794 return 0;
795 }
796
797 if (_get_table_rate(hw, &cfg, rate, parent_rate) &&
798 pll->params->calc_rate(hw, &cfg, rate, parent_rate)) {
799 pr_err("%s: Failed to set %s rate %lu\n", __func__,
800 clk_hw_get_name(hw), rate);
801 WARN_ON(1);
802 return -EINVAL;
803 }
804 if (pll->lock)
805 spin_lock_irqsave(pll->lock, flags);
806
807 _get_pll_mnp(pll, &old_cfg);
808 if (pll->params->flags & TEGRA_PLL_VCO_OUT)
809 cfg.p = old_cfg.p;
810
811 if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p ||
812 old_cfg.sdm_data != cfg.sdm_data)
813 ret = _program_pll(hw, &cfg, rate);
814
815 if (pll->lock)
816 spin_unlock_irqrestore(pll->lock, flags);
817
818 return ret;
819 }
820
821 static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
822 unsigned long *prate)
823 {
824 struct tegra_clk_pll *pll = to_clk_pll(hw);
825 struct tegra_clk_pll_freq_table cfg;
826
827 if (pll->params->flags & TEGRA_PLL_FIXED) {
828 /* PLLM/MB are used for memory; we do not change rate */
829 if (pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB))
830 return clk_hw_get_rate(hw);
831 return pll->params->fixed_rate;
832 }
833
834 if (_get_table_rate(hw, &cfg, rate, *prate) &&
835 pll->params->calc_rate(hw, &cfg, rate, *prate))
836 return -EINVAL;
837
838 return cfg.output_rate;
839 }
840
841 static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
842 unsigned long parent_rate)
843 {
844 struct tegra_clk_pll *pll = to_clk_pll(hw);
845 struct tegra_clk_pll_freq_table cfg;
846 u32 val;
847 u64 rate = parent_rate;
848 int pdiv;
849
850 val = pll_readl_base(pll);
851
852 if ((pll->params->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS))
853 return parent_rate;
854
855 if ((pll->params->flags & TEGRA_PLL_FIXED) &&
856 !(pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
857 !(val & PLL_BASE_OVERRIDE)) {
858 struct tegra_clk_pll_freq_table sel;
859 if (_get_table_rate(hw, &sel, pll->params->fixed_rate,
860 parent_rate)) {
861 pr_err("Clock %s has unknown fixed frequency\n",
862 clk_hw_get_name(hw));
863 BUG();
864 }
865 return pll->params->fixed_rate;
866 }
867
868 _get_pll_mnp(pll, &cfg);
869
870 if (pll->params->flags & TEGRA_PLL_VCO_OUT) {
871 pdiv = 1;
872 } else {
873 pdiv = _hw_to_p_div(hw, cfg.p);
874 if (pdiv < 0) {
875 WARN(1, "Clock %s has invalid pdiv value : 0x%x\n",
876 clk_hw_get_name(hw), cfg.p);
877 pdiv = 1;
878 }
879 }
880
881 if (pll->params->set_gain)
882 pll->params->set_gain(&cfg);
883
884 cfg.m *= pdiv;
885
886 rate *= cfg.n;
887 do_div(rate, cfg.m);
888
889 return rate;
890 }
891
892 static int clk_plle_training(struct tegra_clk_pll *pll)
893 {
894 u32 val;
895 unsigned long timeout;
896
897 if (!pll->pmc)
898 return -ENOSYS;
899
900 /*
901 * PLLE is already disabled, and setup cleared;
902 * create falling edge on PLLE IDDQ input.
903 */
904 val = readl(pll->pmc + PMC_SATA_PWRGT);
905 val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
906 writel(val, pll->pmc + PMC_SATA_PWRGT);
907
908 val = readl(pll->pmc + PMC_SATA_PWRGT);
909 val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
910 writel(val, pll->pmc + PMC_SATA_PWRGT);
911
912 val = readl(pll->pmc + PMC_SATA_PWRGT);
913 val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
914 writel(val, pll->pmc + PMC_SATA_PWRGT);
915
916 val = pll_readl_misc(pll);
917
918 timeout = jiffies + msecs_to_jiffies(100);
919 while (1) {
920 val = pll_readl_misc(pll);
921 if (val & PLLE_MISC_READY)
922 break;
923 if (time_after(jiffies, timeout)) {
924 pr_err("%s: timeout waiting for PLLE\n", __func__);
925 return -EBUSY;
926 }
927 udelay(300);
928 }
929
930 return 0;
931 }
932
933 static int clk_plle_enable(struct clk_hw *hw)
934 {
935 struct tegra_clk_pll *pll = to_clk_pll(hw);
936 unsigned long input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
937 struct tegra_clk_pll_freq_table sel;
938 u32 val;
939 int err;
940
941 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
942 return -EINVAL;
943
944 clk_pll_disable(hw);
945
946 val = pll_readl_misc(pll);
947 val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK);
948 pll_writel_misc(val, pll);
949
950 val = pll_readl_misc(pll);
951 if (!(val & PLLE_MISC_READY)) {
952 err = clk_plle_training(pll);
953 if (err)
954 return err;
955 }
956
957 if (pll->params->flags & TEGRA_PLLE_CONFIGURE) {
958 /* configure dividers */
959 val = pll_readl_base(pll);
960 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
961 divm_mask_shifted(pll));
962 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
963 val |= sel.m << divm_shift(pll);
964 val |= sel.n << divn_shift(pll);
965 val |= sel.p << divp_shift(pll);
966 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
967 pll_writel_base(val, pll);
968 }
969
970 val = pll_readl_misc(pll);
971 val |= PLLE_MISC_SETUP_VALUE;
972 val |= PLLE_MISC_LOCK_ENABLE;
973 pll_writel_misc(val, pll);
974
975 val = readl(pll->clk_base + PLLE_SS_CTRL);
976 val &= ~PLLE_SS_COEFFICIENTS_MASK;
977 val |= PLLE_SS_DISABLE;
978 writel(val, pll->clk_base + PLLE_SS_CTRL);
979
980 val = pll_readl_base(pll);
981 val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE);
982 pll_writel_base(val, pll);
983
984 clk_pll_wait_for_lock(pll);
985
986 return 0;
987 }
988
989 static unsigned long clk_plle_recalc_rate(struct clk_hw *hw,
990 unsigned long parent_rate)
991 {
992 struct tegra_clk_pll *pll = to_clk_pll(hw);
993 u32 val = pll_readl_base(pll);
994 u32 divn = 0, divm = 0, divp = 0;
995 u64 rate = parent_rate;
996
997 divp = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll));
998 divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll));
999 divm = (val >> pll->params->div_nmp->divm_shift) & (divm_mask(pll));
1000 divm *= divp;
1001
1002 rate *= divn;
1003 do_div(rate, divm);
1004 return rate;
1005 }
1006
1007 const struct clk_ops tegra_clk_pll_ops = {
1008 .is_enabled = clk_pll_is_enabled,
1009 .enable = clk_pll_enable,
1010 .disable = clk_pll_disable,
1011 .recalc_rate = clk_pll_recalc_rate,
1012 .round_rate = clk_pll_round_rate,
1013 .set_rate = clk_pll_set_rate,
1014 };
1015
1016 const struct clk_ops tegra_clk_plle_ops = {
1017 .recalc_rate = clk_plle_recalc_rate,
1018 .is_enabled = clk_pll_is_enabled,
1019 .disable = clk_pll_disable,
1020 .enable = clk_plle_enable,
1021 };
1022
1023 /*
1024 * Structure defining the fields for USB UTMI clocks Parameters.
1025 */
1026 struct utmi_clk_param {
1027 /* Oscillator Frequency in Hz */
1028 u32 osc_frequency;
1029 /* UTMIP PLL Enable Delay Count */
1030 u8 enable_delay_count;
1031 /* UTMIP PLL Stable count */
1032 u8 stable_count;
1033 /* UTMIP PLL Active delay count */
1034 u8 active_delay_count;
1035 /* UTMIP PLL Xtal frequency count */
1036 u8 xtal_freq_count;
1037 };
1038
1039 static const struct utmi_clk_param utmi_parameters[] = {
1040 {
1041 .osc_frequency = 13000000, .enable_delay_count = 0x02,
1042 .stable_count = 0x33, .active_delay_count = 0x05,
1043 .xtal_freq_count = 0x7f
1044 }, {
1045 .osc_frequency = 19200000, .enable_delay_count = 0x03,
1046 .stable_count = 0x4b, .active_delay_count = 0x06,
1047 .xtal_freq_count = 0xbb
1048 }, {
1049 .osc_frequency = 12000000, .enable_delay_count = 0x02,
1050 .stable_count = 0x2f, .active_delay_count = 0x04,
1051 .xtal_freq_count = 0x76
1052 }, {
1053 .osc_frequency = 26000000, .enable_delay_count = 0x04,
1054 .stable_count = 0x66, .active_delay_count = 0x09,
1055 .xtal_freq_count = 0xfe
1056 }, {
1057 .osc_frequency = 16800000, .enable_delay_count = 0x03,
1058 .stable_count = 0x41, .active_delay_count = 0x0a,
1059 .xtal_freq_count = 0xa4
1060 }, {
1061 .osc_frequency = 38400000, .enable_delay_count = 0x0,
1062 .stable_count = 0x0, .active_delay_count = 0x6,
1063 .xtal_freq_count = 0x80
1064 },
1065 };
1066
1067 static int clk_pllu_enable(struct clk_hw *hw)
1068 {
1069 struct tegra_clk_pll *pll = to_clk_pll(hw);
1070 struct clk_hw *pll_ref = clk_hw_get_parent(hw);
1071 struct clk_hw *osc = clk_hw_get_parent(pll_ref);
1072 const struct utmi_clk_param *params = NULL;
1073 unsigned long flags = 0, input_rate;
1074 unsigned int i;
1075 int ret = 0;
1076 u32 value;
1077
1078 if (!osc) {
1079 pr_err("%s: failed to get OSC clock\n", __func__);
1080 return -EINVAL;
1081 }
1082
1083 input_rate = clk_hw_get_rate(osc);
1084
1085 if (pll->lock)
1086 spin_lock_irqsave(pll->lock, flags);
1087
1088 _clk_pll_enable(hw);
1089
1090 ret = clk_pll_wait_for_lock(pll);
1091 if (ret < 0)
1092 goto out;
1093
1094 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
1095 if (input_rate == utmi_parameters[i].osc_frequency) {
1096 params = &utmi_parameters[i];
1097 break;
1098 }
1099 }
1100
1101 if (!params) {
1102 pr_err("%s: unexpected input rate %lu Hz\n", __func__,
1103 input_rate);
1104 ret = -EINVAL;
1105 goto out;
1106 }
1107
1108 value = pll_readl_base(pll);
1109 value &= ~PLLU_BASE_OVERRIDE;
1110 pll_writel_base(value, pll);
1111
1112 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2);
1113 /* Program UTMIP PLL stable and active counts */
1114 value &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
1115 value |= UTMIP_PLL_CFG2_STABLE_COUNT(params->stable_count);
1116 value &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
1117 value |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(params->active_delay_count);
1118 /* Remove power downs from UTMIP PLL control bits */
1119 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
1120 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
1121 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
1122 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2);
1123
1124 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
1125 /* Program UTMIP PLL delay and oscillator frequency counts */
1126 value &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1127 value |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(params->enable_delay_count);
1128 value &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1129 value |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(params->xtal_freq_count);
1130 /* Remove power downs from UTMIP PLL control bits */
1131 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1132 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
1133 value &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
1134 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
1135
1136 out:
1137 if (pll->lock)
1138 spin_unlock_irqrestore(pll->lock, flags);
1139
1140 return ret;
1141 }
1142
1143 static const struct clk_ops tegra_clk_pllu_ops = {
1144 .is_enabled = clk_pll_is_enabled,
1145 .enable = clk_pllu_enable,
1146 .disable = clk_pll_disable,
1147 .recalc_rate = clk_pll_recalc_rate,
1148 .round_rate = clk_pll_round_rate,
1149 .set_rate = clk_pll_set_rate,
1150 };
1151
1152 static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params,
1153 unsigned long parent_rate)
1154 {
1155 u16 mdiv = parent_rate / pll_params->cf_min;
1156
1157 if (pll_params->flags & TEGRA_MDIV_NEW)
1158 return (!pll_params->mdiv_default ? mdiv :
1159 min(mdiv, pll_params->mdiv_default));
1160
1161 if (pll_params->mdiv_default)
1162 return pll_params->mdiv_default;
1163
1164 if (parent_rate > pll_params->cf_max)
1165 return 2;
1166 else
1167 return 1;
1168 }
1169
1170 static int _calc_dynamic_ramp_rate(struct clk_hw *hw,
1171 struct tegra_clk_pll_freq_table *cfg,
1172 unsigned long rate, unsigned long parent_rate)
1173 {
1174 struct tegra_clk_pll *pll = to_clk_pll(hw);
1175 unsigned int p;
1176 int p_div;
1177
1178 if (!rate)
1179 return -EINVAL;
1180
1181 p = DIV_ROUND_UP(pll->params->vco_min, rate);
1182 cfg->m = _pll_fixed_mdiv(pll->params, parent_rate);
1183 cfg->output_rate = rate * p;
1184 cfg->n = cfg->output_rate * cfg->m / parent_rate;
1185 cfg->input_rate = parent_rate;
1186
1187 p_div = _p_div_to_hw(hw, p);
1188 if (p_div < 0)
1189 return p_div;
1190
1191 cfg->p = p_div;
1192
1193 if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max)
1194 return -EINVAL;
1195
1196 return 0;
1197 }
1198
1199 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
1200 defined(CONFIG_ARCH_TEGRA_124_SOC) || \
1201 defined(CONFIG_ARCH_TEGRA_132_SOC) || \
1202 defined(CONFIG_ARCH_TEGRA_210_SOC)
1203
1204 u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate)
1205 {
1206 struct tegra_clk_pll *pll = to_clk_pll(hw);
1207
1208 return (u16)_pll_fixed_mdiv(pll->params, input_rate);
1209 }
1210
1211 static unsigned long _clip_vco_min(unsigned long vco_min,
1212 unsigned long parent_rate)
1213 {
1214 return DIV_ROUND_UP(vco_min, parent_rate) * parent_rate;
1215 }
1216
1217 static int _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params,
1218 void __iomem *clk_base,
1219 unsigned long parent_rate)
1220 {
1221 u32 val;
1222 u32 step_a, step_b;
1223
1224 switch (parent_rate) {
1225 case 12000000:
1226 case 13000000:
1227 case 26000000:
1228 step_a = 0x2B;
1229 step_b = 0x0B;
1230 break;
1231 case 16800000:
1232 step_a = 0x1A;
1233 step_b = 0x09;
1234 break;
1235 case 19200000:
1236 step_a = 0x12;
1237 step_b = 0x08;
1238 break;
1239 default:
1240 pr_err("%s: Unexpected reference rate %lu\n",
1241 __func__, parent_rate);
1242 WARN_ON(1);
1243 return -EINVAL;
1244 }
1245
1246 val = step_a << pll_params->stepa_shift;
1247 val |= step_b << pll_params->stepb_shift;
1248 writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg);
1249
1250 return 0;
1251 }
1252
1253 static int _pll_ramp_calc_pll(struct clk_hw *hw,
1254 struct tegra_clk_pll_freq_table *cfg,
1255 unsigned long rate, unsigned long parent_rate)
1256 {
1257 struct tegra_clk_pll *pll = to_clk_pll(hw);
1258 int err = 0;
1259
1260 err = _get_table_rate(hw, cfg, rate, parent_rate);
1261 if (err < 0)
1262 err = _calc_dynamic_ramp_rate(hw, cfg, rate, parent_rate);
1263 else {
1264 if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) {
1265 WARN_ON(1);
1266 err = -EINVAL;
1267 goto out;
1268 }
1269 }
1270
1271 if (cfg->p > pll->params->max_p)
1272 err = -EINVAL;
1273
1274 out:
1275 return err;
1276 }
1277
1278 static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate,
1279 unsigned long parent_rate)
1280 {
1281 struct tegra_clk_pll *pll = to_clk_pll(hw);
1282 struct tegra_clk_pll_freq_table cfg, old_cfg;
1283 unsigned long flags = 0;
1284 int ret;
1285
1286 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
1287 if (ret < 0)
1288 return ret;
1289
1290 if (pll->lock)
1291 spin_lock_irqsave(pll->lock, flags);
1292
1293 _get_pll_mnp(pll, &old_cfg);
1294 if (pll->params->flags & TEGRA_PLL_VCO_OUT)
1295 cfg.p = old_cfg.p;
1296
1297 if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p)
1298 ret = _program_pll(hw, &cfg, rate);
1299
1300 if (pll->lock)
1301 spin_unlock_irqrestore(pll->lock, flags);
1302
1303 return ret;
1304 }
1305
1306 static long clk_pll_ramp_round_rate(struct clk_hw *hw, unsigned long rate,
1307 unsigned long *prate)
1308 {
1309 struct tegra_clk_pll *pll = to_clk_pll(hw);
1310 struct tegra_clk_pll_freq_table cfg;
1311 int ret, p_div;
1312 u64 output_rate = *prate;
1313
1314 ret = _pll_ramp_calc_pll(hw, &cfg, rate, *prate);
1315 if (ret < 0)
1316 return ret;
1317
1318 p_div = _hw_to_p_div(hw, cfg.p);
1319 if (p_div < 0)
1320 return p_div;
1321
1322 if (pll->params->set_gain)
1323 pll->params->set_gain(&cfg);
1324
1325 output_rate *= cfg.n;
1326 do_div(output_rate, cfg.m * p_div);
1327
1328 return output_rate;
1329 }
1330
1331 static void _pllcx_strobe(struct tegra_clk_pll *pll)
1332 {
1333 u32 val;
1334
1335 val = pll_readl_misc(pll);
1336 val |= PLLCX_MISC_STROBE;
1337 pll_writel_misc(val, pll);
1338 udelay(2);
1339
1340 val &= ~PLLCX_MISC_STROBE;
1341 pll_writel_misc(val, pll);
1342 }
1343
1344 static int clk_pllc_enable(struct clk_hw *hw)
1345 {
1346 struct tegra_clk_pll *pll = to_clk_pll(hw);
1347 u32 val;
1348 int ret;
1349 unsigned long flags = 0;
1350
1351 if (pll->lock)
1352 spin_lock_irqsave(pll->lock, flags);
1353
1354 _clk_pll_enable(hw);
1355 udelay(2);
1356
1357 val = pll_readl_misc(pll);
1358 val &= ~PLLCX_MISC_RESET;
1359 pll_writel_misc(val, pll);
1360 udelay(2);
1361
1362 _pllcx_strobe(pll);
1363
1364 ret = clk_pll_wait_for_lock(pll);
1365
1366 if (pll->lock)
1367 spin_unlock_irqrestore(pll->lock, flags);
1368
1369 return ret;
1370 }
1371
1372 static void _clk_pllc_disable(struct clk_hw *hw)
1373 {
1374 struct tegra_clk_pll *pll = to_clk_pll(hw);
1375 u32 val;
1376
1377 _clk_pll_disable(hw);
1378
1379 val = pll_readl_misc(pll);
1380 val |= PLLCX_MISC_RESET;
1381 pll_writel_misc(val, pll);
1382 udelay(2);
1383 }
1384
1385 static void clk_pllc_disable(struct clk_hw *hw)
1386 {
1387 struct tegra_clk_pll *pll = to_clk_pll(hw);
1388 unsigned long flags = 0;
1389
1390 if (pll->lock)
1391 spin_lock_irqsave(pll->lock, flags);
1392
1393 _clk_pllc_disable(hw);
1394
1395 if (pll->lock)
1396 spin_unlock_irqrestore(pll->lock, flags);
1397 }
1398
1399 static int _pllcx_update_dynamic_coef(struct tegra_clk_pll *pll,
1400 unsigned long input_rate, u32 n)
1401 {
1402 u32 val, n_threshold;
1403
1404 switch (input_rate) {
1405 case 12000000:
1406 n_threshold = 70;
1407 break;
1408 case 13000000:
1409 case 26000000:
1410 n_threshold = 71;
1411 break;
1412 case 16800000:
1413 n_threshold = 55;
1414 break;
1415 case 19200000:
1416 n_threshold = 48;
1417 break;
1418 default:
1419 pr_err("%s: Unexpected reference rate %lu\n",
1420 __func__, input_rate);
1421 return -EINVAL;
1422 }
1423
1424 val = pll_readl_misc(pll);
1425 val &= ~(PLLCX_MISC_SDM_DIV_MASK | PLLCX_MISC_FILT_DIV_MASK);
1426 val |= n <= n_threshold ?
1427 PLLCX_MISC_DIV_LOW_RANGE : PLLCX_MISC_DIV_HIGH_RANGE;
1428 pll_writel_misc(val, pll);
1429
1430 return 0;
1431 }
1432
1433 static int clk_pllc_set_rate(struct clk_hw *hw, unsigned long rate,
1434 unsigned long parent_rate)
1435 {
1436 struct tegra_clk_pll_freq_table cfg, old_cfg;
1437 struct tegra_clk_pll *pll = to_clk_pll(hw);
1438 unsigned long flags = 0;
1439 int state, ret = 0;
1440
1441 if (pll->lock)
1442 spin_lock_irqsave(pll->lock, flags);
1443
1444 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
1445 if (ret < 0)
1446 goto out;
1447
1448 _get_pll_mnp(pll, &old_cfg);
1449
1450 if (cfg.m != old_cfg.m) {
1451 WARN_ON(1);
1452 goto out;
1453 }
1454
1455 if (old_cfg.n == cfg.n && old_cfg.p == cfg.p)
1456 goto out;
1457
1458 state = clk_pll_is_enabled(hw);
1459 if (state)
1460 _clk_pllc_disable(hw);
1461
1462 ret = _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
1463 if (ret < 0)
1464 goto out;
1465
1466 _update_pll_mnp(pll, &cfg);
1467
1468 if (state)
1469 ret = clk_pllc_enable(hw);
1470
1471 out:
1472 if (pll->lock)
1473 spin_unlock_irqrestore(pll->lock, flags);
1474
1475 return ret;
1476 }
1477
1478 static long _pllre_calc_rate(struct tegra_clk_pll *pll,
1479 struct tegra_clk_pll_freq_table *cfg,
1480 unsigned long rate, unsigned long parent_rate)
1481 {
1482 u16 m, n;
1483 u64 output_rate = parent_rate;
1484
1485 m = _pll_fixed_mdiv(pll->params, parent_rate);
1486 n = rate * m / parent_rate;
1487
1488 output_rate *= n;
1489 do_div(output_rate, m);
1490
1491 if (cfg) {
1492 cfg->m = m;
1493 cfg->n = n;
1494 }
1495
1496 return output_rate;
1497 }
1498
1499 static int clk_pllre_set_rate(struct clk_hw *hw, unsigned long rate,
1500 unsigned long parent_rate)
1501 {
1502 struct tegra_clk_pll_freq_table cfg, old_cfg;
1503 struct tegra_clk_pll *pll = to_clk_pll(hw);
1504 unsigned long flags = 0;
1505 int state, ret = 0;
1506
1507 if (pll->lock)
1508 spin_lock_irqsave(pll->lock, flags);
1509
1510 _pllre_calc_rate(pll, &cfg, rate, parent_rate);
1511 _get_pll_mnp(pll, &old_cfg);
1512 cfg.p = old_cfg.p;
1513
1514 if (cfg.m != old_cfg.m || cfg.n != old_cfg.n) {
1515 state = clk_pll_is_enabled(hw);
1516 if (state)
1517 _clk_pll_disable(hw);
1518
1519 _update_pll_mnp(pll, &cfg);
1520
1521 if (state) {
1522 _clk_pll_enable(hw);
1523 ret = clk_pll_wait_for_lock(pll);
1524 }
1525 }
1526
1527 if (pll->lock)
1528 spin_unlock_irqrestore(pll->lock, flags);
1529
1530 return ret;
1531 }
1532
1533 static unsigned long clk_pllre_recalc_rate(struct clk_hw *hw,
1534 unsigned long parent_rate)
1535 {
1536 struct tegra_clk_pll_freq_table cfg;
1537 struct tegra_clk_pll *pll = to_clk_pll(hw);
1538 u64 rate = parent_rate;
1539
1540 _get_pll_mnp(pll, &cfg);
1541
1542 rate *= cfg.n;
1543 do_div(rate, cfg.m);
1544
1545 return rate;
1546 }
1547
1548 static long clk_pllre_round_rate(struct clk_hw *hw, unsigned long rate,
1549 unsigned long *prate)
1550 {
1551 struct tegra_clk_pll *pll = to_clk_pll(hw);
1552
1553 return _pllre_calc_rate(pll, NULL, rate, *prate);
1554 }
1555
1556 static int clk_plle_tegra114_enable(struct clk_hw *hw)
1557 {
1558 struct tegra_clk_pll *pll = to_clk_pll(hw);
1559 struct tegra_clk_pll_freq_table sel;
1560 u32 val;
1561 int ret;
1562 unsigned long flags = 0;
1563 unsigned long input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
1564
1565 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
1566 return -EINVAL;
1567
1568 if (pll->lock)
1569 spin_lock_irqsave(pll->lock, flags);
1570
1571 val = pll_readl_base(pll);
1572 val &= ~BIT(29); /* Disable lock override */
1573 pll_writel_base(val, pll);
1574
1575 val = pll_readl(pll->params->aux_reg, pll);
1576 val |= PLLE_AUX_ENABLE_SWCTL;
1577 val &= ~PLLE_AUX_SEQ_ENABLE;
1578 pll_writel(val, pll->params->aux_reg, pll);
1579 udelay(1);
1580
1581 val = pll_readl_misc(pll);
1582 val |= PLLE_MISC_LOCK_ENABLE;
1583 val |= PLLE_MISC_IDDQ_SW_CTRL;
1584 val &= ~PLLE_MISC_IDDQ_SW_VALUE;
1585 val |= PLLE_MISC_PLLE_PTS;
1586 val &= ~(PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK);
1587 pll_writel_misc(val, pll);
1588 udelay(5);
1589
1590 val = pll_readl(PLLE_SS_CTRL, pll);
1591 val |= PLLE_SS_DISABLE;
1592 pll_writel(val, PLLE_SS_CTRL, pll);
1593
1594 val = pll_readl_base(pll);
1595 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
1596 divm_mask_shifted(pll));
1597 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
1598 val |= sel.m << divm_shift(pll);
1599 val |= sel.n << divn_shift(pll);
1600 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
1601 pll_writel_base(val, pll);
1602 udelay(1);
1603
1604 _clk_pll_enable(hw);
1605 ret = clk_pll_wait_for_lock(pll);
1606
1607 if (ret < 0)
1608 goto out;
1609
1610 val = pll_readl(PLLE_SS_CTRL, pll);
1611 val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
1612 val &= ~PLLE_SS_COEFFICIENTS_MASK;
1613 val |= PLLE_SS_COEFFICIENTS_VAL_TEGRA114;
1614 pll_writel(val, PLLE_SS_CTRL, pll);
1615 val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
1616 pll_writel(val, PLLE_SS_CTRL, pll);
1617 udelay(1);
1618 val &= ~PLLE_SS_CNTL_INTERP_RESET;
1619 pll_writel(val, PLLE_SS_CTRL, pll);
1620 udelay(1);
1621
1622 /* Enable hw control of xusb brick pll */
1623 val = pll_readl_misc(pll);
1624 val &= ~PLLE_MISC_IDDQ_SW_CTRL;
1625 pll_writel_misc(val, pll);
1626
1627 val = pll_readl(pll->params->aux_reg, pll);
1628 val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SEQ_START_STATE);
1629 val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
1630 pll_writel(val, pll->params->aux_reg, pll);
1631 udelay(1);
1632 val |= PLLE_AUX_SEQ_ENABLE;
1633 pll_writel(val, pll->params->aux_reg, pll);
1634
1635 val = pll_readl(XUSBIO_PLL_CFG0, pll);
1636 val |= (XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET |
1637 XUSBIO_PLL_CFG0_SEQ_START_STATE);
1638 val &= ~(XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL |
1639 XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL);
1640 pll_writel(val, XUSBIO_PLL_CFG0, pll);
1641 udelay(1);
1642 val |= XUSBIO_PLL_CFG0_SEQ_ENABLE;
1643 pll_writel(val, XUSBIO_PLL_CFG0, pll);
1644
1645 /* Enable hw control of SATA pll */
1646 val = pll_readl(SATA_PLL_CFG0, pll);
1647 val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL;
1648 val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET;
1649 val |= SATA_PLL_CFG0_SEQ_START_STATE;
1650 pll_writel(val, SATA_PLL_CFG0, pll);
1651
1652 udelay(1);
1653
1654 val = pll_readl(SATA_PLL_CFG0, pll);
1655 val |= SATA_PLL_CFG0_SEQ_ENABLE;
1656 pll_writel(val, SATA_PLL_CFG0, pll);
1657
1658 out:
1659 if (pll->lock)
1660 spin_unlock_irqrestore(pll->lock, flags);
1661
1662 return ret;
1663 }
1664
1665 static void clk_plle_tegra114_disable(struct clk_hw *hw)
1666 {
1667 struct tegra_clk_pll *pll = to_clk_pll(hw);
1668 unsigned long flags = 0;
1669 u32 val;
1670
1671 if (pll->lock)
1672 spin_lock_irqsave(pll->lock, flags);
1673
1674 _clk_pll_disable(hw);
1675
1676 val = pll_readl_misc(pll);
1677 val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
1678 pll_writel_misc(val, pll);
1679 udelay(1);
1680
1681 if (pll->lock)
1682 spin_unlock_irqrestore(pll->lock, flags);
1683 }
1684
1685 static int clk_pllu_tegra114_enable(struct clk_hw *hw)
1686 {
1687 struct tegra_clk_pll *pll = to_clk_pll(hw);
1688 const struct utmi_clk_param *params = NULL;
1689 struct clk *osc = __clk_lookup("osc");
1690 unsigned long flags = 0, input_rate;
1691 unsigned int i;
1692 int ret = 0;
1693 u32 value;
1694
1695 if (!osc) {
1696 pr_err("%s: failed to get OSC clock\n", __func__);
1697 return -EINVAL;
1698 }
1699
1700 input_rate = clk_hw_get_rate(__clk_get_hw(osc));
1701
1702 if (pll->lock)
1703 spin_lock_irqsave(pll->lock, flags);
1704
1705 _clk_pll_enable(hw);
1706
1707 ret = clk_pll_wait_for_lock(pll);
1708 if (ret < 0)
1709 goto out;
1710
1711 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
1712 if (input_rate == utmi_parameters[i].osc_frequency) {
1713 params = &utmi_parameters[i];
1714 break;
1715 }
1716 }
1717
1718 if (!params) {
1719 pr_err("%s: unexpected input rate %lu Hz\n", __func__,
1720 input_rate);
1721 ret = -EINVAL;
1722 goto out;
1723 }
1724
1725 value = pll_readl_base(pll);
1726 value &= ~PLLU_BASE_OVERRIDE;
1727 pll_writel_base(value, pll);
1728
1729 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2);
1730 /* Program UTMIP PLL stable and active counts */
1731 value &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
1732 value |= UTMIP_PLL_CFG2_STABLE_COUNT(params->stable_count);
1733 value &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
1734 value |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(params->active_delay_count);
1735 /* Remove power downs from UTMIP PLL control bits */
1736 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
1737 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
1738 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
1739 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2);
1740
1741 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
1742 /* Program UTMIP PLL delay and oscillator frequency counts */
1743 value &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1744 value |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(params->enable_delay_count);
1745 value &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1746 value |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(params->xtal_freq_count);
1747 /* Remove power downs from UTMIP PLL control bits */
1748 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1749 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
1750 value &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP;
1751 value &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
1752 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
1753
1754 /* Setup HW control of UTMIPLL */
1755 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1756 value |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
1757 value &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
1758 value |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE;
1759 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1760
1761 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
1762 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
1763 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1764 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
1765
1766 udelay(1);
1767
1768 /*
1769 * Setup SW override of UTMIPLL assuming USB2.0 ports are assigned
1770 * to USB2
1771 */
1772 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1773 value |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL;
1774 value &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
1775 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1776
1777 udelay(1);
1778
1779 /* Enable HW control of UTMIPLL */
1780 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1781 value |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
1782 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1783
1784 out:
1785 if (pll->lock)
1786 spin_unlock_irqrestore(pll->lock, flags);
1787
1788 return ret;
1789 }
1790 #endif
1791
1792 static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base,
1793 void __iomem *pmc, struct tegra_clk_pll_params *pll_params,
1794 spinlock_t *lock)
1795 {
1796 struct tegra_clk_pll *pll;
1797
1798 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
1799 if (!pll)
1800 return ERR_PTR(-ENOMEM);
1801
1802 pll->clk_base = clk_base;
1803 pll->pmc = pmc;
1804
1805 pll->params = pll_params;
1806 pll->lock = lock;
1807
1808 if (!pll_params->div_nmp)
1809 pll_params->div_nmp = &default_nmp;
1810
1811 return pll;
1812 }
1813
1814 static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll,
1815 const char *name, const char *parent_name, unsigned long flags,
1816 const struct clk_ops *ops)
1817 {
1818 struct clk_init_data init;
1819
1820 init.name = name;
1821 init.ops = ops;
1822 init.flags = flags;
1823 init.parent_names = (parent_name ? &parent_name : NULL);
1824 init.num_parents = (parent_name ? 1 : 0);
1825
1826 /* Default to _calc_rate if unspecified */
1827 if (!pll->params->calc_rate) {
1828 if (pll->params->flags & TEGRA_PLLM)
1829 pll->params->calc_rate = _calc_dynamic_ramp_rate;
1830 else
1831 pll->params->calc_rate = _calc_rate;
1832 }
1833
1834 if (pll->params->set_defaults)
1835 pll->params->set_defaults(pll);
1836
1837 /* Data in .init is copied by clk_register(), so stack variable OK */
1838 pll->hw.init = &init;
1839
1840 return clk_register(NULL, &pll->hw);
1841 }
1842
1843 struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
1844 void __iomem *clk_base, void __iomem *pmc,
1845 unsigned long flags, struct tegra_clk_pll_params *pll_params,
1846 spinlock_t *lock)
1847 {
1848 struct tegra_clk_pll *pll;
1849 struct clk *clk;
1850
1851 pll_params->flags |= TEGRA_PLL_BYPASS;
1852
1853 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1854 if (IS_ERR(pll))
1855 return ERR_CAST(pll);
1856
1857 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1858 &tegra_clk_pll_ops);
1859 if (IS_ERR(clk))
1860 kfree(pll);
1861
1862 return clk;
1863 }
1864
1865 static struct div_nmp pll_e_nmp = {
1866 .divn_shift = PLLE_BASE_DIVN_SHIFT,
1867 .divn_width = PLLE_BASE_DIVN_WIDTH,
1868 .divm_shift = PLLE_BASE_DIVM_SHIFT,
1869 .divm_width = PLLE_BASE_DIVM_WIDTH,
1870 .divp_shift = PLLE_BASE_DIVP_SHIFT,
1871 .divp_width = PLLE_BASE_DIVP_WIDTH,
1872 };
1873
1874 struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
1875 void __iomem *clk_base, void __iomem *pmc,
1876 unsigned long flags, struct tegra_clk_pll_params *pll_params,
1877 spinlock_t *lock)
1878 {
1879 struct tegra_clk_pll *pll;
1880 struct clk *clk;
1881
1882 pll_params->flags |= TEGRA_PLL_BYPASS;
1883
1884 if (!pll_params->div_nmp)
1885 pll_params->div_nmp = &pll_e_nmp;
1886
1887 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1888 if (IS_ERR(pll))
1889 return ERR_CAST(pll);
1890
1891 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1892 &tegra_clk_plle_ops);
1893 if (IS_ERR(clk))
1894 kfree(pll);
1895
1896 return clk;
1897 }
1898
1899 struct clk *tegra_clk_register_pllu(const char *name, const char *parent_name,
1900 void __iomem *clk_base, unsigned long flags,
1901 struct tegra_clk_pll_params *pll_params, spinlock_t *lock)
1902 {
1903 struct tegra_clk_pll *pll;
1904 struct clk *clk;
1905
1906 pll_params->flags |= TEGRA_PLLU;
1907
1908 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
1909 if (IS_ERR(pll))
1910 return ERR_CAST(pll);
1911
1912 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1913 &tegra_clk_pllu_ops);
1914 if (IS_ERR(clk))
1915 kfree(pll);
1916
1917 return clk;
1918 }
1919
1920 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
1921 defined(CONFIG_ARCH_TEGRA_124_SOC) || \
1922 defined(CONFIG_ARCH_TEGRA_132_SOC) || \
1923 defined(CONFIG_ARCH_TEGRA_210_SOC)
1924 static const struct clk_ops tegra_clk_pllxc_ops = {
1925 .is_enabled = clk_pll_is_enabled,
1926 .enable = clk_pll_enable,
1927 .disable = clk_pll_disable,
1928 .recalc_rate = clk_pll_recalc_rate,
1929 .round_rate = clk_pll_ramp_round_rate,
1930 .set_rate = clk_pllxc_set_rate,
1931 };
1932
1933 static const struct clk_ops tegra_clk_pllc_ops = {
1934 .is_enabled = clk_pll_is_enabled,
1935 .enable = clk_pllc_enable,
1936 .disable = clk_pllc_disable,
1937 .recalc_rate = clk_pll_recalc_rate,
1938 .round_rate = clk_pll_ramp_round_rate,
1939 .set_rate = clk_pllc_set_rate,
1940 };
1941
1942 static const struct clk_ops tegra_clk_pllre_ops = {
1943 .is_enabled = clk_pll_is_enabled,
1944 .enable = clk_pll_enable,
1945 .disable = clk_pll_disable,
1946 .recalc_rate = clk_pllre_recalc_rate,
1947 .round_rate = clk_pllre_round_rate,
1948 .set_rate = clk_pllre_set_rate,
1949 };
1950
1951 static const struct clk_ops tegra_clk_plle_tegra114_ops = {
1952 .is_enabled = clk_pll_is_enabled,
1953 .enable = clk_plle_tegra114_enable,
1954 .disable = clk_plle_tegra114_disable,
1955 .recalc_rate = clk_pll_recalc_rate,
1956 };
1957
1958 static const struct clk_ops tegra_clk_pllu_tegra114_ops = {
1959 .is_enabled = clk_pll_is_enabled,
1960 .enable = clk_pllu_tegra114_enable,
1961 .disable = clk_pll_disable,
1962 .recalc_rate = clk_pll_recalc_rate,
1963 };
1964
1965 struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
1966 void __iomem *clk_base, void __iomem *pmc,
1967 unsigned long flags,
1968 struct tegra_clk_pll_params *pll_params,
1969 spinlock_t *lock)
1970 {
1971 struct tegra_clk_pll *pll;
1972 struct clk *clk, *parent;
1973 unsigned long parent_rate;
1974 u32 val, val_iddq;
1975
1976 parent = __clk_lookup(parent_name);
1977 if (!parent) {
1978 WARN(1, "parent clk %s of %s must be registered first\n",
1979 parent_name, name);
1980 return ERR_PTR(-EINVAL);
1981 }
1982
1983 if (!pll_params->pdiv_tohw)
1984 return ERR_PTR(-EINVAL);
1985
1986 parent_rate = clk_get_rate(parent);
1987
1988 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1989
1990 if (pll_params->adjust_vco)
1991 pll_params->vco_min = pll_params->adjust_vco(pll_params,
1992 parent_rate);
1993
1994 /*
1995 * If the pll has a set_defaults callback, it will take care of
1996 * configuring dynamic ramping and setting IDDQ in that path.
1997 */
1998 if (!pll_params->set_defaults) {
1999 int err;
2000
2001 err = _setup_dynamic_ramp(pll_params, clk_base, parent_rate);
2002 if (err)
2003 return ERR_PTR(err);
2004
2005 val = readl_relaxed(clk_base + pll_params->base_reg);
2006 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
2007
2008 if (val & PLL_BASE_ENABLE)
2009 WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx));
2010 else {
2011 val_iddq |= BIT(pll_params->iddq_bit_idx);
2012 writel_relaxed(val_iddq,
2013 clk_base + pll_params->iddq_reg);
2014 }
2015 }
2016
2017 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2018 if (IS_ERR(pll))
2019 return ERR_CAST(pll);
2020
2021 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2022 &tegra_clk_pllxc_ops);
2023 if (IS_ERR(clk))
2024 kfree(pll);
2025
2026 return clk;
2027 }
2028
2029 struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
2030 void __iomem *clk_base, void __iomem *pmc,
2031 unsigned long flags,
2032 struct tegra_clk_pll_params *pll_params,
2033 spinlock_t *lock, unsigned long parent_rate)
2034 {
2035 u32 val;
2036 struct tegra_clk_pll *pll;
2037 struct clk *clk;
2038
2039 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2040
2041 if (pll_params->adjust_vco)
2042 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2043 parent_rate);
2044
2045 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2046 if (IS_ERR(pll))
2047 return ERR_CAST(pll);
2048
2049 /* program minimum rate by default */
2050
2051 val = pll_readl_base(pll);
2052 if (val & PLL_BASE_ENABLE)
2053 WARN_ON(readl_relaxed(clk_base + pll_params->iddq_reg) &
2054 BIT(pll_params->iddq_bit_idx));
2055 else {
2056 int m;
2057
2058 m = _pll_fixed_mdiv(pll_params, parent_rate);
2059 val = m << divm_shift(pll);
2060 val |= (pll_params->vco_min / parent_rate) << divn_shift(pll);
2061 pll_writel_base(val, pll);
2062 }
2063
2064 /* disable lock override */
2065
2066 val = pll_readl_misc(pll);
2067 val &= ~BIT(29);
2068 pll_writel_misc(val, pll);
2069
2070 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2071 &tegra_clk_pllre_ops);
2072 if (IS_ERR(clk))
2073 kfree(pll);
2074
2075 return clk;
2076 }
2077
2078 struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
2079 void __iomem *clk_base, void __iomem *pmc,
2080 unsigned long flags,
2081 struct tegra_clk_pll_params *pll_params,
2082 spinlock_t *lock)
2083 {
2084 struct tegra_clk_pll *pll;
2085 struct clk *clk, *parent;
2086 unsigned long parent_rate;
2087
2088 if (!pll_params->pdiv_tohw)
2089 return ERR_PTR(-EINVAL);
2090
2091 parent = __clk_lookup(parent_name);
2092 if (!parent) {
2093 WARN(1, "parent clk %s of %s must be registered first\n",
2094 parent_name, name);
2095 return ERR_PTR(-EINVAL);
2096 }
2097
2098 parent_rate = clk_get_rate(parent);
2099
2100 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2101
2102 if (pll_params->adjust_vco)
2103 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2104 parent_rate);
2105
2106 pll_params->flags |= TEGRA_PLL_BYPASS;
2107 pll_params->flags |= TEGRA_PLLM;
2108 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2109 if (IS_ERR(pll))
2110 return ERR_CAST(pll);
2111
2112 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2113 &tegra_clk_pll_ops);
2114 if (IS_ERR(clk))
2115 kfree(pll);
2116
2117 return clk;
2118 }
2119
2120 struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
2121 void __iomem *clk_base, void __iomem *pmc,
2122 unsigned long flags,
2123 struct tegra_clk_pll_params *pll_params,
2124 spinlock_t *lock)
2125 {
2126 struct clk *parent, *clk;
2127 const struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
2128 struct tegra_clk_pll *pll;
2129 struct tegra_clk_pll_freq_table cfg;
2130 unsigned long parent_rate;
2131
2132 if (!p_tohw)
2133 return ERR_PTR(-EINVAL);
2134
2135 parent = __clk_lookup(parent_name);
2136 if (!parent) {
2137 WARN(1, "parent clk %s of %s must be registered first\n",
2138 parent_name, name);
2139 return ERR_PTR(-EINVAL);
2140 }
2141
2142 parent_rate = clk_get_rate(parent);
2143
2144 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2145
2146 pll_params->flags |= TEGRA_PLL_BYPASS;
2147 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2148 if (IS_ERR(pll))
2149 return ERR_CAST(pll);
2150
2151 /*
2152 * Most of PLLC register fields are shadowed, and can not be read
2153 * directly from PLL h/w. Hence, actual PLLC boot state is unknown.
2154 * Initialize PLL to default state: disabled, reset; shadow registers
2155 * loaded with default parameters; dividers are preset for half of
2156 * minimum VCO rate (the latter assured that shadowed divider settings
2157 * are within supported range).
2158 */
2159
2160 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
2161 cfg.n = cfg.m * pll_params->vco_min / parent_rate;
2162
2163 while (p_tohw->pdiv) {
2164 if (p_tohw->pdiv == 2) {
2165 cfg.p = p_tohw->hw_val;
2166 break;
2167 }
2168 p_tohw++;
2169 }
2170
2171 if (!p_tohw->pdiv) {
2172 WARN_ON(1);
2173 return ERR_PTR(-EINVAL);
2174 }
2175
2176 pll_writel_base(0, pll);
2177 _update_pll_mnp(pll, &cfg);
2178
2179 pll_writel_misc(PLLCX_MISC_DEFAULT, pll);
2180 pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll);
2181 pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll);
2182 pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll);
2183
2184 _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
2185
2186 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2187 &tegra_clk_pllc_ops);
2188 if (IS_ERR(clk))
2189 kfree(pll);
2190
2191 return clk;
2192 }
2193
2194 struct clk *tegra_clk_register_plle_tegra114(const char *name,
2195 const char *parent_name,
2196 void __iomem *clk_base, unsigned long flags,
2197 struct tegra_clk_pll_params *pll_params,
2198 spinlock_t *lock)
2199 {
2200 struct tegra_clk_pll *pll;
2201 struct clk *clk;
2202 u32 val, val_aux;
2203
2204 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2205 if (IS_ERR(pll))
2206 return ERR_CAST(pll);
2207
2208 /* ensure parent is set to pll_re_vco */
2209
2210 val = pll_readl_base(pll);
2211 val_aux = pll_readl(pll_params->aux_reg, pll);
2212
2213 if (val & PLL_BASE_ENABLE) {
2214 if ((val_aux & PLLE_AUX_PLLRE_SEL) ||
2215 (val_aux & PLLE_AUX_PLLP_SEL))
2216 WARN(1, "pll_e enabled with unsupported parent %s\n",
2217 (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" :
2218 "pll_re_vco");
2219 } else {
2220 val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
2221 pll_writel(val_aux, pll_params->aux_reg, pll);
2222 }
2223
2224 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2225 &tegra_clk_plle_tegra114_ops);
2226 if (IS_ERR(clk))
2227 kfree(pll);
2228
2229 return clk;
2230 }
2231
2232 struct clk *
2233 tegra_clk_register_pllu_tegra114(const char *name, const char *parent_name,
2234 void __iomem *clk_base, unsigned long flags,
2235 struct tegra_clk_pll_params *pll_params,
2236 spinlock_t *lock)
2237 {
2238 struct tegra_clk_pll *pll;
2239 struct clk *clk;
2240
2241 pll_params->flags |= TEGRA_PLLU;
2242
2243 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2244 if (IS_ERR(pll))
2245 return ERR_CAST(pll);
2246
2247 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2248 &tegra_clk_pllu_tegra114_ops);
2249 if (IS_ERR(clk))
2250 kfree(pll);
2251
2252 return clk;
2253 }
2254 #endif
2255
2256 #if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC)
2257 static const struct clk_ops tegra_clk_pllss_ops = {
2258 .is_enabled = clk_pll_is_enabled,
2259 .enable = clk_pll_enable,
2260 .disable = clk_pll_disable,
2261 .recalc_rate = clk_pll_recalc_rate,
2262 .round_rate = clk_pll_ramp_round_rate,
2263 .set_rate = clk_pllxc_set_rate,
2264 };
2265
2266 struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
2267 void __iomem *clk_base, unsigned long flags,
2268 struct tegra_clk_pll_params *pll_params,
2269 spinlock_t *lock)
2270 {
2271 struct tegra_clk_pll *pll;
2272 struct clk *clk, *parent;
2273 struct tegra_clk_pll_freq_table cfg;
2274 unsigned long parent_rate;
2275 u32 val, val_iddq;
2276 int i;
2277
2278 if (!pll_params->div_nmp)
2279 return ERR_PTR(-EINVAL);
2280
2281 parent = __clk_lookup(parent_name);
2282 if (!parent) {
2283 WARN(1, "parent clk %s of %s must be registered first\n",
2284 parent_name, name);
2285 return ERR_PTR(-EINVAL);
2286 }
2287
2288 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2289 if (IS_ERR(pll))
2290 return ERR_CAST(pll);
2291
2292 val = pll_readl_base(pll);
2293 val &= ~PLLSS_REF_SRC_SEL_MASK;
2294 pll_writel_base(val, pll);
2295
2296 parent_rate = clk_get_rate(parent);
2297
2298 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2299
2300 /* initialize PLL to minimum rate */
2301
2302 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
2303 cfg.n = cfg.m * pll_params->vco_min / parent_rate;
2304
2305 for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++)
2306 ;
2307 if (!i) {
2308 kfree(pll);
2309 return ERR_PTR(-EINVAL);
2310 }
2311
2312 cfg.p = pll_params->pdiv_tohw[i-1].hw_val;
2313
2314 _update_pll_mnp(pll, &cfg);
2315
2316 pll_writel_misc(PLLSS_MISC_DEFAULT, pll);
2317 pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll);
2318 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll);
2319 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll);
2320
2321 val = pll_readl_base(pll);
2322 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
2323 if (val & PLL_BASE_ENABLE) {
2324 if (val_iddq & BIT(pll_params->iddq_bit_idx)) {
2325 WARN(1, "%s is on but IDDQ set\n", name);
2326 kfree(pll);
2327 return ERR_PTR(-EINVAL);
2328 }
2329 } else {
2330 val_iddq |= BIT(pll_params->iddq_bit_idx);
2331 writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg);
2332 }
2333
2334 val &= ~PLLSS_LOCK_OVERRIDE;
2335 pll_writel_base(val, pll);
2336
2337 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2338 &tegra_clk_pllss_ops);
2339
2340 if (IS_ERR(clk))
2341 kfree(pll);
2342
2343 return clk;
2344 }
2345 #endif
2346
2347 #if defined(CONFIG_ARCH_TEGRA_210_SOC)
2348 struct clk *tegra_clk_register_pllre_tegra210(const char *name,
2349 const char *parent_name, void __iomem *clk_base,
2350 void __iomem *pmc, unsigned long flags,
2351 struct tegra_clk_pll_params *pll_params,
2352 spinlock_t *lock, unsigned long parent_rate)
2353 {
2354 u32 val;
2355 struct tegra_clk_pll *pll;
2356 struct clk *clk;
2357
2358 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2359
2360 if (pll_params->adjust_vco)
2361 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2362 parent_rate);
2363
2364 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2365 if (IS_ERR(pll))
2366 return ERR_CAST(pll);
2367
2368 /* program minimum rate by default */
2369
2370 val = pll_readl_base(pll);
2371 if (val & PLL_BASE_ENABLE)
2372 WARN_ON(readl_relaxed(clk_base + pll_params->iddq_reg) &
2373 BIT(pll_params->iddq_bit_idx));
2374 else {
2375 val = 0x4 << divm_shift(pll);
2376 val |= 0x41 << divn_shift(pll);
2377 pll_writel_base(val, pll);
2378 }
2379
2380 /* disable lock override */
2381
2382 val = pll_readl_misc(pll);
2383 val &= ~BIT(29);
2384 pll_writel_misc(val, pll);
2385
2386 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2387 &tegra_clk_pllre_ops);
2388 if (IS_ERR(clk))
2389 kfree(pll);
2390
2391 return clk;
2392 }
2393
2394 static int clk_plle_tegra210_enable(struct clk_hw *hw)
2395 {
2396 struct tegra_clk_pll *pll = to_clk_pll(hw);
2397 struct tegra_clk_pll_freq_table sel;
2398 u32 val;
2399 int ret = 0;
2400 unsigned long flags = 0;
2401 unsigned long input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
2402
2403 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
2404 return -EINVAL;
2405
2406 if (pll->lock)
2407 spin_lock_irqsave(pll->lock, flags);
2408
2409 val = pll_readl(pll->params->aux_reg, pll);
2410 if (val & PLLE_AUX_SEQ_ENABLE)
2411 goto out;
2412
2413 val = pll_readl_base(pll);
2414 val &= ~BIT(30); /* Disable lock override */
2415 pll_writel_base(val, pll);
2416
2417 val = pll_readl_misc(pll);
2418 val |= PLLE_MISC_LOCK_ENABLE;
2419 val |= PLLE_MISC_IDDQ_SW_CTRL;
2420 val &= ~PLLE_MISC_IDDQ_SW_VALUE;
2421 val |= PLLE_MISC_PLLE_PTS;
2422 val &= ~(PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK);
2423 pll_writel_misc(val, pll);
2424 udelay(5);
2425
2426 val = pll_readl(PLLE_SS_CTRL, pll);
2427 val |= PLLE_SS_DISABLE;
2428 pll_writel(val, PLLE_SS_CTRL, pll);
2429
2430 val = pll_readl_base(pll);
2431 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
2432 divm_mask_shifted(pll));
2433 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
2434 val |= sel.m << divm_shift(pll);
2435 val |= sel.n << divn_shift(pll);
2436 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
2437 pll_writel_base(val, pll);
2438 udelay(1);
2439
2440 val = pll_readl_base(pll);
2441 val |= PLLE_BASE_ENABLE;
2442 pll_writel_base(val, pll);
2443
2444 ret = clk_pll_wait_for_lock(pll);
2445
2446 if (ret < 0)
2447 goto out;
2448
2449 val = pll_readl(PLLE_SS_CTRL, pll);
2450 val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
2451 val &= ~PLLE_SS_COEFFICIENTS_MASK;
2452 val |= PLLE_SS_COEFFICIENTS_VAL_TEGRA210;
2453 pll_writel(val, PLLE_SS_CTRL, pll);
2454 val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
2455 pll_writel(val, PLLE_SS_CTRL, pll);
2456 udelay(1);
2457 val &= ~PLLE_SS_CNTL_INTERP_RESET;
2458 pll_writel(val, PLLE_SS_CTRL, pll);
2459 udelay(1);
2460
2461 val = pll_readl_misc(pll);
2462 val &= ~PLLE_MISC_IDDQ_SW_CTRL;
2463 pll_writel_misc(val, pll);
2464
2465 val = pll_readl(pll->params->aux_reg, pll);
2466 val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SS_SEQ_INCLUDE);
2467 val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
2468 pll_writel(val, pll->params->aux_reg, pll);
2469 udelay(1);
2470 val |= PLLE_AUX_SEQ_ENABLE;
2471 pll_writel(val, pll->params->aux_reg, pll);
2472
2473 out:
2474 if (pll->lock)
2475 spin_unlock_irqrestore(pll->lock, flags);
2476
2477 return ret;
2478 }
2479
2480 static void clk_plle_tegra210_disable(struct clk_hw *hw)
2481 {
2482 struct tegra_clk_pll *pll = to_clk_pll(hw);
2483 unsigned long flags = 0;
2484 u32 val;
2485
2486 if (pll->lock)
2487 spin_lock_irqsave(pll->lock, flags);
2488
2489 /* If PLLE HW sequencer is enabled, SW should not disable PLLE */
2490 val = pll_readl(pll->params->aux_reg, pll);
2491 if (val & PLLE_AUX_SEQ_ENABLE)
2492 goto out;
2493
2494 val = pll_readl_base(pll);
2495 val &= ~PLLE_BASE_ENABLE;
2496 pll_writel_base(val, pll);
2497
2498 val = pll_readl(pll->params->aux_reg, pll);
2499 val |= PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL;
2500 pll_writel(val, pll->params->aux_reg, pll);
2501
2502 val = pll_readl_misc(pll);
2503 val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
2504 pll_writel_misc(val, pll);
2505 udelay(1);
2506
2507 out:
2508 if (pll->lock)
2509 spin_unlock_irqrestore(pll->lock, flags);
2510 }
2511
2512 static int clk_plle_tegra210_is_enabled(struct clk_hw *hw)
2513 {
2514 struct tegra_clk_pll *pll = to_clk_pll(hw);
2515 u32 val;
2516
2517 val = pll_readl_base(pll);
2518
2519 return val & PLLE_BASE_ENABLE ? 1 : 0;
2520 }
2521
2522 static int clk_pllu_tegra210_enable(struct clk_hw *hw)
2523 {
2524 struct tegra_clk_pll *pll = to_clk_pll(hw);
2525 struct clk_hw *pll_ref = clk_hw_get_parent(hw);
2526 struct clk_hw *osc = clk_hw_get_parent(pll_ref);
2527 const struct utmi_clk_param *params = NULL;
2528 unsigned long flags = 0, input_rate;
2529 unsigned int i;
2530 int ret = 0;
2531 u32 value;
2532
2533 if (!osc) {
2534 pr_err("%s: failed to get OSC clock\n", __func__);
2535 return -EINVAL;
2536 }
2537
2538 input_rate = clk_hw_get_rate(osc);
2539
2540 if (pll->lock)
2541 spin_lock_irqsave(pll->lock, flags);
2542
2543 _clk_pll_enable(hw);
2544
2545 ret = clk_pll_wait_for_lock(pll);
2546 if (ret < 0)
2547 goto out;
2548
2549 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
2550 if (input_rate == utmi_parameters[i].osc_frequency) {
2551 params = &utmi_parameters[i];
2552 break;
2553 }
2554 }
2555
2556 if (!params) {
2557 pr_err("%s: unexpected input rate %lu Hz\n", __func__,
2558 input_rate);
2559 ret = -EINVAL;
2560 goto out;
2561 }
2562
2563 value = pll_readl_base(pll);
2564 value &= ~PLLU_BASE_OVERRIDE;
2565 pll_writel_base(value, pll);
2566
2567 /* Put PLLU under HW control */
2568 value = readl_relaxed(pll->clk_base + PLLU_HW_PWRDN_CFG0);
2569 value |= PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE |
2570 PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT |
2571 PLLU_HW_PWRDN_CFG0_USE_LOCKDET;
2572 value &= ~(PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL |
2573 PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL);
2574 writel_relaxed(value, pll->clk_base + PLLU_HW_PWRDN_CFG0);
2575
2576 value = readl_relaxed(pll->clk_base + XUSB_PLL_CFG0);
2577 value &= ~XUSB_PLL_CFG0_PLLU_LOCK_DLY;
2578 writel_relaxed(value, pll->clk_base + XUSB_PLL_CFG0);
2579
2580 udelay(1);
2581
2582 value = readl_relaxed(pll->clk_base + PLLU_HW_PWRDN_CFG0);
2583 value |= PLLU_HW_PWRDN_CFG0_SEQ_ENABLE;
2584 writel_relaxed(value, pll->clk_base + PLLU_HW_PWRDN_CFG0);
2585
2586 udelay(1);
2587
2588 /* Disable PLLU clock branch to UTMIPLL since it uses OSC */
2589 value = pll_readl_base(pll);
2590 value &= ~PLLU_BASE_CLKENABLE_USB;
2591 pll_writel_base(value, pll);
2592
2593 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
2594 if (value & UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE) {
2595 pr_debug("UTMIPLL already enabled\n");
2596 goto out;
2597 }
2598
2599 value &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
2600 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
2601
2602 /* Program UTMIP PLL stable and active counts */
2603 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2);
2604 value &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
2605 value |= UTMIP_PLL_CFG2_STABLE_COUNT(params->stable_count);
2606 value &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
2607 value |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(params->active_delay_count);
2608 value |= UTMIP_PLL_CFG2_PHY_XTAL_CLOCKEN;
2609 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2);
2610
2611 /* Program UTMIP PLL delay and oscillator frequency counts */
2612 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
2613 value &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
2614 value |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(params->enable_delay_count);
2615 value &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
2616 value |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(params->xtal_freq_count);
2617 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
2618
2619 /* Remove power downs from UTMIP PLL control bits */
2620 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
2621 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
2622 value |= UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
2623 writel(value, pll->clk_base + UTMIP_PLL_CFG1);
2624
2625 udelay(1);
2626
2627 /* Enable samplers for SNPS, XUSB_HOST, XUSB_DEV */
2628 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2);
2629 value |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP;
2630 value |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP;
2631 value |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP;
2632 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
2633 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
2634 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN;
2635 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2);
2636
2637 /* Setup HW control of UTMIPLL */
2638 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
2639 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
2640 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
2641 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
2642
2643 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
2644 value |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
2645 value &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
2646 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
2647
2648 udelay(1);
2649
2650 value = readl_relaxed(pll->clk_base + XUSB_PLL_CFG0);
2651 value &= ~XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY;
2652 writel_relaxed(value, pll->clk_base + XUSB_PLL_CFG0);
2653
2654 udelay(1);
2655
2656 /* Enable HW control of UTMIPLL */
2657 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
2658 value |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
2659 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
2660
2661 out:
2662 if (pll->lock)
2663 spin_unlock_irqrestore(pll->lock, flags);
2664
2665 return ret;
2666 }
2667
2668 static const struct clk_ops tegra_clk_plle_tegra210_ops = {
2669 .is_enabled = clk_plle_tegra210_is_enabled,
2670 .enable = clk_plle_tegra210_enable,
2671 .disable = clk_plle_tegra210_disable,
2672 .recalc_rate = clk_pll_recalc_rate,
2673 };
2674
2675 static const struct clk_ops tegra_clk_pllu_tegra210_ops = {
2676 .is_enabled = clk_pll_is_enabled,
2677 .enable = clk_pllu_tegra210_enable,
2678 .disable = clk_pll_disable,
2679 .recalc_rate = clk_pllre_recalc_rate,
2680 };
2681
2682 struct clk *tegra_clk_register_plle_tegra210(const char *name,
2683 const char *parent_name,
2684 void __iomem *clk_base, unsigned long flags,
2685 struct tegra_clk_pll_params *pll_params,
2686 spinlock_t *lock)
2687 {
2688 struct tegra_clk_pll *pll;
2689 struct clk *clk;
2690 u32 val, val_aux;
2691
2692 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2693 if (IS_ERR(pll))
2694 return ERR_CAST(pll);
2695
2696 /* ensure parent is set to pll_re_vco */
2697
2698 val = pll_readl_base(pll);
2699 val_aux = pll_readl(pll_params->aux_reg, pll);
2700
2701 if (val & PLLE_BASE_ENABLE) {
2702 if ((val_aux & PLLE_AUX_PLLRE_SEL) ||
2703 (val_aux & PLLE_AUX_PLLP_SEL))
2704 WARN(1, "pll_e enabled with unsupported parent %s\n",
2705 (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" :
2706 "pll_re_vco");
2707 } else {
2708 val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
2709 pll_writel(val_aux, pll_params->aux_reg, pll);
2710 }
2711
2712 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2713 &tegra_clk_plle_tegra210_ops);
2714 if (IS_ERR(clk))
2715 kfree(pll);
2716
2717 return clk;
2718 }
2719
2720 struct clk *tegra_clk_register_pllc_tegra210(const char *name,
2721 const char *parent_name, void __iomem *clk_base,
2722 void __iomem *pmc, unsigned long flags,
2723 struct tegra_clk_pll_params *pll_params,
2724 spinlock_t *lock)
2725 {
2726 struct clk *parent, *clk;
2727 const struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
2728 struct tegra_clk_pll *pll;
2729 unsigned long parent_rate;
2730
2731 if (!p_tohw)
2732 return ERR_PTR(-EINVAL);
2733
2734 parent = __clk_lookup(parent_name);
2735 if (!parent) {
2736 WARN(1, "parent clk %s of %s must be registered first\n",
2737 name, parent_name);
2738 return ERR_PTR(-EINVAL);
2739 }
2740
2741 parent_rate = clk_get_rate(parent);
2742
2743 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2744
2745 if (pll_params->adjust_vco)
2746 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2747 parent_rate);
2748
2749 pll_params->flags |= TEGRA_PLL_BYPASS;
2750 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2751 if (IS_ERR(pll))
2752 return ERR_CAST(pll);
2753
2754 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2755 &tegra_clk_pll_ops);
2756 if (IS_ERR(clk))
2757 kfree(pll);
2758
2759 return clk;
2760 }
2761
2762 struct clk *tegra_clk_register_pllxc_tegra210(const char *name,
2763 const char *parent_name, void __iomem *clk_base,
2764 void __iomem *pmc, unsigned long flags,
2765 struct tegra_clk_pll_params *pll_params,
2766 spinlock_t *lock)
2767 {
2768 struct tegra_clk_pll *pll;
2769 struct clk *clk, *parent;
2770 unsigned long parent_rate;
2771
2772 parent = __clk_lookup(parent_name);
2773 if (!parent) {
2774 WARN(1, "parent clk %s of %s must be registered first\n",
2775 name, parent_name);
2776 return ERR_PTR(-EINVAL);
2777 }
2778
2779 if (!pll_params->pdiv_tohw)
2780 return ERR_PTR(-EINVAL);
2781
2782 parent_rate = clk_get_rate(parent);
2783
2784 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2785
2786 if (pll_params->adjust_vco)
2787 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2788 parent_rate);
2789
2790 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2791 if (IS_ERR(pll))
2792 return ERR_CAST(pll);
2793
2794 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2795 &tegra_clk_pll_ops);
2796 if (IS_ERR(clk))
2797 kfree(pll);
2798
2799 return clk;
2800 }
2801
2802 struct clk *tegra_clk_register_pllss_tegra210(const char *name,
2803 const char *parent_name, void __iomem *clk_base,
2804 unsigned long flags,
2805 struct tegra_clk_pll_params *pll_params,
2806 spinlock_t *lock)
2807 {
2808 struct tegra_clk_pll *pll;
2809 struct clk *clk, *parent;
2810 struct tegra_clk_pll_freq_table cfg;
2811 unsigned long parent_rate;
2812 u32 val;
2813 int i;
2814
2815 if (!pll_params->div_nmp)
2816 return ERR_PTR(-EINVAL);
2817
2818 parent = __clk_lookup(parent_name);
2819 if (!parent) {
2820 WARN(1, "parent clk %s of %s must be registered first\n",
2821 name, parent_name);
2822 return ERR_PTR(-EINVAL);
2823 }
2824
2825 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2826 if (IS_ERR(pll))
2827 return ERR_CAST(pll);
2828
2829 val = pll_readl_base(pll);
2830 val &= ~PLLSS_REF_SRC_SEL_MASK;
2831 pll_writel_base(val, pll);
2832
2833 parent_rate = clk_get_rate(parent);
2834
2835 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2836
2837 if (pll_params->adjust_vco)
2838 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2839 parent_rate);
2840
2841 /* initialize PLL to minimum rate */
2842
2843 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
2844 cfg.n = cfg.m * pll_params->vco_min / parent_rate;
2845
2846 for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++)
2847 ;
2848 if (!i) {
2849 kfree(pll);
2850 return ERR_PTR(-EINVAL);
2851 }
2852
2853 cfg.p = pll_params->pdiv_tohw[i-1].hw_val;
2854
2855 _update_pll_mnp(pll, &cfg);
2856
2857 pll_writel_misc(PLLSS_MISC_DEFAULT, pll);
2858
2859 val = pll_readl_base(pll);
2860 if (val & PLL_BASE_ENABLE) {
2861 if (val & BIT(pll_params->iddq_bit_idx)) {
2862 WARN(1, "%s is on but IDDQ set\n", name);
2863 kfree(pll);
2864 return ERR_PTR(-EINVAL);
2865 }
2866 } else
2867 val |= BIT(pll_params->iddq_bit_idx);
2868
2869 val &= ~PLLSS_LOCK_OVERRIDE;
2870 pll_writel_base(val, pll);
2871
2872 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2873 &tegra_clk_pll_ops);
2874
2875 if (IS_ERR(clk))
2876 kfree(pll);
2877
2878 return clk;
2879 }
2880
2881 struct clk *tegra_clk_register_pllmb(const char *name, const char *parent_name,
2882 void __iomem *clk_base, void __iomem *pmc,
2883 unsigned long flags,
2884 struct tegra_clk_pll_params *pll_params,
2885 spinlock_t *lock)
2886 {
2887 struct tegra_clk_pll *pll;
2888 struct clk *clk, *parent;
2889 unsigned long parent_rate;
2890
2891 if (!pll_params->pdiv_tohw)
2892 return ERR_PTR(-EINVAL);
2893
2894 parent = __clk_lookup(parent_name);
2895 if (!parent) {
2896 WARN(1, "parent clk %s of %s must be registered first\n",
2897 parent_name, name);
2898 return ERR_PTR(-EINVAL);
2899 }
2900
2901 parent_rate = clk_get_rate(parent);
2902
2903 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2904
2905 if (pll_params->adjust_vco)
2906 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2907 parent_rate);
2908
2909 pll_params->flags |= TEGRA_PLL_BYPASS;
2910 pll_params->flags |= TEGRA_PLLMB;
2911 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2912 if (IS_ERR(pll))
2913 return ERR_CAST(pll);
2914
2915 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2916 &tegra_clk_pll_ops);
2917 if (IS_ERR(clk))
2918 kfree(pll);
2919
2920 return clk;
2921 }
2922
2923 struct clk *tegra_clk_register_pllu_tegra210(const char *name,
2924 const char *parent_name, void __iomem *clk_base,
2925 unsigned long flags, struct tegra_clk_pll_params *pll_params,
2926 spinlock_t *lock)
2927 {
2928 struct tegra_clk_pll *pll;
2929 struct clk *clk;
2930
2931 pll_params->flags |= TEGRA_PLLU;
2932
2933 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2934 if (IS_ERR(pll))
2935 return ERR_CAST(pll);
2936
2937 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2938 &tegra_clk_pllu_tegra210_ops);
2939 if (IS_ERR(clk))
2940 kfree(pll);
2941
2942 return clk;
2943 }
2944 #endif
Linux with added FPC-III support