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gpio: Fix irqchip initialization order
[linux/fpc-iii.git] / drivers / gpio / gpio-pca953x.c
blob378b206d2dc9495dc32c3ffc6fdf06e35262a31e
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * PCA953x 4/8/16/24/40 bit I/O ports
4 *
5 * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com>
6 * Copyright (C) 2007 Marvell International Ltd.
7 *
8 * Derived from drivers/i2c/chips/pca9539.c
9 */
10
11 #include <linux/acpi.h>
12 #include <linux/gpio/driver.h>
13 #include <linux/gpio/consumer.h>
14 #include <linux/i2c.h>
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
17 #include <linux/module.h>
18 #include <linux/of_platform.h>
19 #include <linux/platform_data/pca953x.h>
20 #include <linux/regmap.h>
21 #include <linux/regulator/consumer.h>
22 #include <linux/slab.h>
23
24 #include <asm/unaligned.h>
25
26 #define PCA953X_INPUT 0x00
27 #define PCA953X_OUTPUT 0x01
28 #define PCA953X_INVERT 0x02
29 #define PCA953X_DIRECTION 0x03
30
31 #define REG_ADDR_MASK 0x3f
32 #define REG_ADDR_EXT 0x40
33 #define REG_ADDR_AI 0x80
34
35 #define PCA957X_IN 0x00
36 #define PCA957X_INVRT 0x01
37 #define PCA957X_BKEN 0x02
38 #define PCA957X_PUPD 0x03
39 #define PCA957X_CFG 0x04
40 #define PCA957X_OUT 0x05
41 #define PCA957X_MSK 0x06
42 #define PCA957X_INTS 0x07
43
44 #define PCAL953X_OUT_STRENGTH 0x20
45 #define PCAL953X_IN_LATCH 0x22
46 #define PCAL953X_PULL_EN 0x23
47 #define PCAL953X_PULL_SEL 0x24
48 #define PCAL953X_INT_MASK 0x25
49 #define PCAL953X_INT_STAT 0x26
50 #define PCAL953X_OUT_CONF 0x27
51
52 #define PCAL6524_INT_EDGE 0x28
53 #define PCAL6524_INT_CLR 0x2a
54 #define PCAL6524_IN_STATUS 0x2b
55 #define PCAL6524_OUT_INDCONF 0x2c
56 #define PCAL6524_DEBOUNCE 0x2d
57
58 #define PCA_GPIO_MASK 0x00FF
59
60 #define PCAL_GPIO_MASK 0x1f
61 #define PCAL_PINCTRL_MASK 0x60
62
63 #define PCA_INT 0x0100
64 #define PCA_PCAL 0x0200
65 #define PCA_LATCH_INT (PCA_PCAL | PCA_INT)
66 #define PCA953X_TYPE 0x1000
67 #define PCA957X_TYPE 0x2000
68 #define PCA_TYPE_MASK 0xF000
69
70 #define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK)
71
72 static const struct i2c_device_id pca953x_id[] = {
73 { "pca6416", 16 | PCA953X_TYPE | PCA_INT, },
74 { "pca9505", 40 | PCA953X_TYPE | PCA_INT, },
75 { "pca9534", 8 | PCA953X_TYPE | PCA_INT, },
76 { "pca9535", 16 | PCA953X_TYPE | PCA_INT, },
77 { "pca9536", 4 | PCA953X_TYPE, },
78 { "pca9537", 4 | PCA953X_TYPE | PCA_INT, },
79 { "pca9538", 8 | PCA953X_TYPE | PCA_INT, },
80 { "pca9539", 16 | PCA953X_TYPE | PCA_INT, },
81 { "pca9554", 8 | PCA953X_TYPE | PCA_INT, },
82 { "pca9555", 16 | PCA953X_TYPE | PCA_INT, },
83 { "pca9556", 8 | PCA953X_TYPE, },
84 { "pca9557", 8 | PCA953X_TYPE, },
85 { "pca9574", 8 | PCA957X_TYPE | PCA_INT, },
86 { "pca9575", 16 | PCA957X_TYPE | PCA_INT, },
87 { "pca9698", 40 | PCA953X_TYPE, },
88
89 { "pcal6416", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
90 { "pcal6524", 24 | PCA953X_TYPE | PCA_LATCH_INT, },
91 { "pcal9555a", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
92
93 { "max7310", 8 | PCA953X_TYPE, },
94 { "max7312", 16 | PCA953X_TYPE | PCA_INT, },
95 { "max7313", 16 | PCA953X_TYPE | PCA_INT, },
96 { "max7315", 8 | PCA953X_TYPE | PCA_INT, },
97 { "max7318", 16 | PCA953X_TYPE | PCA_INT, },
98 { "pca6107", 8 | PCA953X_TYPE | PCA_INT, },
99 { "tca6408", 8 | PCA953X_TYPE | PCA_INT, },
100 { "tca6416", 16 | PCA953X_TYPE | PCA_INT, },
101 { "tca6424", 24 | PCA953X_TYPE | PCA_INT, },
102 { "tca9539", 16 | PCA953X_TYPE | PCA_INT, },
103 { "tca9554", 8 | PCA953X_TYPE | PCA_INT, },
104 { "xra1202", 8 | PCA953X_TYPE },
105 { }
106 };
107 MODULE_DEVICE_TABLE(i2c, pca953x_id);
108
109 static const struct acpi_device_id pca953x_acpi_ids[] = {
110 { "INT3491", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
111 { }
112 };
113 MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids);
114
115 #define MAX_BANK 5
116 #define BANK_SZ 8
117
118 #define NBANK(chip) DIV_ROUND_UP(chip->gpio_chip.ngpio, BANK_SZ)
119
120 struct pca953x_reg_config {
121 int direction;
122 int output;
123 int input;
124 int invert;
125 };
126
127 static const struct pca953x_reg_config pca953x_regs = {
128 .direction = PCA953X_DIRECTION,
129 .output = PCA953X_OUTPUT,
130 .input = PCA953X_INPUT,
131 .invert = PCA953X_INVERT,
132 };
133
134 static const struct pca953x_reg_config pca957x_regs = {
135 .direction = PCA957X_CFG,
136 .output = PCA957X_OUT,
137 .input = PCA957X_IN,
138 .invert = PCA957X_INVRT,
139 };
140
141 struct pca953x_chip {
142 unsigned gpio_start;
143 struct mutex i2c_lock;
144 struct regmap *regmap;
145
146 #ifdef CONFIG_GPIO_PCA953X_IRQ
147 struct mutex irq_lock;
148 u8 irq_mask[MAX_BANK];
149 u8 irq_stat[MAX_BANK];
150 u8 irq_trig_raise[MAX_BANK];
151 u8 irq_trig_fall[MAX_BANK];
152 struct irq_chip irq_chip;
153 #endif
154 atomic_t wakeup_path;
155
156 struct i2c_client *client;
157 struct gpio_chip gpio_chip;
158 const char *const *names;
159 unsigned long driver_data;
160 struct regulator *regulator;
161
162 const struct pca953x_reg_config *regs;
163 };
164
165 static int pca953x_bank_shift(struct pca953x_chip *chip)
166 {
167 return fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
168 }
169
170 #define PCA953x_BANK_INPUT BIT(0)
171 #define PCA953x_BANK_OUTPUT BIT(1)
172 #define PCA953x_BANK_POLARITY BIT(2)
173 #define PCA953x_BANK_CONFIG BIT(3)
174
175 #define PCA957x_BANK_INPUT BIT(0)
176 #define PCA957x_BANK_POLARITY BIT(1)
177 #define PCA957x_BANK_BUSHOLD BIT(2)
178 #define PCA957x_BANK_CONFIG BIT(4)
179 #define PCA957x_BANK_OUTPUT BIT(5)
180
181 #define PCAL9xxx_BANK_IN_LATCH BIT(8 + 2)
182 #define PCAL9xxx_BANK_PULL_EN BIT(8 + 3)
183 #define PCAL9xxx_BANK_PULL_SEL BIT(8 + 4)
184 #define PCAL9xxx_BANK_IRQ_MASK BIT(8 + 5)
185 #define PCAL9xxx_BANK_IRQ_STAT BIT(8 + 6)
186
187 /*
188 * We care about the following registers:
189 * - Standard set, below 0x40, each port can be replicated up to 8 times
190 * - PCA953x standard
191 * Input port 0x00 + 0 * bank_size R
192 * Output port 0x00 + 1 * bank_size RW
193 * Polarity Inversion port 0x00 + 2 * bank_size RW
194 * Configuration port 0x00 + 3 * bank_size RW
195 * - PCA957x with mixed up registers
196 * Input port 0x00 + 0 * bank_size R
197 * Polarity Inversion port 0x00 + 1 * bank_size RW
198 * Bus hold port 0x00 + 2 * bank_size RW
199 * Configuration port 0x00 + 4 * bank_size RW
200 * Output port 0x00 + 5 * bank_size RW
201 *
202 * - Extended set, above 0x40, often chip specific.
203 * - PCAL6524/PCAL9555A with custom PCAL IRQ handling:
204 * Input latch register 0x40 + 2 * bank_size RW
205 * Pull-up/pull-down enable reg 0x40 + 3 * bank_size RW
206 * Pull-up/pull-down select reg 0x40 + 4 * bank_size RW
207 * Interrupt mask register 0x40 + 5 * bank_size RW
208 * Interrupt status register 0x40 + 6 * bank_size R
209 *
210 * - Registers with bit 0x80 set, the AI bit
211 * The bit is cleared and the registers fall into one of the
212 * categories above.
213 */
214
215 static bool pca953x_check_register(struct pca953x_chip *chip, unsigned int reg,
216 u32 checkbank)
217 {
218 int bank_shift = pca953x_bank_shift(chip);
219 int bank = (reg & REG_ADDR_MASK) >> bank_shift;
220 int offset = reg & (BIT(bank_shift) - 1);
221
222 /* Special PCAL extended register check. */
223 if (reg & REG_ADDR_EXT) {
224 if (!(chip->driver_data & PCA_PCAL))
225 return false;
226 bank += 8;
227 }
228
229 /* Register is not in the matching bank. */
230 if (!(BIT(bank) & checkbank))
231 return false;
232
233 /* Register is not within allowed range of bank. */
234 if (offset >= NBANK(chip))
235 return false;
236
237 return true;
238 }
239
240 static bool pca953x_readable_register(struct device *dev, unsigned int reg)
241 {
242 struct pca953x_chip *chip = dev_get_drvdata(dev);
243 u32 bank;
244
245 if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) {
246 bank = PCA953x_BANK_INPUT | PCA953x_BANK_OUTPUT |
247 PCA953x_BANK_POLARITY | PCA953x_BANK_CONFIG;
248 } else {
249 bank = PCA957x_BANK_INPUT | PCA957x_BANK_OUTPUT |
250 PCA957x_BANK_POLARITY | PCA957x_BANK_CONFIG |
251 PCA957x_BANK_BUSHOLD;
252 }
253
254 if (chip->driver_data & PCA_PCAL) {
255 bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN |
256 PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK |
257 PCAL9xxx_BANK_IRQ_STAT;
258 }
259
260 return pca953x_check_register(chip, reg, bank);
261 }
262
263 static bool pca953x_writeable_register(struct device *dev, unsigned int reg)
264 {
265 struct pca953x_chip *chip = dev_get_drvdata(dev);
266 u32 bank;
267
268 if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) {
269 bank = PCA953x_BANK_OUTPUT | PCA953x_BANK_POLARITY |
270 PCA953x_BANK_CONFIG;
271 } else {
272 bank = PCA957x_BANK_OUTPUT | PCA957x_BANK_POLARITY |
273 PCA957x_BANK_CONFIG | PCA957x_BANK_BUSHOLD;
274 }
275
276 if (chip->driver_data & PCA_PCAL)
277 bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN |
278 PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK;
279
280 return pca953x_check_register(chip, reg, bank);
281 }
282
283 static bool pca953x_volatile_register(struct device *dev, unsigned int reg)
284 {
285 struct pca953x_chip *chip = dev_get_drvdata(dev);
286 u32 bank;
287
288 if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE)
289 bank = PCA953x_BANK_INPUT;
290 else
291 bank = PCA957x_BANK_INPUT;
292
293 if (chip->driver_data & PCA_PCAL)
294 bank |= PCAL9xxx_BANK_IRQ_STAT;
295
296 return pca953x_check_register(chip, reg, bank);
297 }
298
299 static const struct regmap_config pca953x_i2c_regmap = {
300 .reg_bits = 8,
301 .val_bits = 8,
302
303 .readable_reg = pca953x_readable_register,
304 .writeable_reg = pca953x_writeable_register,
305 .volatile_reg = pca953x_volatile_register,
306
307 .cache_type = REGCACHE_RBTREE,
308 /* REVISIT: should be 0x7f but some 24 bit chips use REG_ADDR_AI */
309 .max_register = 0xff,
310 };
311
312 static u8 pca953x_recalc_addr(struct pca953x_chip *chip, int reg, int off,
313 bool write, bool addrinc)
314 {
315 int bank_shift = pca953x_bank_shift(chip);
316 int addr = (reg & PCAL_GPIO_MASK) << bank_shift;
317 int pinctrl = (reg & PCAL_PINCTRL_MASK) << 1;
318 u8 regaddr = pinctrl | addr | (off / BANK_SZ);
319
320 /* Single byte read doesn't need AI bit set. */
321 if (!addrinc)
322 return regaddr;
323
324 /* Chips with 24 and more GPIOs always support Auto Increment */
325 if (write && NBANK(chip) > 2)
326 regaddr |= REG_ADDR_AI;
327
328 /* PCA9575 needs address-increment on multi-byte writes */
329 if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE)
330 regaddr |= REG_ADDR_AI;
331
332 return regaddr;
333 }
334
335 static int pca953x_write_regs(struct pca953x_chip *chip, int reg, u8 *val)
336 {
337 u8 regaddr = pca953x_recalc_addr(chip, reg, 0, true, true);
338 int ret;
339
340 ret = regmap_bulk_write(chip->regmap, regaddr, val, NBANK(chip));
341 if (ret < 0) {
342 dev_err(&chip->client->dev, "failed writing register\n");
343 return ret;
344 }
345
346 return 0;
347 }
348
349 static int pca953x_read_regs(struct pca953x_chip *chip, int reg, u8 *val)
350 {
351 u8 regaddr = pca953x_recalc_addr(chip, reg, 0, false, true);
352 int ret;
353
354 ret = regmap_bulk_read(chip->regmap, regaddr, val, NBANK(chip));
355 if (ret < 0) {
356 dev_err(&chip->client->dev, "failed reading register\n");
357 return ret;
358 }
359
360 return 0;
361 }
362
363 static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off)
364 {
365 struct pca953x_chip *chip = gpiochip_get_data(gc);
366 u8 dirreg = pca953x_recalc_addr(chip, chip->regs->direction, off,
367 true, false);
368 u8 bit = BIT(off % BANK_SZ);
369 int ret;
370
371 mutex_lock(&chip->i2c_lock);
372 ret = regmap_write_bits(chip->regmap, dirreg, bit, bit);
373 mutex_unlock(&chip->i2c_lock);
374 return ret;
375 }
376
377 static int pca953x_gpio_direction_output(struct gpio_chip *gc,
378 unsigned off, int val)
379 {
380 struct pca953x_chip *chip = gpiochip_get_data(gc);
381 u8 dirreg = pca953x_recalc_addr(chip, chip->regs->direction, off,
382 true, false);
383 u8 outreg = pca953x_recalc_addr(chip, chip->regs->output, off,
384 true, false);
385 u8 bit = BIT(off % BANK_SZ);
386 int ret;
387
388 mutex_lock(&chip->i2c_lock);
389 /* set output level */
390 ret = regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0);
391 if (ret)
392 goto exit;
393
394 /* then direction */
395 ret = regmap_write_bits(chip->regmap, dirreg, bit, 0);
396 exit:
397 mutex_unlock(&chip->i2c_lock);
398 return ret;
399 }
400
401 static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off)
402 {
403 struct pca953x_chip *chip = gpiochip_get_data(gc);
404 u8 inreg = pca953x_recalc_addr(chip, chip->regs->input, off,
405 true, false);
406 u8 bit = BIT(off % BANK_SZ);
407 u32 reg_val;
408 int ret;
409
410 mutex_lock(&chip->i2c_lock);
411 ret = regmap_read(chip->regmap, inreg, &reg_val);
412 mutex_unlock(&chip->i2c_lock);
413 if (ret < 0) {
414 /* NOTE: diagnostic already emitted; that's all we should
415 * do unless gpio_*_value_cansleep() calls become different
416 * from their nonsleeping siblings (and report faults).
417 */
418 return 0;
419 }
420
421 return !!(reg_val & bit);
422 }
423
424 static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val)
425 {
426 struct pca953x_chip *chip = gpiochip_get_data(gc);
427 u8 outreg = pca953x_recalc_addr(chip, chip->regs->output, off,
428 true, false);
429 u8 bit = BIT(off % BANK_SZ);
430
431 mutex_lock(&chip->i2c_lock);
432 regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0);
433 mutex_unlock(&chip->i2c_lock);
434 }
435
436 static int pca953x_gpio_get_direction(struct gpio_chip *gc, unsigned off)
437 {
438 struct pca953x_chip *chip = gpiochip_get_data(gc);
439 u8 dirreg = pca953x_recalc_addr(chip, chip->regs->direction, off,
440 true, false);
441 u8 bit = BIT(off % BANK_SZ);
442 u32 reg_val;
443 int ret;
444
445 mutex_lock(&chip->i2c_lock);
446 ret = regmap_read(chip->regmap, dirreg, &reg_val);
447 mutex_unlock(&chip->i2c_lock);
448 if (ret < 0)
449 return ret;
450
451 return !!(reg_val & bit);
452 }
453
454 static void pca953x_gpio_set_multiple(struct gpio_chip *gc,
455 unsigned long *mask, unsigned long *bits)
456 {
457 struct pca953x_chip *chip = gpiochip_get_data(gc);
458 unsigned int bank_mask, bank_val;
459 int bank;
460 u8 reg_val[MAX_BANK];
461 int ret;
462
463 mutex_lock(&chip->i2c_lock);
464 ret = pca953x_read_regs(chip, chip->regs->output, reg_val);
465 if (ret)
466 goto exit;
467
468 for (bank = 0; bank < NBANK(chip); bank++) {
469 bank_mask = mask[bank / sizeof(*mask)] >>
470 ((bank % sizeof(*mask)) * 8);
471 if (bank_mask) {
472 bank_val = bits[bank / sizeof(*bits)] >>
473 ((bank % sizeof(*bits)) * 8);
474 bank_val &= bank_mask;
475 reg_val[bank] = (reg_val[bank] & ~bank_mask) | bank_val;
476 }
477 }
478
479 pca953x_write_regs(chip, chip->regs->output, reg_val);
480 exit:
481 mutex_unlock(&chip->i2c_lock);
482 }
483
484 static int pca953x_gpio_set_pull_up_down(struct pca953x_chip *chip,
485 unsigned int offset,
486 unsigned long config)
487 {
488 u8 pull_en_reg = pca953x_recalc_addr(chip, PCAL953X_PULL_EN, offset,
489 true, false);
490 u8 pull_sel_reg = pca953x_recalc_addr(chip, PCAL953X_PULL_SEL, offset,
491 true, false);
492 u8 bit = BIT(offset % BANK_SZ);
493 int ret;
494
495 /*
496 * pull-up/pull-down configuration requires PCAL extended
497 * registers
498 */
499 if (!(chip->driver_data & PCA_PCAL))
500 return -ENOTSUPP;
501
502 mutex_lock(&chip->i2c_lock);
503
504 /* Disable pull-up/pull-down */
505 ret = regmap_write_bits(chip->regmap, pull_en_reg, bit, 0);
506 if (ret)
507 goto exit;
508
509 /* Configure pull-up/pull-down */
510 if (config == PIN_CONFIG_BIAS_PULL_UP)
511 ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, bit);
512 else if (config == PIN_CONFIG_BIAS_PULL_DOWN)
513 ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, 0);
514 if (ret)
515 goto exit;
516
517 /* Enable pull-up/pull-down */
518 ret = regmap_write_bits(chip->regmap, pull_en_reg, bit, bit);
519
520 exit:
521 mutex_unlock(&chip->i2c_lock);
522 return ret;
523 }
524
525 static int pca953x_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
526 unsigned long config)
527 {
528 struct pca953x_chip *chip = gpiochip_get_data(gc);
529
530 switch (config) {
531 case PIN_CONFIG_BIAS_PULL_UP:
532 case PIN_CONFIG_BIAS_PULL_DOWN:
533 return pca953x_gpio_set_pull_up_down(chip, offset, config);
534 default:
535 return -ENOTSUPP;
536 }
537 }
538
539 static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios)
540 {
541 struct gpio_chip *gc;
542
543 gc = &chip->gpio_chip;
544
545 gc->direction_input = pca953x_gpio_direction_input;
546 gc->direction_output = pca953x_gpio_direction_output;
547 gc->get = pca953x_gpio_get_value;
548 gc->set = pca953x_gpio_set_value;
549 gc->get_direction = pca953x_gpio_get_direction;
550 gc->set_multiple = pca953x_gpio_set_multiple;
551 gc->set_config = pca953x_gpio_set_config;
552 gc->can_sleep = true;
553
554 gc->base = chip->gpio_start;
555 gc->ngpio = gpios;
556 gc->label = dev_name(&chip->client->dev);
557 gc->parent = &chip->client->dev;
558 gc->owner = THIS_MODULE;
559 gc->names = chip->names;
560 }
561
562 #ifdef CONFIG_GPIO_PCA953X_IRQ
563 static void pca953x_irq_mask(struct irq_data *d)
564 {
565 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
566 struct pca953x_chip *chip = gpiochip_get_data(gc);
567
568 chip->irq_mask[d->hwirq / BANK_SZ] &= ~(1 << (d->hwirq % BANK_SZ));
569 }
570
571 static void pca953x_irq_unmask(struct irq_data *d)
572 {
573 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
574 struct pca953x_chip *chip = gpiochip_get_data(gc);
575
576 chip->irq_mask[d->hwirq / BANK_SZ] |= 1 << (d->hwirq % BANK_SZ);
577 }
578
579 static int pca953x_irq_set_wake(struct irq_data *d, unsigned int on)
580 {
581 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
582 struct pca953x_chip *chip = gpiochip_get_data(gc);
583
584 if (on)
585 atomic_inc(&chip->wakeup_path);
586 else
587 atomic_dec(&chip->wakeup_path);
588
589 return irq_set_irq_wake(chip->client->irq, on);
590 }
591
592 static void pca953x_irq_bus_lock(struct irq_data *d)
593 {
594 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
595 struct pca953x_chip *chip = gpiochip_get_data(gc);
596
597 mutex_lock(&chip->irq_lock);
598 }
599
600 static void pca953x_irq_bus_sync_unlock(struct irq_data *d)
601 {
602 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
603 struct pca953x_chip *chip = gpiochip_get_data(gc);
604 u8 new_irqs;
605 int level, i;
606 u8 invert_irq_mask[MAX_BANK];
607 int reg_direction[MAX_BANK];
608
609 regmap_bulk_read(chip->regmap, chip->regs->direction, reg_direction,
610 NBANK(chip));
611
612 if (chip->driver_data & PCA_PCAL) {
613 /* Enable latch on interrupt-enabled inputs */
614 pca953x_write_regs(chip, PCAL953X_IN_LATCH, chip->irq_mask);
615
616 for (i = 0; i < NBANK(chip); i++)
617 invert_irq_mask[i] = ~chip->irq_mask[i];
618
619 /* Unmask enabled interrupts */
620 pca953x_write_regs(chip, PCAL953X_INT_MASK, invert_irq_mask);
621 }
622
623 /* Look for any newly setup interrupt */
624 for (i = 0; i < NBANK(chip); i++) {
625 new_irqs = chip->irq_trig_fall[i] | chip->irq_trig_raise[i];
626 new_irqs &= reg_direction[i];
627
628 while (new_irqs) {
629 level = __ffs(new_irqs);
630 pca953x_gpio_direction_input(&chip->gpio_chip,
631 level + (BANK_SZ * i));
632 new_irqs &= ~(1 << level);
633 }
634 }
635
636 mutex_unlock(&chip->irq_lock);
637 }
638
639 static int pca953x_irq_set_type(struct irq_data *d, unsigned int type)
640 {
641 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
642 struct pca953x_chip *chip = gpiochip_get_data(gc);
643 int bank_nb = d->hwirq / BANK_SZ;
644 u8 mask = 1 << (d->hwirq % BANK_SZ);
645
646 if (!(type & IRQ_TYPE_EDGE_BOTH)) {
647 dev_err(&chip->client->dev, "irq %d: unsupported type %d\n",
648 d->irq, type);
649 return -EINVAL;
650 }
651
652 if (type & IRQ_TYPE_EDGE_FALLING)
653 chip->irq_trig_fall[bank_nb] |= mask;
654 else
655 chip->irq_trig_fall[bank_nb] &= ~mask;
656
657 if (type & IRQ_TYPE_EDGE_RISING)
658 chip->irq_trig_raise[bank_nb] |= mask;
659 else
660 chip->irq_trig_raise[bank_nb] &= ~mask;
661
662 return 0;
663 }
664
665 static void pca953x_irq_shutdown(struct irq_data *d)
666 {
667 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
668 struct pca953x_chip *chip = gpiochip_get_data(gc);
669 u8 mask = 1 << (d->hwirq % BANK_SZ);
670
671 chip->irq_trig_raise[d->hwirq / BANK_SZ] &= ~mask;
672 chip->irq_trig_fall[d->hwirq / BANK_SZ] &= ~mask;
673 }
674
675 static bool pca953x_irq_pending(struct pca953x_chip *chip, u8 *pending)
676 {
677 u8 cur_stat[MAX_BANK];
678 u8 old_stat[MAX_BANK];
679 bool pending_seen = false;
680 bool trigger_seen = false;
681 u8 trigger[MAX_BANK];
682 int reg_direction[MAX_BANK];
683 int ret, i;
684
685 if (chip->driver_data & PCA_PCAL) {
686 /* Read the current interrupt status from the device */
687 ret = pca953x_read_regs(chip, PCAL953X_INT_STAT, trigger);
688 if (ret)
689 return false;
690
691 /* Check latched inputs and clear interrupt status */
692 ret = pca953x_read_regs(chip, PCA953X_INPUT, cur_stat);
693 if (ret)
694 return false;
695
696 for (i = 0; i < NBANK(chip); i++) {
697 /* Apply filter for rising/falling edge selection */
698 pending[i] = (~cur_stat[i] & chip->irq_trig_fall[i]) |
699 (cur_stat[i] & chip->irq_trig_raise[i]);
700 pending[i] &= trigger[i];
701 if (pending[i])
702 pending_seen = true;
703 }
704
705 return pending_seen;
706 }
707
708 ret = pca953x_read_regs(chip, chip->regs->input, cur_stat);
709 if (ret)
710 return false;
711
712 /* Remove output pins from the equation */
713 regmap_bulk_read(chip->regmap, chip->regs->direction, reg_direction,
714 NBANK(chip));
715 for (i = 0; i < NBANK(chip); i++)
716 cur_stat[i] &= reg_direction[i];
717
718 memcpy(old_stat, chip->irq_stat, NBANK(chip));
719
720 for (i = 0; i < NBANK(chip); i++) {
721 trigger[i] = (cur_stat[i] ^ old_stat[i]) & chip->irq_mask[i];
722 if (trigger[i])
723 trigger_seen = true;
724 }
725
726 if (!trigger_seen)
727 return false;
728
729 memcpy(chip->irq_stat, cur_stat, NBANK(chip));
730
731 for (i = 0; i < NBANK(chip); i++) {
732 pending[i] = (old_stat[i] & chip->irq_trig_fall[i]) |
733 (cur_stat[i] & chip->irq_trig_raise[i]);
734 pending[i] &= trigger[i];
735 if (pending[i])
736 pending_seen = true;
737 }
738
739 return pending_seen;
740 }
741
742 static irqreturn_t pca953x_irq_handler(int irq, void *devid)
743 {
744 struct pca953x_chip *chip = devid;
745 u8 pending[MAX_BANK];
746 u8 level;
747 unsigned nhandled = 0;
748 int i;
749
750 if (!pca953x_irq_pending(chip, pending))
751 return IRQ_NONE;
752
753 for (i = 0; i < NBANK(chip); i++) {
754 while (pending[i]) {
755 level = __ffs(pending[i]);
756 handle_nested_irq(irq_find_mapping(chip->gpio_chip.irq.domain,
757 level + (BANK_SZ * i)));
758 pending[i] &= ~(1 << level);
759 nhandled++;
760 }
761 }
762
763 return (nhandled > 0) ? IRQ_HANDLED : IRQ_NONE;
764 }
765
766 static int pca953x_irq_setup(struct pca953x_chip *chip,
767 int irq_base)
768 {
769 struct i2c_client *client = chip->client;
770 struct irq_chip *irq_chip = &chip->irq_chip;
771 int reg_direction[MAX_BANK];
772 int ret, i;
773
774 if (!client->irq)
775 return 0;
776
777 if (irq_base == -1)
778 return 0;
779
780 if (!(chip->driver_data & PCA_INT))
781 return 0;
782
783 ret = pca953x_read_regs(chip, chip->regs->input, chip->irq_stat);
784 if (ret)
785 return ret;
786
787 /*
788 * There is no way to know which GPIO line generated the
789 * interrupt. We have to rely on the previous read for
790 * this purpose.
791 */
792 regmap_bulk_read(chip->regmap, chip->regs->direction, reg_direction,
793 NBANK(chip));
794 for (i = 0; i < NBANK(chip); i++)
795 chip->irq_stat[i] &= reg_direction[i];
796 mutex_init(&chip->irq_lock);
797
798 ret = devm_request_threaded_irq(&client->dev, client->irq,
799 NULL, pca953x_irq_handler,
800 IRQF_TRIGGER_LOW | IRQF_ONESHOT |
801 IRQF_SHARED,
802 dev_name(&client->dev), chip);
803 if (ret) {
804 dev_err(&client->dev, "failed to request irq %d\n",
805 client->irq);
806 return ret;
807 }
808
809 irq_chip->name = dev_name(&chip->client->dev);
810 irq_chip->irq_mask = pca953x_irq_mask;
811 irq_chip->irq_unmask = pca953x_irq_unmask;
812 irq_chip->irq_set_wake = pca953x_irq_set_wake;
813 irq_chip->irq_bus_lock = pca953x_irq_bus_lock;
814 irq_chip->irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock;
815 irq_chip->irq_set_type = pca953x_irq_set_type;
816 irq_chip->irq_shutdown = pca953x_irq_shutdown;
817
818 ret = gpiochip_irqchip_add_nested(&chip->gpio_chip, irq_chip,
819 irq_base, handle_simple_irq,
820 IRQ_TYPE_NONE);
821 if (ret) {
822 dev_err(&client->dev,
823 "could not connect irqchip to gpiochip\n");
824 return ret;
825 }
826
827 gpiochip_set_nested_irqchip(&chip->gpio_chip, irq_chip, client->irq);
828
829 return 0;
830 }
831
832 #else /* CONFIG_GPIO_PCA953X_IRQ */
833 static int pca953x_irq_setup(struct pca953x_chip *chip,
834 int irq_base)
835 {
836 struct i2c_client *client = chip->client;
837
838 if (client->irq && irq_base != -1 && (chip->driver_data & PCA_INT))
839 dev_warn(&client->dev, "interrupt support not compiled in\n");
840
841 return 0;
842 }
843 #endif
844
845 static int device_pca95xx_init(struct pca953x_chip *chip, u32 invert)
846 {
847 int ret;
848 u8 val[MAX_BANK];
849
850 ret = regcache_sync_region(chip->regmap, chip->regs->output,
851 chip->regs->output + NBANK(chip));
852 if (ret != 0)
853 goto out;
854
855 ret = regcache_sync_region(chip->regmap, chip->regs->direction,
856 chip->regs->direction + NBANK(chip));
857 if (ret != 0)
858 goto out;
859
860 /* set platform specific polarity inversion */
861 if (invert)
862 memset(val, 0xFF, NBANK(chip));
863 else
864 memset(val, 0, NBANK(chip));
865
866 ret = pca953x_write_regs(chip, chip->regs->invert, val);
867 out:
868 return ret;
869 }
870
871 static int device_pca957x_init(struct pca953x_chip *chip, u32 invert)
872 {
873 int ret;
874 u8 val[MAX_BANK];
875
876 ret = device_pca95xx_init(chip, invert);
877 if (ret)
878 goto out;
879
880 /* To enable register 6, 7 to control pull up and pull down */
881 memset(val, 0x02, NBANK(chip));
882 ret = pca953x_write_regs(chip, PCA957X_BKEN, val);
883 if (ret)
884 goto out;
885
886 return 0;
887 out:
888 return ret;
889 }
890
891 static const struct of_device_id pca953x_dt_ids[];
892
893 static int pca953x_probe(struct i2c_client *client,
894 const struct i2c_device_id *i2c_id)
895 {
896 struct pca953x_platform_data *pdata;
897 struct pca953x_chip *chip;
898 int irq_base = 0;
899 int ret;
900 u32 invert = 0;
901 struct regulator *reg;
902
903 chip = devm_kzalloc(&client->dev,
904 sizeof(struct pca953x_chip), GFP_KERNEL);
905 if (chip == NULL)
906 return -ENOMEM;
907
908 pdata = dev_get_platdata(&client->dev);
909 if (pdata) {
910 irq_base = pdata->irq_base;
911 chip->gpio_start = pdata->gpio_base;
912 invert = pdata->invert;
913 chip->names = pdata->names;
914 } else {
915 struct gpio_desc *reset_gpio;
916
917 chip->gpio_start = -1;
918 irq_base = 0;
919
920 /*
921 * See if we need to de-assert a reset pin.
922 *
923 * There is no known ACPI-enabled platforms that are
924 * using "reset" GPIO. Otherwise any of those platform
925 * must use _DSD method with corresponding property.
926 */
927 reset_gpio = devm_gpiod_get_optional(&client->dev, "reset",
928 GPIOD_OUT_LOW);
929 if (IS_ERR(reset_gpio))
930 return PTR_ERR(reset_gpio);
931 }
932
933 chip->client = client;
934
935 reg = devm_regulator_get(&client->dev, "vcc");
936 if (IS_ERR(reg)) {
937 ret = PTR_ERR(reg);
938 if (ret != -EPROBE_DEFER)
939 dev_err(&client->dev, "reg get err: %d\n", ret);
940 return ret;
941 }
942 ret = regulator_enable(reg);
943 if (ret) {
944 dev_err(&client->dev, "reg en err: %d\n", ret);
945 return ret;
946 }
947 chip->regulator = reg;
948
949 if (i2c_id) {
950 chip->driver_data = i2c_id->driver_data;
951 } else {
952 const struct acpi_device_id *acpi_id;
953 struct device *dev = &client->dev;
954
955 chip->driver_data = (uintptr_t)of_device_get_match_data(dev);
956 if (!chip->driver_data) {
957 acpi_id = acpi_match_device(pca953x_acpi_ids, dev);
958 if (!acpi_id) {
959 ret = -ENODEV;
960 goto err_exit;
961 }
962
963 chip->driver_data = acpi_id->driver_data;
964 }
965 }
966
967 i2c_set_clientdata(client, chip);
968
969 chip->regmap = devm_regmap_init_i2c(client, &pca953x_i2c_regmap);
970 if (IS_ERR(chip->regmap)) {
971 ret = PTR_ERR(chip->regmap);
972 goto err_exit;
973 }
974
975 regcache_mark_dirty(chip->regmap);
976
977 mutex_init(&chip->i2c_lock);
978 /*
979 * In case we have an i2c-mux controlled by a GPIO provided by an
980 * expander using the same driver higher on the device tree, read the
981 * i2c adapter nesting depth and use the retrieved value as lockdep
982 * subclass for chip->i2c_lock.
983 *
984 * REVISIT: This solution is not complete. It protects us from lockdep
985 * false positives when the expander controlling the i2c-mux is on
986 * a different level on the device tree, but not when it's on the same
987 * level on a different branch (in which case the subclass number
988 * would be the same).
989 *
990 * TODO: Once a correct solution is developed, a similar fix should be
991 * applied to all other i2c-controlled GPIO expanders (and potentially
992 * regmap-i2c).
993 */
994 lockdep_set_subclass(&chip->i2c_lock,
995 i2c_adapter_depth(client->adapter));
996
997 /* initialize cached registers from their original values.
998 * we can't share this chip with another i2c master.
999 */
1000 pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK);
1001
1002 if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) {
1003 chip->regs = &pca953x_regs;
1004 ret = device_pca95xx_init(chip, invert);
1005 } else {
1006 chip->regs = &pca957x_regs;
1007 ret = device_pca957x_init(chip, invert);
1008 }
1009 if (ret)
1010 goto err_exit;
1011
1012 ret = devm_gpiochip_add_data(&client->dev, &chip->gpio_chip, chip);
1013 if (ret)
1014 goto err_exit;
1015
1016 ret = pca953x_irq_setup(chip, irq_base);
1017 if (ret)
1018 goto err_exit;
1019
1020 if (pdata && pdata->setup) {
1021 ret = pdata->setup(client, chip->gpio_chip.base,
1022 chip->gpio_chip.ngpio, pdata->context);
1023 if (ret < 0)
1024 dev_warn(&client->dev, "setup failed, %d\n", ret);
1025 }
1026
1027 return 0;
1028
1029 err_exit:
1030 regulator_disable(chip->regulator);
1031 return ret;
1032 }
1033
1034 static int pca953x_remove(struct i2c_client *client)
1035 {
1036 struct pca953x_platform_data *pdata = dev_get_platdata(&client->dev);
1037 struct pca953x_chip *chip = i2c_get_clientdata(client);
1038 int ret;
1039
1040 if (pdata && pdata->teardown) {
1041 ret = pdata->teardown(client, chip->gpio_chip.base,
1042 chip->gpio_chip.ngpio, pdata->context);
1043 if (ret < 0)
1044 dev_err(&client->dev, "%s failed, %d\n",
1045 "teardown", ret);
1046 } else {
1047 ret = 0;
1048 }
1049
1050 regulator_disable(chip->regulator);
1051
1052 return ret;
1053 }
1054
1055 #ifdef CONFIG_PM_SLEEP
1056 static int pca953x_regcache_sync(struct device *dev)
1057 {
1058 struct pca953x_chip *chip = dev_get_drvdata(dev);
1059 int ret;
1060
1061 /*
1062 * The ordering between direction and output is important,
1063 * sync these registers first and only then sync the rest.
1064 */
1065 ret = regcache_sync_region(chip->regmap, chip->regs->direction,
1066 chip->regs->direction + NBANK(chip));
1067 if (ret != 0) {
1068 dev_err(dev, "Failed to sync GPIO dir registers: %d\n", ret);
1069 return ret;
1070 }
1071
1072 ret = regcache_sync_region(chip->regmap, chip->regs->output,
1073 chip->regs->output + NBANK(chip));
1074 if (ret != 0) {
1075 dev_err(dev, "Failed to sync GPIO out registers: %d\n", ret);
1076 return ret;
1077 }
1078
1079 #ifdef CONFIG_GPIO_PCA953X_IRQ
1080 if (chip->driver_data & PCA_PCAL) {
1081 ret = regcache_sync_region(chip->regmap, PCAL953X_IN_LATCH,
1082 PCAL953X_IN_LATCH + NBANK(chip));
1083 if (ret != 0) {
1084 dev_err(dev, "Failed to sync INT latch registers: %d\n",
1085 ret);
1086 return ret;
1087 }
1088
1089 ret = regcache_sync_region(chip->regmap, PCAL953X_INT_MASK,
1090 PCAL953X_INT_MASK + NBANK(chip));
1091 if (ret != 0) {
1092 dev_err(dev, "Failed to sync INT mask registers: %d\n",
1093 ret);
1094 return ret;
1095 }
1096 }
1097 #endif
1098
1099 return 0;
1100 }
1101
1102 static int pca953x_suspend(struct device *dev)
1103 {
1104 struct pca953x_chip *chip = dev_get_drvdata(dev);
1105
1106 regcache_cache_only(chip->regmap, true);
1107
1108 if (atomic_read(&chip->wakeup_path))
1109 device_set_wakeup_path(dev);
1110 else
1111 regulator_disable(chip->regulator);
1112
1113 return 0;
1114 }
1115
1116 static int pca953x_resume(struct device *dev)
1117 {
1118 struct pca953x_chip *chip = dev_get_drvdata(dev);
1119 int ret;
1120
1121 if (!atomic_read(&chip->wakeup_path)) {
1122 ret = regulator_enable(chip->regulator);
1123 if (ret != 0) {
1124 dev_err(dev, "Failed to enable regulator: %d\n", ret);
1125 return 0;
1126 }
1127 }
1128
1129 regcache_cache_only(chip->regmap, false);
1130 regcache_mark_dirty(chip->regmap);
1131 ret = pca953x_regcache_sync(dev);
1132 if (ret)
1133 return ret;
1134
1135 ret = regcache_sync(chip->regmap);
1136 if (ret != 0) {
1137 dev_err(dev, "Failed to restore register map: %d\n", ret);
1138 return ret;
1139 }
1140
1141 return 0;
1142 }
1143 #endif
1144
1145 /* convenience to stop overlong match-table lines */
1146 #define OF_953X(__nrgpio, __int) (void *)(__nrgpio | PCA953X_TYPE | __int)
1147 #define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int)
1148
1149 static const struct of_device_id pca953x_dt_ids[] = {
1150 { .compatible = "nxp,pca6416", .data = OF_953X(16, PCA_INT), },
1151 { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), },
1152 { .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), },
1153 { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), },
1154 { .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), },
1155 { .compatible = "nxp,pca9537", .data = OF_953X( 4, PCA_INT), },
1156 { .compatible = "nxp,pca9538", .data = OF_953X( 8, PCA_INT), },
1157 { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), },
1158 { .compatible = "nxp,pca9554", .data = OF_953X( 8, PCA_INT), },
1159 { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), },
1160 { .compatible = "nxp,pca9556", .data = OF_953X( 8, 0), },
1161 { .compatible = "nxp,pca9557", .data = OF_953X( 8, 0), },
1162 { .compatible = "nxp,pca9574", .data = OF_957X( 8, PCA_INT), },
1163 { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), },
1164 { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), },
1165
1166 { .compatible = "nxp,pcal6416", .data = OF_953X(16, PCA_LATCH_INT), },
1167 { .compatible = "nxp,pcal6524", .data = OF_953X(24, PCA_LATCH_INT), },
1168 { .compatible = "nxp,pcal9555a", .data = OF_953X(16, PCA_LATCH_INT), },
1169
1170 { .compatible = "maxim,max7310", .data = OF_953X( 8, 0), },
1171 { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), },
1172 { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), },
1173 { .compatible = "maxim,max7315", .data = OF_953X( 8, PCA_INT), },
1174 { .compatible = "maxim,max7318", .data = OF_953X(16, PCA_INT), },
1175
1176 { .compatible = "ti,pca6107", .data = OF_953X( 8, PCA_INT), },
1177 { .compatible = "ti,pca9536", .data = OF_953X( 4, 0), },
1178 { .compatible = "ti,tca6408", .data = OF_953X( 8, PCA_INT), },
1179 { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), },
1180 { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), },
1181 { .compatible = "ti,tca9539", .data = OF_953X(16, PCA_INT), },
1182
1183 { .compatible = "onnn,cat9554", .data = OF_953X( 8, PCA_INT), },
1184 { .compatible = "onnn,pca9654", .data = OF_953X( 8, PCA_INT), },
1185
1186 { .compatible = "exar,xra1202", .data = OF_953X( 8, 0), },
1187 { }
1188 };
1189
1190 MODULE_DEVICE_TABLE(of, pca953x_dt_ids);
1191
1192 static SIMPLE_DEV_PM_OPS(pca953x_pm_ops, pca953x_suspend, pca953x_resume);
1193
1194 static struct i2c_driver pca953x_driver = {
1195 .driver = {
1196 .name = "pca953x",
1197 .pm = &pca953x_pm_ops,
1198 .of_match_table = pca953x_dt_ids,
1199 .acpi_match_table = ACPI_PTR(pca953x_acpi_ids),
1200 },
1201 .probe = pca953x_probe,
1202 .remove = pca953x_remove,
1203 .id_table = pca953x_id,
1204 };
1205
1206 static int __init pca953x_init(void)
1207 {
1208 return i2c_add_driver(&pca953x_driver);
1209 }
1210 /* register after i2c postcore initcall and before
1211 * subsys initcalls that may rely on these GPIOs
1212 */
1213 subsys_initcall(pca953x_init);
1214
1215 static void __exit pca953x_exit(void)
1216 {
1217 i2c_del_driver(&pca953x_driver);
1218 }
1219 module_exit(pca953x_exit);
1220
1221 MODULE_AUTHOR("eric miao <eric.miao@marvell.com>");
1222 MODULE_DESCRIPTION("GPIO expander driver for PCA953x");
1223 MODULE_LICENSE("GPL");
Linux with added FPC-III support