drivers/misc/mei/hw-me-regs.h

   1 /******************************************************************************
   2  * Intel Management Engine Interface (Intel MEI) Linux driver
   3  * Intel MEI Interface Header
   4  *
   5  * This file is provided under a dual BSD/GPLv2 license.  When using or
   6  * redistributing this file, you may do so under either license.
   7  *
   8  * GPL LICENSE SUMMARY
   9  *
  10  * Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved.
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of version 2 of the GNU General Public License as
  14  * published by the Free Software Foundation.
  15  *
  16  * This program is distributed in the hope that it will be useful, but
  17  * WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  19  * General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  24  * USA
  25  *
  26  * The full GNU General Public License is included in this distribution
  27  * in the file called LICENSE.GPL.
  28  *
  29  * Contact Information:
  30  *      Intel Corporation.
  31  *      linux-mei@linux.intel.com
  32  *      http://www.intel.com
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  34  * BSD LICENSE
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  36  * Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved.
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  51  *    from this software without specific prior written permission.
  52  *
  53  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  54  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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  59  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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  63  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  64  *
  65  *****************************************************************************/
  66 #ifndef _MEI_HW_MEI_REGS_H_
  67 #define _MEI_HW_MEI_REGS_H_
  68
  69 /*
  70  * MEI device IDs
  71  */
  72 #define MEI_DEV_ID_82946GZ    0x2974  /* 82946GZ/GL */
  73 #define MEI_DEV_ID_82G35      0x2984  /* 82G35 Express */
  74 #define MEI_DEV_ID_82Q965     0x2994  /* 82Q963/Q965 */
  75 #define MEI_DEV_ID_82G965     0x29A4  /* 82P965/G965 */
  76
  77 #define MEI_DEV_ID_82GM965    0x2A04  /* Mobile PM965/GM965 */
  78 #define MEI_DEV_ID_82GME965   0x2A14  /* Mobile GME965/GLE960 */
  79
  80 #define MEI_DEV_ID_ICH9_82Q35 0x29B4  /* 82Q35 Express */
  81 #define MEI_DEV_ID_ICH9_82G33 0x29C4  /* 82G33/G31/P35/P31 Express */
  82 #define MEI_DEV_ID_ICH9_82Q33 0x29D4  /* 82Q33 Express */
  83 #define MEI_DEV_ID_ICH9_82X38 0x29E4  /* 82X38/X48 Express */
  84 #define MEI_DEV_ID_ICH9_3200  0x29F4  /* 3200/3210 Server */
  85
  86 #define MEI_DEV_ID_ICH9_6     0x28B4  /* Bearlake */
  87 #define MEI_DEV_ID_ICH9_7     0x28C4  /* Bearlake */
  88 #define MEI_DEV_ID_ICH9_8     0x28D4  /* Bearlake */
  89 #define MEI_DEV_ID_ICH9_9     0x28E4  /* Bearlake */
  90 #define MEI_DEV_ID_ICH9_10    0x28F4  /* Bearlake */
  91
  92 #define MEI_DEV_ID_ICH9M_1    0x2A44  /* Cantiga */
  93 #define MEI_DEV_ID_ICH9M_2    0x2A54  /* Cantiga */
  94 #define MEI_DEV_ID_ICH9M_3    0x2A64  /* Cantiga */
  95 #define MEI_DEV_ID_ICH9M_4    0x2A74  /* Cantiga */
  96
  97 #define MEI_DEV_ID_ICH10_1    0x2E04  /* Eaglelake */
  98 #define MEI_DEV_ID_ICH10_2    0x2E14  /* Eaglelake */
  99 #define MEI_DEV_ID_ICH10_3    0x2E24  /* Eaglelake */
 100 #define MEI_DEV_ID_ICH10_4    0x2E34  /* Eaglelake */
 101
 102 #define MEI_DEV_ID_IBXPK_1    0x3B64  /* Calpella */
 103 #define MEI_DEV_ID_IBXPK_2    0x3B65  /* Calpella */
 104
 105 #define MEI_DEV_ID_CPT_1      0x1C3A  /* Couger Point */
 106 #define MEI_DEV_ID_PBG_1      0x1D3A  /* C600/X79 Patsburg */
 107
 108 #define MEI_DEV_ID_PPT_1      0x1E3A  /* Panther Point */
 109 #define MEI_DEV_ID_PPT_2      0x1CBA  /* Panther Point */
 110 #define MEI_DEV_ID_PPT_3      0x1DBA  /* Panther Point */
 111
 112 #define MEI_DEV_ID_LPT_H      0x8C3A  /* Lynx Point H */
 113 #define MEI_DEV_ID_LPT_W      0x8D3A  /* Lynx Point - Wellsburg */
 114 #define MEI_DEV_ID_LPT_LP     0x9C3A  /* Lynx Point LP */
 115 #define MEI_DEV_ID_LPT_HR     0x8CBA  /* Lynx Point H Refresh */
 116
 117 #define MEI_DEV_ID_WPT_LP     0x9CBA  /* Wildcat Point LP */
 118 #define MEI_DEV_ID_WPT_LP_2   0x9CBB  /* Wildcat Point LP 2 */
 119
 120 #define MEI_DEV_ID_SPT        0x9D3A  /* Sunrise Point */
 121 #define MEI_DEV_ID_SPT_2      0x9D3B  /* Sunrise Point 2 */
 122 #define MEI_DEV_ID_SPT_H      0xA13A  /* Sunrise Point H */
 123 #define MEI_DEV_ID_SPT_H_2    0xA13B  /* Sunrise Point H 2 */
 124
 125 #define MEI_DEV_ID_LBG        0xA1BA  /* Lewisburg (SPT) */
 126
 127 #define MEI_DEV_ID_BXT_M      0x1A9A  /* Broxton M */
 128 #define MEI_DEV_ID_APL_I      0x5A9A  /* Apollo Lake I */
 129
 130 #define MEI_DEV_ID_GLK        0x319A  /* Gemini Lake */
 131
 132 #define MEI_DEV_ID_KBP        0xA2BA  /* Kaby Point */
 133 #define MEI_DEV_ID_KBP_2      0xA2BB  /* Kaby Point 2 */
 134
 135 #define MEI_DEV_ID_CNP_LP     0x9DE0  /* Cannon Point LP */
 136 #define MEI_DEV_ID_CNP_LP_4   0x9DE4  /* Cannon Point LP 4 (iTouch) */
 137 #define MEI_DEV_ID_CNP_H      0xA360  /* Cannon Point H */
 138 #define MEI_DEV_ID_CNP_H_4    0xA364  /* Cannon Point H 4 (iTouch) */
 139
 140 /*
 141  * MEI HW Section
 142  */
 143
 144 /* Host Firmware Status Registers in PCI Config Space */
 145 #define PCI_CFG_HFS_1         0x40
 146 #  define PCI_CFG_HFS_1_D0I3_MSK     0x80000000
 147 #define PCI_CFG_HFS_2         0x48
 148 #define PCI_CFG_HFS_3         0x60
 149 #define PCI_CFG_HFS_4         0x64
 150 #define PCI_CFG_HFS_5         0x68
 151 #define PCI_CFG_HFS_6         0x6C
 152
 153 /* MEI registers */
 154 /* H_CB_WW - Host Circular Buffer (CB) Write Window register */
 155 #define H_CB_WW    0
 156 /* H_CSR - Host Control Status register */
 157 #define H_CSR      4
 158 /* ME_CB_RW - ME Circular Buffer Read Window register (read only) */
 159 #define ME_CB_RW   8
 160 /* ME_CSR_HA - ME Control Status Host Access register (read only) */
 161 #define ME_CSR_HA  0xC
 162 /* H_HGC_CSR - PGI register */
 163 #define H_HPG_CSR  0x10
 164 /* H_D0I3C - D0I3 Control  */
 165 #define H_D0I3C    0x800
 166
 167 /* register bits of H_CSR (Host Control Status register) */
 168 /* Host Circular Buffer Depth - maximum number of 32-bit entries in CB */
 169 #define H_CBD             0xFF000000
 170 /* Host Circular Buffer Write Pointer */
 171 #define H_CBWP            0x00FF0000
 172 /* Host Circular Buffer Read Pointer */
 173 #define H_CBRP            0x0000FF00
 174 /* Host Reset */
 175 #define H_RST             0x00000010
 176 /* Host Ready */
 177 #define H_RDY             0x00000008
 178 /* Host Interrupt Generate */
 179 #define H_IG              0x00000004
 180 /* Host Interrupt Status */
 181 #define H_IS              0x00000002
 182 /* Host Interrupt Enable */
 183 #define H_IE              0x00000001
 184 /* Host D0I3 Interrupt Enable */
 185 #define H_D0I3C_IE        0x00000020
 186 /* Host D0I3 Interrupt Status */
 187 #define H_D0I3C_IS        0x00000040
 188
 189 /* H_CSR masks */
 190 #define H_CSR_IE_MASK     (H_IE | H_D0I3C_IE)
 191 #define H_CSR_IS_MASK     (H_IS | H_D0I3C_IS)
 192
 193 /* register bits of ME_CSR_HA (ME Control Status Host Access register) */
 194 /* ME CB (Circular Buffer) Depth HRA (Host Read Access) - host read only
 195 access to ME_CBD */
 196 #define ME_CBD_HRA        0xFF000000
 197 /* ME CB Write Pointer HRA - host read only access to ME_CBWP */
 198 #define ME_CBWP_HRA       0x00FF0000
 199 /* ME CB Read Pointer HRA - host read only access to ME_CBRP */
 200 #define ME_CBRP_HRA       0x0000FF00
 201 /* ME Power Gate Isolation Capability HRA  - host ready only access */
 202 #define ME_PGIC_HRA       0x00000040
 203 /* ME Reset HRA - host read only access to ME_RST */
 204 #define ME_RST_HRA        0x00000010
 205 /* ME Ready HRA - host read only access to ME_RDY */
 206 #define ME_RDY_HRA        0x00000008
 207 /* ME Interrupt Generate HRA - host read only access to ME_IG */
 208 #define ME_IG_HRA         0x00000004
 209 /* ME Interrupt Status HRA - host read only access to ME_IS */
 210 #define ME_IS_HRA         0x00000002
 211 /* ME Interrupt Enable HRA - host read only access to ME_IE */
 212 #define ME_IE_HRA         0x00000001
 213
 214
 215 /* H_HPG_CSR register bits */
 216 #define H_HPG_CSR_PGIHEXR 0x00000001
 217 #define H_HPG_CSR_PGI     0x00000002
 218
 219 /* H_D0I3C register bits */
 220 #define H_D0I3C_CIP      0x00000001
 221 #define H_D0I3C_IR       0x00000002
 222 #define H_D0I3C_I3       0x00000004
 223 #define H_D0I3C_RR       0x00000008
 224
 225 #endif /* _MEI_HW_MEI_REGS_H_ */