drivers/pci/hotplug/pciehp_hpc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * PCI Express PCI Hot Plug Driver
   4  *
   5  * Copyright (C) 1995,2001 Compaq Computer Corporation
   6  * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
   7  * Copyright (C) 2001 IBM Corp.
   8  * Copyright (C) 2003-2004 Intel Corporation
   9  *
  10  * All rights reserved.
  11  *
  12  * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/types.h>
  17 #include <linux/jiffies.h>
  18 #include <linux/kthread.h>
  19 #include <linux/pci.h>
  20 #include <linux/pm_runtime.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/slab.h>
  23
  24 #include "../pci.h"
  25 #include "pciehp.h"
  26
  27 static inline struct pci_dev *ctrl_dev(struct controller *ctrl)
  28 {
  29         return ctrl->pcie->port;
  30 }
  31
  32 static irqreturn_t pciehp_isr(int irq, void *dev_id);
  33 static irqreturn_t pciehp_ist(int irq, void *dev_id);
  34 static int pciehp_poll(void *data);
  35
  36 static inline int pciehp_request_irq(struct controller *ctrl)
  37 {
  38         int retval, irq = ctrl->pcie->irq;
  39
  40         if (pciehp_poll_mode) {
  41                 ctrl->poll_thread = kthread_run(&pciehp_poll, ctrl,
  42                                                 "pciehp_poll-%s",
  43                                                 slot_name(ctrl));
  44                 return PTR_ERR_OR_ZERO(ctrl->poll_thread);
  45         }
  46
  47         /* Installs the interrupt handler */
  48         retval = request_threaded_irq(irq, pciehp_isr, pciehp_ist,
  49                                       IRQF_SHARED, MY_NAME, ctrl);
  50         if (retval)
  51                 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
  52                          irq);
  53         return retval;
  54 }
  55
  56 static inline void pciehp_free_irq(struct controller *ctrl)
  57 {
  58         if (pciehp_poll_mode)
  59                 kthread_stop(ctrl->poll_thread);
  60         else
  61                 free_irq(ctrl->pcie->irq, ctrl);
  62 }
  63
  64 static int pcie_poll_cmd(struct controller *ctrl, int timeout)
  65 {
  66         struct pci_dev *pdev = ctrl_dev(ctrl);
  67         u16 slot_status;
  68
  69         while (true) {
  70                 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
  71                 if (slot_status == (u16) ~0) {
  72                         ctrl_info(ctrl, "%s: no response from device\n",
  73                                   __func__);
  74                         return 0;
  75                 }
  76
  77                 if (slot_status & PCI_EXP_SLTSTA_CC) {
  78                         pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
  79                                                    PCI_EXP_SLTSTA_CC);
  80                         return 1;
  81                 }
  82                 if (timeout < 0)
  83                         break;
  84                 msleep(10);
  85                 timeout -= 10;
  86         }
  87         return 0;       /* timeout */
  88 }
  89
  90 static void pcie_wait_cmd(struct controller *ctrl)
  91 {
  92         unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
  93         unsigned long duration = msecs_to_jiffies(msecs);
  94         unsigned long cmd_timeout = ctrl->cmd_started + duration;
  95         unsigned long now, timeout;
  96         int rc;
  97
  98         /*
  99          * If the controller does not generate notifications for command
 100          * completions, we never need to wait between writes.
 101          */
 102         if (NO_CMD_CMPL(ctrl))
 103                 return;
 104
 105         if (!ctrl->cmd_busy)
 106                 return;
 107
 108         /*
 109          * Even if the command has already timed out, we want to call
 110          * pcie_poll_cmd() so it can clear PCI_EXP_SLTSTA_CC.
 111          */
 112         now = jiffies;
 113         if (time_before_eq(cmd_timeout, now))
 114                 timeout = 1;
 115         else
 116                 timeout = cmd_timeout - now;
 117
 118         if (ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE &&
 119             ctrl->slot_ctrl & PCI_EXP_SLTCTL_CCIE)
 120                 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
 121         else
 122                 rc = pcie_poll_cmd(ctrl, jiffies_to_msecs(timeout));
 123
 124         if (!rc)
 125                 ctrl_info(ctrl, "Timeout on hotplug command %#06x (issued %u msec ago)\n",
 126                           ctrl->slot_ctrl,
 127                           jiffies_to_msecs(jiffies - ctrl->cmd_started));
 128 }
 129
 130 #define CC_ERRATUM_MASK         (PCI_EXP_SLTCTL_PCC |   \
 131                                  PCI_EXP_SLTCTL_PIC |   \
 132                                  PCI_EXP_SLTCTL_AIC |   \
 133                                  PCI_EXP_SLTCTL_EIC)
 134
 135 static void pcie_do_write_cmd(struct controller *ctrl, u16 cmd,
 136                               u16 mask, bool wait)
 137 {
 138         struct pci_dev *pdev = ctrl_dev(ctrl);
 139         u16 slot_ctrl_orig, slot_ctrl;
 140
 141         mutex_lock(&ctrl->ctrl_lock);
 142
 143         /*
 144          * Always wait for any previous command that might still be in progress
 145          */
 146         pcie_wait_cmd(ctrl);
 147
 148         pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
 149         if (slot_ctrl == (u16) ~0) {
 150                 ctrl_info(ctrl, "%s: no response from device\n", __func__);
 151                 goto out;
 152         }
 153
 154         slot_ctrl_orig = slot_ctrl;
 155         slot_ctrl &= ~mask;
 156         slot_ctrl |= (cmd & mask);
 157         ctrl->cmd_busy = 1;
 158         smp_mb();
 159         pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl);
 160         ctrl->cmd_started = jiffies;
 161         ctrl->slot_ctrl = slot_ctrl;
 162
 163         /*
 164          * Controllers with the Intel CF118 and similar errata advertise
 165          * Command Completed support, but they only set Command Completed
 166          * if we change the "Control" bits for power, power indicator,
 167          * attention indicator, or interlock.  If we only change the
 168          * "Enable" bits, they never set the Command Completed bit.
 169          */
 170         if (pdev->broken_cmd_compl &&
 171             (slot_ctrl_orig & CC_ERRATUM_MASK) == (slot_ctrl & CC_ERRATUM_MASK))
 172                 ctrl->cmd_busy = 0;
 173
 174         /*
 175          * Optionally wait for the hardware to be ready for a new command,
 176          * indicating completion of the above issued command.
 177          */
 178         if (wait)
 179                 pcie_wait_cmd(ctrl);
 180
 181 out:
 182         mutex_unlock(&ctrl->ctrl_lock);
 183 }
 184
 185 /**
 186  * pcie_write_cmd - Issue controller command
 187  * @ctrl: controller to which the command is issued
 188  * @cmd:  command value written to slot control register
 189  * @mask: bitmask of slot control register to be modified
 190  */
 191 static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
 192 {
 193         pcie_do_write_cmd(ctrl, cmd, mask, true);
 194 }
 195
 196 /* Same as above without waiting for the hardware to latch */
 197 static void pcie_write_cmd_nowait(struct controller *ctrl, u16 cmd, u16 mask)
 198 {
 199         pcie_do_write_cmd(ctrl, cmd, mask, false);
 200 }
 201
 202 bool pciehp_check_link_active(struct controller *ctrl)
 203 {
 204         struct pci_dev *pdev = ctrl_dev(ctrl);
 205         u16 lnk_status;
 206         bool ret;
 207
 208         pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
 209         ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
 210
 211         if (ret)
 212                 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
 213
 214         return ret;
 215 }
 216
 217 static bool pci_bus_check_dev(struct pci_bus *bus, int devfn)
 218 {
 219         u32 l;
 220         int count = 0;
 221         int delay = 1000, step = 20;
 222         bool found = false;
 223
 224         do {
 225                 found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0);
 226                 count++;
 227
 228                 if (found)
 229                         break;
 230
 231                 msleep(step);
 232                 delay -= step;
 233         } while (delay > 0);
 234
 235         if (count > 1 && pciehp_debug)
 236                 printk(KERN_DEBUG "pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n",
 237                         pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
 238                         PCI_FUNC(devfn), count, step, l);
 239
 240         return found;
 241 }
 242
 243 int pciehp_check_link_status(struct controller *ctrl)
 244 {
 245         struct pci_dev *pdev = ctrl_dev(ctrl);
 246         bool found;
 247         u16 lnk_status;
 248
 249         if (!pcie_wait_for_link(pdev, true))
 250                 return -1;
 251
 252         found = pci_bus_check_dev(ctrl->pcie->port->subordinate,
 253                                         PCI_DEVFN(0, 0));
 254
 255         /* ignore link or presence changes up to this point */
 256         if (found)
 257                 atomic_and(~(PCI_EXP_SLTSTA_DLLSC | PCI_EXP_SLTSTA_PDC),
 258                            &ctrl->pending_events);
 259
 260         pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
 261         ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
 262         if ((lnk_status & PCI_EXP_LNKSTA_LT) ||
 263             !(lnk_status & PCI_EXP_LNKSTA_NLW)) {
 264                 ctrl_err(ctrl, "link training error: status %#06x\n",
 265                          lnk_status);
 266                 return -1;
 267         }
 268
 269         pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
 270
 271         if (!found)
 272                 return -1;
 273
 274         return 0;
 275 }
 276
 277 static int __pciehp_link_set(struct controller *ctrl, bool enable)
 278 {
 279         struct pci_dev *pdev = ctrl_dev(ctrl);
 280         u16 lnk_ctrl;
 281
 282         pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &lnk_ctrl);
 283
 284         if (enable)
 285                 lnk_ctrl &= ~PCI_EXP_LNKCTL_LD;
 286         else
 287                 lnk_ctrl |= PCI_EXP_LNKCTL_LD;
 288
 289         pcie_capability_write_word(pdev, PCI_EXP_LNKCTL, lnk_ctrl);
 290         ctrl_dbg(ctrl, "%s: lnk_ctrl = %x\n", __func__, lnk_ctrl);
 291         return 0;
 292 }
 293
 294 static int pciehp_link_enable(struct controller *ctrl)
 295 {
 296         return __pciehp_link_set(ctrl, true);
 297 }
 298
 299 int pciehp_get_raw_indicator_status(struct hotplug_slot *hotplug_slot,
 300                                     u8 *status)
 301 {
 302         struct controller *ctrl = to_ctrl(hotplug_slot);
 303         struct pci_dev *pdev = ctrl_dev(ctrl);
 304         u16 slot_ctrl;
 305
 306         pci_config_pm_runtime_get(pdev);
 307         pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
 308         pci_config_pm_runtime_put(pdev);
 309         *status = (slot_ctrl & (PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC)) >> 6;
 310         return 0;
 311 }
 312
 313 int pciehp_get_attention_status(struct hotplug_slot *hotplug_slot, u8 *status)
 314 {
 315         struct controller *ctrl = to_ctrl(hotplug_slot);
 316         struct pci_dev *pdev = ctrl_dev(ctrl);
 317         u16 slot_ctrl;
 318
 319         pci_config_pm_runtime_get(pdev);
 320         pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
 321         pci_config_pm_runtime_put(pdev);
 322         ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__,
 323                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
 324
 325         switch (slot_ctrl & PCI_EXP_SLTCTL_AIC) {
 326         case PCI_EXP_SLTCTL_ATTN_IND_ON:
 327                 *status = 1;    /* On */
 328                 break;
 329         case PCI_EXP_SLTCTL_ATTN_IND_BLINK:
 330                 *status = 2;    /* Blink */
 331                 break;
 332         case PCI_EXP_SLTCTL_ATTN_IND_OFF:
 333                 *status = 0;    /* Off */
 334                 break;
 335         default:
 336                 *status = 0xFF;
 337                 break;
 338         }
 339
 340         return 0;
 341 }
 342
 343 void pciehp_get_power_status(struct controller *ctrl, u8 *status)
 344 {
 345         struct pci_dev *pdev = ctrl_dev(ctrl);
 346         u16 slot_ctrl;
 347
 348         pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
 349         ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__,
 350                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
 351
 352         switch (slot_ctrl & PCI_EXP_SLTCTL_PCC) {
 353         case PCI_EXP_SLTCTL_PWR_ON:
 354                 *status = 1;    /* On */
 355                 break;
 356         case PCI_EXP_SLTCTL_PWR_OFF:
 357                 *status = 0;    /* Off */
 358                 break;
 359         default:
 360                 *status = 0xFF;
 361                 break;
 362         }
 363 }
 364
 365 void pciehp_get_latch_status(struct controller *ctrl, u8 *status)
 366 {
 367         struct pci_dev *pdev = ctrl_dev(ctrl);
 368         u16 slot_status;
 369
 370         pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
 371         *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);
 372 }
 373
 374 bool pciehp_card_present(struct controller *ctrl)
 375 {
 376         struct pci_dev *pdev = ctrl_dev(ctrl);
 377         u16 slot_status;
 378
 379         pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
 380         return slot_status & PCI_EXP_SLTSTA_PDS;
 381 }
 382
 383 /**
 384  * pciehp_card_present_or_link_active() - whether given slot is occupied
 385  * @ctrl: PCIe hotplug controller
 386  *
 387  * Unlike pciehp_card_present(), which determines presence solely from the
 388  * Presence Detect State bit, this helper also returns true if the Link Active
 389  * bit is set.  This is a concession to broken hotplug ports which hardwire
 390  * Presence Detect State to zero, such as Wilocity's [1ae9:0200].
 391  */
 392 bool pciehp_card_present_or_link_active(struct controller *ctrl)
 393 {
 394         return pciehp_card_present(ctrl) || pciehp_check_link_active(ctrl);
 395 }
 396
 397 int pciehp_query_power_fault(struct controller *ctrl)
 398 {
 399         struct pci_dev *pdev = ctrl_dev(ctrl);
 400         u16 slot_status;
 401
 402         pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
 403         return !!(slot_status & PCI_EXP_SLTSTA_PFD);
 404 }
 405
 406 int pciehp_set_raw_indicator_status(struct hotplug_slot *hotplug_slot,
 407                                     u8 status)
 408 {
 409         struct controller *ctrl = to_ctrl(hotplug_slot);
 410         struct pci_dev *pdev = ctrl_dev(ctrl);
 411
 412         pci_config_pm_runtime_get(pdev);
 413         pcie_write_cmd_nowait(ctrl, status << 6,
 414                               PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC);
 415         pci_config_pm_runtime_put(pdev);
 416         return 0;
 417 }
 418
 419 void pciehp_set_attention_status(struct controller *ctrl, u8 value)
 420 {
 421         u16 slot_cmd;
 422
 423         if (!ATTN_LED(ctrl))
 424                 return;
 425
 426         switch (value) {
 427         case 0:         /* turn off */
 428                 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_OFF;
 429                 break;
 430         case 1:         /* turn on */
 431                 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_ON;
 432                 break;
 433         case 2:         /* turn blink */
 434                 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_BLINK;
 435                 break;
 436         default:
 437                 return;
 438         }
 439         pcie_write_cmd_nowait(ctrl, slot_cmd, PCI_EXP_SLTCTL_AIC);
 440         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 441                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
 442 }
 443
 444 void pciehp_green_led_on(struct controller *ctrl)
 445 {
 446         if (!PWR_LED(ctrl))
 447                 return;
 448
 449         pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_ON,
 450                               PCI_EXP_SLTCTL_PIC);
 451         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 452                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
 453                  PCI_EXP_SLTCTL_PWR_IND_ON);
 454 }
 455
 456 void pciehp_green_led_off(struct controller *ctrl)
 457 {
 458         if (!PWR_LED(ctrl))
 459                 return;
 460
 461         pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF,
 462                               PCI_EXP_SLTCTL_PIC);
 463         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 464                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
 465                  PCI_EXP_SLTCTL_PWR_IND_OFF);
 466 }
 467
 468 void pciehp_green_led_blink(struct controller *ctrl)
 469 {
 470         if (!PWR_LED(ctrl))
 471                 return;
 472
 473         pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_BLINK,
 474                               PCI_EXP_SLTCTL_PIC);
 475         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 476                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
 477                  PCI_EXP_SLTCTL_PWR_IND_BLINK);
 478 }
 479
 480 int pciehp_power_on_slot(struct controller *ctrl)
 481 {
 482         struct pci_dev *pdev = ctrl_dev(ctrl);
 483         u16 slot_status;
 484         int retval;
 485
 486         /* Clear power-fault bit from previous power failures */
 487         pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
 488         if (slot_status & PCI_EXP_SLTSTA_PFD)
 489                 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
 490                                            PCI_EXP_SLTSTA_PFD);
 491         ctrl->power_fault_detected = 0;
 492
 493         pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_ON, PCI_EXP_SLTCTL_PCC);
 494         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 495                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
 496                  PCI_EXP_SLTCTL_PWR_ON);
 497
 498         retval = pciehp_link_enable(ctrl);
 499         if (retval)
 500                 ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__);
 501
 502         return retval;
 503 }
 504
 505 void pciehp_power_off_slot(struct controller *ctrl)
 506 {
 507         pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_OFF, PCI_EXP_SLTCTL_PCC);
 508         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 509                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
 510                  PCI_EXP_SLTCTL_PWR_OFF);
 511 }
 512
 513 static irqreturn_t pciehp_isr(int irq, void *dev_id)
 514 {
 515         struct controller *ctrl = (struct controller *)dev_id;
 516         struct pci_dev *pdev = ctrl_dev(ctrl);
 517         struct device *parent = pdev->dev.parent;
 518         u16 status, events;
 519
 520         /*
 521          * Interrupts only occur in D3hot or shallower and only if enabled
 522          * in the Slot Control register (PCIe r4.0, sec 6.7.3.4).
 523          */
 524         if (pdev->current_state == PCI_D3cold ||
 525             (!(ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE) && !pciehp_poll_mode))
 526                 return IRQ_NONE;
 527
 528         /*
 529          * Keep the port accessible by holding a runtime PM ref on its parent.
 530          * Defer resume of the parent to the IRQ thread if it's suspended.
 531          * Mask the interrupt until then.
 532          */
 533         if (parent) {
 534                 pm_runtime_get_noresume(parent);
 535                 if (!pm_runtime_active(parent)) {
 536                         pm_runtime_put(parent);
 537                         disable_irq_nosync(irq);
 538                         atomic_or(RERUN_ISR, &ctrl->pending_events);
 539                         return IRQ_WAKE_THREAD;
 540                 }
 541         }
 542
 543         pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &status);
 544         if (status == (u16) ~0) {
 545                 ctrl_info(ctrl, "%s: no response from device\n", __func__);
 546                 if (parent)
 547                         pm_runtime_put(parent);
 548                 return IRQ_NONE;
 549         }
 550
 551         /*
 552          * Slot Status contains plain status bits as well as event
 553          * notification bits; right now we only want the event bits.
 554          */
 555         events = status & (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
 556                            PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_CC |
 557                            PCI_EXP_SLTSTA_DLLSC);
 558
 559         /*
 560          * If we've already reported a power fault, don't report it again
 561          * until we've done something to handle it.
 562          */
 563         if (ctrl->power_fault_detected)
 564                 events &= ~PCI_EXP_SLTSTA_PFD;
 565
 566         if (!events) {
 567                 if (parent)
 568                         pm_runtime_put(parent);
 569                 return IRQ_NONE;
 570         }
 571
 572         pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, events);
 573         ctrl_dbg(ctrl, "pending interrupts %#06x from Slot Status\n", events);
 574         if (parent)
 575                 pm_runtime_put(parent);
 576
 577         /*
 578          * Command Completed notifications are not deferred to the
 579          * IRQ thread because it may be waiting for their arrival.
 580          */
 581         if (events & PCI_EXP_SLTSTA_CC) {
 582                 ctrl->cmd_busy = 0;
 583                 smp_mb();
 584                 wake_up(&ctrl->queue);
 585
 586                 if (events == PCI_EXP_SLTSTA_CC)
 587                         return IRQ_HANDLED;
 588
 589                 events &= ~PCI_EXP_SLTSTA_CC;
 590         }
 591
 592         if (pdev->ignore_hotplug) {
 593                 ctrl_dbg(ctrl, "ignoring hotplug event %#06x\n", events);
 594                 return IRQ_HANDLED;
 595         }
 596
 597         /* Save pending events for consumption by IRQ thread. */
 598         atomic_or(events, &ctrl->pending_events);
 599         return IRQ_WAKE_THREAD;
 600 }
 601
 602 static irqreturn_t pciehp_ist(int irq, void *dev_id)
 603 {
 604         struct controller *ctrl = (struct controller *)dev_id;
 605         struct pci_dev *pdev = ctrl_dev(ctrl);
 606         irqreturn_t ret;
 607         u32 events;
 608
 609         pci_config_pm_runtime_get(pdev);
 610
 611         /* rerun pciehp_isr() if the port was inaccessible on interrupt */
 612         if (atomic_fetch_and(~RERUN_ISR, &ctrl->pending_events) & RERUN_ISR) {
 613                 ret = pciehp_isr(irq, dev_id);
 614                 enable_irq(irq);
 615                 if (ret != IRQ_WAKE_THREAD) {
 616                         pci_config_pm_runtime_put(pdev);
 617                         return ret;
 618                 }
 619         }
 620
 621         synchronize_hardirq(irq);
 622         events = atomic_xchg(&ctrl->pending_events, 0);
 623         if (!events) {
 624                 pci_config_pm_runtime_put(pdev);
 625                 return IRQ_NONE;
 626         }
 627
 628         /* Check Attention Button Pressed */
 629         if (events & PCI_EXP_SLTSTA_ABP) {
 630                 ctrl_info(ctrl, "Slot(%s): Attention button pressed\n",
 631                           slot_name(ctrl));
 632                 pciehp_handle_button_press(ctrl);
 633         }
 634
 635         /* Check Power Fault Detected */
 636         if ((events & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) {
 637                 ctrl->power_fault_detected = 1;
 638                 ctrl_err(ctrl, "Slot(%s): Power fault\n", slot_name(ctrl));
 639                 pciehp_set_attention_status(ctrl, 1);
 640                 pciehp_green_led_off(ctrl);
 641         }
 642
 643         /*
 644          * Disable requests have higher priority than Presence Detect Changed
 645          * or Data Link Layer State Changed events.
 646          */
 647         down_read(&ctrl->reset_lock);
 648         if (events & DISABLE_SLOT)
 649                 pciehp_handle_disable_request(ctrl);
 650         else if (events & (PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_DLLSC))
 651                 pciehp_handle_presence_or_link_change(ctrl, events);
 652         up_read(&ctrl->reset_lock);
 653
 654         pci_config_pm_runtime_put(pdev);
 655         wake_up(&ctrl->requester);
 656         return IRQ_HANDLED;
 657 }
 658
 659 static int pciehp_poll(void *data)
 660 {
 661         struct controller *ctrl = data;
 662
 663         schedule_timeout_idle(10 * HZ); /* start with 10 sec delay */
 664
 665         while (!kthread_should_stop()) {
 666                 /* poll for interrupt events or user requests */
 667                 while (pciehp_isr(IRQ_NOTCONNECTED, ctrl) == IRQ_WAKE_THREAD ||
 668                        atomic_read(&ctrl->pending_events))
 669                         pciehp_ist(IRQ_NOTCONNECTED, ctrl);
 670
 671                 if (pciehp_poll_time <= 0 || pciehp_poll_time > 60)
 672                         pciehp_poll_time = 2; /* clamp to sane value */
 673
 674                 schedule_timeout_idle(pciehp_poll_time * HZ);
 675         }
 676
 677         return 0;
 678 }
 679
 680 static void pcie_enable_notification(struct controller *ctrl)
 681 {
 682         u16 cmd, mask;
 683
 684         /*
 685          * TBD: Power fault detected software notification support.
 686          *
 687          * Power fault detected software notification is not enabled
 688          * now, because it caused power fault detected interrupt storm
 689          * on some machines. On those machines, power fault detected
 690          * bit in the slot status register was set again immediately
 691          * when it is cleared in the interrupt service routine, and
 692          * next power fault detected interrupt was notified again.
 693          */
 694
 695         /*
 696          * Always enable link events: thus link-up and link-down shall
 697          * always be treated as hotplug and unplug respectively. Enable
 698          * presence detect only if Attention Button is not present.
 699          */
 700         cmd = PCI_EXP_SLTCTL_DLLSCE;
 701         if (ATTN_BUTTN(ctrl))
 702                 cmd |= PCI_EXP_SLTCTL_ABPE;
 703         else
 704                 cmd |= PCI_EXP_SLTCTL_PDCE;
 705         if (!pciehp_poll_mode)
 706                 cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE;
 707
 708         mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
 709                 PCI_EXP_SLTCTL_PFDE |
 710                 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
 711                 PCI_EXP_SLTCTL_DLLSCE);
 712
 713         pcie_write_cmd_nowait(ctrl, cmd, mask);
 714         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 715                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd);
 716 }
 717
 718 static void pcie_disable_notification(struct controller *ctrl)
 719 {
 720         u16 mask;
 721
 722         mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
 723                 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
 724                 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
 725                 PCI_EXP_SLTCTL_DLLSCE);
 726         pcie_write_cmd(ctrl, 0, mask);
 727         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 728                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
 729 }
 730
 731 void pcie_clear_hotplug_events(struct controller *ctrl)
 732 {
 733         pcie_capability_write_word(ctrl_dev(ctrl), PCI_EXP_SLTSTA,
 734                                    PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_DLLSC);
 735 }
 736
 737 void pcie_enable_interrupt(struct controller *ctrl)
 738 {
 739         pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_HPIE, PCI_EXP_SLTCTL_HPIE);
 740 }
 741
 742 void pcie_disable_interrupt(struct controller *ctrl)
 743 {
 744         pcie_write_cmd(ctrl, 0, PCI_EXP_SLTCTL_HPIE);
 745 }
 746
 747 /*
 748  * pciehp has a 1:1 bus:slot relationship so we ultimately want a secondary
 749  * bus reset of the bridge, but at the same time we want to ensure that it is
 750  * not seen as a hot-unplug, followed by the hot-plug of the device. Thus,
 751  * disable link state notification and presence detection change notification
 752  * momentarily, if we see that they could interfere. Also, clear any spurious
 753  * events after.
 754  */
 755 int pciehp_reset_slot(struct hotplug_slot *hotplug_slot, int probe)
 756 {
 757         struct controller *ctrl = to_ctrl(hotplug_slot);
 758         struct pci_dev *pdev = ctrl_dev(ctrl);
 759         u16 stat_mask = 0, ctrl_mask = 0;
 760         int rc;
 761
 762         if (probe)
 763                 return 0;
 764
 765         down_write(&ctrl->reset_lock);
 766
 767         if (!ATTN_BUTTN(ctrl)) {
 768                 ctrl_mask |= PCI_EXP_SLTCTL_PDCE;
 769                 stat_mask |= PCI_EXP_SLTSTA_PDC;
 770         }
 771         ctrl_mask |= PCI_EXP_SLTCTL_DLLSCE;
 772         stat_mask |= PCI_EXP_SLTSTA_DLLSC;
 773
 774         pcie_write_cmd(ctrl, 0, ctrl_mask);
 775         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 776                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
 777
 778         rc = pci_bridge_secondary_bus_reset(ctrl->pcie->port);
 779
 780         pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, stat_mask);
 781         pcie_write_cmd_nowait(ctrl, ctrl_mask, ctrl_mask);
 782         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 783                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, ctrl_mask);
 784
 785         up_write(&ctrl->reset_lock);
 786         return rc;
 787 }
 788
 789 int pcie_init_notification(struct controller *ctrl)
 790 {
 791         if (pciehp_request_irq(ctrl))
 792                 return -1;
 793         pcie_enable_notification(ctrl);
 794         ctrl->notification_enabled = 1;
 795         return 0;
 796 }
 797
 798 void pcie_shutdown_notification(struct controller *ctrl)
 799 {
 800         if (ctrl->notification_enabled) {
 801                 pcie_disable_notification(ctrl);
 802                 pciehp_free_irq(ctrl);
 803                 ctrl->notification_enabled = 0;
 804         }
 805 }
 806
 807 static inline void dbg_ctrl(struct controller *ctrl)
 808 {
 809         struct pci_dev *pdev = ctrl->pcie->port;
 810         u16 reg16;
 811
 812         if (!pciehp_debug)
 813                 return;
 814
 815         ctrl_info(ctrl, "Slot Capabilities      : 0x%08x\n", ctrl->slot_cap);
 816         pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &reg16);
 817         ctrl_info(ctrl, "Slot Status            : 0x%04x\n", reg16);
 818         pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &reg16);
 819         ctrl_info(ctrl, "Slot Control           : 0x%04x\n", reg16);
 820 }
 821
 822 #define FLAG(x, y)      (((x) & (y)) ? '+' : '-')
 823
 824 struct controller *pcie_init(struct pcie_device *dev)
 825 {
 826         struct controller *ctrl;
 827         u32 slot_cap, link_cap;
 828         u8 poweron;
 829         struct pci_dev *pdev = dev->port;
 830         struct pci_bus *subordinate = pdev->subordinate;
 831
 832         ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
 833         if (!ctrl)
 834                 return NULL;
 835
 836         ctrl->pcie = dev;
 837         pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
 838
 839         if (pdev->hotplug_user_indicators)
 840                 slot_cap &= ~(PCI_EXP_SLTCAP_AIP | PCI_EXP_SLTCAP_PIP);
 841
 842         /*
 843          * We assume no Thunderbolt controllers support Command Complete events,
 844          * but some controllers falsely claim they do.
 845          */
 846         if (pdev->is_thunderbolt)
 847                 slot_cap |= PCI_EXP_SLTCAP_NCCS;
 848
 849         ctrl->slot_cap = slot_cap;
 850         mutex_init(&ctrl->ctrl_lock);
 851         mutex_init(&ctrl->state_lock);
 852         init_rwsem(&ctrl->reset_lock);
 853         init_waitqueue_head(&ctrl->requester);
 854         init_waitqueue_head(&ctrl->queue);
 855         INIT_DELAYED_WORK(&ctrl->button_work, pciehp_queue_pushbutton_work);
 856         dbg_ctrl(ctrl);
 857
 858         down_read(&pci_bus_sem);
 859         ctrl->state = list_empty(&subordinate->devices) ? OFF_STATE : ON_STATE;
 860         up_read(&pci_bus_sem);
 861
 862         /* Check if Data Link Layer Link Active Reporting is implemented */
 863         pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap);
 864
 865         /* Clear all remaining event bits in Slot Status register. */
 866         pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
 867                 PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
 868                 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_CC |
 869                 PCI_EXP_SLTSTA_DLLSC | PCI_EXP_SLTSTA_PDC);
 870
 871         ctrl_info(ctrl, "Slot #%d AttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c Interlock%c NoCompl%c LLActRep%c%s\n",
 872                 (slot_cap & PCI_EXP_SLTCAP_PSN) >> 19,
 873                 FLAG(slot_cap, PCI_EXP_SLTCAP_ABP),
 874                 FLAG(slot_cap, PCI_EXP_SLTCAP_PCP),
 875                 FLAG(slot_cap, PCI_EXP_SLTCAP_MRLSP),
 876                 FLAG(slot_cap, PCI_EXP_SLTCAP_AIP),
 877                 FLAG(slot_cap, PCI_EXP_SLTCAP_PIP),
 878                 FLAG(slot_cap, PCI_EXP_SLTCAP_HPC),
 879                 FLAG(slot_cap, PCI_EXP_SLTCAP_HPS),
 880                 FLAG(slot_cap, PCI_EXP_SLTCAP_EIP),
 881                 FLAG(slot_cap, PCI_EXP_SLTCAP_NCCS),
 882                 FLAG(link_cap, PCI_EXP_LNKCAP_DLLLARC),
 883                 pdev->broken_cmd_compl ? " (with Cmd Compl erratum)" : "");
 884
 885         /*
 886          * If empty slot's power status is on, turn power off.  The IRQ isn't
 887          * requested yet, so avoid triggering a notification with this command.
 888          */
 889         if (POWER_CTRL(ctrl)) {
 890                 pciehp_get_power_status(ctrl, &poweron);
 891                 if (!pciehp_card_present_or_link_active(ctrl) && poweron) {
 892                         pcie_disable_notification(ctrl);
 893                         pciehp_power_off_slot(ctrl);
 894                 }
 895         }
 896
 897         return ctrl;
 898 }
 899
 900 void pciehp_release_ctrl(struct controller *ctrl)
 901 {
 902         cancel_delayed_work_sync(&ctrl->button_work);
 903         kfree(ctrl);
 904 }
 905
 906 static void quirk_cmd_compl(struct pci_dev *pdev)
 907 {
 908         u32 slot_cap;
 909
 910         if (pci_is_pcie(pdev)) {
 911                 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
 912                 if (slot_cap & PCI_EXP_SLTCAP_HPC &&
 913                     !(slot_cap & PCI_EXP_SLTCAP_NCCS))
 914                         pdev->broken_cmd_compl = 1;
 915         }
 916 }
 917 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
 918                               PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
 919 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x0400,
 920                               PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
 921 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x0401,
 922                               PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);