drivers/rtc/rtc-tegra.c

   1 /*
   2  * An RTC driver for the NVIDIA Tegra 200 series internal RTC.
   3  *
   4  * Copyright (c) 2010, NVIDIA Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along
  17  * with this program; if not, write to the Free Software Foundation, Inc.,
  18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  19  */
  20
  21 #include <linux/clk.h>
  22 #include <linux/delay.h>
  23 #include <linux/init.h>
  24 #include <linux/io.h>
  25 #include <linux/irq.h>
  26 #include <linux/kernel.h>
  27 #include <linux/module.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/pm.h>
  30 #include <linux/rtc.h>
  31 #include <linux/slab.h>
  32
  33 /* set to 1 = busy every eight 32kHz clocks during copy of sec+msec to AHB */
  34 #define TEGRA_RTC_REG_BUSY                      0x004
  35 #define TEGRA_RTC_REG_SECONDS                   0x008
  36 /* when msec is read, the seconds are buffered into shadow seconds. */
  37 #define TEGRA_RTC_REG_SHADOW_SECONDS            0x00c
  38 #define TEGRA_RTC_REG_MILLI_SECONDS             0x010
  39 #define TEGRA_RTC_REG_SECONDS_ALARM0            0x014
  40 #define TEGRA_RTC_REG_SECONDS_ALARM1            0x018
  41 #define TEGRA_RTC_REG_MILLI_SECONDS_ALARM0      0x01c
  42 #define TEGRA_RTC_REG_INTR_MASK                 0x028
  43 /* write 1 bits to clear status bits */
  44 #define TEGRA_RTC_REG_INTR_STATUS               0x02c
  45
  46 /* bits in INTR_MASK */
  47 #define TEGRA_RTC_INTR_MASK_MSEC_CDN_ALARM      (1<<4)
  48 #define TEGRA_RTC_INTR_MASK_SEC_CDN_ALARM       (1<<3)
  49 #define TEGRA_RTC_INTR_MASK_MSEC_ALARM          (1<<2)
  50 #define TEGRA_RTC_INTR_MASK_SEC_ALARM1          (1<<1)
  51 #define TEGRA_RTC_INTR_MASK_SEC_ALARM0          (1<<0)
  52
  53 /* bits in INTR_STATUS */
  54 #define TEGRA_RTC_INTR_STATUS_MSEC_CDN_ALARM    (1<<4)
  55 #define TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM     (1<<3)
  56 #define TEGRA_RTC_INTR_STATUS_MSEC_ALARM        (1<<2)
  57 #define TEGRA_RTC_INTR_STATUS_SEC_ALARM1        (1<<1)
  58 #define TEGRA_RTC_INTR_STATUS_SEC_ALARM0        (1<<0)
  59
  60 struct tegra_rtc_info {
  61         struct platform_device  *pdev;
  62         struct rtc_device       *rtc_dev;
  63         void __iomem            *rtc_base; /* NULL if not initialized. */
  64         struct clk              *clk;
  65         int                     tegra_rtc_irq; /* alarm and periodic irq */
  66         spinlock_t              tegra_rtc_lock;
  67 };
  68
  69 /* RTC hardware is busy when it is updating its values over AHB once
  70  * every eight 32kHz clocks (~250uS).
  71  * outside of these updates the CPU is free to write.
  72  * CPU is always free to read.
  73  */
  74 static inline u32 tegra_rtc_check_busy(struct tegra_rtc_info *info)
  75 {
  76         return readl(info->rtc_base + TEGRA_RTC_REG_BUSY) & 1;
  77 }
  78
  79 /* Wait for hardware to be ready for writing.
  80  * This function tries to maximize the amount of time before the next update.
  81  * It does this by waiting for the RTC to become busy with its periodic update,
  82  * then returning once the RTC first becomes not busy.
  83  * This periodic update (where the seconds and milliseconds are copied to the
  84  * AHB side) occurs every eight 32kHz clocks (~250uS).
  85  * The behavior of this function allows us to make some assumptions without
  86  * introducing a race, because 250uS is plenty of time to read/write a value.
  87  */
  88 static int tegra_rtc_wait_while_busy(struct device *dev)
  89 {
  90         struct tegra_rtc_info *info = dev_get_drvdata(dev);
  91
  92         int retries = 500; /* ~490 us is the worst case, ~250 us is best. */
  93
  94         /* first wait for the RTC to become busy. this is when it
  95          * posts its updated seconds+msec registers to AHB side. */
  96         while (tegra_rtc_check_busy(info)) {
  97                 if (!retries--)
  98                         goto retry_failed;
  99                 udelay(1);
 100         }
 101
 102         /* now we have about 250 us to manipulate registers */
 103         return 0;
 104
 105 retry_failed:
 106         dev_err(dev, "write failed:retry count exceeded.\n");
 107         return -ETIMEDOUT;
 108 }
 109
 110 static int tegra_rtc_read_time(struct device *dev, struct rtc_time *tm)
 111 {
 112         struct tegra_rtc_info *info = dev_get_drvdata(dev);
 113         unsigned long sec, msec;
 114         unsigned long sl_irq_flags;
 115
 116         /* RTC hardware copies seconds to shadow seconds when a read
 117          * of milliseconds occurs. use a lock to keep other threads out. */
 118         spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags);
 119
 120         msec = readl(info->rtc_base + TEGRA_RTC_REG_MILLI_SECONDS);
 121         sec = readl(info->rtc_base + TEGRA_RTC_REG_SHADOW_SECONDS);
 122
 123         spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags);
 124
 125         rtc_time_to_tm(sec, tm);
 126
 127         dev_vdbg(dev, "time read as %lu. %d/%d/%d %d:%02u:%02u\n",
 128                 sec,
 129                 tm->tm_mon + 1,
 130                 tm->tm_mday,
 131                 tm->tm_year + 1900,
 132                 tm->tm_hour,
 133                 tm->tm_min,
 134                 tm->tm_sec
 135         );
 136
 137         return 0;
 138 }
 139
 140 static int tegra_rtc_set_time(struct device *dev, struct rtc_time *tm)
 141 {
 142         struct tegra_rtc_info *info = dev_get_drvdata(dev);
 143         unsigned long sec;
 144         int ret;
 145
 146         /* convert tm to seconds. */
 147         ret = rtc_valid_tm(tm);
 148         if (ret)
 149                 return ret;
 150
 151         rtc_tm_to_time(tm, &sec);
 152
 153         dev_vdbg(dev, "time set to %lu. %d/%d/%d %d:%02u:%02u\n",
 154                 sec,
 155                 tm->tm_mon+1,
 156                 tm->tm_mday,
 157                 tm->tm_year+1900,
 158                 tm->tm_hour,
 159                 tm->tm_min,
 160                 tm->tm_sec
 161         );
 162
 163         /* seconds only written if wait succeeded. */
 164         ret = tegra_rtc_wait_while_busy(dev);
 165         if (!ret)
 166                 writel(sec, info->rtc_base + TEGRA_RTC_REG_SECONDS);
 167
 168         dev_vdbg(dev, "time read back as %d\n",
 169                 readl(info->rtc_base + TEGRA_RTC_REG_SECONDS));
 170
 171         return ret;
 172 }
 173
 174 static int tegra_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
 175 {
 176         struct tegra_rtc_info *info = dev_get_drvdata(dev);
 177         unsigned long sec;
 178         unsigned tmp;
 179
 180         sec = readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0);
 181
 182         if (sec == 0) {
 183                 /* alarm is disabled. */
 184                 alarm->enabled = 0;
 185         } else {
 186                 /* alarm is enabled. */
 187                 alarm->enabled = 1;
 188                 rtc_time_to_tm(sec, &alarm->time);
 189         }
 190
 191         tmp = readl(info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
 192         alarm->pending = (tmp & TEGRA_RTC_INTR_STATUS_SEC_ALARM0) != 0;
 193
 194         return 0;
 195 }
 196
 197 static int tegra_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
 198 {
 199         struct tegra_rtc_info *info = dev_get_drvdata(dev);
 200         unsigned status;
 201         unsigned long sl_irq_flags;
 202
 203         tegra_rtc_wait_while_busy(dev);
 204         spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags);
 205
 206         /* read the original value, and OR in the flag. */
 207         status = readl(info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
 208         if (enabled)
 209                 status |= TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* set it */
 210         else
 211                 status &= ~TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* clear it */
 212
 213         writel(status, info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
 214
 215         spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags);
 216
 217         return 0;
 218 }
 219
 220 static int tegra_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
 221 {
 222         struct tegra_rtc_info *info = dev_get_drvdata(dev);
 223         unsigned long sec;
 224
 225         if (alarm->enabled)
 226                 rtc_tm_to_time(&alarm->time, &sec);
 227         else
 228                 sec = 0;
 229
 230         tegra_rtc_wait_while_busy(dev);
 231         writel(sec, info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0);
 232         dev_vdbg(dev, "alarm read back as %d\n",
 233                 readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0));
 234
 235         /* if successfully written and alarm is enabled ... */
 236         if (sec) {
 237                 tegra_rtc_alarm_irq_enable(dev, 1);
 238
 239                 dev_vdbg(dev, "alarm set as %lu. %d/%d/%d %d:%02u:%02u\n",
 240                         sec,
 241                         alarm->time.tm_mon+1,
 242                         alarm->time.tm_mday,
 243                         alarm->time.tm_year+1900,
 244                         alarm->time.tm_hour,
 245                         alarm->time.tm_min,
 246                         alarm->time.tm_sec);
 247         } else {
 248                 /* disable alarm if 0 or write error. */
 249                 dev_vdbg(dev, "alarm disabled\n");
 250                 tegra_rtc_alarm_irq_enable(dev, 0);
 251         }
 252
 253         return 0;
 254 }
 255
 256 static int tegra_rtc_proc(struct device *dev, struct seq_file *seq)
 257 {
 258         if (!dev || !dev->driver)
 259                 return 0;
 260
 261         seq_printf(seq, "name\t\t: %s\n", dev_name(dev));
 262
 263         return 0;
 264 }
 265
 266 static irqreturn_t tegra_rtc_irq_handler(int irq, void *data)
 267 {
 268         struct device *dev = data;
 269         struct tegra_rtc_info *info = dev_get_drvdata(dev);
 270         unsigned long events = 0;
 271         unsigned status;
 272         unsigned long sl_irq_flags;
 273
 274         status = readl(info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
 275         if (status) {
 276                 /* clear the interrupt masks and status on any irq. */
 277                 tegra_rtc_wait_while_busy(dev);
 278                 spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags);
 279                 writel(0, info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
 280                 writel(status, info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
 281                 spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags);
 282         }
 283
 284         /* check if Alarm */
 285         if ((status & TEGRA_RTC_INTR_STATUS_SEC_ALARM0))
 286                 events |= RTC_IRQF | RTC_AF;
 287
 288         /* check if Periodic */
 289         if ((status & TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM))
 290                 events |= RTC_IRQF | RTC_PF;
 291
 292         rtc_update_irq(info->rtc_dev, 1, events);
 293
 294         return IRQ_HANDLED;
 295 }
 296
 297 static const struct rtc_class_ops tegra_rtc_ops = {
 298         .read_time      = tegra_rtc_read_time,
 299         .set_time       = tegra_rtc_set_time,
 300         .read_alarm     = tegra_rtc_read_alarm,
 301         .set_alarm      = tegra_rtc_set_alarm,
 302         .proc           = tegra_rtc_proc,
 303         .alarm_irq_enable = tegra_rtc_alarm_irq_enable,
 304 };
 305
 306 static const struct of_device_id tegra_rtc_dt_match[] = {
 307         { .compatible = "nvidia,tegra20-rtc", },
 308         {}
 309 };
 310 MODULE_DEVICE_TABLE(of, tegra_rtc_dt_match);
 311
 312 static int __init tegra_rtc_probe(struct platform_device *pdev)
 313 {
 314         struct tegra_rtc_info *info;
 315         struct resource *res;
 316         int ret;
 317
 318         info = devm_kzalloc(&pdev->dev, sizeof(struct tegra_rtc_info),
 319                 GFP_KERNEL);
 320         if (!info)
 321                 return -ENOMEM;
 322
 323         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 324         info->rtc_base = devm_ioremap_resource(&pdev->dev, res);
 325         if (IS_ERR(info->rtc_base))
 326                 return PTR_ERR(info->rtc_base);
 327
 328         info->tegra_rtc_irq = platform_get_irq(pdev, 0);
 329         if (info->tegra_rtc_irq <= 0)
 330                 return -EBUSY;
 331
 332         info->clk = devm_clk_get(&pdev->dev, NULL);
 333         if (IS_ERR(info->clk))
 334                 return PTR_ERR(info->clk);
 335
 336         ret = clk_prepare_enable(info->clk);
 337         if (ret < 0)
 338                 return ret;
 339
 340         /* set context info. */
 341         info->pdev = pdev;
 342         spin_lock_init(&info->tegra_rtc_lock);
 343
 344         platform_set_drvdata(pdev, info);
 345
 346         /* clear out the hardware. */
 347         writel(0, info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0);
 348         writel(0xffffffff, info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
 349         writel(0, info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
 350
 351         device_init_wakeup(&pdev->dev, 1);
 352
 353         info->rtc_dev = devm_rtc_device_register(&pdev->dev,
 354                                 dev_name(&pdev->dev), &tegra_rtc_ops,
 355                                 THIS_MODULE);
 356         if (IS_ERR(info->rtc_dev)) {
 357                 ret = PTR_ERR(info->rtc_dev);
 358                 dev_err(&pdev->dev, "Unable to register device (err=%d).\n",
 359                         ret);
 360                 goto disable_clk;
 361         }
 362
 363         ret = devm_request_irq(&pdev->dev, info->tegra_rtc_irq,
 364                         tegra_rtc_irq_handler, IRQF_TRIGGER_HIGH,
 365                         dev_name(&pdev->dev), &pdev->dev);
 366         if (ret) {
 367                 dev_err(&pdev->dev,
 368                         "Unable to request interrupt for device (err=%d).\n",
 369                         ret);
 370                 goto disable_clk;
 371         }
 372
 373         dev_notice(&pdev->dev, "Tegra internal Real Time Clock\n");
 374
 375         return 0;
 376
 377 disable_clk:
 378         clk_disable_unprepare(info->clk);
 379         return ret;
 380 }
 381
 382 static int tegra_rtc_remove(struct platform_device *pdev)
 383 {
 384         struct tegra_rtc_info *info = platform_get_drvdata(pdev);
 385
 386         clk_disable_unprepare(info->clk);
 387
 388         return 0;
 389 }
 390
 391 #ifdef CONFIG_PM_SLEEP
 392 static int tegra_rtc_suspend(struct device *dev)
 393 {
 394         struct tegra_rtc_info *info = dev_get_drvdata(dev);
 395
 396         tegra_rtc_wait_while_busy(dev);
 397
 398         /* only use ALARM0 as a wake source. */
 399         writel(0xffffffff, info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
 400         writel(TEGRA_RTC_INTR_STATUS_SEC_ALARM0,
 401                 info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
 402
 403         dev_vdbg(dev, "alarm sec = %d\n",
 404                 readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0));
 405
 406         dev_vdbg(dev, "Suspend (device_may_wakeup=%d) irq:%d\n",
 407                 device_may_wakeup(dev), info->tegra_rtc_irq);
 408
 409         /* leave the alarms on as a wake source. */
 410         if (device_may_wakeup(dev))
 411                 enable_irq_wake(info->tegra_rtc_irq);
 412
 413         return 0;
 414 }
 415
 416 static int tegra_rtc_resume(struct device *dev)
 417 {
 418         struct tegra_rtc_info *info = dev_get_drvdata(dev);
 419
 420         dev_vdbg(dev, "Resume (device_may_wakeup=%d)\n",
 421                 device_may_wakeup(dev));
 422         /* alarms were left on as a wake source, turn them off. */
 423         if (device_may_wakeup(dev))
 424                 disable_irq_wake(info->tegra_rtc_irq);
 425
 426         return 0;
 427 }
 428 #endif
 429
 430 static SIMPLE_DEV_PM_OPS(tegra_rtc_pm_ops, tegra_rtc_suspend, tegra_rtc_resume);
 431
 432 static void tegra_rtc_shutdown(struct platform_device *pdev)
 433 {
 434         dev_vdbg(&pdev->dev, "disabling interrupts.\n");
 435         tegra_rtc_alarm_irq_enable(&pdev->dev, 0);
 436 }
 437
 438 MODULE_ALIAS("platform:tegra_rtc");
 439 static struct platform_driver tegra_rtc_driver = {
 440         .remove         = tegra_rtc_remove,
 441         .shutdown       = tegra_rtc_shutdown,
 442         .driver         = {
 443                 .name   = "tegra_rtc",
 444                 .of_match_table = tegra_rtc_dt_match,
 445                 .pm     = &tegra_rtc_pm_ops,
 446         },
 447 };
 448
 449 module_platform_driver_probe(tegra_rtc_driver, tegra_rtc_probe);
 450
 451 MODULE_AUTHOR("Jon Mayo <jmayo@nvidia.com>");
 452 MODULE_DESCRIPTION("driver for Tegra internal RTC");
 453 MODULE_LICENSE("GPL");