arch/arm64/include/asm/cache.h

   1 /*
   2  * Copyright (C) 2012 ARM Ltd.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16 #ifndef __ASM_CACHE_H
  17 #define __ASM_CACHE_H
  18
  19 #include <asm/cputype.h>
  20
  21 #define CTR_L1IP_SHIFT          14
  22 #define CTR_L1IP_MASK           3
  23 #define CTR_DMINLINE_SHIFT      16
  24 #define CTR_IMINLINE_SHIFT      0
  25 #define CTR_ERG_SHIFT           20
  26 #define CTR_CWG_SHIFT           24
  27 #define CTR_CWG_MASK            15
  28 #define CTR_IDC_SHIFT           28
  29 #define CTR_DIC_SHIFT           29
  30
  31 #define CTR_CACHE_MINLINE_MASK  \
  32         (0xf << CTR_DMINLINE_SHIFT | 0xf << CTR_IMINLINE_SHIFT)
  33
  34 #define CTR_L1IP(ctr)           (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK)
  35
  36 #define ICACHE_POLICY_VPIPT     0
  37 #define ICACHE_POLICY_VIPT      2
  38 #define ICACHE_POLICY_PIPT      3
  39
  40 #define L1_CACHE_SHIFT          (6)
  41 #define L1_CACHE_BYTES          (1 << L1_CACHE_SHIFT)
  42
  43 /*
  44  * Memory returned by kmalloc() may be used for DMA, so we must make
  45  * sure that all such allocations are cache aligned. Otherwise,
  46  * unrelated code may cause parts of the buffer to be read into the
  47  * cache before the transfer is done, causing old data to be seen by
  48  * the CPU.
  49  */
  50 #define ARCH_DMA_MINALIGN       (128)
  51
  52 #ifndef __ASSEMBLY__
  53
  54 #include <linux/bitops.h>
  55
  56 #define ICACHEF_ALIASING        0
  57 #define ICACHEF_VPIPT           1
  58 extern unsigned long __icache_flags;
  59
  60 /*
  61  * Whilst the D-side always behaves as PIPT on AArch64, aliasing is
  62  * permitted in the I-cache.
  63  */
  64 static inline int icache_is_aliasing(void)
  65 {
  66         return test_bit(ICACHEF_ALIASING, &__icache_flags);
  67 }
  68
  69 static inline int icache_is_vpipt(void)
  70 {
  71         return test_bit(ICACHEF_VPIPT, &__icache_flags);
  72 }
  73
  74 static inline u32 cache_type_cwg(void)
  75 {
  76         return (read_cpuid_cachetype() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;
  77 }
  78
  79 #define __read_mostly __attribute__((__section__(".data..read_mostly")))
  80
  81 static inline int cache_line_size(void)
  82 {
  83         u32 cwg = cache_type_cwg();
  84         return cwg ? 4 << cwg : ARCH_DMA_MINALIGN;
  85 }
  86
  87 #endif  /* __ASSEMBLY__ */
  88
  89 #endif