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Linux 4.18.10
[linux/fpc-iii.git] / drivers / phy / mediatek / phy-mtk-tphy.c
blob38c281b5abbb0dfe339cf04929ee06fce6a5688e
1 /*
2 * Copyright (c) 2015 MediaTek Inc.
3 * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 */
15
16 #include <dt-bindings/phy/phy.h>
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/io.h>
20 #include <linux/iopoll.h>
21 #include <linux/module.h>
22 #include <linux/of_address.h>
23 #include <linux/of_device.h>
24 #include <linux/phy/phy.h>
25 #include <linux/platform_device.h>
26
27 /* version V1 sub-banks offset base address */
28 /* banks shared by multiple phys */
29 #define SSUSB_SIFSLV_V1_SPLLC 0x000 /* shared by u3 phys */
30 #define SSUSB_SIFSLV_V1_U2FREQ 0x100 /* shared by u2 phys */
31 #define SSUSB_SIFSLV_V1_CHIP 0x300 /* shared by u3 phys */
32 /* u2 phy bank */
33 #define SSUSB_SIFSLV_V1_U2PHY_COM 0x000
34 /* u3/pcie/sata phy banks */
35 #define SSUSB_SIFSLV_V1_U3PHYD 0x000
36 #define SSUSB_SIFSLV_V1_U3PHYA 0x200
37
38 /* version V2 sub-banks offset base address */
39 /* u2 phy banks */
40 #define SSUSB_SIFSLV_V2_MISC 0x000
41 #define SSUSB_SIFSLV_V2_U2FREQ 0x100
42 #define SSUSB_SIFSLV_V2_U2PHY_COM 0x300
43 /* u3/pcie/sata phy banks */
44 #define SSUSB_SIFSLV_V2_SPLLC 0x000
45 #define SSUSB_SIFSLV_V2_CHIP 0x100
46 #define SSUSB_SIFSLV_V2_U3PHYD 0x200
47 #define SSUSB_SIFSLV_V2_U3PHYA 0x400
48
49 #define U3P_USBPHYACR0 0x000
50 #define PA0_RG_U2PLL_FORCE_ON BIT(15)
51 #define PA0_RG_USB20_INTR_EN BIT(5)
52
53 #define U3P_USBPHYACR2 0x008
54 #define PA2_RG_SIF_U2PLL_FORCE_EN BIT(18)
55
56 #define U3P_USBPHYACR5 0x014
57 #define PA5_RG_U2_HSTX_SRCAL_EN BIT(15)
58 #define PA5_RG_U2_HSTX_SRCTRL GENMASK(14, 12)
59 #define PA5_RG_U2_HSTX_SRCTRL_VAL(x) ((0x7 & (x)) << 12)
60 #define PA5_RG_U2_HS_100U_U3_EN BIT(11)
61
62 #define U3P_USBPHYACR6 0x018
63 #define PA6_RG_U2_BC11_SW_EN BIT(23)
64 #define PA6_RG_U2_OTG_VBUSCMP_EN BIT(20)
65 #define PA6_RG_U2_SQTH GENMASK(3, 0)
66 #define PA6_RG_U2_SQTH_VAL(x) (0xf & (x))
67
68 #define U3P_U2PHYACR4 0x020
69 #define P2C_RG_USB20_GPIO_CTL BIT(9)
70 #define P2C_USB20_GPIO_MODE BIT(8)
71 #define P2C_U2_GPIO_CTR_MSK (P2C_RG_USB20_GPIO_CTL | P2C_USB20_GPIO_MODE)
72
73 #define U3D_U2PHYDCR0 0x060
74 #define P2C_RG_SIF_U2PLL_FORCE_ON BIT(24)
75
76 #define U3P_U2PHYDTM0 0x068
77 #define P2C_FORCE_UART_EN BIT(26)
78 #define P2C_FORCE_DATAIN BIT(23)
79 #define P2C_FORCE_DM_PULLDOWN BIT(21)
80 #define P2C_FORCE_DP_PULLDOWN BIT(20)
81 #define P2C_FORCE_XCVRSEL BIT(19)
82 #define P2C_FORCE_SUSPENDM BIT(18)
83 #define P2C_FORCE_TERMSEL BIT(17)
84 #define P2C_RG_DATAIN GENMASK(13, 10)
85 #define P2C_RG_DATAIN_VAL(x) ((0xf & (x)) << 10)
86 #define P2C_RG_DMPULLDOWN BIT(7)
87 #define P2C_RG_DPPULLDOWN BIT(6)
88 #define P2C_RG_XCVRSEL GENMASK(5, 4)
89 #define P2C_RG_XCVRSEL_VAL(x) ((0x3 & (x)) << 4)
90 #define P2C_RG_SUSPENDM BIT(3)
91 #define P2C_RG_TERMSEL BIT(2)
92 #define P2C_DTM0_PART_MASK \
93 (P2C_FORCE_DATAIN | P2C_FORCE_DM_PULLDOWN | \
94 P2C_FORCE_DP_PULLDOWN | P2C_FORCE_XCVRSEL | \
95 P2C_FORCE_TERMSEL | P2C_RG_DMPULLDOWN | \
96 P2C_RG_DPPULLDOWN | P2C_RG_TERMSEL)
97
98 #define U3P_U2PHYDTM1 0x06C
99 #define P2C_RG_UART_EN BIT(16)
100 #define P2C_FORCE_IDDIG BIT(9)
101 #define P2C_RG_VBUSVALID BIT(5)
102 #define P2C_RG_SESSEND BIT(4)
103 #define P2C_RG_AVALID BIT(2)
104 #define P2C_RG_IDDIG BIT(1)
105
106 #define U3P_U3_CHIP_GPIO_CTLD 0x0c
107 #define P3C_REG_IP_SW_RST BIT(31)
108 #define P3C_MCU_BUS_CK_GATE_EN BIT(30)
109 #define P3C_FORCE_IP_SW_RST BIT(29)
110
111 #define U3P_U3_CHIP_GPIO_CTLE 0x10
112 #define P3C_RG_SWRST_U3_PHYD BIT(25)
113 #define P3C_RG_SWRST_U3_PHYD_FORCE_EN BIT(24)
114
115 #define U3P_U3_PHYA_REG0 0x000
116 #define P3A_RG_CLKDRV_OFF GENMASK(3, 2)
117 #define P3A_RG_CLKDRV_OFF_VAL(x) ((0x3 & (x)) << 2)
118
119 #define U3P_U3_PHYA_REG1 0x004
120 #define P3A_RG_CLKDRV_AMP GENMASK(31, 29)
121 #define P3A_RG_CLKDRV_AMP_VAL(x) ((0x7 & (x)) << 29)
122
123 #define U3P_U3_PHYA_REG6 0x018
124 #define P3A_RG_TX_EIDLE_CM GENMASK(31, 28)
125 #define P3A_RG_TX_EIDLE_CM_VAL(x) ((0xf & (x)) << 28)
126
127 #define U3P_U3_PHYA_REG9 0x024
128 #define P3A_RG_RX_DAC_MUX GENMASK(5, 1)
129 #define P3A_RG_RX_DAC_MUX_VAL(x) ((0x1f & (x)) << 1)
130
131 #define U3P_U3_PHYA_DA_REG0 0x100
132 #define P3A_RG_XTAL_EXT_PE2H GENMASK(17, 16)
133 #define P3A_RG_XTAL_EXT_PE2H_VAL(x) ((0x3 & (x)) << 16)
134 #define P3A_RG_XTAL_EXT_PE1H GENMASK(13, 12)
135 #define P3A_RG_XTAL_EXT_PE1H_VAL(x) ((0x3 & (x)) << 12)
136 #define P3A_RG_XTAL_EXT_EN_U3 GENMASK(11, 10)
137 #define P3A_RG_XTAL_EXT_EN_U3_VAL(x) ((0x3 & (x)) << 10)
138
139 #define U3P_U3_PHYA_DA_REG4 0x108
140 #define P3A_RG_PLL_DIVEN_PE2H GENMASK(21, 19)
141 #define P3A_RG_PLL_BC_PE2H GENMASK(7, 6)
142 #define P3A_RG_PLL_BC_PE2H_VAL(x) ((0x3 & (x)) << 6)
143
144 #define U3P_U3_PHYA_DA_REG5 0x10c
145 #define P3A_RG_PLL_BR_PE2H GENMASK(29, 28)
146 #define P3A_RG_PLL_BR_PE2H_VAL(x) ((0x3 & (x)) << 28)
147 #define P3A_RG_PLL_IC_PE2H GENMASK(15, 12)
148 #define P3A_RG_PLL_IC_PE2H_VAL(x) ((0xf & (x)) << 12)
149
150 #define U3P_U3_PHYA_DA_REG6 0x110
151 #define P3A_RG_PLL_IR_PE2H GENMASK(19, 16)
152 #define P3A_RG_PLL_IR_PE2H_VAL(x) ((0xf & (x)) << 16)
153
154 #define U3P_U3_PHYA_DA_REG7 0x114
155 #define P3A_RG_PLL_BP_PE2H GENMASK(19, 16)
156 #define P3A_RG_PLL_BP_PE2H_VAL(x) ((0xf & (x)) << 16)
157
158 #define U3P_U3_PHYA_DA_REG20 0x13c
159 #define P3A_RG_PLL_DELTA1_PE2H GENMASK(31, 16)
160 #define P3A_RG_PLL_DELTA1_PE2H_VAL(x) ((0xffff & (x)) << 16)
161
162 #define U3P_U3_PHYA_DA_REG25 0x148
163 #define P3A_RG_PLL_DELTA_PE2H GENMASK(15, 0)
164 #define P3A_RG_PLL_DELTA_PE2H_VAL(x) (0xffff & (x))
165
166 #define U3P_U3_PHYD_LFPS1 0x00c
167 #define P3D_RG_FWAKE_TH GENMASK(21, 16)
168 #define P3D_RG_FWAKE_TH_VAL(x) ((0x3f & (x)) << 16)
169
170 #define U3P_U3_PHYD_CDR1 0x05c
171 #define P3D_RG_CDR_BIR_LTD1 GENMASK(28, 24)
172 #define P3D_RG_CDR_BIR_LTD1_VAL(x) ((0x1f & (x)) << 24)
173 #define P3D_RG_CDR_BIR_LTD0 GENMASK(12, 8)
174 #define P3D_RG_CDR_BIR_LTD0_VAL(x) ((0x1f & (x)) << 8)
175
176 #define U3P_U3_PHYD_RXDET1 0x128
177 #define P3D_RG_RXDET_STB2_SET GENMASK(17, 9)
178 #define P3D_RG_RXDET_STB2_SET_VAL(x) ((0x1ff & (x)) << 9)
179
180 #define U3P_U3_PHYD_RXDET2 0x12c
181 #define P3D_RG_RXDET_STB2_SET_P3 GENMASK(8, 0)
182 #define P3D_RG_RXDET_STB2_SET_P3_VAL(x) (0x1ff & (x))
183
184 #define U3P_SPLLC_XTALCTL3 0x018
185 #define XC3_RG_U3_XTAL_RX_PWD BIT(9)
186 #define XC3_RG_U3_FRC_XTAL_RX_PWD BIT(8)
187
188 #define U3P_U2FREQ_FMCR0 0x00
189 #define P2F_RG_MONCLK_SEL GENMASK(27, 26)
190 #define P2F_RG_MONCLK_SEL_VAL(x) ((0x3 & (x)) << 26)
191 #define P2F_RG_FREQDET_EN BIT(24)
192 #define P2F_RG_CYCLECNT GENMASK(23, 0)
193 #define P2F_RG_CYCLECNT_VAL(x) ((P2F_RG_CYCLECNT) & (x))
194
195 #define U3P_U2FREQ_VALUE 0x0c
196
197 #define U3P_U2FREQ_FMMONR1 0x10
198 #define P2F_USB_FM_VALID BIT(0)
199 #define P2F_RG_FRCK_EN BIT(8)
200
201 #define U3P_REF_CLK 26 /* MHZ */
202 #define U3P_SLEW_RATE_COEF 28
203 #define U3P_SR_COEF_DIVISOR 1000
204 #define U3P_FM_DET_CYCLE_CNT 1024
205
206 /* SATA register setting */
207 #define PHYD_CTRL_SIGNAL_MODE4 0x1c
208 /* CDR Charge Pump P-path current adjustment */
209 #define RG_CDR_BICLTD1_GEN1_MSK GENMASK(23, 20)
210 #define RG_CDR_BICLTD1_GEN1_VAL(x) ((0xf & (x)) << 20)
211 #define RG_CDR_BICLTD0_GEN1_MSK GENMASK(11, 8)
212 #define RG_CDR_BICLTD0_GEN1_VAL(x) ((0xf & (x)) << 8)
213
214 #define PHYD_DESIGN_OPTION2 0x24
215 /* Symbol lock count selection */
216 #define RG_LOCK_CNT_SEL_MSK GENMASK(5, 4)
217 #define RG_LOCK_CNT_SEL_VAL(x) ((0x3 & (x)) << 4)
218
219 #define PHYD_DESIGN_OPTION9 0x40
220 /* COMWAK GAP width window */
221 #define RG_TG_MAX_MSK GENMASK(20, 16)
222 #define RG_TG_MAX_VAL(x) ((0x1f & (x)) << 16)
223 /* COMINIT GAP width window */
224 #define RG_T2_MAX_MSK GENMASK(13, 8)
225 #define RG_T2_MAX_VAL(x) ((0x3f & (x)) << 8)
226 /* COMWAK GAP width window */
227 #define RG_TG_MIN_MSK GENMASK(7, 5)
228 #define RG_TG_MIN_VAL(x) ((0x7 & (x)) << 5)
229 /* COMINIT GAP width window */
230 #define RG_T2_MIN_MSK GENMASK(4, 0)
231 #define RG_T2_MIN_VAL(x) (0x1f & (x))
232
233 #define ANA_RG_CTRL_SIGNAL1 0x4c
234 /* TX driver tail current control for 0dB de-empahsis mdoe for Gen1 speed */
235 #define RG_IDRV_0DB_GEN1_MSK GENMASK(13, 8)
236 #define RG_IDRV_0DB_GEN1_VAL(x) ((0x3f & (x)) << 8)
237
238 #define ANA_RG_CTRL_SIGNAL4 0x58
239 #define RG_CDR_BICLTR_GEN1_MSK GENMASK(23, 20)
240 #define RG_CDR_BICLTR_GEN1_VAL(x) ((0xf & (x)) << 20)
241 /* Loop filter R1 resistance adjustment for Gen1 speed */
242 #define RG_CDR_BR_GEN2_MSK GENMASK(10, 8)
243 #define RG_CDR_BR_GEN2_VAL(x) ((0x7 & (x)) << 8)
244
245 #define ANA_RG_CTRL_SIGNAL6 0x60
246 /* I-path capacitance adjustment for Gen1 */
247 #define RG_CDR_BC_GEN1_MSK GENMASK(28, 24)
248 #define RG_CDR_BC_GEN1_VAL(x) ((0x1f & (x)) << 24)
249 #define RG_CDR_BIRLTR_GEN1_MSK GENMASK(4, 0)
250 #define RG_CDR_BIRLTR_GEN1_VAL(x) (0x1f & (x))
251
252 #define ANA_EQ_EYE_CTRL_SIGNAL1 0x6c
253 /* RX Gen1 LEQ tuning step */
254 #define RG_EQ_DLEQ_LFI_GEN1_MSK GENMASK(11, 8)
255 #define RG_EQ_DLEQ_LFI_GEN1_VAL(x) ((0xf & (x)) << 8)
256
257 #define ANA_EQ_EYE_CTRL_SIGNAL4 0xd8
258 #define RG_CDR_BIRLTD0_GEN1_MSK GENMASK(20, 16)
259 #define RG_CDR_BIRLTD0_GEN1_VAL(x) ((0x1f & (x)) << 16)
260
261 #define ANA_EQ_EYE_CTRL_SIGNAL5 0xdc
262 #define RG_CDR_BIRLTD0_GEN3_MSK GENMASK(4, 0)
263 #define RG_CDR_BIRLTD0_GEN3_VAL(x) (0x1f & (x))
264
265 enum mtk_phy_version {
266 MTK_PHY_V1 = 1,
267 MTK_PHY_V2,
268 };
269
270 struct mtk_phy_pdata {
271 /* avoid RX sensitivity level degradation only for mt8173 */
272 bool avoid_rx_sen_degradation;
273 enum mtk_phy_version version;
274 };
275
276 struct u2phy_banks {
277 void __iomem *misc;
278 void __iomem *fmreg;
279 void __iomem *com;
280 };
281
282 struct u3phy_banks {
283 void __iomem *spllc;
284 void __iomem *chip;
285 void __iomem *phyd; /* include u3phyd_bank2 */
286 void __iomem *phya; /* include u3phya_da */
287 };
288
289 struct mtk_phy_instance {
290 struct phy *phy;
291 void __iomem *port_base;
292 union {
293 struct u2phy_banks u2_banks;
294 struct u3phy_banks u3_banks;
295 };
296 struct clk *ref_clk; /* reference clock of anolog phy */
297 u32 index;
298 u8 type;
299 };
300
301 struct mtk_tphy {
302 struct device *dev;
303 void __iomem *sif_base; /* only shared sif */
304 /* deprecated, use @ref_clk instead in phy instance */
305 struct clk *u3phya_ref; /* reference clock of usb3 anolog phy */
306 const struct mtk_phy_pdata *pdata;
307 struct mtk_phy_instance **phys;
308 int nphys;
309 int src_ref_clk; /* MHZ, reference clock for slew rate calibrate */
310 int src_coef; /* coefficient for slew rate calibrate */
311 };
312
313 static void hs_slew_rate_calibrate(struct mtk_tphy *tphy,
314 struct mtk_phy_instance *instance)
315 {
316 struct u2phy_banks *u2_banks = &instance->u2_banks;
317 void __iomem *fmreg = u2_banks->fmreg;
318 void __iomem *com = u2_banks->com;
319 int calibration_val;
320 int fm_out;
321 u32 tmp;
322
323 /* enable USB ring oscillator */
324 tmp = readl(com + U3P_USBPHYACR5);
325 tmp |= PA5_RG_U2_HSTX_SRCAL_EN;
326 writel(tmp, com + U3P_USBPHYACR5);
327 udelay(1);
328
329 /*enable free run clock */
330 tmp = readl(fmreg + U3P_U2FREQ_FMMONR1);
331 tmp |= P2F_RG_FRCK_EN;
332 writel(tmp, fmreg + U3P_U2FREQ_FMMONR1);
333
334 /* set cycle count as 1024, and select u2 channel */
335 tmp = readl(fmreg + U3P_U2FREQ_FMCR0);
336 tmp &= ~(P2F_RG_CYCLECNT | P2F_RG_MONCLK_SEL);
337 tmp |= P2F_RG_CYCLECNT_VAL(U3P_FM_DET_CYCLE_CNT);
338 if (tphy->pdata->version == MTK_PHY_V1)
339 tmp |= P2F_RG_MONCLK_SEL_VAL(instance->index >> 1);
340
341 writel(tmp, fmreg + U3P_U2FREQ_FMCR0);
342
343 /* enable frequency meter */
344 tmp = readl(fmreg + U3P_U2FREQ_FMCR0);
345 tmp |= P2F_RG_FREQDET_EN;
346 writel(tmp, fmreg + U3P_U2FREQ_FMCR0);
347
348 /* ignore return value */
349 readl_poll_timeout(fmreg + U3P_U2FREQ_FMMONR1, tmp,
350 (tmp & P2F_USB_FM_VALID), 10, 200);
351
352 fm_out = readl(fmreg + U3P_U2FREQ_VALUE);
353
354 /* disable frequency meter */
355 tmp = readl(fmreg + U3P_U2FREQ_FMCR0);
356 tmp &= ~P2F_RG_FREQDET_EN;
357 writel(tmp, fmreg + U3P_U2FREQ_FMCR0);
358
359 /*disable free run clock */
360 tmp = readl(fmreg + U3P_U2FREQ_FMMONR1);
361 tmp &= ~P2F_RG_FRCK_EN;
362 writel(tmp, fmreg + U3P_U2FREQ_FMMONR1);
363
364 if (fm_out) {
365 /* ( 1024 / FM_OUT ) x reference clock frequency x coef */
366 tmp = tphy->src_ref_clk * tphy->src_coef;
367 tmp = (tmp * U3P_FM_DET_CYCLE_CNT) / fm_out;
368 calibration_val = DIV_ROUND_CLOSEST(tmp, U3P_SR_COEF_DIVISOR);
369 } else {
370 /* if FM detection fail, set default value */
371 calibration_val = 4;
372 }
373 dev_dbg(tphy->dev, "phy:%d, fm_out:%d, calib:%d (clk:%d, coef:%d)\n",
374 instance->index, fm_out, calibration_val,
375 tphy->src_ref_clk, tphy->src_coef);
376
377 /* set HS slew rate */
378 tmp = readl(com + U3P_USBPHYACR5);
379 tmp &= ~PA5_RG_U2_HSTX_SRCTRL;
380 tmp |= PA5_RG_U2_HSTX_SRCTRL_VAL(calibration_val);
381 writel(tmp, com + U3P_USBPHYACR5);
382
383 /* disable USB ring oscillator */
384 tmp = readl(com + U3P_USBPHYACR5);
385 tmp &= ~PA5_RG_U2_HSTX_SRCAL_EN;
386 writel(tmp, com + U3P_USBPHYACR5);
387 }
388
389 static void u3_phy_instance_init(struct mtk_tphy *tphy,
390 struct mtk_phy_instance *instance)
391 {
392 struct u3phy_banks *u3_banks = &instance->u3_banks;
393 u32 tmp;
394
395 /* gating PCIe Analog XTAL clock */
396 tmp = readl(u3_banks->spllc + U3P_SPLLC_XTALCTL3);
397 tmp |= XC3_RG_U3_XTAL_RX_PWD | XC3_RG_U3_FRC_XTAL_RX_PWD;
398 writel(tmp, u3_banks->spllc + U3P_SPLLC_XTALCTL3);
399
400 /* gating XSQ */
401 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG0);
402 tmp &= ~P3A_RG_XTAL_EXT_EN_U3;
403 tmp |= P3A_RG_XTAL_EXT_EN_U3_VAL(2);
404 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG0);
405
406 tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG9);
407 tmp &= ~P3A_RG_RX_DAC_MUX;
408 tmp |= P3A_RG_RX_DAC_MUX_VAL(4);
409 writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG9);
410
411 tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG6);
412 tmp &= ~P3A_RG_TX_EIDLE_CM;
413 tmp |= P3A_RG_TX_EIDLE_CM_VAL(0xe);
414 writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG6);
415
416 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_CDR1);
417 tmp &= ~(P3D_RG_CDR_BIR_LTD0 | P3D_RG_CDR_BIR_LTD1);
418 tmp |= P3D_RG_CDR_BIR_LTD0_VAL(0xc) | P3D_RG_CDR_BIR_LTD1_VAL(0x3);
419 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_CDR1);
420
421 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_LFPS1);
422 tmp &= ~P3D_RG_FWAKE_TH;
423 tmp |= P3D_RG_FWAKE_TH_VAL(0x34);
424 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_LFPS1);
425
426 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET1);
427 tmp &= ~P3D_RG_RXDET_STB2_SET;
428 tmp |= P3D_RG_RXDET_STB2_SET_VAL(0x10);
429 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET1);
430
431 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET2);
432 tmp &= ~P3D_RG_RXDET_STB2_SET_P3;
433 tmp |= P3D_RG_RXDET_STB2_SET_P3_VAL(0x10);
434 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET2);
435
436 dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
437 }
438
439 static void u2_phy_instance_init(struct mtk_tphy *tphy,
440 struct mtk_phy_instance *instance)
441 {
442 struct u2phy_banks *u2_banks = &instance->u2_banks;
443 void __iomem *com = u2_banks->com;
444 u32 index = instance->index;
445 u32 tmp;
446
447 /* switch to USB function, and enable usb pll */
448 tmp = readl(com + U3P_U2PHYDTM0);
449 tmp &= ~(P2C_FORCE_UART_EN | P2C_FORCE_SUSPENDM);
450 tmp |= P2C_RG_XCVRSEL_VAL(1) | P2C_RG_DATAIN_VAL(0);
451 writel(tmp, com + U3P_U2PHYDTM0);
452
453 tmp = readl(com + U3P_U2PHYDTM1);
454 tmp &= ~P2C_RG_UART_EN;
455 writel(tmp, com + U3P_U2PHYDTM1);
456
457 tmp = readl(com + U3P_USBPHYACR0);
458 tmp |= PA0_RG_USB20_INTR_EN;
459 writel(tmp, com + U3P_USBPHYACR0);
460
461 /* disable switch 100uA current to SSUSB */
462 tmp = readl(com + U3P_USBPHYACR5);
463 tmp &= ~PA5_RG_U2_HS_100U_U3_EN;
464 writel(tmp, com + U3P_USBPHYACR5);
465
466 if (!index) {
467 tmp = readl(com + U3P_U2PHYACR4);
468 tmp &= ~P2C_U2_GPIO_CTR_MSK;
469 writel(tmp, com + U3P_U2PHYACR4);
470 }
471
472 if (tphy->pdata->avoid_rx_sen_degradation) {
473 if (!index) {
474 tmp = readl(com + U3P_USBPHYACR2);
475 tmp |= PA2_RG_SIF_U2PLL_FORCE_EN;
476 writel(tmp, com + U3P_USBPHYACR2);
477
478 tmp = readl(com + U3D_U2PHYDCR0);
479 tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON;
480 writel(tmp, com + U3D_U2PHYDCR0);
481 } else {
482 tmp = readl(com + U3D_U2PHYDCR0);
483 tmp |= P2C_RG_SIF_U2PLL_FORCE_ON;
484 writel(tmp, com + U3D_U2PHYDCR0);
485
486 tmp = readl(com + U3P_U2PHYDTM0);
487 tmp |= P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM;
488 writel(tmp, com + U3P_U2PHYDTM0);
489 }
490 }
491
492 tmp = readl(com + U3P_USBPHYACR6);
493 tmp &= ~PA6_RG_U2_BC11_SW_EN; /* DP/DM BC1.1 path Disable */
494 tmp &= ~PA6_RG_U2_SQTH;
495 tmp |= PA6_RG_U2_SQTH_VAL(2);
496 writel(tmp, com + U3P_USBPHYACR6);
497
498 dev_dbg(tphy->dev, "%s(%d)\n", __func__, index);
499 }
500
501 static void u2_phy_instance_power_on(struct mtk_tphy *tphy,
502 struct mtk_phy_instance *instance)
503 {
504 struct u2phy_banks *u2_banks = &instance->u2_banks;
505 void __iomem *com = u2_banks->com;
506 u32 index = instance->index;
507 u32 tmp;
508
509 tmp = readl(com + U3P_U2PHYDTM0);
510 tmp &= ~(P2C_RG_XCVRSEL | P2C_RG_DATAIN | P2C_DTM0_PART_MASK);
511 writel(tmp, com + U3P_U2PHYDTM0);
512
513 /* OTG Enable */
514 tmp = readl(com + U3P_USBPHYACR6);
515 tmp |= PA6_RG_U2_OTG_VBUSCMP_EN;
516 writel(tmp, com + U3P_USBPHYACR6);
517
518 tmp = readl(com + U3P_U2PHYDTM1);
519 tmp |= P2C_RG_VBUSVALID | P2C_RG_AVALID;
520 tmp &= ~P2C_RG_SESSEND;
521 writel(tmp, com + U3P_U2PHYDTM1);
522
523 if (tphy->pdata->avoid_rx_sen_degradation && index) {
524 tmp = readl(com + U3D_U2PHYDCR0);
525 tmp |= P2C_RG_SIF_U2PLL_FORCE_ON;
526 writel(tmp, com + U3D_U2PHYDCR0);
527
528 tmp = readl(com + U3P_U2PHYDTM0);
529 tmp |= P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM;
530 writel(tmp, com + U3P_U2PHYDTM0);
531 }
532 dev_dbg(tphy->dev, "%s(%d)\n", __func__, index);
533 }
534
535 static void u2_phy_instance_power_off(struct mtk_tphy *tphy,
536 struct mtk_phy_instance *instance)
537 {
538 struct u2phy_banks *u2_banks = &instance->u2_banks;
539 void __iomem *com = u2_banks->com;
540 u32 index = instance->index;
541 u32 tmp;
542
543 tmp = readl(com + U3P_U2PHYDTM0);
544 tmp &= ~(P2C_RG_XCVRSEL | P2C_RG_DATAIN);
545 writel(tmp, com + U3P_U2PHYDTM0);
546
547 /* OTG Disable */
548 tmp = readl(com + U3P_USBPHYACR6);
549 tmp &= ~PA6_RG_U2_OTG_VBUSCMP_EN;
550 writel(tmp, com + U3P_USBPHYACR6);
551
552 tmp = readl(com + U3P_U2PHYDTM1);
553 tmp &= ~(P2C_RG_VBUSVALID | P2C_RG_AVALID);
554 tmp |= P2C_RG_SESSEND;
555 writel(tmp, com + U3P_U2PHYDTM1);
556
557 if (tphy->pdata->avoid_rx_sen_degradation && index) {
558 tmp = readl(com + U3P_U2PHYDTM0);
559 tmp &= ~(P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM);
560 writel(tmp, com + U3P_U2PHYDTM0);
561
562 tmp = readl(com + U3D_U2PHYDCR0);
563 tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON;
564 writel(tmp, com + U3D_U2PHYDCR0);
565 }
566
567 dev_dbg(tphy->dev, "%s(%d)\n", __func__, index);
568 }
569
570 static void u2_phy_instance_exit(struct mtk_tphy *tphy,
571 struct mtk_phy_instance *instance)
572 {
573 struct u2phy_banks *u2_banks = &instance->u2_banks;
574 void __iomem *com = u2_banks->com;
575 u32 index = instance->index;
576 u32 tmp;
577
578 if (tphy->pdata->avoid_rx_sen_degradation && index) {
579 tmp = readl(com + U3D_U2PHYDCR0);
580 tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON;
581 writel(tmp, com + U3D_U2PHYDCR0);
582
583 tmp = readl(com + U3P_U2PHYDTM0);
584 tmp &= ~P2C_FORCE_SUSPENDM;
585 writel(tmp, com + U3P_U2PHYDTM0);
586 }
587 }
588
589 static void u2_phy_instance_set_mode(struct mtk_tphy *tphy,
590 struct mtk_phy_instance *instance,
591 enum phy_mode mode)
592 {
593 struct u2phy_banks *u2_banks = &instance->u2_banks;
594 u32 tmp;
595
596 tmp = readl(u2_banks->com + U3P_U2PHYDTM1);
597 switch (mode) {
598 case PHY_MODE_USB_DEVICE:
599 tmp |= P2C_FORCE_IDDIG | P2C_RG_IDDIG;
600 break;
601 case PHY_MODE_USB_HOST:
602 tmp |= P2C_FORCE_IDDIG;
603 tmp &= ~P2C_RG_IDDIG;
604 break;
605 case PHY_MODE_USB_OTG:
606 tmp &= ~(P2C_FORCE_IDDIG | P2C_RG_IDDIG);
607 break;
608 default:
609 return;
610 }
611 writel(tmp, u2_banks->com + U3P_U2PHYDTM1);
612 }
613
614 static void pcie_phy_instance_init(struct mtk_tphy *tphy,
615 struct mtk_phy_instance *instance)
616 {
617 struct u3phy_banks *u3_banks = &instance->u3_banks;
618 u32 tmp;
619
620 if (tphy->pdata->version != MTK_PHY_V1)
621 return;
622
623 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG0);
624 tmp &= ~(P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H);
625 tmp |= P3A_RG_XTAL_EXT_PE1H_VAL(0x2) | P3A_RG_XTAL_EXT_PE2H_VAL(0x2);
626 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG0);
627
628 /* ref clk drive */
629 tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG1);
630 tmp &= ~P3A_RG_CLKDRV_AMP;
631 tmp |= P3A_RG_CLKDRV_AMP_VAL(0x4);
632 writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG1);
633
634 tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG0);
635 tmp &= ~P3A_RG_CLKDRV_OFF;
636 tmp |= P3A_RG_CLKDRV_OFF_VAL(0x1);
637 writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0);
638
639 /* SSC delta -5000ppm */
640 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG20);
641 tmp &= ~P3A_RG_PLL_DELTA1_PE2H;
642 tmp |= P3A_RG_PLL_DELTA1_PE2H_VAL(0x3c);
643 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG20);
644
645 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG25);
646 tmp &= ~P3A_RG_PLL_DELTA_PE2H;
647 tmp |= P3A_RG_PLL_DELTA_PE2H_VAL(0x36);
648 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG25);
649
650 /* change pll BW 0.6M */
651 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG5);
652 tmp &= ~(P3A_RG_PLL_BR_PE2H | P3A_RG_PLL_IC_PE2H);
653 tmp |= P3A_RG_PLL_BR_PE2H_VAL(0x1) | P3A_RG_PLL_IC_PE2H_VAL(0x1);
654 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG5);
655
656 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG4);
657 tmp &= ~(P3A_RG_PLL_DIVEN_PE2H | P3A_RG_PLL_BC_PE2H);
658 tmp |= P3A_RG_PLL_BC_PE2H_VAL(0x3);
659 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG4);
660
661 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG6);
662 tmp &= ~P3A_RG_PLL_IR_PE2H;
663 tmp |= P3A_RG_PLL_IR_PE2H_VAL(0x2);
664 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG6);
665
666 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG7);
667 tmp &= ~P3A_RG_PLL_BP_PE2H;
668 tmp |= P3A_RG_PLL_BP_PE2H_VAL(0xa);
669 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG7);
670
671 /* Tx Detect Rx Timing: 10us -> 5us */
672 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET1);
673 tmp &= ~P3D_RG_RXDET_STB2_SET;
674 tmp |= P3D_RG_RXDET_STB2_SET_VAL(0x10);
675 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET1);
676
677 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET2);
678 tmp &= ~P3D_RG_RXDET_STB2_SET_P3;
679 tmp |= P3D_RG_RXDET_STB2_SET_P3_VAL(0x10);
680 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET2);
681
682 /* wait for PCIe subsys register to active */
683 usleep_range(2500, 3000);
684 dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
685 }
686
687 static void pcie_phy_instance_power_on(struct mtk_tphy *tphy,
688 struct mtk_phy_instance *instance)
689 {
690 struct u3phy_banks *bank = &instance->u3_banks;
691 u32 tmp;
692
693 tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLD);
694 tmp &= ~(P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST);
695 writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLD);
696
697 tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLE);
698 tmp &= ~(P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD);
699 writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLE);
700 }
701
702 static void pcie_phy_instance_power_off(struct mtk_tphy *tphy,
703 struct mtk_phy_instance *instance)
704
705 {
706 struct u3phy_banks *bank = &instance->u3_banks;
707 u32 tmp;
708
709 tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLD);
710 tmp |= P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST;
711 writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLD);
712
713 tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLE);
714 tmp |= P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD;
715 writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLE);
716 }
717
718 static void sata_phy_instance_init(struct mtk_tphy *tphy,
719 struct mtk_phy_instance *instance)
720 {
721 struct u3phy_banks *u3_banks = &instance->u3_banks;
722 void __iomem *phyd = u3_banks->phyd;
723 u32 tmp;
724
725 /* charge current adjustment */
726 tmp = readl(phyd + ANA_RG_CTRL_SIGNAL6);
727 tmp &= ~(RG_CDR_BIRLTR_GEN1_MSK | RG_CDR_BC_GEN1_MSK);
728 tmp |= RG_CDR_BIRLTR_GEN1_VAL(0x6) | RG_CDR_BC_GEN1_VAL(0x1a);
729 writel(tmp, phyd + ANA_RG_CTRL_SIGNAL6);
730
731 tmp = readl(phyd + ANA_EQ_EYE_CTRL_SIGNAL4);
732 tmp &= ~RG_CDR_BIRLTD0_GEN1_MSK;
733 tmp |= RG_CDR_BIRLTD0_GEN1_VAL(0x18);
734 writel(tmp, phyd + ANA_EQ_EYE_CTRL_SIGNAL4);
735
736 tmp = readl(phyd + ANA_EQ_EYE_CTRL_SIGNAL5);
737 tmp &= ~RG_CDR_BIRLTD0_GEN3_MSK;
738 tmp |= RG_CDR_BIRLTD0_GEN3_VAL(0x06);
739 writel(tmp, phyd + ANA_EQ_EYE_CTRL_SIGNAL5);
740
741 tmp = readl(phyd + ANA_RG_CTRL_SIGNAL4);
742 tmp &= ~(RG_CDR_BICLTR_GEN1_MSK | RG_CDR_BR_GEN2_MSK);
743 tmp |= RG_CDR_BICLTR_GEN1_VAL(0x0c) | RG_CDR_BR_GEN2_VAL(0x07);
744 writel(tmp, phyd + ANA_RG_CTRL_SIGNAL4);
745
746 tmp = readl(phyd + PHYD_CTRL_SIGNAL_MODE4);
747 tmp &= ~(RG_CDR_BICLTD0_GEN1_MSK | RG_CDR_BICLTD1_GEN1_MSK);
748 tmp |= RG_CDR_BICLTD0_GEN1_VAL(0x08) | RG_CDR_BICLTD1_GEN1_VAL(0x02);
749 writel(tmp, phyd + PHYD_CTRL_SIGNAL_MODE4);
750
751 tmp = readl(phyd + PHYD_DESIGN_OPTION2);
752 tmp &= ~RG_LOCK_CNT_SEL_MSK;
753 tmp |= RG_LOCK_CNT_SEL_VAL(0x02);
754 writel(tmp, phyd + PHYD_DESIGN_OPTION2);
755
756 tmp = readl(phyd + PHYD_DESIGN_OPTION9);
757 tmp &= ~(RG_T2_MIN_MSK | RG_TG_MIN_MSK |
758 RG_T2_MAX_MSK | RG_TG_MAX_MSK);
759 tmp |= RG_T2_MIN_VAL(0x12) | RG_TG_MIN_VAL(0x04) |
760 RG_T2_MAX_VAL(0x31) | RG_TG_MAX_VAL(0x0e);
761 writel(tmp, phyd + PHYD_DESIGN_OPTION9);
762
763 tmp = readl(phyd + ANA_RG_CTRL_SIGNAL1);
764 tmp &= ~RG_IDRV_0DB_GEN1_MSK;
765 tmp |= RG_IDRV_0DB_GEN1_VAL(0x20);
766 writel(tmp, phyd + ANA_RG_CTRL_SIGNAL1);
767
768 tmp = readl(phyd + ANA_EQ_EYE_CTRL_SIGNAL1);
769 tmp &= ~RG_EQ_DLEQ_LFI_GEN1_MSK;
770 tmp |= RG_EQ_DLEQ_LFI_GEN1_VAL(0x03);
771 writel(tmp, phyd + ANA_EQ_EYE_CTRL_SIGNAL1);
772
773 dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
774 }
775
776 static void phy_v1_banks_init(struct mtk_tphy *tphy,
777 struct mtk_phy_instance *instance)
778 {
779 struct u2phy_banks *u2_banks = &instance->u2_banks;
780 struct u3phy_banks *u3_banks = &instance->u3_banks;
781
782 switch (instance->type) {
783 case PHY_TYPE_USB2:
784 u2_banks->misc = NULL;
785 u2_banks->fmreg = tphy->sif_base + SSUSB_SIFSLV_V1_U2FREQ;
786 u2_banks->com = instance->port_base + SSUSB_SIFSLV_V1_U2PHY_COM;
787 break;
788 case PHY_TYPE_USB3:
789 case PHY_TYPE_PCIE:
790 u3_banks->spllc = tphy->sif_base + SSUSB_SIFSLV_V1_SPLLC;
791 u3_banks->chip = tphy->sif_base + SSUSB_SIFSLV_V1_CHIP;
792 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;
793 u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA;
794 break;
795 case PHY_TYPE_SATA:
796 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;
797 break;
798 default:
799 dev_err(tphy->dev, "incompatible PHY type\n");
800 return;
801 }
802 }
803
804 static void phy_v2_banks_init(struct mtk_tphy *tphy,
805 struct mtk_phy_instance *instance)
806 {
807 struct u2phy_banks *u2_banks = &instance->u2_banks;
808 struct u3phy_banks *u3_banks = &instance->u3_banks;
809
810 switch (instance->type) {
811 case PHY_TYPE_USB2:
812 u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC;
813 u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ;
814 u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM;
815 break;
816 case PHY_TYPE_USB3:
817 case PHY_TYPE_PCIE:
818 u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC;
819 u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP;
820 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD;
821 u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA;
822 break;
823 default:
824 dev_err(tphy->dev, "incompatible PHY type\n");
825 return;
826 }
827 }
828
829 static int mtk_phy_init(struct phy *phy)
830 {
831 struct mtk_phy_instance *instance = phy_get_drvdata(phy);
832 struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);
833 int ret;
834
835 ret = clk_prepare_enable(tphy->u3phya_ref);
836 if (ret) {
837 dev_err(tphy->dev, "failed to enable u3phya_ref\n");
838 return ret;
839 }
840
841 ret = clk_prepare_enable(instance->ref_clk);
842 if (ret) {
843 dev_err(tphy->dev, "failed to enable ref_clk\n");
844 return ret;
845 }
846
847 switch (instance->type) {
848 case PHY_TYPE_USB2:
849 u2_phy_instance_init(tphy, instance);
850 break;
851 case PHY_TYPE_USB3:
852 u3_phy_instance_init(tphy, instance);
853 break;
854 case PHY_TYPE_PCIE:
855 pcie_phy_instance_init(tphy, instance);
856 break;
857 case PHY_TYPE_SATA:
858 sata_phy_instance_init(tphy, instance);
859 break;
860 default:
861 dev_err(tphy->dev, "incompatible PHY type\n");
862 return -EINVAL;
863 }
864
865 return 0;
866 }
867
868 static int mtk_phy_power_on(struct phy *phy)
869 {
870 struct mtk_phy_instance *instance = phy_get_drvdata(phy);
871 struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);
872
873 if (instance->type == PHY_TYPE_USB2) {
874 u2_phy_instance_power_on(tphy, instance);
875 hs_slew_rate_calibrate(tphy, instance);
876 } else if (instance->type == PHY_TYPE_PCIE) {
877 pcie_phy_instance_power_on(tphy, instance);
878 }
879
880 return 0;
881 }
882
883 static int mtk_phy_power_off(struct phy *phy)
884 {
885 struct mtk_phy_instance *instance = phy_get_drvdata(phy);
886 struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);
887
888 if (instance->type == PHY_TYPE_USB2)
889 u2_phy_instance_power_off(tphy, instance);
890 else if (instance->type == PHY_TYPE_PCIE)
891 pcie_phy_instance_power_off(tphy, instance);
892
893 return 0;
894 }
895
896 static int mtk_phy_exit(struct phy *phy)
897 {
898 struct mtk_phy_instance *instance = phy_get_drvdata(phy);
899 struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);
900
901 if (instance->type == PHY_TYPE_USB2)
902 u2_phy_instance_exit(tphy, instance);
903
904 clk_disable_unprepare(instance->ref_clk);
905 clk_disable_unprepare(tphy->u3phya_ref);
906 return 0;
907 }
908
909 static int mtk_phy_set_mode(struct phy *phy, enum phy_mode mode)
910 {
911 struct mtk_phy_instance *instance = phy_get_drvdata(phy);
912 struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);
913
914 if (instance->type == PHY_TYPE_USB2)
915 u2_phy_instance_set_mode(tphy, instance, mode);
916
917 return 0;
918 }
919
920 static struct phy *mtk_phy_xlate(struct device *dev,
921 struct of_phandle_args *args)
922 {
923 struct mtk_tphy *tphy = dev_get_drvdata(dev);
924 struct mtk_phy_instance *instance = NULL;
925 struct device_node *phy_np = args->np;
926 int index;
927
928 if (args->args_count != 1) {
929 dev_err(dev, "invalid number of cells in 'phy' property\n");
930 return ERR_PTR(-EINVAL);
931 }
932
933 for (index = 0; index < tphy->nphys; index++)
934 if (phy_np == tphy->phys[index]->phy->dev.of_node) {
935 instance = tphy->phys[index];
936 break;
937 }
938
939 if (!instance) {
940 dev_err(dev, "failed to find appropriate phy\n");
941 return ERR_PTR(-EINVAL);
942 }
943
944 instance->type = args->args[0];
945 if (!(instance->type == PHY_TYPE_USB2 ||
946 instance->type == PHY_TYPE_USB3 ||
947 instance->type == PHY_TYPE_PCIE ||
948 instance->type == PHY_TYPE_SATA)) {
949 dev_err(dev, "unsupported device type: %d\n", instance->type);
950 return ERR_PTR(-EINVAL);
951 }
952
953 if (tphy->pdata->version == MTK_PHY_V1) {
954 phy_v1_banks_init(tphy, instance);
955 } else if (tphy->pdata->version == MTK_PHY_V2) {
956 phy_v2_banks_init(tphy, instance);
957 } else {
958 dev_err(dev, "phy version is not supported\n");
959 return ERR_PTR(-EINVAL);
960 }
961
962 return instance->phy;
963 }
964
965 static const struct phy_ops mtk_tphy_ops = {
966 .init = mtk_phy_init,
967 .exit = mtk_phy_exit,
968 .power_on = mtk_phy_power_on,
969 .power_off = mtk_phy_power_off,
970 .set_mode = mtk_phy_set_mode,
971 .owner = THIS_MODULE,
972 };
973
974 static const struct mtk_phy_pdata tphy_v1_pdata = {
975 .avoid_rx_sen_degradation = false,
976 .version = MTK_PHY_V1,
977 };
978
979 static const struct mtk_phy_pdata tphy_v2_pdata = {
980 .avoid_rx_sen_degradation = false,
981 .version = MTK_PHY_V2,
982 };
983
984 static const struct mtk_phy_pdata mt8173_pdata = {
985 .avoid_rx_sen_degradation = true,
986 .version = MTK_PHY_V1,
987 };
988
989 static const struct of_device_id mtk_tphy_id_table[] = {
990 { .compatible = "mediatek,mt2701-u3phy", .data = &tphy_v1_pdata },
991 { .compatible = "mediatek,mt2712-u3phy", .data = &tphy_v2_pdata },
992 { .compatible = "mediatek,mt8173-u3phy", .data = &mt8173_pdata },
993 { .compatible = "mediatek,generic-tphy-v1", .data = &tphy_v1_pdata },
994 { .compatible = "mediatek,generic-tphy-v2", .data = &tphy_v2_pdata },
995 { },
996 };
997 MODULE_DEVICE_TABLE(of, mtk_tphy_id_table);
998
999 static int mtk_tphy_probe(struct platform_device *pdev)
1000 {
1001 struct device *dev = &pdev->dev;
1002 struct device_node *np = dev->of_node;
1003 struct device_node *child_np;
1004 struct phy_provider *provider;
1005 struct resource *sif_res;
1006 struct mtk_tphy *tphy;
1007 struct resource res;
1008 int port, retval;
1009
1010 tphy = devm_kzalloc(dev, sizeof(*tphy), GFP_KERNEL);
1011 if (!tphy)
1012 return -ENOMEM;
1013
1014 tphy->pdata = of_device_get_match_data(dev);
1015 if (!tphy->pdata)
1016 return -EINVAL;
1017
1018 tphy->nphys = of_get_child_count(np);
1019 tphy->phys = devm_kcalloc(dev, tphy->nphys,
1020 sizeof(*tphy->phys), GFP_KERNEL);
1021 if (!tphy->phys)
1022 return -ENOMEM;
1023
1024 tphy->dev = dev;
1025 platform_set_drvdata(pdev, tphy);
1026
1027 sif_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1028 /* SATA phy of V1 needn't it if not shared with PCIe or USB */
1029 if (sif_res && tphy->pdata->version == MTK_PHY_V1) {
1030 /* get banks shared by multiple phys */
1031 tphy->sif_base = devm_ioremap_resource(dev, sif_res);
1032 if (IS_ERR(tphy->sif_base)) {
1033 dev_err(dev, "failed to remap sif regs\n");
1034 return PTR_ERR(tphy->sif_base);
1035 }
1036 }
1037
1038 /* it's deprecated, make it optional for backward compatibility */
1039 tphy->u3phya_ref = devm_clk_get(dev, "u3phya_ref");
1040 if (IS_ERR(tphy->u3phya_ref)) {
1041 if (PTR_ERR(tphy->u3phya_ref) == -EPROBE_DEFER)
1042 return -EPROBE_DEFER;
1043
1044 tphy->u3phya_ref = NULL;
1045 }
1046
1047 tphy->src_ref_clk = U3P_REF_CLK;
1048 tphy->src_coef = U3P_SLEW_RATE_COEF;
1049 /* update parameters of slew rate calibrate if exist */
1050 device_property_read_u32(dev, "mediatek,src-ref-clk-mhz",
1051 &tphy->src_ref_clk);
1052 device_property_read_u32(dev, "mediatek,src-coef", &tphy->src_coef);
1053
1054 port = 0;
1055 for_each_child_of_node(np, child_np) {
1056 struct mtk_phy_instance *instance;
1057 struct phy *phy;
1058
1059 instance = devm_kzalloc(dev, sizeof(*instance), GFP_KERNEL);
1060 if (!instance) {
1061 retval = -ENOMEM;
1062 goto put_child;
1063 }
1064
1065 tphy->phys[port] = instance;
1066
1067 phy = devm_phy_create(dev, child_np, &mtk_tphy_ops);
1068 if (IS_ERR(phy)) {
1069 dev_err(dev, "failed to create phy\n");
1070 retval = PTR_ERR(phy);
1071 goto put_child;
1072 }
1073
1074 retval = of_address_to_resource(child_np, 0, &res);
1075 if (retval) {
1076 dev_err(dev, "failed to get address resource(id-%d)\n",
1077 port);
1078 goto put_child;
1079 }
1080
1081 instance->port_base = devm_ioremap_resource(&phy->dev, &res);
1082 if (IS_ERR(instance->port_base)) {
1083 dev_err(dev, "failed to remap phy regs\n");
1084 retval = PTR_ERR(instance->port_base);
1085 goto put_child;
1086 }
1087
1088 instance->phy = phy;
1089 instance->index = port;
1090 phy_set_drvdata(phy, instance);
1091 port++;
1092
1093 /* if deprecated clock is provided, ignore instance's one */
1094 if (tphy->u3phya_ref)
1095 continue;
1096
1097 instance->ref_clk = devm_clk_get(&phy->dev, "ref");
1098 if (IS_ERR(instance->ref_clk)) {
1099 dev_err(dev, "failed to get ref_clk(id-%d)\n", port);
1100 retval = PTR_ERR(instance->ref_clk);
1101 goto put_child;
1102 }
1103 }
1104
1105 provider = devm_of_phy_provider_register(dev, mtk_phy_xlate);
1106
1107 return PTR_ERR_OR_ZERO(provider);
1108 put_child:
1109 of_node_put(child_np);
1110 return retval;
1111 }
1112
1113 static struct platform_driver mtk_tphy_driver = {
1114 .probe = mtk_tphy_probe,
1115 .driver = {
1116 .name = "mtk-tphy",
1117 .of_match_table = mtk_tphy_id_table,
1118 },
1119 };
1120
1121 module_platform_driver(mtk_tphy_driver);
1122
1123 MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
1124 MODULE_DESCRIPTION("MediaTek T-PHY driver");
1125 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support