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[linux/fpc-iii.git] / drivers / scsi / mpt3sas / mpi / mpi2_pci.h
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1 /*
2 * Copyright 2012-2015 Avago Technologies. All rights reserved.
5 * Name: mpi2_pci.h
6 * Title: MPI PCIe Attached Devices structures and definitions.
7 * Creation Date: October 9, 2012
9 * mpi2_pci.h Version: 02.00.02
11 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
12 * prefix are for use only on MPI v2.5 products, and must not be used
13 * with MPI v2.0 products. Unless otherwise noted, names beginning with
14 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
16 * Version History
17 * ---------------
19 * Date Version Description
20 * -------- -------- ------------------------------------------------------
21 * 03-16-15 02.00.00 Initial version.
22 * 02-17-16 02.00.01 Removed AHCI support.
23 * Removed SOP support.
24 * 07-01-16 02.00.02 Added MPI26_NVME_FLAGS_FORCE_ADMIN_ERR_RESP to
25 * NVME Encapsulated Request.
26 * --------------------------------------------------------------------------
29 #ifndef MPI2_PCI_H
30 #define MPI2_PCI_H
34 *Values for the PCIe DeviceInfo field used in PCIe Device Status Change Event
35 *data and PCIe Configuration pages.
37 #define MPI26_PCIE_DEVINFO_DIRECT_ATTACH (0x00000010)
39 #define MPI26_PCIE_DEVINFO_MASK_DEVICE_TYPE (0x0000000F)
40 #define MPI26_PCIE_DEVINFO_NO_DEVICE (0x00000000)
41 #define MPI26_PCIE_DEVINFO_PCI_SWITCH (0x00000001)
42 #define MPI26_PCIE_DEVINFO_NVME (0x00000003)
45 /****************************************************************************
46 * NVMe Encapsulated message
47 ****************************************************************************/
49 /*NVME Encapsulated Request Message */
50 typedef struct _MPI26_NVME_ENCAPSULATED_REQUEST {
51 U16 DevHandle; /*0x00 */
52 U8 ChainOffset; /*0x02 */
53 U8 Function; /*0x03 */
54 U16 EncapsulatedCommandLength; /*0x04 */
55 U8 Reserved1; /*0x06 */
56 U8 MsgFlags; /*0x07 */
57 U8 VP_ID; /*0x08 */
58 U8 VF_ID; /*0x09 */
59 U16 Reserved2; /*0x0A */
60 U32 Reserved3; /*0x0C */
61 U64 ErrorResponseBaseAddress; /*0x10 */
62 U16 ErrorResponseAllocationLength; /*0x18 */
63 U16 Flags; /*0x1A */
64 U32 DataLength; /*0x1C */
65 U8 NVMe_Command[4]; /*0x20 */
67 } MPI26_NVME_ENCAPSULATED_REQUEST, *PTR_MPI26_NVME_ENCAPSULATED_REQUEST,
68 Mpi26NVMeEncapsulatedRequest_t, *pMpi26NVMeEncapsulatedRequest_t;
70 /*defines for the Flags field */
71 #define MPI26_NVME_FLAGS_FORCE_ADMIN_ERR_RESP (0x0020)
72 /*Submission Queue Type*/
73 #define MPI26_NVME_FLAGS_SUBMISSIONQ_MASK (0x0010)
74 #define MPI26_NVME_FLAGS_SUBMISSIONQ_IO (0x0000)
75 #define MPI26_NVME_FLAGS_SUBMISSIONQ_ADMIN (0x0010)
76 /*Error Response Address Space */
77 #define MPI26_NVME_FLAGS_MASK_ERROR_RSP_ADDR (0x000C)
78 #define MPI26_NVME_FLAGS_SYSTEM_RSP_ADDR (0x0000)
79 #define MPI26_NVME_FLAGS_IOCPLB_RSP_ADDR (0x0008)
80 #define MPI26_NVME_FLAGS_IOCPLBNTA_RSP_ADDR (0x000C)
81 /*Data Direction*/
82 #define MPI26_NVME_FLAGS_DATADIRECTION_MASK (0x0003)
83 #define MPI26_NVME_FLAGS_NODATATRANSFER (0x0000)
84 #define MPI26_NVME_FLAGS_WRITE (0x0001)
85 #define MPI26_NVME_FLAGS_READ (0x0002)
86 #define MPI26_NVME_FLAGS_BIDIRECTIONAL (0x0003)
89 /*NVMe Encapuslated Reply Message */
90 typedef struct _MPI26_NVME_ENCAPSULATED_ERROR_REPLY {
91 U16 DevHandle; /*0x00 */
92 U8 MsgLength; /*0x02 */
93 U8 Function; /*0x03 */
94 U16 EncapsulatedCommandLength; /*0x04 */
95 U8 Reserved1; /*0x06 */
96 U8 MsgFlags; /*0x07 */
97 U8 VP_ID; /*0x08 */
98 U8 VF_ID; /*0x09 */
99 U16 Reserved2; /*0x0A */
100 U16 Reserved3; /*0x0C */
101 U16 IOCStatus; /*0x0E */
102 U32 IOCLogInfo; /*0x10 */
103 U16 ErrorResponseCount; /*0x14 */
104 U16 Reserved4; /*0x16 */
105 } MPI26_NVME_ENCAPSULATED_ERROR_REPLY,
106 *PTR_MPI26_NVME_ENCAPSULATED_ERROR_REPLY,
107 Mpi26NVMeEncapsulatedErrorReply_t,
108 *pMpi26NVMeEncapsulatedErrorReply_t;
111 #endif