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Linux 4.18.10
[linux/fpc-iii.git] / drivers / spi / spi-sh-msiof.c
blob0e74cbf9929d4a9b2d6fe4a6c05d3c328a485ec2
1 /*
2 * SuperH MSIOF SPI Master Interface
3 *
4 * Copyright (c) 2009 Magnus Damm
5 * Copyright (C) 2014 Renesas Electronics Corporation
6 * Copyright (C) 2014-2017 Glider bvba
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
13
14 #include <linux/bitmap.h>
15 #include <linux/clk.h>
16 #include <linux/completion.h>
17 #include <linux/delay.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/dmaengine.h>
20 #include <linux/err.h>
21 #include <linux/gpio.h>
22 #include <linux/gpio/consumer.h>
23 #include <linux/interrupt.h>
24 #include <linux/io.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/of.h>
28 #include <linux/of_device.h>
29 #include <linux/platform_device.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/sh_dma.h>
32
33 #include <linux/spi/sh_msiof.h>
34 #include <linux/spi/spi.h>
35
36 #include <asm/unaligned.h>
37
38 struct sh_msiof_chipdata {
39 u16 tx_fifo_size;
40 u16 rx_fifo_size;
41 u16 master_flags;
42 u16 min_div_pow;
43 };
44
45 struct sh_msiof_spi_priv {
46 struct spi_master *master;
47 void __iomem *mapbase;
48 struct clk *clk;
49 struct platform_device *pdev;
50 struct sh_msiof_spi_info *info;
51 struct completion done;
52 unsigned int tx_fifo_size;
53 unsigned int rx_fifo_size;
54 unsigned int min_div_pow;
55 void *tx_dma_page;
56 void *rx_dma_page;
57 dma_addr_t tx_dma_addr;
58 dma_addr_t rx_dma_addr;
59 unsigned short unused_ss;
60 bool native_cs_inited;
61 bool native_cs_high;
62 bool slave_aborted;
63 };
64
65 #define MAX_SS 3 /* Maximum number of native chip selects */
66
67 #define TMDR1 0x00 /* Transmit Mode Register 1 */
68 #define TMDR2 0x04 /* Transmit Mode Register 2 */
69 #define TMDR3 0x08 /* Transmit Mode Register 3 */
70 #define RMDR1 0x10 /* Receive Mode Register 1 */
71 #define RMDR2 0x14 /* Receive Mode Register 2 */
72 #define RMDR3 0x18 /* Receive Mode Register 3 */
73 #define TSCR 0x20 /* Transmit Clock Select Register */
74 #define RSCR 0x22 /* Receive Clock Select Register (SH, A1, APE6) */
75 #define CTR 0x28 /* Control Register */
76 #define FCTR 0x30 /* FIFO Control Register */
77 #define STR 0x40 /* Status Register */
78 #define IER 0x44 /* Interrupt Enable Register */
79 #define TDR1 0x48 /* Transmit Control Data Register 1 (SH, A1) */
80 #define TDR2 0x4c /* Transmit Control Data Register 2 (SH, A1) */
81 #define TFDR 0x50 /* Transmit FIFO Data Register */
82 #define RDR1 0x58 /* Receive Control Data Register 1 (SH, A1) */
83 #define RDR2 0x5c /* Receive Control Data Register 2 (SH, A1) */
84 #define RFDR 0x60 /* Receive FIFO Data Register */
85
86 /* TMDR1 and RMDR1 */
87 #define MDR1_TRMD 0x80000000 /* Transfer Mode (1 = Master mode) */
88 #define MDR1_SYNCMD_MASK 0x30000000 /* SYNC Mode */
89 #define MDR1_SYNCMD_SPI 0x20000000 /* Level mode/SPI */
90 #define MDR1_SYNCMD_LR 0x30000000 /* L/R mode */
91 #define MDR1_SYNCAC_SHIFT 25 /* Sync Polarity (1 = Active-low) */
92 #define MDR1_BITLSB_SHIFT 24 /* MSB/LSB First (1 = LSB first) */
93 #define MDR1_DTDL_SHIFT 20 /* Data Pin Bit Delay for MSIOF_SYNC */
94 #define MDR1_SYNCDL_SHIFT 16 /* Frame Sync Signal Timing Delay */
95 #define MDR1_FLD_MASK 0x0000000c /* Frame Sync Signal Interval (0-3) */
96 #define MDR1_FLD_SHIFT 2
97 #define MDR1_XXSTP 0x00000001 /* Transmission/Reception Stop on FIFO */
98 /* TMDR1 */
99 #define TMDR1_PCON 0x40000000 /* Transfer Signal Connection */
100 #define TMDR1_SYNCCH_MASK 0xc000000 /* Synchronization Signal Channel Select */
101 #define TMDR1_SYNCCH_SHIFT 26 /* 0=MSIOF_SYNC, 1=MSIOF_SS1, 2=MSIOF_SS2 */
102
103 /* TMDR2 and RMDR2 */
104 #define MDR2_BITLEN1(i) (((i) - 1) << 24) /* Data Size (8-32 bits) */
105 #define MDR2_WDLEN1(i) (((i) - 1) << 16) /* Word Count (1-64/256 (SH, A1))) */
106 #define MDR2_GRPMASK1 0x00000001 /* Group Output Mask 1 (SH, A1) */
107
108 /* TSCR and RSCR */
109 #define SCR_BRPS_MASK 0x1f00 /* Prescaler Setting (1-32) */
110 #define SCR_BRPS(i) (((i) - 1) << 8)
111 #define SCR_BRDV_MASK 0x0007 /* Baud Rate Generator's Division Ratio */
112 #define SCR_BRDV_DIV_2 0x0000
113 #define SCR_BRDV_DIV_4 0x0001
114 #define SCR_BRDV_DIV_8 0x0002
115 #define SCR_BRDV_DIV_16 0x0003
116 #define SCR_BRDV_DIV_32 0x0004
117 #define SCR_BRDV_DIV_1 0x0007
118
119 /* CTR */
120 #define CTR_TSCKIZ_MASK 0xc0000000 /* Transmit Clock I/O Polarity Select */
121 #define CTR_TSCKIZ_SCK 0x80000000 /* Disable SCK when TX disabled */
122 #define CTR_TSCKIZ_POL_SHIFT 30 /* Transmit Clock Polarity */
123 #define CTR_RSCKIZ_MASK 0x30000000 /* Receive Clock Polarity Select */
124 #define CTR_RSCKIZ_SCK 0x20000000 /* Must match CTR_TSCKIZ_SCK */
125 #define CTR_RSCKIZ_POL_SHIFT 28 /* Receive Clock Polarity */
126 #define CTR_TEDG_SHIFT 27 /* Transmit Timing (1 = falling edge) */
127 #define CTR_REDG_SHIFT 26 /* Receive Timing (1 = falling edge) */
128 #define CTR_TXDIZ_MASK 0x00c00000 /* Pin Output When TX is Disabled */
129 #define CTR_TXDIZ_LOW 0x00000000 /* 0 */
130 #define CTR_TXDIZ_HIGH 0x00400000 /* 1 */
131 #define CTR_TXDIZ_HIZ 0x00800000 /* High-impedance */
132 #define CTR_TSCKE 0x00008000 /* Transmit Serial Clock Output Enable */
133 #define CTR_TFSE 0x00004000 /* Transmit Frame Sync Signal Output Enable */
134 #define CTR_TXE 0x00000200 /* Transmit Enable */
135 #define CTR_RXE 0x00000100 /* Receive Enable */
136
137 /* FCTR */
138 #define FCTR_TFWM_MASK 0xe0000000 /* Transmit FIFO Watermark */
139 #define FCTR_TFWM_64 0x00000000 /* Transfer Request when 64 empty stages */
140 #define FCTR_TFWM_32 0x20000000 /* Transfer Request when 32 empty stages */
141 #define FCTR_TFWM_24 0x40000000 /* Transfer Request when 24 empty stages */
142 #define FCTR_TFWM_16 0x60000000 /* Transfer Request when 16 empty stages */
143 #define FCTR_TFWM_12 0x80000000 /* Transfer Request when 12 empty stages */
144 #define FCTR_TFWM_8 0xa0000000 /* Transfer Request when 8 empty stages */
145 #define FCTR_TFWM_4 0xc0000000 /* Transfer Request when 4 empty stages */
146 #define FCTR_TFWM_1 0xe0000000 /* Transfer Request when 1 empty stage */
147 #define FCTR_TFUA_MASK 0x07f00000 /* Transmit FIFO Usable Area */
148 #define FCTR_TFUA_SHIFT 20
149 #define FCTR_TFUA(i) ((i) << FCTR_TFUA_SHIFT)
150 #define FCTR_RFWM_MASK 0x0000e000 /* Receive FIFO Watermark */
151 #define FCTR_RFWM_1 0x00000000 /* Transfer Request when 1 valid stages */
152 #define FCTR_RFWM_4 0x00002000 /* Transfer Request when 4 valid stages */
153 #define FCTR_RFWM_8 0x00004000 /* Transfer Request when 8 valid stages */
154 #define FCTR_RFWM_16 0x00006000 /* Transfer Request when 16 valid stages */
155 #define FCTR_RFWM_32 0x00008000 /* Transfer Request when 32 valid stages */
156 #define FCTR_RFWM_64 0x0000a000 /* Transfer Request when 64 valid stages */
157 #define FCTR_RFWM_128 0x0000c000 /* Transfer Request when 128 valid stages */
158 #define FCTR_RFWM_256 0x0000e000 /* Transfer Request when 256 valid stages */
159 #define FCTR_RFUA_MASK 0x00001ff0 /* Receive FIFO Usable Area (0x40 = full) */
160 #define FCTR_RFUA_SHIFT 4
161 #define FCTR_RFUA(i) ((i) << FCTR_RFUA_SHIFT)
162
163 /* STR */
164 #define STR_TFEMP 0x20000000 /* Transmit FIFO Empty */
165 #define STR_TDREQ 0x10000000 /* Transmit Data Transfer Request */
166 #define STR_TEOF 0x00800000 /* Frame Transmission End */
167 #define STR_TFSERR 0x00200000 /* Transmit Frame Synchronization Error */
168 #define STR_TFOVF 0x00100000 /* Transmit FIFO Overflow */
169 #define STR_TFUDF 0x00080000 /* Transmit FIFO Underflow */
170 #define STR_RFFUL 0x00002000 /* Receive FIFO Full */
171 #define STR_RDREQ 0x00001000 /* Receive Data Transfer Request */
172 #define STR_REOF 0x00000080 /* Frame Reception End */
173 #define STR_RFSERR 0x00000020 /* Receive Frame Synchronization Error */
174 #define STR_RFUDF 0x00000010 /* Receive FIFO Underflow */
175 #define STR_RFOVF 0x00000008 /* Receive FIFO Overflow */
176
177 /* IER */
178 #define IER_TDMAE 0x80000000 /* Transmit Data DMA Transfer Req. Enable */
179 #define IER_TFEMPE 0x20000000 /* Transmit FIFO Empty Enable */
180 #define IER_TDREQE 0x10000000 /* Transmit Data Transfer Request Enable */
181 #define IER_TEOFE 0x00800000 /* Frame Transmission End Enable */
182 #define IER_TFSERRE 0x00200000 /* Transmit Frame Sync Error Enable */
183 #define IER_TFOVFE 0x00100000 /* Transmit FIFO Overflow Enable */
184 #define IER_TFUDFE 0x00080000 /* Transmit FIFO Underflow Enable */
185 #define IER_RDMAE 0x00008000 /* Receive Data DMA Transfer Req. Enable */
186 #define IER_RFFULE 0x00002000 /* Receive FIFO Full Enable */
187 #define IER_RDREQE 0x00001000 /* Receive Data Transfer Request Enable */
188 #define IER_REOFE 0x00000080 /* Frame Reception End Enable */
189 #define IER_RFSERRE 0x00000020 /* Receive Frame Sync Error Enable */
190 #define IER_RFUDFE 0x00000010 /* Receive FIFO Underflow Enable */
191 #define IER_RFOVFE 0x00000008 /* Receive FIFO Overflow Enable */
192
193
194 static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs)
195 {
196 switch (reg_offs) {
197 case TSCR:
198 case RSCR:
199 return ioread16(p->mapbase + reg_offs);
200 default:
201 return ioread32(p->mapbase + reg_offs);
202 }
203 }
204
205 static void sh_msiof_write(struct sh_msiof_spi_priv *p, int reg_offs,
206 u32 value)
207 {
208 switch (reg_offs) {
209 case TSCR:
210 case RSCR:
211 iowrite16(value, p->mapbase + reg_offs);
212 break;
213 default:
214 iowrite32(value, p->mapbase + reg_offs);
215 break;
216 }
217 }
218
219 static int sh_msiof_modify_ctr_wait(struct sh_msiof_spi_priv *p,
220 u32 clr, u32 set)
221 {
222 u32 mask = clr | set;
223 u32 data;
224 int k;
225
226 data = sh_msiof_read(p, CTR);
227 data &= ~clr;
228 data |= set;
229 sh_msiof_write(p, CTR, data);
230
231 for (k = 100; k > 0; k--) {
232 if ((sh_msiof_read(p, CTR) & mask) == set)
233 break;
234
235 udelay(10);
236 }
237
238 return k > 0 ? 0 : -ETIMEDOUT;
239 }
240
241 static irqreturn_t sh_msiof_spi_irq(int irq, void *data)
242 {
243 struct sh_msiof_spi_priv *p = data;
244
245 /* just disable the interrupt and wake up */
246 sh_msiof_write(p, IER, 0);
247 complete(&p->done);
248
249 return IRQ_HANDLED;
250 }
251
252 static const u32 sh_msiof_spi_div_array[] = {
253 SCR_BRDV_DIV_1, SCR_BRDV_DIV_2, SCR_BRDV_DIV_4,
254 SCR_BRDV_DIV_8, SCR_BRDV_DIV_16, SCR_BRDV_DIV_32,
255 };
256
257 static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
258 unsigned long parent_rate, u32 spi_hz)
259 {
260 unsigned long div;
261 u32 brps, scr;
262 unsigned int div_pow = p->min_div_pow;
263
264 if (!spi_hz || !parent_rate) {
265 WARN(1, "Invalid clock rate parameters %lu and %u\n",
266 parent_rate, spi_hz);
267 return;
268 }
269
270 div = DIV_ROUND_UP(parent_rate, spi_hz);
271 if (div <= 1024) {
272 /* SCR_BRDV_DIV_1 is valid only if BRPS is x 1/1 or x 1/2 */
273 if (!div_pow && div <= 32 && div > 2)
274 div_pow = 1;
275
276 if (div_pow)
277 brps = (div + 1) >> div_pow;
278 else
279 brps = div;
280
281 for (; brps > 32; div_pow++)
282 brps = (brps + 1) >> 1;
283 } else {
284 /* Set transfer rate composite divisor to 2^5 * 32 = 1024 */
285 dev_err(&p->pdev->dev,
286 "Requested SPI transfer rate %d is too low\n", spi_hz);
287 div_pow = 5;
288 brps = 32;
289 }
290
291 scr = sh_msiof_spi_div_array[div_pow] | SCR_BRPS(brps);
292 sh_msiof_write(p, TSCR, scr);
293 if (!(p->master->flags & SPI_MASTER_MUST_TX))
294 sh_msiof_write(p, RSCR, scr);
295 }
296
297 static u32 sh_msiof_get_delay_bit(u32 dtdl_or_syncdl)
298 {
299 /*
300 * DTDL/SYNCDL bit : p->info->dtdl or p->info->syncdl
301 * b'000 : 0
302 * b'001 : 100
303 * b'010 : 200
304 * b'011 (SYNCDL only) : 300
305 * b'101 : 50
306 * b'110 : 150
307 */
308 if (dtdl_or_syncdl % 100)
309 return dtdl_or_syncdl / 100 + 5;
310 else
311 return dtdl_or_syncdl / 100;
312 }
313
314 static u32 sh_msiof_spi_get_dtdl_and_syncdl(struct sh_msiof_spi_priv *p)
315 {
316 u32 val;
317
318 if (!p->info)
319 return 0;
320
321 /* check if DTDL and SYNCDL is allowed value */
322 if (p->info->dtdl > 200 || p->info->syncdl > 300) {
323 dev_warn(&p->pdev->dev, "DTDL or SYNCDL is too large\n");
324 return 0;
325 }
326
327 /* check if the sum of DTDL and SYNCDL becomes an integer value */
328 if ((p->info->dtdl + p->info->syncdl) % 100) {
329 dev_warn(&p->pdev->dev, "the sum of DTDL/SYNCDL is not good\n");
330 return 0;
331 }
332
333 val = sh_msiof_get_delay_bit(p->info->dtdl) << MDR1_DTDL_SHIFT;
334 val |= sh_msiof_get_delay_bit(p->info->syncdl) << MDR1_SYNCDL_SHIFT;
335
336 return val;
337 }
338
339 static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p, u32 ss,
340 u32 cpol, u32 cpha,
341 u32 tx_hi_z, u32 lsb_first, u32 cs_high)
342 {
343 u32 tmp;
344 int edge;
345
346 /*
347 * CPOL CPHA TSCKIZ RSCKIZ TEDG REDG
348 * 0 0 10 10 1 1
349 * 0 1 10 10 0 0
350 * 1 0 11 11 0 0
351 * 1 1 11 11 1 1
352 */
353 tmp = MDR1_SYNCMD_SPI | 1 << MDR1_FLD_SHIFT | MDR1_XXSTP;
354 tmp |= !cs_high << MDR1_SYNCAC_SHIFT;
355 tmp |= lsb_first << MDR1_BITLSB_SHIFT;
356 tmp |= sh_msiof_spi_get_dtdl_and_syncdl(p);
357 if (spi_controller_is_slave(p->master)) {
358 sh_msiof_write(p, TMDR1, tmp | TMDR1_PCON);
359 } else {
360 sh_msiof_write(p, TMDR1,
361 tmp | MDR1_TRMD | TMDR1_PCON |
362 (ss < MAX_SS ? ss : 0) << TMDR1_SYNCCH_SHIFT);
363 }
364 if (p->master->flags & SPI_MASTER_MUST_TX) {
365 /* These bits are reserved if RX needs TX */
366 tmp &= ~0x0000ffff;
367 }
368 sh_msiof_write(p, RMDR1, tmp);
369
370 tmp = 0;
371 tmp |= CTR_TSCKIZ_SCK | cpol << CTR_TSCKIZ_POL_SHIFT;
372 tmp |= CTR_RSCKIZ_SCK | cpol << CTR_RSCKIZ_POL_SHIFT;
373
374 edge = cpol ^ !cpha;
375
376 tmp |= edge << CTR_TEDG_SHIFT;
377 tmp |= edge << CTR_REDG_SHIFT;
378 tmp |= tx_hi_z ? CTR_TXDIZ_HIZ : CTR_TXDIZ_LOW;
379 sh_msiof_write(p, CTR, tmp);
380 }
381
382 static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p,
383 const void *tx_buf, void *rx_buf,
384 u32 bits, u32 words)
385 {
386 u32 dr2 = MDR2_BITLEN1(bits) | MDR2_WDLEN1(words);
387
388 if (tx_buf || (p->master->flags & SPI_MASTER_MUST_TX))
389 sh_msiof_write(p, TMDR2, dr2);
390 else
391 sh_msiof_write(p, TMDR2, dr2 | MDR2_GRPMASK1);
392
393 if (rx_buf)
394 sh_msiof_write(p, RMDR2, dr2);
395 }
396
397 static void sh_msiof_reset_str(struct sh_msiof_spi_priv *p)
398 {
399 sh_msiof_write(p, STR, sh_msiof_read(p, STR));
400 }
401
402 static void sh_msiof_spi_write_fifo_8(struct sh_msiof_spi_priv *p,
403 const void *tx_buf, int words, int fs)
404 {
405 const u8 *buf_8 = tx_buf;
406 int k;
407
408 for (k = 0; k < words; k++)
409 sh_msiof_write(p, TFDR, buf_8[k] << fs);
410 }
411
412 static void sh_msiof_spi_write_fifo_16(struct sh_msiof_spi_priv *p,
413 const void *tx_buf, int words, int fs)
414 {
415 const u16 *buf_16 = tx_buf;
416 int k;
417
418 for (k = 0; k < words; k++)
419 sh_msiof_write(p, TFDR, buf_16[k] << fs);
420 }
421
422 static void sh_msiof_spi_write_fifo_16u(struct sh_msiof_spi_priv *p,
423 const void *tx_buf, int words, int fs)
424 {
425 const u16 *buf_16 = tx_buf;
426 int k;
427
428 for (k = 0; k < words; k++)
429 sh_msiof_write(p, TFDR, get_unaligned(&buf_16[k]) << fs);
430 }
431
432 static void sh_msiof_spi_write_fifo_32(struct sh_msiof_spi_priv *p,
433 const void *tx_buf, int words, int fs)
434 {
435 const u32 *buf_32 = tx_buf;
436 int k;
437
438 for (k = 0; k < words; k++)
439 sh_msiof_write(p, TFDR, buf_32[k] << fs);
440 }
441
442 static void sh_msiof_spi_write_fifo_32u(struct sh_msiof_spi_priv *p,
443 const void *tx_buf, int words, int fs)
444 {
445 const u32 *buf_32 = tx_buf;
446 int k;
447
448 for (k = 0; k < words; k++)
449 sh_msiof_write(p, TFDR, get_unaligned(&buf_32[k]) << fs);
450 }
451
452 static void sh_msiof_spi_write_fifo_s32(struct sh_msiof_spi_priv *p,
453 const void *tx_buf, int words, int fs)
454 {
455 const u32 *buf_32 = tx_buf;
456 int k;
457
458 for (k = 0; k < words; k++)
459 sh_msiof_write(p, TFDR, swab32(buf_32[k] << fs));
460 }
461
462 static void sh_msiof_spi_write_fifo_s32u(struct sh_msiof_spi_priv *p,
463 const void *tx_buf, int words, int fs)
464 {
465 const u32 *buf_32 = tx_buf;
466 int k;
467
468 for (k = 0; k < words; k++)
469 sh_msiof_write(p, TFDR, swab32(get_unaligned(&buf_32[k]) << fs));
470 }
471
472 static void sh_msiof_spi_read_fifo_8(struct sh_msiof_spi_priv *p,
473 void *rx_buf, int words, int fs)
474 {
475 u8 *buf_8 = rx_buf;
476 int k;
477
478 for (k = 0; k < words; k++)
479 buf_8[k] = sh_msiof_read(p, RFDR) >> fs;
480 }
481
482 static void sh_msiof_spi_read_fifo_16(struct sh_msiof_spi_priv *p,
483 void *rx_buf, int words, int fs)
484 {
485 u16 *buf_16 = rx_buf;
486 int k;
487
488 for (k = 0; k < words; k++)
489 buf_16[k] = sh_msiof_read(p, RFDR) >> fs;
490 }
491
492 static void sh_msiof_spi_read_fifo_16u(struct sh_msiof_spi_priv *p,
493 void *rx_buf, int words, int fs)
494 {
495 u16 *buf_16 = rx_buf;
496 int k;
497
498 for (k = 0; k < words; k++)
499 put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_16[k]);
500 }
501
502 static void sh_msiof_spi_read_fifo_32(struct sh_msiof_spi_priv *p,
503 void *rx_buf, int words, int fs)
504 {
505 u32 *buf_32 = rx_buf;
506 int k;
507
508 for (k = 0; k < words; k++)
509 buf_32[k] = sh_msiof_read(p, RFDR) >> fs;
510 }
511
512 static void sh_msiof_spi_read_fifo_32u(struct sh_msiof_spi_priv *p,
513 void *rx_buf, int words, int fs)
514 {
515 u32 *buf_32 = rx_buf;
516 int k;
517
518 for (k = 0; k < words; k++)
519 put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_32[k]);
520 }
521
522 static void sh_msiof_spi_read_fifo_s32(struct sh_msiof_spi_priv *p,
523 void *rx_buf, int words, int fs)
524 {
525 u32 *buf_32 = rx_buf;
526 int k;
527
528 for (k = 0; k < words; k++)
529 buf_32[k] = swab32(sh_msiof_read(p, RFDR) >> fs);
530 }
531
532 static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv *p,
533 void *rx_buf, int words, int fs)
534 {
535 u32 *buf_32 = rx_buf;
536 int k;
537
538 for (k = 0; k < words; k++)
539 put_unaligned(swab32(sh_msiof_read(p, RFDR) >> fs), &buf_32[k]);
540 }
541
542 static int sh_msiof_spi_setup(struct spi_device *spi)
543 {
544 struct device_node *np = spi->master->dev.of_node;
545 struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master);
546 u32 clr, set, tmp;
547
548 if (!np) {
549 /*
550 * Use spi->controller_data for CS (same strategy as spi_gpio),
551 * if any. otherwise let HW control CS
552 */
553 spi->cs_gpio = (uintptr_t)spi->controller_data;
554 }
555
556 if (gpio_is_valid(spi->cs_gpio)) {
557 gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
558 return 0;
559 }
560
561 if (spi_controller_is_slave(p->master))
562 return 0;
563
564 if (p->native_cs_inited &&
565 (p->native_cs_high == !!(spi->mode & SPI_CS_HIGH)))
566 return 0;
567
568 /* Configure native chip select mode/polarity early */
569 clr = MDR1_SYNCMD_MASK;
570 set = MDR1_SYNCMD_SPI;
571 if (spi->mode & SPI_CS_HIGH)
572 clr |= BIT(MDR1_SYNCAC_SHIFT);
573 else
574 set |= BIT(MDR1_SYNCAC_SHIFT);
575 pm_runtime_get_sync(&p->pdev->dev);
576 tmp = sh_msiof_read(p, TMDR1) & ~clr;
577 sh_msiof_write(p, TMDR1, tmp | set | MDR1_TRMD | TMDR1_PCON);
578 tmp = sh_msiof_read(p, RMDR1) & ~clr;
579 sh_msiof_write(p, RMDR1, tmp | set);
580 pm_runtime_put(&p->pdev->dev);
581 p->native_cs_high = spi->mode & SPI_CS_HIGH;
582 p->native_cs_inited = true;
583 return 0;
584 }
585
586 static int sh_msiof_prepare_message(struct spi_master *master,
587 struct spi_message *msg)
588 {
589 struct sh_msiof_spi_priv *p = spi_master_get_devdata(master);
590 const struct spi_device *spi = msg->spi;
591 u32 ss, cs_high;
592
593 /* Configure pins before asserting CS */
594 if (gpio_is_valid(spi->cs_gpio)) {
595 ss = p->unused_ss;
596 cs_high = p->native_cs_high;
597 } else {
598 ss = spi->chip_select;
599 cs_high = !!(spi->mode & SPI_CS_HIGH);
600 }
601 sh_msiof_spi_set_pin_regs(p, ss, !!(spi->mode & SPI_CPOL),
602 !!(spi->mode & SPI_CPHA),
603 !!(spi->mode & SPI_3WIRE),
604 !!(spi->mode & SPI_LSB_FIRST), cs_high);
605 return 0;
606 }
607
608 static int sh_msiof_spi_start(struct sh_msiof_spi_priv *p, void *rx_buf)
609 {
610 bool slave = spi_controller_is_slave(p->master);
611 int ret = 0;
612
613 /* setup clock and rx/tx signals */
614 if (!slave)
615 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TSCKE);
616 if (rx_buf && !ret)
617 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_RXE);
618 if (!ret)
619 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TXE);
620
621 /* start by setting frame bit */
622 if (!ret && !slave)
623 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TFSE);
624
625 return ret;
626 }
627
628 static int sh_msiof_spi_stop(struct sh_msiof_spi_priv *p, void *rx_buf)
629 {
630 bool slave = spi_controller_is_slave(p->master);
631 int ret = 0;
632
633 /* shut down frame, rx/tx and clock signals */
634 if (!slave)
635 ret = sh_msiof_modify_ctr_wait(p, CTR_TFSE, 0);
636 if (!ret)
637 ret = sh_msiof_modify_ctr_wait(p, CTR_TXE, 0);
638 if (rx_buf && !ret)
639 ret = sh_msiof_modify_ctr_wait(p, CTR_RXE, 0);
640 if (!ret && !slave)
641 ret = sh_msiof_modify_ctr_wait(p, CTR_TSCKE, 0);
642
643 return ret;
644 }
645
646 static int sh_msiof_slave_abort(struct spi_master *master)
647 {
648 struct sh_msiof_spi_priv *p = spi_master_get_devdata(master);
649
650 p->slave_aborted = true;
651 complete(&p->done);
652 return 0;
653 }
654
655 static int sh_msiof_wait_for_completion(struct sh_msiof_spi_priv *p)
656 {
657 if (spi_controller_is_slave(p->master)) {
658 if (wait_for_completion_interruptible(&p->done) ||
659 p->slave_aborted) {
660 dev_dbg(&p->pdev->dev, "interrupted\n");
661 return -EINTR;
662 }
663 } else {
664 if (!wait_for_completion_timeout(&p->done, HZ)) {
665 dev_err(&p->pdev->dev, "timeout\n");
666 return -ETIMEDOUT;
667 }
668 }
669
670 return 0;
671 }
672
673 static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p,
674 void (*tx_fifo)(struct sh_msiof_spi_priv *,
675 const void *, int, int),
676 void (*rx_fifo)(struct sh_msiof_spi_priv *,
677 void *, int, int),
678 const void *tx_buf, void *rx_buf,
679 int words, int bits)
680 {
681 int fifo_shift;
682 int ret;
683
684 /* limit maximum word transfer to rx/tx fifo size */
685 if (tx_buf)
686 words = min_t(int, words, p->tx_fifo_size);
687 if (rx_buf)
688 words = min_t(int, words, p->rx_fifo_size);
689
690 /* the fifo contents need shifting */
691 fifo_shift = 32 - bits;
692
693 /* default FIFO watermarks for PIO */
694 sh_msiof_write(p, FCTR, 0);
695
696 /* setup msiof transfer mode registers */
697 sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words);
698 sh_msiof_write(p, IER, IER_TEOFE | IER_REOFE);
699
700 /* write tx fifo */
701 if (tx_buf)
702 tx_fifo(p, tx_buf, words, fifo_shift);
703
704 reinit_completion(&p->done);
705 p->slave_aborted = false;
706
707 ret = sh_msiof_spi_start(p, rx_buf);
708 if (ret) {
709 dev_err(&p->pdev->dev, "failed to start hardware\n");
710 goto stop_ier;
711 }
712
713 /* wait for tx fifo to be emptied / rx fifo to be filled */
714 ret = sh_msiof_wait_for_completion(p);
715 if (ret)
716 goto stop_reset;
717
718 /* read rx fifo */
719 if (rx_buf)
720 rx_fifo(p, rx_buf, words, fifo_shift);
721
722 /* clear status bits */
723 sh_msiof_reset_str(p);
724
725 ret = sh_msiof_spi_stop(p, rx_buf);
726 if (ret) {
727 dev_err(&p->pdev->dev, "failed to shut down hardware\n");
728 return ret;
729 }
730
731 return words;
732
733 stop_reset:
734 sh_msiof_reset_str(p);
735 sh_msiof_spi_stop(p, rx_buf);
736 stop_ier:
737 sh_msiof_write(p, IER, 0);
738 return ret;
739 }
740
741 static void sh_msiof_dma_complete(void *arg)
742 {
743 struct sh_msiof_spi_priv *p = arg;
744
745 sh_msiof_write(p, IER, 0);
746 complete(&p->done);
747 }
748
749 static int sh_msiof_dma_once(struct sh_msiof_spi_priv *p, const void *tx,
750 void *rx, unsigned int len)
751 {
752 u32 ier_bits = 0;
753 struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL;
754 dma_cookie_t cookie;
755 int ret;
756
757 /* First prepare and submit the DMA request(s), as this may fail */
758 if (rx) {
759 ier_bits |= IER_RDREQE | IER_RDMAE;
760 desc_rx = dmaengine_prep_slave_single(p->master->dma_rx,
761 p->rx_dma_addr, len, DMA_DEV_TO_MEM,
762 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
763 if (!desc_rx)
764 return -EAGAIN;
765
766 desc_rx->callback = sh_msiof_dma_complete;
767 desc_rx->callback_param = p;
768 cookie = dmaengine_submit(desc_rx);
769 if (dma_submit_error(cookie))
770 return cookie;
771 }
772
773 if (tx) {
774 ier_bits |= IER_TDREQE | IER_TDMAE;
775 dma_sync_single_for_device(p->master->dma_tx->device->dev,
776 p->tx_dma_addr, len, DMA_TO_DEVICE);
777 desc_tx = dmaengine_prep_slave_single(p->master->dma_tx,
778 p->tx_dma_addr, len, DMA_MEM_TO_DEV,
779 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
780 if (!desc_tx) {
781 ret = -EAGAIN;
782 goto no_dma_tx;
783 }
784
785 if (rx) {
786 /* No callback */
787 desc_tx->callback = NULL;
788 } else {
789 desc_tx->callback = sh_msiof_dma_complete;
790 desc_tx->callback_param = p;
791 }
792 cookie = dmaengine_submit(desc_tx);
793 if (dma_submit_error(cookie)) {
794 ret = cookie;
795 goto no_dma_tx;
796 }
797 }
798
799 /* 1 stage FIFO watermarks for DMA */
800 sh_msiof_write(p, FCTR, FCTR_TFWM_1 | FCTR_RFWM_1);
801
802 /* setup msiof transfer mode registers (32-bit words) */
803 sh_msiof_spi_set_mode_regs(p, tx, rx, 32, len / 4);
804
805 sh_msiof_write(p, IER, ier_bits);
806
807 reinit_completion(&p->done);
808 p->slave_aborted = false;
809
810 /* Now start DMA */
811 if (rx)
812 dma_async_issue_pending(p->master->dma_rx);
813 if (tx)
814 dma_async_issue_pending(p->master->dma_tx);
815
816 ret = sh_msiof_spi_start(p, rx);
817 if (ret) {
818 dev_err(&p->pdev->dev, "failed to start hardware\n");
819 goto stop_dma;
820 }
821
822 /* wait for tx/rx DMA completion */
823 ret = sh_msiof_wait_for_completion(p);
824 if (ret)
825 goto stop_reset;
826
827 if (!rx) {
828 reinit_completion(&p->done);
829 sh_msiof_write(p, IER, IER_TEOFE);
830
831 /* wait for tx fifo to be emptied */
832 ret = sh_msiof_wait_for_completion(p);
833 if (ret)
834 goto stop_reset;
835 }
836
837 /* clear status bits */
838 sh_msiof_reset_str(p);
839
840 ret = sh_msiof_spi_stop(p, rx);
841 if (ret) {
842 dev_err(&p->pdev->dev, "failed to shut down hardware\n");
843 return ret;
844 }
845
846 if (rx)
847 dma_sync_single_for_cpu(p->master->dma_rx->device->dev,
848 p->rx_dma_addr, len,
849 DMA_FROM_DEVICE);
850
851 return 0;
852
853 stop_reset:
854 sh_msiof_reset_str(p);
855 sh_msiof_spi_stop(p, rx);
856 stop_dma:
857 if (tx)
858 dmaengine_terminate_all(p->master->dma_tx);
859 no_dma_tx:
860 if (rx)
861 dmaengine_terminate_all(p->master->dma_rx);
862 sh_msiof_write(p, IER, 0);
863 return ret;
864 }
865
866 static void copy_bswap32(u32 *dst, const u32 *src, unsigned int words)
867 {
868 /* src or dst can be unaligned, but not both */
869 if ((unsigned long)src & 3) {
870 while (words--) {
871 *dst++ = swab32(get_unaligned(src));
872 src++;
873 }
874 } else if ((unsigned long)dst & 3) {
875 while (words--) {
876 put_unaligned(swab32(*src++), dst);
877 dst++;
878 }
879 } else {
880 while (words--)
881 *dst++ = swab32(*src++);
882 }
883 }
884
885 static void copy_wswap32(u32 *dst, const u32 *src, unsigned int words)
886 {
887 /* src or dst can be unaligned, but not both */
888 if ((unsigned long)src & 3) {
889 while (words--) {
890 *dst++ = swahw32(get_unaligned(src));
891 src++;
892 }
893 } else if ((unsigned long)dst & 3) {
894 while (words--) {
895 put_unaligned(swahw32(*src++), dst);
896 dst++;
897 }
898 } else {
899 while (words--)
900 *dst++ = swahw32(*src++);
901 }
902 }
903
904 static void copy_plain32(u32 *dst, const u32 *src, unsigned int words)
905 {
906 memcpy(dst, src, words * 4);
907 }
908
909 static int sh_msiof_transfer_one(struct spi_master *master,
910 struct spi_device *spi,
911 struct spi_transfer *t)
912 {
913 struct sh_msiof_spi_priv *p = spi_master_get_devdata(master);
914 void (*copy32)(u32 *, const u32 *, unsigned int);
915 void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int);
916 void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int);
917 const void *tx_buf = t->tx_buf;
918 void *rx_buf = t->rx_buf;
919 unsigned int len = t->len;
920 unsigned int bits = t->bits_per_word;
921 unsigned int bytes_per_word;
922 unsigned int words;
923 int n;
924 bool swab;
925 int ret;
926
927 /* setup clocks (clock already enabled in chipselect()) */
928 if (!spi_controller_is_slave(p->master))
929 sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk), t->speed_hz);
930
931 while (master->dma_tx && len > 15) {
932 /*
933 * DMA supports 32-bit words only, hence pack 8-bit and 16-bit
934 * words, with byte resp. word swapping.
935 */
936 unsigned int l = 0;
937
938 if (tx_buf)
939 l = min(len, p->tx_fifo_size * 4);
940 if (rx_buf)
941 l = min(len, p->rx_fifo_size * 4);
942
943 if (bits <= 8) {
944 if (l & 3)
945 break;
946 copy32 = copy_bswap32;
947 } else if (bits <= 16) {
948 if (l & 3)
949 break;
950 copy32 = copy_wswap32;
951 } else {
952 copy32 = copy_plain32;
953 }
954
955 if (tx_buf)
956 copy32(p->tx_dma_page, tx_buf, l / 4);
957
958 ret = sh_msiof_dma_once(p, tx_buf, rx_buf, l);
959 if (ret == -EAGAIN) {
960 dev_warn_once(&p->pdev->dev,
961 "DMA not available, falling back to PIO\n");
962 break;
963 }
964 if (ret)
965 return ret;
966
967 if (rx_buf) {
968 copy32(rx_buf, p->rx_dma_page, l / 4);
969 rx_buf += l;
970 }
971 if (tx_buf)
972 tx_buf += l;
973
974 len -= l;
975 if (!len)
976 return 0;
977 }
978
979 if (bits <= 8 && len > 15 && !(len & 3)) {
980 bits = 32;
981 swab = true;
982 } else {
983 swab = false;
984 }
985
986 /* setup bytes per word and fifo read/write functions */
987 if (bits <= 8) {
988 bytes_per_word = 1;
989 tx_fifo = sh_msiof_spi_write_fifo_8;
990 rx_fifo = sh_msiof_spi_read_fifo_8;
991 } else if (bits <= 16) {
992 bytes_per_word = 2;
993 if ((unsigned long)tx_buf & 0x01)
994 tx_fifo = sh_msiof_spi_write_fifo_16u;
995 else
996 tx_fifo = sh_msiof_spi_write_fifo_16;
997
998 if ((unsigned long)rx_buf & 0x01)
999 rx_fifo = sh_msiof_spi_read_fifo_16u;
1000 else
1001 rx_fifo = sh_msiof_spi_read_fifo_16;
1002 } else if (swab) {
1003 bytes_per_word = 4;
1004 if ((unsigned long)tx_buf & 0x03)
1005 tx_fifo = sh_msiof_spi_write_fifo_s32u;
1006 else
1007 tx_fifo = sh_msiof_spi_write_fifo_s32;
1008
1009 if ((unsigned long)rx_buf & 0x03)
1010 rx_fifo = sh_msiof_spi_read_fifo_s32u;
1011 else
1012 rx_fifo = sh_msiof_spi_read_fifo_s32;
1013 } else {
1014 bytes_per_word = 4;
1015 if ((unsigned long)tx_buf & 0x03)
1016 tx_fifo = sh_msiof_spi_write_fifo_32u;
1017 else
1018 tx_fifo = sh_msiof_spi_write_fifo_32;
1019
1020 if ((unsigned long)rx_buf & 0x03)
1021 rx_fifo = sh_msiof_spi_read_fifo_32u;
1022 else
1023 rx_fifo = sh_msiof_spi_read_fifo_32;
1024 }
1025
1026 /* transfer in fifo sized chunks */
1027 words = len / bytes_per_word;
1028
1029 while (words > 0) {
1030 n = sh_msiof_spi_txrx_once(p, tx_fifo, rx_fifo, tx_buf, rx_buf,
1031 words, bits);
1032 if (n < 0)
1033 return n;
1034
1035 if (tx_buf)
1036 tx_buf += n * bytes_per_word;
1037 if (rx_buf)
1038 rx_buf += n * bytes_per_word;
1039 words -= n;
1040 }
1041
1042 return 0;
1043 }
1044
1045 static const struct sh_msiof_chipdata sh_data = {
1046 .tx_fifo_size = 64,
1047 .rx_fifo_size = 64,
1048 .master_flags = 0,
1049 .min_div_pow = 0,
1050 };
1051
1052 static const struct sh_msiof_chipdata rcar_gen2_data = {
1053 .tx_fifo_size = 64,
1054 .rx_fifo_size = 64,
1055 .master_flags = SPI_MASTER_MUST_TX,
1056 .min_div_pow = 0,
1057 };
1058
1059 static const struct sh_msiof_chipdata rcar_gen3_data = {
1060 .tx_fifo_size = 64,
1061 .rx_fifo_size = 64,
1062 .master_flags = SPI_MASTER_MUST_TX,
1063 .min_div_pow = 1,
1064 };
1065
1066 static const struct of_device_id sh_msiof_match[] = {
1067 { .compatible = "renesas,sh-mobile-msiof", .data = &sh_data },
1068 { .compatible = "renesas,msiof-r8a7743", .data = &rcar_gen2_data },
1069 { .compatible = "renesas,msiof-r8a7745", .data = &rcar_gen2_data },
1070 { .compatible = "renesas,msiof-r8a7790", .data = &rcar_gen2_data },
1071 { .compatible = "renesas,msiof-r8a7791", .data = &rcar_gen2_data },
1072 { .compatible = "renesas,msiof-r8a7792", .data = &rcar_gen2_data },
1073 { .compatible = "renesas,msiof-r8a7793", .data = &rcar_gen2_data },
1074 { .compatible = "renesas,msiof-r8a7794", .data = &rcar_gen2_data },
1075 { .compatible = "renesas,rcar-gen2-msiof", .data = &rcar_gen2_data },
1076 { .compatible = "renesas,msiof-r8a7796", .data = &rcar_gen3_data },
1077 { .compatible = "renesas,rcar-gen3-msiof", .data = &rcar_gen3_data },
1078 { .compatible = "renesas,sh-msiof", .data = &sh_data }, /* Deprecated */
1079 {},
1080 };
1081 MODULE_DEVICE_TABLE(of, sh_msiof_match);
1082
1083 #ifdef CONFIG_OF
1084 static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev)
1085 {
1086 struct sh_msiof_spi_info *info;
1087 struct device_node *np = dev->of_node;
1088 u32 num_cs = 1;
1089
1090 info = devm_kzalloc(dev, sizeof(struct sh_msiof_spi_info), GFP_KERNEL);
1091 if (!info)
1092 return NULL;
1093
1094 info->mode = of_property_read_bool(np, "spi-slave") ? MSIOF_SPI_SLAVE
1095 : MSIOF_SPI_MASTER;
1096
1097 /* Parse the MSIOF properties */
1098 if (info->mode == MSIOF_SPI_MASTER)
1099 of_property_read_u32(np, "num-cs", &num_cs);
1100 of_property_read_u32(np, "renesas,tx-fifo-size",
1101 &info->tx_fifo_override);
1102 of_property_read_u32(np, "renesas,rx-fifo-size",
1103 &info->rx_fifo_override);
1104 of_property_read_u32(np, "renesas,dtdl", &info->dtdl);
1105 of_property_read_u32(np, "renesas,syncdl", &info->syncdl);
1106
1107 info->num_chipselect = num_cs;
1108
1109 return info;
1110 }
1111 #else
1112 static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev)
1113 {
1114 return NULL;
1115 }
1116 #endif
1117
1118 static int sh_msiof_get_cs_gpios(struct sh_msiof_spi_priv *p)
1119 {
1120 struct device *dev = &p->pdev->dev;
1121 unsigned int used_ss_mask = 0;
1122 unsigned int cs_gpios = 0;
1123 unsigned int num_cs, i;
1124 int ret;
1125
1126 ret = gpiod_count(dev, "cs");
1127 if (ret <= 0)
1128 return 0;
1129
1130 num_cs = max_t(unsigned int, ret, p->master->num_chipselect);
1131 for (i = 0; i < num_cs; i++) {
1132 struct gpio_desc *gpiod;
1133
1134 gpiod = devm_gpiod_get_index(dev, "cs", i, GPIOD_ASIS);
1135 if (!IS_ERR(gpiod)) {
1136 cs_gpios++;
1137 continue;
1138 }
1139
1140 if (PTR_ERR(gpiod) != -ENOENT)
1141 return PTR_ERR(gpiod);
1142
1143 if (i >= MAX_SS) {
1144 dev_err(dev, "Invalid native chip select %d\n", i);
1145 return -EINVAL;
1146 }
1147 used_ss_mask |= BIT(i);
1148 }
1149 p->unused_ss = ffz(used_ss_mask);
1150 if (cs_gpios && p->unused_ss >= MAX_SS) {
1151 dev_err(dev, "No unused native chip select available\n");
1152 return -EINVAL;
1153 }
1154 return 0;
1155 }
1156
1157 static struct dma_chan *sh_msiof_request_dma_chan(struct device *dev,
1158 enum dma_transfer_direction dir, unsigned int id, dma_addr_t port_addr)
1159 {
1160 dma_cap_mask_t mask;
1161 struct dma_chan *chan;
1162 struct dma_slave_config cfg;
1163 int ret;
1164
1165 dma_cap_zero(mask);
1166 dma_cap_set(DMA_SLAVE, mask);
1167
1168 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
1169 (void *)(unsigned long)id, dev,
1170 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1171 if (!chan) {
1172 dev_warn(dev, "dma_request_slave_channel_compat failed\n");
1173 return NULL;
1174 }
1175
1176 memset(&cfg, 0, sizeof(cfg));
1177 cfg.direction = dir;
1178 if (dir == DMA_MEM_TO_DEV) {
1179 cfg.dst_addr = port_addr;
1180 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1181 } else {
1182 cfg.src_addr = port_addr;
1183 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1184 }
1185
1186 ret = dmaengine_slave_config(chan, &cfg);
1187 if (ret) {
1188 dev_warn(dev, "dmaengine_slave_config failed %d\n", ret);
1189 dma_release_channel(chan);
1190 return NULL;
1191 }
1192
1193 return chan;
1194 }
1195
1196 static int sh_msiof_request_dma(struct sh_msiof_spi_priv *p)
1197 {
1198 struct platform_device *pdev = p->pdev;
1199 struct device *dev = &pdev->dev;
1200 const struct sh_msiof_spi_info *info = dev_get_platdata(dev);
1201 unsigned int dma_tx_id, dma_rx_id;
1202 const struct resource *res;
1203 struct spi_master *master;
1204 struct device *tx_dev, *rx_dev;
1205
1206 if (dev->of_node) {
1207 /* In the OF case we will get the slave IDs from the DT */
1208 dma_tx_id = 0;
1209 dma_rx_id = 0;
1210 } else if (info && info->dma_tx_id && info->dma_rx_id) {
1211 dma_tx_id = info->dma_tx_id;
1212 dma_rx_id = info->dma_rx_id;
1213 } else {
1214 /* The driver assumes no error */
1215 return 0;
1216 }
1217
1218 /* The DMA engine uses the second register set, if present */
1219 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1220 if (!res)
1221 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1222
1223 master = p->master;
1224 master->dma_tx = sh_msiof_request_dma_chan(dev, DMA_MEM_TO_DEV,
1225 dma_tx_id,
1226 res->start + TFDR);
1227 if (!master->dma_tx)
1228 return -ENODEV;
1229
1230 master->dma_rx = sh_msiof_request_dma_chan(dev, DMA_DEV_TO_MEM,
1231 dma_rx_id,
1232 res->start + RFDR);
1233 if (!master->dma_rx)
1234 goto free_tx_chan;
1235
1236 p->tx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
1237 if (!p->tx_dma_page)
1238 goto free_rx_chan;
1239
1240 p->rx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
1241 if (!p->rx_dma_page)
1242 goto free_tx_page;
1243
1244 tx_dev = master->dma_tx->device->dev;
1245 p->tx_dma_addr = dma_map_single(tx_dev, p->tx_dma_page, PAGE_SIZE,
1246 DMA_TO_DEVICE);
1247 if (dma_mapping_error(tx_dev, p->tx_dma_addr))
1248 goto free_rx_page;
1249
1250 rx_dev = master->dma_rx->device->dev;
1251 p->rx_dma_addr = dma_map_single(rx_dev, p->rx_dma_page, PAGE_SIZE,
1252 DMA_FROM_DEVICE);
1253 if (dma_mapping_error(rx_dev, p->rx_dma_addr))
1254 goto unmap_tx_page;
1255
1256 dev_info(dev, "DMA available");
1257 return 0;
1258
1259 unmap_tx_page:
1260 dma_unmap_single(tx_dev, p->tx_dma_addr, PAGE_SIZE, DMA_TO_DEVICE);
1261 free_rx_page:
1262 free_page((unsigned long)p->rx_dma_page);
1263 free_tx_page:
1264 free_page((unsigned long)p->tx_dma_page);
1265 free_rx_chan:
1266 dma_release_channel(master->dma_rx);
1267 free_tx_chan:
1268 dma_release_channel(master->dma_tx);
1269 master->dma_tx = NULL;
1270 return -ENODEV;
1271 }
1272
1273 static void sh_msiof_release_dma(struct sh_msiof_spi_priv *p)
1274 {
1275 struct spi_master *master = p->master;
1276
1277 if (!master->dma_tx)
1278 return;
1279
1280 dma_unmap_single(master->dma_rx->device->dev, p->rx_dma_addr,
1281 PAGE_SIZE, DMA_FROM_DEVICE);
1282 dma_unmap_single(master->dma_tx->device->dev, p->tx_dma_addr,
1283 PAGE_SIZE, DMA_TO_DEVICE);
1284 free_page((unsigned long)p->rx_dma_page);
1285 free_page((unsigned long)p->tx_dma_page);
1286 dma_release_channel(master->dma_rx);
1287 dma_release_channel(master->dma_tx);
1288 }
1289
1290 static int sh_msiof_spi_probe(struct platform_device *pdev)
1291 {
1292 struct resource *r;
1293 struct spi_master *master;
1294 const struct sh_msiof_chipdata *chipdata;
1295 struct sh_msiof_spi_info *info;
1296 struct sh_msiof_spi_priv *p;
1297 int i;
1298 int ret;
1299
1300 chipdata = of_device_get_match_data(&pdev->dev);
1301 if (chipdata) {
1302 info = sh_msiof_spi_parse_dt(&pdev->dev);
1303 } else {
1304 chipdata = (const void *)pdev->id_entry->driver_data;
1305 info = dev_get_platdata(&pdev->dev);
1306 }
1307
1308 if (!info) {
1309 dev_err(&pdev->dev, "failed to obtain device info\n");
1310 return -ENXIO;
1311 }
1312
1313 if (info->mode == MSIOF_SPI_SLAVE)
1314 master = spi_alloc_slave(&pdev->dev,
1315 sizeof(struct sh_msiof_spi_priv));
1316 else
1317 master = spi_alloc_master(&pdev->dev,
1318 sizeof(struct sh_msiof_spi_priv));
1319 if (master == NULL)
1320 return -ENOMEM;
1321
1322 p = spi_master_get_devdata(master);
1323
1324 platform_set_drvdata(pdev, p);
1325 p->master = master;
1326 p->info = info;
1327 p->min_div_pow = chipdata->min_div_pow;
1328
1329 init_completion(&p->done);
1330
1331 p->clk = devm_clk_get(&pdev->dev, NULL);
1332 if (IS_ERR(p->clk)) {
1333 dev_err(&pdev->dev, "cannot get clock\n");
1334 ret = PTR_ERR(p->clk);
1335 goto err1;
1336 }
1337
1338 i = platform_get_irq(pdev, 0);
1339 if (i < 0) {
1340 dev_err(&pdev->dev, "cannot get platform IRQ\n");
1341 ret = -ENOENT;
1342 goto err1;
1343 }
1344
1345 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1346 p->mapbase = devm_ioremap_resource(&pdev->dev, r);
1347 if (IS_ERR(p->mapbase)) {
1348 ret = PTR_ERR(p->mapbase);
1349 goto err1;
1350 }
1351
1352 ret = devm_request_irq(&pdev->dev, i, sh_msiof_spi_irq, 0,
1353 dev_name(&pdev->dev), p);
1354 if (ret) {
1355 dev_err(&pdev->dev, "unable to request irq\n");
1356 goto err1;
1357 }
1358
1359 p->pdev = pdev;
1360 pm_runtime_enable(&pdev->dev);
1361
1362 /* Platform data may override FIFO sizes */
1363 p->tx_fifo_size = chipdata->tx_fifo_size;
1364 p->rx_fifo_size = chipdata->rx_fifo_size;
1365 if (p->info->tx_fifo_override)
1366 p->tx_fifo_size = p->info->tx_fifo_override;
1367 if (p->info->rx_fifo_override)
1368 p->rx_fifo_size = p->info->rx_fifo_override;
1369
1370 /* Setup GPIO chip selects */
1371 master->num_chipselect = p->info->num_chipselect;
1372 ret = sh_msiof_get_cs_gpios(p);
1373 if (ret)
1374 goto err1;
1375
1376 /* init master code */
1377 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1378 master->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE;
1379 master->flags = chipdata->master_flags;
1380 master->bus_num = pdev->id;
1381 master->dev.of_node = pdev->dev.of_node;
1382 master->setup = sh_msiof_spi_setup;
1383 master->prepare_message = sh_msiof_prepare_message;
1384 master->slave_abort = sh_msiof_slave_abort;
1385 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32);
1386 master->auto_runtime_pm = true;
1387 master->transfer_one = sh_msiof_transfer_one;
1388
1389 ret = sh_msiof_request_dma(p);
1390 if (ret < 0)
1391 dev_warn(&pdev->dev, "DMA not available, using PIO\n");
1392
1393 ret = devm_spi_register_master(&pdev->dev, master);
1394 if (ret < 0) {
1395 dev_err(&pdev->dev, "spi_register_master error.\n");
1396 goto err2;
1397 }
1398
1399 return 0;
1400
1401 err2:
1402 sh_msiof_release_dma(p);
1403 pm_runtime_disable(&pdev->dev);
1404 err1:
1405 spi_master_put(master);
1406 return ret;
1407 }
1408
1409 static int sh_msiof_spi_remove(struct platform_device *pdev)
1410 {
1411 struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev);
1412
1413 sh_msiof_release_dma(p);
1414 pm_runtime_disable(&pdev->dev);
1415 return 0;
1416 }
1417
1418 static const struct platform_device_id spi_driver_ids[] = {
1419 { "spi_sh_msiof", (kernel_ulong_t)&sh_data },
1420 {},
1421 };
1422 MODULE_DEVICE_TABLE(platform, spi_driver_ids);
1423
1424 static struct platform_driver sh_msiof_spi_drv = {
1425 .probe = sh_msiof_spi_probe,
1426 .remove = sh_msiof_spi_remove,
1427 .id_table = spi_driver_ids,
1428 .driver = {
1429 .name = "spi_sh_msiof",
1430 .of_match_table = of_match_ptr(sh_msiof_match),
1431 },
1432 };
1433 module_platform_driver(sh_msiof_spi_drv);
1434
1435 MODULE_DESCRIPTION("SuperH MSIOF SPI Master Interface Driver");
1436 MODULE_AUTHOR("Magnus Damm");
1437 MODULE_LICENSE("GPL v2");
1438 MODULE_ALIAS("platform:spi_sh_msiof");
Linux with added FPC-III support