arch/arm/boot/dts/imx6q-dhcom-pdk2.dts

   1 // SPDX-License-Identifier: (GPL-2.0+)
   2 /*
   3  * Copyright (C) 2015 DH electronics GmbH
   4  * Copyright (C) 2018 Marek Vasut <marex@denx.de>
   5  */
   6
   7 /dts-v1/;
   8
   9 #include "imx6q-dhcom-som.dtsi"
  10
  11 / {
  12         model = "Freescale i.MX6 Quad DHCOM Premium Developer Kit (2)";
  13         compatible = "dh,imx6q-dhcom-pdk2", "dh,imx6q-dhcom-som", "fsl,imx6q";
  14
  15         chosen {
  16                 stdout-path = &uart1;
  17         };
  18
  19         clk_ext_audio_codec: clock-codec {
  20                 compatible = "fixed-clock";
  21                 #clock-cells = <0>;
  22                 clock-frequency = <24000000>;
  23         };
  24
  25         sound {
  26                 compatible = "fsl,imx-audio-sgtl5000";
  27                 model = "imx-sgtl5000";
  28                 ssi-controller = <&ssi1>;
  29                 audio-codec = <&sgtl5000>;
  30                 audio-routing =
  31                         "MIC_IN", "Mic Jack",
  32                         "Mic Jack", "Mic Bias",
  33                         "LINE_IN", "Line In Jack",
  34                         "Headphone Jack", "HP_OUT";
  35                 mux-int-port = <1>;
  36                 mux-ext-port = <3>;
  37         };
  38 };
  39
  40 &audmux {
  41         pinctrl-names = "default";
  42         pinctrl-0 = <&pinctrl_audmux_ext>;
  43         status = "okay";
  44 };
  45
  46 &can1 {
  47         status = "okay";
  48 };
  49
  50 &can2 {
  51         status = "disabled";
  52 };
  53
  54 &hdmi {
  55         ddc-i2c-bus = <&i2c2>;
  56         status = "okay";
  57 };
  58
  59 &i2c2 {
  60         sgtl5000: codec@a {
  61                 compatible = "fsl,sgtl5000";
  62                 reg = <0x0a>;
  63                 #sound-dai-cells = <0>;
  64                 clocks = <&clk_ext_audio_codec>;
  65                 VDDA-supply = <&reg_3p3v>;
  66                 VDDIO-supply = <&sw2_reg>;
  67         };
  68 };
  69
  70 &iomuxc {
  71         pinctrl-names = "default";
  72         pinctrl-0 = <&pinctrl_hog_base &pinctrl_hog>;
  73
  74         pinctrl_hog: hog-grp {
  75                 fsl,pins = <
  76                         MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x400120b0
  77                         MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x400120b0
  78                         MX6QDL_PAD_GPIO_5__GPIO1_IO05           0x400120b0
  79                         MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03       0x400120b0
  80                         MX6QDL_PAD_GPIO_19__GPIO4_IO05          0x120b0
  81                         MX6QDL_PAD_DI0_PIN4__GPIO4_IO20         0x400120b0
  82                         MX6QDL_PAD_EIM_D27__GPIO3_IO27          0x120b0
  83                         MX6QDL_PAD_KEY_ROW0__GPIO4_IO07         0x120b0
  84                         MX6QDL_PAD_KEY_COL1__GPIO4_IO08         0x400120b0
  85                         MX6QDL_PAD_NANDF_CS1__GPIO6_IO14        0x400120b0
  86                         MX6QDL_PAD_NANDF_CS2__GPIO6_IO15        0x400120b0
  87                         MX6QDL_PAD_KEY_ROW1__GPIO4_IO09         0x400120b0
  88                         MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x400120b0
  89                         MX6QDL_PAD_SD3_DAT4__GPIO7_IO01         0x400120b0
  90                         MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21       0x400120b0
  91                         MX6QDL_PAD_GPIO_18__GPIO7_IO13          0x400120b0
  92                         MX6QDL_PAD_SD1_CMD__GPIO1_IO18          0x400120b0
  93                         MX6QDL_PAD_SD1_DAT0__GPIO1_IO16         0x400120b0
  94                         MX6QDL_PAD_SD1_DAT1__GPIO1_IO17         0x400120b0
  95                         MX6QDL_PAD_SD1_DAT2__GPIO1_IO19         0x400120b0
  96                         MX6QDL_PAD_SD1_CLK__GPIO1_IO20          0x400120b0
  97                         MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18      0x400120b0
  98                         MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19        0x400120b0
  99                         MX6QDL_PAD_KEY_COL0__GPIO4_IO06         0x400120b0
 100                 >;
 101         };
 102
 103         pinctrl_audmux_ext: audmux-ext-grp {
 104                 fsl,pins = <
 105                         MX6QDL_PAD_CSI0_DAT7__AUD3_RXD          0x130b0
 106                         MX6QDL_PAD_CSI0_DAT4__AUD3_TXC          0x130b0
 107                         MX6QDL_PAD_CSI0_DAT5__AUD3_TXD          0x110b0
 108                         MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS         0x130b0
 109                 >;
 110         };
 111
 112         pinctrl_enet_1G: enet-1G-grp {
 113                 fsl,pins = <
 114                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x100b0
 115                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x100b0
 116                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x100b0
 117                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x100b0
 118                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x100b0
 119                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x100b0
 120                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x100b0
 121                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x100b0
 122                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x100b0
 123                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
 124                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
 125                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
 126                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
 127                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
 128                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
 129                         MX6QDL_PAD_EIM_D29__GPIO3_IO29          0x000b0
 130                         MX6QDL_PAD_GPIO_0__GPIO1_IO00           0x000b1
 131                         MX6QDL_PAD_EIM_D26__GPIO3_IO26          0x000b1
 132                 >;
 133         };
 134
 135         pinctrl_pcie: pcie-grp {
 136                 fsl,pins = <
 137                         MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20     0x1b0b1
 138                 >;
 139         };
 140 };
 141
 142 &pcie {
 143         pinctrl-names = "default";
 144         pinctrl-0 = <&pinctrl_pcie>;
 145         reset-gpio = <&gpio6 14 GPIO_ACTIVE_LOW>;
 146         status = "okay";
 147 };
 148
 149 &ssi1 {
 150         status = "okay";
 151 };
 152
 153 &sata {
 154         status = "okay";
 155 };
 156
 157 &usdhc3 {
 158         status = "okay";
 159 };