arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Copyright (C) 2016-2017 Zodiac Inflight Innovations
   4  */
   5
   6 #include <dt-bindings/gpio/gpio.h>
   7 #include <dt-bindings/sound/fsl-imx-audmux.h>
   8
   9 / {
  10         chosen {
  11                 stdout-path = &uart1;
  12         };
  13
  14         aliases {
  15                 mdio-gpio0 = &mdio1;
  16                 rtc0 = &ds1341;
  17         };
  18
  19         mdio1: mdio {
  20                 compatible = "virtual,mdio-gpio";
  21                 #address-cells = <1>;
  22                 #size-cells = <0>;
  23                 pinctrl-names = "default";
  24                 pinctrl-0 = <&pinctrl_mdio1>;
  25                 gpios = <&gpio6 5 GPIO_ACTIVE_HIGH
  26                          &gpio6 4 GPIO_ACTIVE_HIGH>;
  27
  28                 phy: ethernet-phy@0 {
  29                         pinctrl-0 = <&pinctrl_rmii_phy_irq>;
  30                         pinctrl-names = "default";
  31                         reg = <0>;
  32                         interrupt-parent = <&gpio3>;
  33                         interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
  34                 };
  35         };
  36
  37         reg_28p0v: regulator-28p0v {
  38                 compatible = "regulator-fixed";
  39                 regulator-name = "28V_IN";
  40                 regulator-min-microvolt = <28000000>;
  41                 regulator-max-microvolt = <28000000>;
  42                 regulator-always-on;
  43         };
  44
  45         reg_12p0v: regulator-12p0v {
  46                 compatible = "regulator-fixed";
  47                 vin-supply = <&reg_28p0v>;
  48                 regulator-name = "12V_MAIN";
  49                 regulator-min-microvolt = <12000000>;
  50                 regulator-max-microvolt = <12000000>;
  51                 regulator-always-on;
  52         };
  53
  54         reg_5p0v_main: regulator-5p0v-main {
  55                 compatible = "regulator-fixed";
  56                 vin-supply = <&reg_12p0v>;
  57                 regulator-name = "5V_MAIN";
  58                 regulator-min-microvolt = <5000000>;
  59                 regulator-max-microvolt = <5000000>;
  60                 regulator-always-on;
  61         };
  62
  63         reg_3p3v_pmic: regulator-3p3v-pmic {
  64                 compatible = "regulator-fixed";
  65                 vin-supply = <&reg_12p0v>;
  66                 regulator-name = "PMIC_3V3";
  67                 regulator-min-microvolt = <3300000>;
  68                 regulator-max-microvolt = <3300000>;
  69                 regulator-always-on;
  70         };
  71
  72         reg_3p3v: regulator-3p3v {
  73                 compatible = "regulator-fixed";
  74                 vin-supply = <&reg_3p3v_pmic>;
  75                 regulator-name = "GEN_3V3";
  76                 regulator-min-microvolt = <3300000>;
  77                 regulator-max-microvolt = <3300000>;
  78                 regulator-always-on;
  79         };
  80
  81         reg_3p3v_sd: regulator-3p3v-sd {
  82                 compatible = "regulator-fixed";
  83                 pinctrl-names = "default";
  84                 pinctrl-0 = <&pinctrl_reg_3p3v_sd>;
  85                 vin-supply = <&reg_3p3v>;
  86                 regulator-name = "3V3_SD";
  87                 regulator-min-microvolt = <3300000>;
  88                 regulator-max-microvolt = <3300000>;
  89                 gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>;
  90                 startup-delay-us = <1000>;
  91                 enable-active-high;
  92                 regulator-always-on;
  93         };
  94
  95         reg_3p3v_display: regulator-3p3v-display {
  96                 compatible = "regulator-fixed";
  97                 vin-supply = <&reg_12p0v>;
  98                 regulator-name = "3V3_DISPLAY";
  99                 regulator-min-microvolt = <3300000>;
 100                 regulator-max-microvolt = <3300000>;
 101                 regulator-always-on;
 102         };
 103
 104         reg_3p3v_ssd: regulator-3p3v-ssd {
 105                 compatible = "regulator-fixed";
 106                 vin-supply = <&reg_12p0v>;
 107                 regulator-name = "3V3_SSD";
 108                 regulator-min-microvolt = <3300000>;
 109                 regulator-max-microvolt = <3300000>;
 110                 regulator-always-on;
 111         };
 112
 113         sound1 {
 114                 compatible = "simple-audio-card";
 115                 simple-audio-card,name = "Front";
 116                 simple-audio-card,format = "i2s";
 117                 simple-audio-card,bitclock-master = <&sound1_codec>;
 118                 simple-audio-card,frame-master = <&sound1_codec>;
 119                 simple-audio-card,widgets =
 120                         "Headphone", "Headphone Jack";
 121                 simple-audio-card,routing =
 122                         "Headphone Jack", "HPLEFT",
 123                         "Headphone Jack", "HPRIGHT",
 124                         "LEFTIN", "HPL",
 125                         "RIGHTIN", "HPR";
 126                 simple-audio-card,aux-devs = <&hpa1>;
 127
 128                 sound1_cpu: simple-audio-card,cpu {
 129                         sound-dai = <&ssi2>;
 130                 };
 131
 132                 sound1_codec: simple-audio-card,codec {
 133                         sound-dai = <&codec1>;
 134                         clocks = <&cs2000>;
 135                 };
 136         };
 137
 138         sound2 {
 139                 compatible = "simple-audio-card";
 140                 simple-audio-card,name = "Back";
 141                 simple-audio-card,format = "i2s";
 142                 simple-audio-card,bitclock-master = <&sound2_codec>;
 143                 simple-audio-card,frame-master = <&sound2_codec>;
 144                 simple-audio-card,widgets =
 145                         "Headphone", "Headphone Jack";
 146                 simple-audio-card,routing =
 147                         "Headphone Jack", "HPLEFT",
 148                         "Headphone Jack", "HPRIGHT",
 149                         "LEFTIN", "HPL",
 150                         "RIGHTIN", "HPR";
 151                 simple-audio-card,aux-devs = <&hpa2>;
 152
 153                 sound2_cpu: simple-audio-card,cpu {
 154                         sound-dai = <&ssi1>;
 155                 };
 156
 157                 sound2_codec: simple-audio-card,codec {
 158                         sound-dai = <&codec2>;
 159                         clocks = <&cs2000>;
 160                 };
 161         };
 162
 163         panel {
 164                 power-supply = <&reg_3p3v_display>;
 165                 backlight = <&sp_backlight>;
 166                 status = "disabled";
 167
 168                 port {
 169                         panel_in: endpoint {
 170                                 remote-endpoint = <&lvds0_out>;
 171                         };
 172                 };
 173         };
 174
 175         disp0: disp0 {
 176                 #address-cells = <1>;
 177                 #size-cells = <0>;
 178                 compatible = "fsl,imx-parallel-display";
 179                 pinctrl-names = "default";
 180                 pinctrl-0 = <&pinctrl_disp0>;
 181                 status = "disabled";
 182
 183                 port@0 {
 184                         reg = <0>;
 185
 186                         disp0_in_0: endpoint {
 187                                 remote-endpoint = <&ipu1_di0_disp0>;
 188                         };
 189                 };
 190
 191                 port@1 {
 192                         reg = <1>;
 193
 194                         disp0_out: endpoint {
 195                                 remote-endpoint = <&tc358767_in>;
 196                         };
 197                 };
 198         };
 199
 200         cs2000_ref: cs2000-ref {
 201                 compatible = "fixed-clock";
 202                 #clock-cells = <0>;
 203                 clock-frequency = <24576000>;
 204         };
 205
 206         cs2000_in_dummy: cs2000-in-dummy {
 207                 compatible = "fixed-clock";
 208                 #clock-cells = <0>;
 209                 clock-frequency = <0>;
 210         };
 211
 212         edp_refclk: edp-refclk {
 213                 compatible = "fixed-clock";
 214                 #clock-cells = <0>;
 215                 clock-frequency = <19200000>;
 216         };
 217 };
 218
 219 &cpu0 {
 220         fsl,soc-operating-points = <
 221                 /* ARM kHz  SOC-PU uV */
 222                 1200000 1300000
 223                 996000  1275000
 224                 852000  1275000
 225                 792000  1200000
 226                 396000  1200000
 227         >;
 228 };
 229
 230 &reg_arm {
 231         vin-supply = <&sw1a_reg>;
 232 };
 233
 234 &reg_pu {
 235         vin-supply = <&sw1c_reg>;
 236 };
 237
 238 &reg_soc {
 239         vin-supply = <&sw1c_reg>;
 240 };
 241
 242 &ldb {
 243         lvds-channel@0 {
 244                 port@4 {
 245                         reg = <4>;
 246
 247                         lvds0_out: endpoint {
 248                                 remote-endpoint = <&panel_in>;
 249                         };
 250                 };
 251         };
 252 };
 253
 254 &uart1 {
 255         pinctrl-names = "default";
 256         pinctrl-0 = <&pinctrl_uart1>;
 257         status = "okay";
 258 };
 259
 260 &uart3 {
 261         pinctrl-names = "default";
 262         pinctrl-0 = <&pinctrl_uart3>;
 263         uart-has-rtscts;
 264         linux,rs485-enabled-at-boot-time;
 265         status = "okay";
 266 };
 267
 268 &uart4 {
 269         pinctrl-names = "default";
 270         pinctrl-0 = <&pinctrl_uart4>;
 271         status = "okay";
 272
 273         rave-sp {
 274                 compatible = "zii,rave-sp-rdu2";
 275                 current-speed = <1000000>;
 276                 #address-cells = <1>;
 277                 #size-cells = <1>;
 278
 279                 watchdog {
 280                         compatible = "zii,rave-sp-watchdog";
 281                 };
 282
 283                 sp_backlight: backlight {
 284                         compatible = "zii,rave-sp-backlight";
 285                 };
 286
 287                 pwrbutton {
 288                         compatible = "zii,rave-sp-pwrbutton";
 289                 };
 290
 291                 eeprom@a3 {
 292                         compatible = "zii,rave-sp-eeprom";
 293                         reg = <0xa3 0x4000>;
 294                         #address-cells = <1>;
 295                         #size-cells = <1>;
 296                         zii,eeprom-name = "dds-eeprom";
 297                 };
 298
 299                 eeprom@a4 {
 300                         compatible = "zii,rave-sp-eeprom";
 301                         reg = <0xa4 0x4000>;
 302                         #address-cells = <1>;
 303                         #size-cells = <1>;
 304                         zii,eeprom-name = "main-eeprom";
 305                 };
 306         };
 307 };
 308
 309 &ecspi1 {
 310         pinctrl-names = "default";
 311         pinctrl-0 = <&pinctrl_ecspi1>;
 312         cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>;
 313         status = "okay";
 314
 315         flash@0 {
 316                 compatible = "st,m25p128", "jedec,spi-nor";
 317                 spi-max-frequency = <20000000>;
 318                 reg = <0>;
 319         };
 320 };
 321
 322 &gpio3 {
 323         pinctrl-names = "default";
 324         pinctrl-0 = <&pinctrl_gpio3_hog>;
 325
 326         usb-emulation {
 327                 gpio-hog;
 328                 gpios = <19 GPIO_ACTIVE_HIGH>;
 329                 output-low;
 330                 line-name = "usb-emulation";
 331         };
 332
 333         usb-mode1 {
 334                 gpio-hog;
 335                 gpios = <20 GPIO_ACTIVE_HIGH>;
 336                 output-high;
 337                 line-name = "usb-mode1";
 338         };
 339
 340         usb-pwr {
 341                 gpio-hog;
 342                 gpios = <22 GPIO_ACTIVE_LOW>;
 343                 output-high;
 344                 line-name = "usb-pwr-ctrl-en-n";
 345         };
 346
 347         usb-mode2 {
 348                 gpio-hog;
 349                 gpios = <23 GPIO_ACTIVE_HIGH>;
 350                 output-high;
 351                 line-name = "usb-mode2";
 352         };
 353 };
 354
 355 &i2c1 {
 356         pinctrl-names = "default";
 357         pinctrl-0 = <&pinctrl_i2c1>;
 358         clock-frequency = <100000>;
 359         status = "okay";
 360
 361         codec2: codec@18 {
 362                 compatible = "ti,tlv320dac3100";
 363                 pinctrl-names = "default";
 364                 pinctrl-0 = <&pinctrl_codec2>;
 365                 reg = <0x18>;
 366                 #sound-dai-cells = <0>;
 367                 HPVDD-supply = <&reg_3p3v>;
 368                 SPRVDD-supply = <&reg_3p3v>;
 369                 SPLVDD-supply = <&reg_3p3v>;
 370                 AVDD-supply = <&reg_3p3v>;
 371                 IOVDD-supply = <&reg_3p3v>;
 372                 DVDD-supply = <&vgen4_reg>;
 373                 reset-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
 374         };
 375
 376         accel@1c {
 377                 pinctrl-names = "default";
 378                 pinctrl-0 = <&pinctrl_accel>;
 379                 compatible = "fsl,mma8451";
 380                 reg = <0x1c>;
 381                 interrupt-parent = <&gpio1>;
 382                 interrupt-names = "INT2";
 383                 interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
 384                 vdd-supply = <&reg_3p3v>;
 385                 vddio-supply = <&reg_3p3v>;
 386         };
 387
 388         hpa2: amp@60 {
 389                 compatible = "ti,tpa6130a2";
 390                 pinctrl-names = "default";
 391                 pinctrl-0 = <&pinctrl_tpa2>;
 392                 reg = <0x60>;
 393                 power-gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
 394                 Vdd-supply = <&reg_5p0v_main>;
 395         };
 396
 397         edp-bridge@68 {
 398                 compatible = "toshiba,tc358767";
 399                 pinctrl-names = "default";
 400                 pinctrl-0 = <&pinctrl_tc358767>;
 401                 reg = <0x68>;
 402                 shutdown-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
 403                 clock-names = "ref";
 404                 clocks = <&edp_refclk>;
 405                 status = "disabled";
 406
 407                 ports {
 408                         #address-cells = <1>;
 409                         #size-cells = <0>;
 410
 411                         port@1 {
 412                                 reg = <1>;
 413
 414                                 tc358767_in: endpoint {
 415                                         remote-endpoint = <&disp0_out>;
 416                                 };
 417                         };
 418                 };
 419         };
 420 };
 421
 422 &i2c2 {
 423         pinctrl-names = "default";
 424         pinctrl-0 = <&pinctrl_i2c2>;
 425         clock-frequency = <100000>;
 426         status = "okay";
 427
 428         pmic@8 {
 429                 compatible = "fsl,pfuze100";
 430                 pinctrl-names = "default";
 431                 pinctrl-0 = <&pinctrl_pfuze100_irq>;
 432                 reg = <0x08>;
 433                 interrupt-parent = <&gpio7>;
 434                 interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
 435
 436                 regulators {
 437                         sw1a_reg: sw1ab {
 438                                 regulator-min-microvolt = <300000>;
 439                                 regulator-max-microvolt = <1875000>;
 440                                 regulator-boot-on;
 441                                 regulator-always-on;
 442                                 regulator-ramp-delay = <6250>;
 443                         };
 444
 445                         sw1c_reg: sw1c {
 446                                 regulator-min-microvolt = <300000>;
 447                                 regulator-max-microvolt = <1875000>;
 448                                 regulator-boot-on;
 449                                 regulator-always-on;
 450                                 regulator-ramp-delay = <6250>;
 451                         };
 452
 453                         sw2_reg: sw2 {
 454                                 regulator-min-microvolt = <800000>;
 455                                 regulator-max-microvolt = <3000000>;
 456                                 regulator-boot-on;
 457                                 regulator-always-on;
 458                         };
 459
 460                         sw3a_reg: sw3a {
 461                                 regulator-min-microvolt = <400000>;
 462                                 regulator-max-microvolt = <1500000>;
 463                                 regulator-boot-on;
 464                                 regulator-always-on;
 465                         };
 466
 467                         sw3b_reg: sw3b {
 468                                 regulator-min-microvolt = <400000>;
 469                                 regulator-max-microvolt = <1500000>;
 470                                 regulator-boot-on;
 471                                 regulator-always-on;
 472                         };
 473
 474                         sw4_reg: sw4 {
 475                                 regulator-min-microvolt = <800000>;
 476                                 regulator-max-microvolt = <1800000>;
 477                                 regulator-boot-on;
 478                                 regulator-always-on;
 479                         };
 480
 481                         snvs_reg: vsnvs {
 482                                 regulator-min-microvolt = <1000000>;
 483                                 regulator-max-microvolt = <3000000>;
 484                                 regulator-boot-on;
 485                                 regulator-always-on;
 486                         };
 487
 488                         vref_reg: vrefddr {
 489                                 regulator-boot-on;
 490                                 regulator-always-on;
 491                         };
 492
 493                         vgen2_reg: vgen2 {
 494                                 regulator-min-microvolt = <1000000>;
 495                                 regulator-max-microvolt = <1500000>;
 496                                 regulator-always-on;
 497                         };
 498
 499                         vgen4_reg: vgen4 {
 500                                 regulator-min-microvolt = <1200000>;
 501                                 regulator-max-microvolt = <1800000>;
 502                                 regulator-always-on;
 503                         };
 504
 505                         vgen5_reg: vgen5 {
 506                                 regulator-min-microvolt = <1800000>;
 507                                 regulator-max-microvolt = <2500000>;
 508                                 regulator-always-on;
 509                         };
 510
 511                         vgen6_reg: vgen6 {
 512                                 regulator-min-microvolt = <1800000>;
 513                                 regulator-max-microvolt = <2800000>;
 514                                 regulator-always-on;
 515                         };
 516                 };
 517         };
 518
 519         watchdog@38 {
 520                 compatible = "zii,rave-wdt";
 521                 reg = <0x38>;
 522         };
 523
 524         temp-sense@48 {
 525                 compatible = "national,lm75";
 526                 reg = <0x48>;
 527         };
 528
 529         cs2000: clkgen@4e {
 530                 compatible = "cirrus,cs2000-cp";
 531                 reg = <0x4e>;
 532                 #clock-cells = <0>;
 533                 clock-names = "clk_in", "ref_clk";
 534                 clocks = <&cs2000_in_dummy>, <&cs2000_ref>;
 535                 assigned-clocks = <&cs2000>;
 536                 assigned-clock-rates = <24000000>;
 537         };
 538
 539         eeprom@54 {
 540                 compatible = "atmel,24c128";
 541                 reg = <0x54>;
 542         };
 543
 544         ds1341: rtc@68 {
 545                 compatible = "dallas,ds1341";
 546                 reg = <0x68>;
 547         };
 548 };
 549
 550 &i2c3 {
 551         pinctrl-names = "default";
 552         pinctrl-0 = <&pinctrl_i2c3>;
 553         clock-frequency = <400000>;
 554         status = "okay";
 555
 556         codec1: codec@18 {
 557                 compatible = "ti,tlv320dac3100";
 558                 pinctrl-names = "default";
 559                 pinctrl-0 = <&pinctrl_codec1>;
 560                 reg = <0x18>;
 561                 #sound-dai-cells = <0>;
 562                 HPVDD-supply = <&reg_3p3v>;
 563                 SPRVDD-supply = <&reg_3p3v>;
 564                 SPLVDD-supply = <&reg_3p3v>;
 565                 AVDD-supply = <&reg_3p3v>;
 566                 IOVDD-supply = <&reg_3p3v>;
 567                 DVDD-supply = <&vgen4_reg>;
 568                 reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
 569         };
 570
 571         touchscreen@20 {
 572                 compatible = "syna,rmi4-i2c";
 573                 pinctrl-names = "default";
 574                 pinctrl-0 = <&pinctrl_ts>;
 575                 reg = <0x20>;
 576                 interrupt-parent = <&gpio1>;
 577                 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
 578                 vdd-supply = <&reg_5p0v_main>;
 579                 vio-supply = <&reg_3p3v>;
 580
 581                 #address-cells = <1>;
 582                 #size-cells = <0>;
 583
 584                 rmi4-f01@1 {
 585                         reg = <0x1>;
 586                         syna,nosleep-mode = <2>;
 587                 };
 588
 589                 rmi4-f11@11 {
 590                         reg = <0x11>;
 591                         touchscreen-inverted-x;
 592                         touchscreen-swapped-x-y;
 593                         syna,sensor-type = <1>;
 594                 };
 595
 596                 rmi4-f12@12 {
 597                         reg = <0x12>;
 598                         touchscreen-inverted-x;
 599                         touchscreen-swapped-x-y;
 600                         syna,sensor-type = <1>;
 601                 };
 602         };
 603
 604         touchscreen@2a {
 605                 compatible = "eeti,exc3000";
 606                 pinctrl-names = "default";
 607                 pinctrl-0 = <&pinctrl_ts>;
 608                 reg = <0x2a>;
 609                 interrupt-parent = <&gpio1>;
 610                 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
 611                 touchscreen-inverted-x;
 612                 touchscreen-swapped-x-y;
 613                 status = "disabled";
 614         };
 615
 616         reg_5p0v_user_usb: charger@32 {
 617                 compatible = "microchip,ucs1002";
 618                 pinctrl-names = "default";
 619                 pinctrl-0 = <&pinctrl_ucs1002_pins>;
 620                 reg = <0x32>;
 621                 interrupts-extended = <&gpio5 2 IRQ_TYPE_EDGE_BOTH>,
 622                                       <&gpio3 21 IRQ_TYPE_EDGE_BOTH>;
 623                 interrupt-names = "a_det", "alert";
 624         };
 625
 626         hpa1: amp@60 {
 627                 compatible = "ti,tpa6130a2";
 628                 pinctrl-names = "default";
 629                 pinctrl-0 = <&pinctrl_tpa1>;
 630                 reg = <0x60>;
 631                 power-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
 632                 Vdd-supply = <&reg_5p0v_main>;
 633         };
 634 };
 635
 636 &ipu1_di0_disp0 {
 637         remote-endpoint = <&disp0_in_0>;
 638 };
 639
 640 &pcie {
 641         pinctrl-names = "default";
 642         pinctrl-0 = <&pinctrl_pcie>;
 643         reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
 644         status = "okay";
 645
 646         host@0 {
 647                 reg = <0 0 0 0 0>;
 648
 649                 #address-cells = <3>;
 650                 #size-cells = <2>;
 651
 652                 i210: i210@0 {
 653                         reg = <0 0 0 0 0>;
 654                 };
 655         };
 656 };
 657
 658 &usdhc2 {
 659         pinctrl-names = "default";
 660         pinctrl-0 = <&pinctrl_usdhc2>;
 661         bus-width = <4>;
 662         cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
 663         disable-wp;
 664         vmmc-supply = <&reg_3p3v_sd>;
 665         vqmmc-supply = <&reg_3p3v>;
 666         no-1-8-v;
 667         no-sdio;
 668         status = "okay";
 669 };
 670
 671 &usdhc3 {
 672         pinctrl-names = "default";
 673         pinctrl-0 = <&pinctrl_usdhc3>;
 674         bus-width = <4>;
 675         cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
 676         disable-wp;
 677         vmmc-supply = <&reg_3p3v_sd>;
 678         vqmmc-supply = <&reg_3p3v>;
 679         no-1-8-v;
 680         no-sdio;
 681         status = "okay";
 682 };
 683
 684 &usdhc4 {
 685         pinctrl-names = "default";
 686         pinctrl-0 = <&pinctrl_usdhc4>;
 687         bus-width = <8>;
 688         vmmc-supply = <&reg_3p3v>;
 689         vqmmc-supply = <&reg_3p3v>;
 690         no-1-8-v;
 691         non-removable;
 692         no-sdio;
 693         no-sd;
 694         status = "okay";
 695 };
 696
 697 &sata {
 698         target-supply = <&reg_3p3v_ssd>;
 699         status = "okay";
 700 };
 701
 702 &fec {
 703         pinctrl-names = "default";
 704         pinctrl-0 = <&pinctrl_enet>;
 705         phy-mode = "rmii";
 706         phy-handle = <&phy>;
 707         phy-reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
 708         phy-reset-duration = <100>;
 709         phy-supply = <&reg_3p3v>;
 710         status = "okay";
 711
 712         mdio {
 713                 #address-cells = <1>;
 714                 #size-cells = <0>;
 715                 status = "okay";
 716
 717                 switch: switch@0 {
 718                         compatible = "marvell,mv88e6085";
 719                         pinctrl-0 = <&pinctrl_switch_irq>;
 720                         pinctrl-names = "default";
 721                         reg = <0>;
 722                         dsa,member = <0 0>;
 723                         eeprom-length = <512>;
 724                         interrupt-parent = <&gpio6>;
 725                         interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
 726                         interrupt-controller;
 727                         #interrupt-cells = <2>;
 728
 729                         ports {
 730                                 #address-cells = <1>;
 731                                 #size-cells = <0>;
 732
 733                                 port@0 {
 734                                         reg = <0>;
 735                                         label = "gigabit_proc";
 736                                         phy-handle = <&switchphy0>;
 737                                 };
 738
 739                                 port@1 {
 740                                         reg = <1>;
 741                                         label = "netaux";
 742                                         phy-handle = <&switchphy1>;
 743                                 };
 744
 745                                 port@2 {
 746                                         reg = <2>;
 747                                         label = "cpu";
 748                                         ethernet = <&fec>;
 749
 750                                         fixed-link {
 751                                                 speed = <100>;
 752                                                 full-duplex;
 753                                         };
 754                                 };
 755
 756                                 port@3 {
 757                                         reg = <3>;
 758                                         label = "netright";
 759                                         phy-handle = <&switchphy3>;
 760                                 };
 761
 762                                 port@4 {
 763                                         reg = <4>;
 764                                         label = "netleft";
 765                                         phy-handle = <&switchphy4>;
 766                                 };
 767                         };
 768
 769                         mdio {
 770                                 #address-cells = <1>;
 771                                 #size-cells = <0>;
 772
 773                                 switchphy0: switchphy@0 {
 774                                         reg = <0>;
 775                                         interrupt-parent = <&switch>;
 776                                         interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
 777                                 };
 778
 779                                 switchphy1: switchphy@1 {
 780                                         reg = <1>;
 781                                         interrupt-parent = <&switch>;
 782                                         interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
 783                                 };
 784
 785                                 switchphy2: switchphy@2 {
 786                                         reg = <2>;
 787                                         interrupt-parent = <&switch>;
 788                                         interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
 789                                 };
 790
 791                                 switchphy3: switchphy@3 {
 792                                         reg = <3>;
 793                                         interrupt-parent = <&switch>;
 794                                         interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
 795                                 };
 796
 797                                 switchphy4: switchphy@4 {
 798                                         reg = <4>;
 799                                         interrupt-parent = <&switch>;
 800                                         interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
 801                                 };
 802                         };
 803                 };
 804         };
 805 };
 806
 807 &usbh1 {
 808         vbus-supply = <&reg_5p0v_main>;
 809         disable-over-current;
 810         maximum-speed = "full-speed";
 811         status = "okay";
 812 };
 813
 814 &usbotg {
 815         vbus-supply = <&reg_5p0v_user_usb>;
 816         disable-over-current;
 817         dr_mode = "host";
 818         status = "okay";
 819 };
 820
 821 &snvs_rtc {
 822         status = "disabled";
 823 };
 824
 825 &ssi1 {
 826         status = "okay";
 827 };
 828
 829 &ssi2 {
 830         status = "okay";
 831 };
 832
 833 &audmux {
 834         pinctrl-names = "default";
 835         pinctrl-0 = <&pinctrl_audmux>;
 836         status = "okay";
 837
 838         ssi1 {
 839                 fsl,audmux-port = <0>;
 840                 fsl,port-config = <
 841                         (IMX_AUDMUX_V2_PTCR_SYN |
 842                          IMX_AUDMUX_V2_PTCR_TFSEL(2) |
 843                          IMX_AUDMUX_V2_PTCR_TCSEL(2) |
 844                          IMX_AUDMUX_V2_PTCR_TFSDIR |
 845                          IMX_AUDMUX_V2_PTCR_TCLKDIR)
 846                         IMX_AUDMUX_V2_PDCR_RXDSEL(2)
 847                 >;
 848         };
 849
 850         aud3 {
 851                 fsl,audmux-port = <2>;
 852                 fsl,port-config = <
 853                         IMX_AUDMUX_V2_PTCR_SYN
 854                         IMX_AUDMUX_V2_PDCR_RXDSEL(0)
 855                 >;
 856         };
 857
 858         ssi2 {
 859                 fsl,audmux-port = <1>;
 860                 fsl,port-config = <
 861                         (IMX_AUDMUX_V2_PTCR_SYN |
 862                          IMX_AUDMUX_V2_PTCR_TFSEL(4) |
 863                          IMX_AUDMUX_V2_PTCR_TCSEL(4) |
 864                          IMX_AUDMUX_V2_PTCR_TFSDIR |
 865                          IMX_AUDMUX_V2_PTCR_TCLKDIR)
 866                         IMX_AUDMUX_V2_PDCR_RXDSEL(4)
 867                 >;
 868         };
 869
 870         aud5 {
 871                 fsl,audmux-port = <4>;
 872                 fsl,port-config = <
 873                         IMX_AUDMUX_V2_PTCR_SYN
 874                         IMX_AUDMUX_V2_PDCR_RXDSEL(1)
 875                 >;
 876         };
 877 };
 878
 879 &wdog1 {
 880         status = "disabled";
 881 };
 882
 883 &iomuxc {
 884         pinctrl_accel: accelgrp {
 885                 fsl,pins = <
 886                         MX6QDL_PAD_SD1_CLK__GPIO1_IO20          0x4001b000
 887                 >;
 888         };
 889
 890         pinctrl_audmux: audmuxgrp {
 891                 fsl,pins = <
 892                         MX6QDL_PAD_KEY_COL0__AUD5_TXC           0x130b0
 893                         MX6QDL_PAD_KEY_ROW0__AUD5_TXD           0x130b0
 894                         MX6QDL_PAD_KEY_COL1__AUD5_TXFS          0x130b0
 895                         MX6QDL_PAD_CSI0_DAT4__AUD3_TXC          0x130b0
 896                         MX6QDL_PAD_CSI0_DAT5__AUD3_TXD          0x130b0
 897                         MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS         0x130b0
 898                 >;
 899         };
 900
 901         pinctrl_codec1: dac1grp {
 902                 fsl,pins = <
 903                         MX6QDL_PAD_GPIO_0__GPIO1_IO00           0x40000038
 904                 >;
 905         };
 906
 907         pinctrl_codec2: dac2grp {
 908                 fsl,pins = <
 909                         MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x40000038
 910                 >;
 911         };
 912
 913         pinctrl_disp0: disp0grp {
 914                 fsl,pins = <
 915                         MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x100f9
 916                         MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x100f9
 917                         MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x100f9
 918                         MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x100f9
 919                         MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x100f9
 920                         MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x100f9
 921                         MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x100f9
 922                         MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x100f9
 923                         MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x100f9
 924                         MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x100f9
 925                         MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x100f9
 926                         MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x100f9
 927                         MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x100f9
 928                         MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x100f9
 929                         MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x100f9
 930                         MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x100f9
 931                         MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x100f9
 932                         MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x100f9
 933                         MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x100f9
 934                         MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x100f9
 935                         MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x100f9
 936                         MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x100f9
 937                         MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x100f9
 938                         MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x100f9
 939                         MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x100f9
 940                         MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x100f9
 941                         MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x100f9
 942                         MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x100f9
 943                 >;
 944         };
 945
 946         pinctrl_ecspi1: ecspi1grp {
 947                 fsl,pins = <
 948                         MX6QDL_PAD_EIM_D17__ECSPI1_MISO         0x100b1
 949                         MX6QDL_PAD_EIM_D18__ECSPI1_MOSI         0x100b1
 950                         MX6QDL_PAD_EIM_D16__ECSPI1_SCLK         0x100b1
 951                         MX6QDL_PAD_EIM_EB2__GPIO2_IO30          0x1b0b1
 952                 >;
 953         };
 954
 955         pinctrl_enet: enetgrp {
 956                 fsl,pins = <
 957                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x000b1
 958                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x100b1
 959                         MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN      0x100f5
 960                         MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN       0x100f5
 961                         MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0     0x100c0
 962                         MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1     0x100c0
 963                         MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0     0x100f5
 964                         MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1     0x100f5
 965                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x40010040
 966                         MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER       0x100b0
 967                         MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23     0x1b0b0
 968                 >;
 969         };
 970
 971         pinctrl_gpio3_hog: gpio3hoggrp {
 972                 fsl,pins = <
 973                         MX6QDL_PAD_EIM_D19__GPIO3_IO19          0x1b0b0
 974                         MX6QDL_PAD_EIM_D20__GPIO3_IO20          0x1b0b0
 975                         MX6QDL_PAD_EIM_D22__GPIO3_IO22          0x1b0b0
 976                         MX6QDL_PAD_EIM_D23__GPIO3_IO23          0x1b0b0
 977                 >;
 978         };
 979
 980         pinctrl_i2c1: i2c1grp {
 981                 fsl,pins = <
 982                         MX6QDL_PAD_CSI0_DAT8__I2C1_SDA          0x4001b8b1
 983                         MX6QDL_PAD_CSI0_DAT9__I2C1_SCL          0x4001b8b1
 984                 >;
 985         };
 986
 987         pinctrl_i2c2: i2c2grp {
 988                 fsl,pins = <
 989                         MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 990                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 991                 >;
 992         };
 993
 994         pinctrl_i2c3: i2c3grp {
 995                 fsl,pins = <
 996                         MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 997                         MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 998                 >;
 999         };
1000
1001         pinctrl_mdio1: bitbangmdiogrp {
1002                 fsl,pins = <
1003                         /* Bitbang MDIO for DEB Switch */
1004                         MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05       0x4001b030
1005                         MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04       0x40018830
1006                 >;
1007         };
1008
1009         pinctrl_pcie: pciegrp {
1010                 fsl,pins = <
1011                         MX6QDL_PAD_GPIO_17__GPIO7_IO12          0x10038
1012                 >;
1013         };
1014
1015         pinctrl_pfuze100_irq: pfuze100grp {
1016                 fsl,pins = <
1017                         MX6QDL_PAD_GPIO_18__GPIO7_IO13          0x40010000
1018                 >;
1019         };
1020
1021         pinctrl_reg_3p3v_sd: mmcsupply1grp {
1022                 fsl,pins = <
1023                         MX6QDL_PAD_SD3_RST__GPIO7_IO08          0x858
1024                 >;
1025         };
1026
1027         pinctrl_rmii_phy_irq: phygrp {
1028                 fsl,pins = <
1029                         MX6QDL_PAD_EIM_D30__GPIO3_IO30          0x40010000
1030                 >;
1031         };
1032
1033         pinctrl_switch_irq: switchgrp {
1034                 fsl,pins = <
1035                         MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03       0x4001b000
1036                 >;
1037         };
1038
1039         pinctrl_tc358767: tc358767grp {
1040                 fsl,pins = <
1041                         MX6QDL_PAD_GPIO_9__GPIO1_IO09           0x10
1042                 >;
1043         };
1044
1045         pinctrl_tpa1: tpa6130-1grp {
1046                 fsl,pins = <
1047                         MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x40000038
1048                 >;
1049         };
1050
1051         pinctrl_tpa2: tpa6130-2grp {
1052                 fsl,pins = <
1053                         MX6QDL_PAD_GPIO_5__GPIO1_IO05           0x40000038
1054                 >;
1055         };
1056
1057         pinctrl_ts: tsgrp {
1058                 fsl,pins = <
1059                         MX6QDL_PAD_GPIO_8__GPIO1_IO08           0x1b0b0
1060                         MX6QDL_PAD_GPIO_7__GPIO1_IO07           0x1b0b0
1061                 >;
1062         };
1063
1064         pinctrl_uart1: uart1grp {
1065                 fsl,pins = <
1066                         MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA    0x1b0b1
1067                         MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA    0x1b0b1
1068                 >;
1069         };
1070
1071         pinctrl_uart3: uart3grp {
1072                 fsl,pins = <
1073                         MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
1074                         MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
1075                         MX6QDL_PAD_EIM_D31__UART3_RTS_B         0x1b0b1
1076                 >;
1077         };
1078
1079         pinctrl_uart4: uart4grp {
1080                 fsl,pins = <
1081                         MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA    0x1b0b1
1082                         MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA    0x1b0b1
1083                 >;
1084         };
1085
1086         pinctrl_ucs1002_pins: ucs1002grp {
1087                 fsl,pins = <
1088                         MX6QDL_PAD_EIM_A25__GPIO5_IO02          0x1b0b0
1089                         MX6QDL_PAD_EIM_D21__GPIO3_IO21          0x1b0b0
1090                 >;
1091         };
1092
1093         pinctrl_usdhc2: usdhc2grp {
1094                 fsl,pins = <
1095                         MX6QDL_PAD_SD2_CMD__SD2_CMD             0x10059
1096                         MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10069
1097                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17059
1098                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17059
1099                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17059
1100                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17059
1101                         MX6QDL_PAD_NANDF_D2__GPIO2_IO02         0x40010040
1102                 >;
1103         };
1104
1105         pinctrl_usdhc3: usdhc3grp {
1106                 fsl,pins = <
1107                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x10059
1108                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10069
1109                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
1110                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
1111                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
1112                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
1113                         MX6QDL_PAD_NANDF_D0__GPIO2_IO00         0x40010040
1114
1115                 >;
1116         };
1117
1118         pinctrl_usdhc4: usdhc4grp {
1119                 fsl,pins = <
1120                         MX6QDL_PAD_SD4_CMD__SD4_CMD             0x17059
1121                         MX6QDL_PAD_SD4_CLK__SD4_CLK             0x10059
1122                         MX6QDL_PAD_SD4_DAT0__SD4_DATA0          0x17059
1123                         MX6QDL_PAD_SD4_DAT1__SD4_DATA1          0x17059
1124                         MX6QDL_PAD_SD4_DAT2__SD4_DATA2          0x17059
1125                         MX6QDL_PAD_SD4_DAT3__SD4_DATA3          0x17059
1126                         MX6QDL_PAD_SD4_DAT4__SD4_DATA4          0x17059
1127                         MX6QDL_PAD_SD4_DAT5__SD4_DATA5          0x17059
1128                         MX6QDL_PAD_SD4_DAT6__SD4_DATA6          0x17059
1129                         MX6QDL_PAD_SD4_DAT7__SD4_DATA7          0x17059
1130                         MX6QDL_PAD_NANDF_ALE__SD4_RESET         0x1b0b1
1131                 >;
1132         };
1133 };