| blob | d9fdca12819b21c022443bb325d3e8e9ba1e3469 |
1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Copyright 2015 Freescale Semiconductor, Inc.
5 #include <dt-bindings/clock/imx6ul-clock.h>
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include "imx6ul-pinfunc.h"
11 / {
12 #address-cells = <1>;
13 #size-cells = <1>;
14 /*
15 * The decompressor and also some bootloaders rely on a
16 * pre-existing /chosen node to be available to insert the
17 * command line and merge other ATAGS info.
18 */
19 chosen {};
21 aliases {
22 ethernet0 = &fec1;
23 ethernet1 = &fec2;
24 gpio0 = &gpio1;
25 gpio1 = &gpio2;
26 gpio2 = &gpio3;
27 gpio3 = &gpio4;
28 gpio4 = &gpio5;
29 i2c0 = &i2c1;
30 i2c1 = &i2c2;
31 i2c2 = &i2c3;
32 i2c3 = &i2c4;
33 mmc0 = &usdhc1;
34 mmc1 = &usdhc2;
35 serial0 = &uart1;
36 serial1 = &uart2;
37 serial2 = &uart3;
38 serial3 = &uart4;
39 serial4 = &uart5;
40 serial5 = &uart6;
41 serial6 = &uart7;
42 serial7 = &uart8;
43 sai1 = &sai1;
44 sai2 = &sai2;
45 sai3 = &sai3;
46 spi0 = &ecspi1;
47 spi1 = &ecspi2;
48 spi2 = &ecspi3;
49 spi3 = &ecspi4;
50 usbphy0 = &usbphy1;
51 usbphy1 = &usbphy2;
52 };
54 cpus {
55 #address-cells = <1>;
56 #size-cells = <0>;
58 cpu0: cpu@0 {
59 compatible = "arm,cortex-a7";
60 device_type = "cpu";
61 reg = <0>;
62 clock-frequency = <696000000>;
63 clock-latency = <61036>; /* two CLK32 periods */
64 #cooling-cells = <2>;
65 operating-points = <
66 /* kHz uV */
67 696000 1275000
68 528000 1175000
69 396000 1025000
70 198000 950000
71 >;
72 fsl,soc-operating-points = <
73 /* KHz uV */
74 696000 1275000
75 528000 1175000
76 396000 1175000
77 198000 1175000
78 >;
79 clocks = <&clks IMX6UL_CLK_ARM>,
80 <&clks IMX6UL_CLK_PLL2_BUS>,
81 <&clks IMX6UL_CLK_PLL2_PFD2>,
82 <&clks IMX6UL_CA7_SECONDARY_SEL>,
83 <&clks IMX6UL_CLK_STEP>,
84 <&clks IMX6UL_CLK_PLL1_SW>,
85 <&clks IMX6UL_CLK_PLL1_SYS>;
86 clock-names = "arm", "pll2_bus", "pll2_pfd2_396m",
87 "secondary_sel", "step", "pll1_sw",
88 "pll1_sys";
89 arm-supply = <®_arm>;
90 soc-supply = <®_soc>;
91 nvmem-cells = <&cpu_speed_grade>;
92 nvmem-cell-names = "speed_grade";
93 };
94 };
96 timer {
97 compatible = "arm,armv7-timer";
98 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
99 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
100 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
101 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
102 interrupt-parent = <&intc>;
103 status = "disabled";
104 };
106 ckil: clock-cli {
107 compatible = "fixed-clock";
108 #clock-cells = <0>;
109 clock-frequency = <32768>;
110 clock-output-names = "ckil";
111 };
113 osc: clock-osc {
114 compatible = "fixed-clock";
115 #clock-cells = <0>;
116 clock-frequency = <24000000>;
117 clock-output-names = "osc";
118 };
120 ipp_di0: clock-di0 {
121 compatible = "fixed-clock";
122 #clock-cells = <0>;
123 clock-frequency = <0>;
124 clock-output-names = "ipp_di0";
125 };
127 ipp_di1: clock-di1 {
128 compatible = "fixed-clock";
129 #clock-cells = <0>;
130 clock-frequency = <0>;
131 clock-output-names = "ipp_di1";
132 };
134 tempmon: tempmon {
135 compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon";
136 interrupt-parent = <&gpc>;
137 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
138 fsl,tempmon = <&anatop>;
139 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
140 nvmem-cell-names = "calib", "temp_grade";
141 clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;
142 };
144 pmu {
145 compatible = "arm,cortex-a7-pmu";
146 interrupt-parent = <&gpc>;
147 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
148 };
150 soc {
151 #address-cells = <1>;
152 #size-cells = <1>;
153 compatible = "simple-bus";
154 interrupt-parent = <&gpc>;
155 ranges;
157 ocram: sram@900000 {
158 compatible = "mmio-sram";
159 reg = <0x00900000 0x20000>;
160 };
162 intc: interrupt-controller@a01000 {
163 compatible = "arm,gic-400", "arm,cortex-a7-gic";
164 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
165 #interrupt-cells = <3>;
166 interrupt-controller;
167 interrupt-parent = <&intc>;
168 reg = <0x00a01000 0x1000>,
169 <0x00a02000 0x2000>,
170 <0x00a04000 0x2000>,
171 <0x00a06000 0x2000>;
172 };
174 dma_apbh: dma-apbh@1804000 {
175 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
176 reg = <0x01804000 0x2000>;
177 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
178 <0 13 IRQ_TYPE_LEVEL_HIGH>,
179 <0 13 IRQ_TYPE_LEVEL_HIGH>,
180 <0 13 IRQ_TYPE_LEVEL_HIGH>;
181 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
182 #dma-cells = <1>;
183 dma-channels = <4>;
184 clocks = <&clks IMX6UL_CLK_APBHDMA>;
185 };
187 gpmi: gpmi-nand@1806000 {
188 compatible = "fsl,imx6q-gpmi-nand";
189 #address-cells = <1>;
190 #size-cells = <1>;
191 reg = <0x01806000 0x2000>, <0x01808000 0x2000>;
192 reg-names = "gpmi-nand", "bch";
193 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
194 interrupt-names = "bch";
195 clocks = <&clks IMX6UL_CLK_GPMI_IO>,
196 <&clks IMX6UL_CLK_GPMI_APB>,
197 <&clks IMX6UL_CLK_GPMI_BCH>,
198 <&clks IMX6UL_CLK_GPMI_BCH_APB>,
199 <&clks IMX6UL_CLK_PER_BCH>;
200 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
201 "gpmi_bch_apb", "per1_bch";
202 dmas = <&dma_apbh 0>;
203 dma-names = "rx-tx";
204 status = "disabled";
205 };
207 aips1: aips-bus@2000000 {
208 compatible = "fsl,aips-bus", "simple-bus";
209 #address-cells = <1>;
210 #size-cells = <1>;
211 reg = <0x02000000 0x100000>;
212 ranges;
214 spba-bus@2000000 {
215 compatible = "fsl,spba-bus", "simple-bus";
216 #address-cells = <1>;
217 #size-cells = <1>;
218 reg = <0x02000000 0x40000>;
219 ranges;
221 ecspi1: spi@2008000 {
222 #address-cells = <1>;
223 #size-cells = <0>;
224 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
225 reg = <0x02008000 0x4000>;
226 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
227 clocks = <&clks IMX6UL_CLK_ECSPI1>,
228 <&clks IMX6UL_CLK_ECSPI1>;
229 clock-names = "ipg", "per";
230 dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
231 dma-names = "rx", "tx";
232 status = "disabled";
233 };
235 ecspi2: spi@200c000 {
236 #address-cells = <1>;
237 #size-cells = <0>;
238 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
239 reg = <0x0200c000 0x4000>;
240 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
241 clocks = <&clks IMX6UL_CLK_ECSPI2>,
242 <&clks IMX6UL_CLK_ECSPI2>;
243 clock-names = "ipg", "per";
244 dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
245 dma-names = "rx", "tx";
246 status = "disabled";
247 };
249 ecspi3: spi@2010000 {
250 #address-cells = <1>;
251 #size-cells = <0>;
252 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
253 reg = <0x02010000 0x4000>;
254 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
255 clocks = <&clks IMX6UL_CLK_ECSPI3>,
256 <&clks IMX6UL_CLK_ECSPI3>;
257 clock-names = "ipg", "per";
258 dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
259 dma-names = "rx", "tx";
260 status = "disabled";
261 };
263 ecspi4: spi@2014000 {
264 #address-cells = <1>;
265 #size-cells = <0>;
266 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
267 reg = <0x02014000 0x4000>;
268 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
269 clocks = <&clks IMX6UL_CLK_ECSPI4>,
270 <&clks IMX6UL_CLK_ECSPI4>;
271 clock-names = "ipg", "per";
272 dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
273 dma-names = "rx", "tx";
274 status = "disabled";
275 };
277 uart7: serial@2018000 {
278 compatible = "fsl,imx6ul-uart",
279 "fsl,imx6q-uart";
280 reg = <0x02018000 0x4000>;
281 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
282 clocks = <&clks IMX6UL_CLK_UART7_IPG>,
283 <&clks IMX6UL_CLK_UART7_SERIAL>;
284 clock-names = "ipg", "per";
285 status = "disabled";
286 };
288 uart1: serial@2020000 {
289 compatible = "fsl,imx6ul-uart",
290 "fsl,imx6q-uart";
291 reg = <0x02020000 0x4000>;
292 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
293 clocks = <&clks IMX6UL_CLK_UART1_IPG>,
294 <&clks IMX6UL_CLK_UART1_SERIAL>;
295 clock-names = "ipg", "per";
296 status = "disabled";
297 };
299 uart8: serial@2024000 {
300 compatible = "fsl,imx6ul-uart",
301 "fsl,imx6q-uart";
302 reg = <0x02024000 0x4000>;
303 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&clks IMX6UL_CLK_UART8_IPG>,
305 <&clks IMX6UL_CLK_UART8_SERIAL>;
306 clock-names = "ipg", "per";
307 status = "disabled";
308 };
310 sai1: sai@2028000 {
311 #sound-dai-cells = <0>;
312 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
313 reg = <0x02028000 0x4000>;
314 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
315 clocks = <&clks IMX6UL_CLK_SAI1_IPG>,
316 <&clks IMX6UL_CLK_SAI1>,
317 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
318 clock-names = "bus", "mclk1", "mclk2", "mclk3";
319 dmas = <&sdma 35 24 0>,
320 <&sdma 36 24 0>;
321 dma-names = "rx", "tx";
322 status = "disabled";
323 };
325 sai2: sai@202c000 {
326 #sound-dai-cells = <0>;
327 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
328 reg = <0x0202c000 0x4000>;
329 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
330 clocks = <&clks IMX6UL_CLK_SAI2_IPG>,
331 <&clks IMX6UL_CLK_SAI2>,
332 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
333 clock-names = "bus", "mclk1", "mclk2", "mclk3";
334 dmas = <&sdma 37 24 0>,
335 <&sdma 38 24 0>;
336 dma-names = "rx", "tx";
337 status = "disabled";
338 };
340 sai3: sai@2030000 {
341 #sound-dai-cells = <0>;
342 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
343 reg = <0x02030000 0x4000>;
344 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
345 clocks = <&clks IMX6UL_CLK_SAI3_IPG>,
346 <&clks IMX6UL_CLK_SAI3>,
347 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
348 clock-names = "bus", "mclk1", "mclk2", "mclk3";
349 dmas = <&sdma 39 24 0>,
350 <&sdma 40 24 0>;
351 dma-names = "rx", "tx";
352 status = "disabled";
353 };
354 };
356 tsc: tsc@2040000 {
357 compatible = "fsl,imx6ul-tsc";
358 reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
359 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
360 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
361 clocks = <&clks IMX6UL_CLK_IPG>,
362 <&clks IMX6UL_CLK_ADC2>;
363 clock-names = "tsc", "adc";
364 status = "disabled";
365 };
367 pwm1: pwm@2080000 {
368 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
369 reg = <0x02080000 0x4000>;
370 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
371 clocks = <&clks IMX6UL_CLK_PWM1>,
372 <&clks IMX6UL_CLK_PWM1>;
373 clock-names = "ipg", "per";
374 #pwm-cells = <2>;
375 status = "disabled";
376 };
378 pwm2: pwm@2084000 {
379 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
380 reg = <0x02084000 0x4000>;
381 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
382 clocks = <&clks IMX6UL_CLK_PWM2>,
383 <&clks IMX6UL_CLK_PWM2>;
384 clock-names = "ipg", "per";
385 #pwm-cells = <2>;
386 status = "disabled";
387 };
389 pwm3: pwm@2088000 {
390 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
391 reg = <0x02088000 0x4000>;
392 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
393 clocks = <&clks IMX6UL_CLK_PWM3>,
394 <&clks IMX6UL_CLK_PWM3>;
395 clock-names = "ipg", "per";
396 #pwm-cells = <2>;
397 status = "disabled";
398 };
400 pwm4: pwm@208c000 {
401 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
402 reg = <0x0208c000 0x4000>;
403 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
404 clocks = <&clks IMX6UL_CLK_PWM4>,
405 <&clks IMX6UL_CLK_PWM4>;
406 clock-names = "ipg", "per";
407 #pwm-cells = <2>;
408 status = "disabled";
409 };
411 can1: flexcan@2090000 {
412 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
413 reg = <0x02090000 0x4000>;
414 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
415 clocks = <&clks IMX6UL_CLK_CAN1_IPG>,
416 <&clks IMX6UL_CLK_CAN1_SERIAL>;
417 clock-names = "ipg", "per";
418 fsl,stop-mode = <&gpr 0x10 1 0x10 17>;
419 status = "disabled";
420 };
422 can2: flexcan@2094000 {
423 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
424 reg = <0x02094000 0x4000>;
425 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
426 clocks = <&clks IMX6UL_CLK_CAN2_IPG>,
427 <&clks IMX6UL_CLK_CAN2_SERIAL>;
428 clock-names = "ipg", "per";
429 fsl,stop-mode = <&gpr 0x10 2 0x10 18>;
430 status = "disabled";
431 };
433 gpt1: gpt@2098000 {
434 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
435 reg = <0x02098000 0x4000>;
436 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
437 clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
438 <&clks IMX6UL_CLK_GPT1_SERIAL>;
439 clock-names = "ipg", "per";
440 };
442 gpio1: gpio@209c000 {
443 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
444 reg = <0x0209c000 0x4000>;
445 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
446 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
447 clocks = <&clks IMX6UL_CLK_GPIO1>;
448 gpio-controller;
449 #gpio-cells = <2>;
450 interrupt-controller;
451 #interrupt-cells = <2>;
452 gpio-ranges = <&iomuxc 0 23 10>, <&iomuxc 10 17 6>,
453 <&iomuxc 16 33 16>;
454 };
456 gpio2: gpio@20a0000 {
457 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
458 reg = <0x020a0000 0x4000>;
459 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
460 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
461 clocks = <&clks IMX6UL_CLK_GPIO2>;
462 gpio-controller;
463 #gpio-cells = <2>;
464 interrupt-controller;
465 #interrupt-cells = <2>;
466 gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>;
467 };
469 gpio3: gpio@20a4000 {
470 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
471 reg = <0x020a4000 0x4000>;
472 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
473 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
474 clocks = <&clks IMX6UL_CLK_GPIO3>;
475 gpio-controller;
476 #gpio-cells = <2>;
477 interrupt-controller;
478 #interrupt-cells = <2>;
479 gpio-ranges = <&iomuxc 0 65 29>;
480 };
482 gpio4: gpio@20a8000 {
483 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
484 reg = <0x020a8000 0x4000>;
485 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
486 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
487 clocks = <&clks IMX6UL_CLK_GPIO4>;
488 gpio-controller;
489 #gpio-cells = <2>;
490 interrupt-controller;
491 #interrupt-cells = <2>;
492 gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>;
493 };
495 gpio5: gpio@20ac000 {
496 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
497 reg = <0x020ac000 0x4000>;
498 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
499 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
500 clocks = <&clks IMX6UL_CLK_GPIO5>;
501 gpio-controller;
502 #gpio-cells = <2>;
503 interrupt-controller;
504 #interrupt-cells = <2>;
505 gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>;
506 };
508 fec2: ethernet@20b4000 {
509 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
510 reg = <0x020b4000 0x4000>;
511 interrupt-names = "int0", "pps";
512 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
513 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
514 clocks = <&clks IMX6UL_CLK_ENET>,
515 <&clks IMX6UL_CLK_ENET_AHB>,
516 <&clks IMX6UL_CLK_ENET_PTP>,
517 <&clks IMX6UL_CLK_ENET2_REF_125M>,
518 <&clks IMX6UL_CLK_ENET2_REF_125M>;
519 clock-names = "ipg", "ahb", "ptp",
520 "enet_clk_ref", "enet_out";
521 fsl,num-tx-queues = <1>;
522 fsl,num-rx-queues = <1>;
523 status = "disabled";
524 };
526 kpp: kpp@20b8000 {
527 compatible = "fsl,imx6ul-kpp", "fsl,imx6q-kpp", "fsl,imx21-kpp";
528 reg = <0x020b8000 0x4000>;
529 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
530 clocks = <&clks IMX6UL_CLK_KPP>;
531 status = "disabled";
532 };
534 wdog1: wdog@20bc000 {
535 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
536 reg = <0x020bc000 0x4000>;
537 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
538 clocks = <&clks IMX6UL_CLK_WDOG1>;
539 };
541 wdog2: wdog@20c0000 {
542 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
543 reg = <0x020c0000 0x4000>;
544 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
545 clocks = <&clks IMX6UL_CLK_WDOG2>;
546 status = "disabled";
547 };
549 clks: ccm@20c4000 {
550 compatible = "fsl,imx6ul-ccm";
551 reg = <0x020c4000 0x4000>;
552 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
553 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
554 #clock-cells = <1>;
555 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
556 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
557 };
559 anatop: anatop@20c8000 {
560 compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
561 "syscon", "simple-mfd";
562 reg = <0x020c8000 0x1000>;
563 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
564 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
565 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
567 reg_3p0: regulator-3p0 {
568 compatible = "fsl,anatop-regulator";
569 regulator-name = "vdd3p0";
570 regulator-min-microvolt = <2625000>;
571 regulator-max-microvolt = <3400000>;
572 anatop-reg-offset = <0x120>;
573 anatop-vol-bit-shift = <8>;
574 anatop-vol-bit-width = <5>;
575 anatop-min-bit-val = <0>;
576 anatop-min-voltage = <2625000>;
577 anatop-max-voltage = <3400000>;
578 anatop-enable-bit = <0>;
579 };
581 reg_arm: regulator-vddcore {
582 compatible = "fsl,anatop-regulator";
583 regulator-name = "cpu";
584 regulator-min-microvolt = <725000>;
585 regulator-max-microvolt = <1450000>;
586 regulator-always-on;
587 anatop-reg-offset = <0x140>;
588 anatop-vol-bit-shift = <0>;
589 anatop-vol-bit-width = <5>;
590 anatop-delay-reg-offset = <0x170>;
591 anatop-delay-bit-shift = <24>;
592 anatop-delay-bit-width = <2>;
593 anatop-min-bit-val = <1>;
594 anatop-min-voltage = <725000>;
595 anatop-max-voltage = <1450000>;
596 };
598 reg_soc: regulator-vddsoc {
599 compatible = "fsl,anatop-regulator";
600 regulator-name = "vddsoc";
601 regulator-min-microvolt = <725000>;
602 regulator-max-microvolt = <1450000>;
603 regulator-always-on;
604 anatop-reg-offset = <0x140>;
605 anatop-vol-bit-shift = <18>;
606 anatop-vol-bit-width = <5>;
607 anatop-delay-reg-offset = <0x170>;
608 anatop-delay-bit-shift = <28>;
609 anatop-delay-bit-width = <2>;
610 anatop-min-bit-val = <1>;
611 anatop-min-voltage = <725000>;
612 anatop-max-voltage = <1450000>;
613 };
614 };
616 usbphy1: usbphy@20c9000 {
617 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
618 reg = <0x020c9000 0x1000>;
619 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
620 clocks = <&clks IMX6UL_CLK_USBPHY1>;
621 phy-3p0-supply = <®_3p0>;
622 fsl,anatop = <&anatop>;
623 };
625 usbphy2: usbphy@20ca000 {
626 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
627 reg = <0x020ca000 0x1000>;
628 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
629 clocks = <&clks IMX6UL_CLK_USBPHY2>;
630 phy-3p0-supply = <®_3p0>;
631 fsl,anatop = <&anatop>;
632 };
634 snvs: snvs@20cc000 {
635 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
636 reg = <0x020cc000 0x4000>;
638 snvs_rtc: snvs-rtc-lp {
639 compatible = "fsl,sec-v4.0-mon-rtc-lp";
640 regmap = <&snvs>;
641 offset = <0x34>;
642 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
643 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
644 };
646 snvs_poweroff: snvs-poweroff {
647 compatible = "syscon-poweroff";
648 regmap = <&snvs>;
649 offset = <0x38>;
650 value = <0x60>;
651 mask = <0x60>;
652 status = "disabled";
653 };
655 snvs_pwrkey: snvs-powerkey {
656 compatible = "fsl,sec-v4.0-pwrkey";
657 regmap = <&snvs>;
658 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
659 linux,keycode = <KEY_POWER>;
660 wakeup-source;
661 status = "disabled";
662 };
664 snvs_lpgpr: snvs-lpgpr {
665 compatible = "fsl,imx6ul-snvs-lpgpr";
666 };
667 };
669 epit1: epit@20d0000 {
670 reg = <0x020d0000 0x4000>;
671 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
672 };
674 epit2: epit@20d4000 {
675 reg = <0x020d4000 0x4000>;
676 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
677 };
679 src: src@20d8000 {
680 compatible = "fsl,imx6ul-src", "fsl,imx51-src";
681 reg = <0x020d8000 0x4000>;
682 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
683 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
684 #reset-cells = <1>;
685 };
687 gpc: gpc@20dc000 {
688 compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
689 reg = <0x020dc000 0x4000>;
690 interrupt-controller;
691 #interrupt-cells = <3>;
692 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
693 interrupt-parent = <&intc>;
694 };
696 iomuxc: iomuxc@20e0000 {
697 compatible = "fsl,imx6ul-iomuxc";
698 reg = <0x020e0000 0x4000>;
699 };
701 gpr: iomuxc-gpr@20e4000 {
702 compatible = "fsl,imx6ul-iomuxc-gpr",
703 "fsl,imx6q-iomuxc-gpr", "syscon";
704 reg = <0x020e4000 0x4000>;
705 };
707 gpt2: gpt@20e8000 {
708 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
709 reg = <0x020e8000 0x4000>;
710 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
711 clocks = <&clks IMX6UL_CLK_GPT2_BUS>,
712 <&clks IMX6UL_CLK_GPT2_SERIAL>;
713 clock-names = "ipg", "per";
714 status = "disabled";
715 };
717 sdma: sdma@20ec000 {
718 compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma",
719 "fsl,imx35-sdma";
720 reg = <0x020ec000 0x4000>;
721 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
722 clocks = <&clks IMX6UL_CLK_IPG>,
723 <&clks IMX6UL_CLK_SDMA>;
724 clock-names = "ipg", "ahb";
725 #dma-cells = <3>;
726 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
727 };
729 pwm5: pwm@20f0000 {
730 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
731 reg = <0x020f0000 0x4000>;
732 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
733 clocks = <&clks IMX6UL_CLK_PWM5>,
734 <&clks IMX6UL_CLK_PWM5>;
735 clock-names = "ipg", "per";
736 #pwm-cells = <2>;
737 status = "disabled";
738 };
740 pwm6: pwm@20f4000 {
741 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
742 reg = <0x020f4000 0x4000>;
743 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
744 clocks = <&clks IMX6UL_CLK_PWM6>,
745 <&clks IMX6UL_CLK_PWM6>;
746 clock-names = "ipg", "per";
747 #pwm-cells = <2>;
748 status = "disabled";
749 };
751 pwm7: pwm@20f8000 {
752 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
753 reg = <0x020f8000 0x4000>;
754 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
755 clocks = <&clks IMX6UL_CLK_PWM7>,
756 <&clks IMX6UL_CLK_PWM7>;
757 clock-names = "ipg", "per";
758 #pwm-cells = <2>;
759 status = "disabled";
760 };
762 pwm8: pwm@20fc000 {
763 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
764 reg = <0x020fc000 0x4000>;
765 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
766 clocks = <&clks IMX6UL_CLK_PWM8>,
767 <&clks IMX6UL_CLK_PWM8>;
768 clock-names = "ipg", "per";
769 #pwm-cells = <2>;
770 status = "disabled";
771 };
772 };
774 aips2: aips-bus@2100000 {
775 compatible = "fsl,aips-bus", "simple-bus";
776 #address-cells = <1>;
777 #size-cells = <1>;
778 reg = <0x02100000 0x100000>;
779 ranges;
781 crypto: caam@2140000 {
782 compatible = "fsl,imx6ul-caam", "fsl,sec-v4.0";
783 #address-cells = <1>;
784 #size-cells = <1>;
785 reg = <0x2140000 0x3c000>;
786 ranges = <0 0x2140000 0x3c000>;
787 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
788 clocks = <&clks IMX6UL_CLK_CAAM_IPG>, <&clks IMX6UL_CLK_CAAM_ACLK>,
789 <&clks IMX6UL_CLK_CAAM_MEM>;
790 clock-names = "ipg", "aclk", "mem";
792 sec_jr0: jr0@1000 {
793 compatible = "fsl,sec-v4.0-job-ring";
794 reg = <0x1000 0x1000>;
795 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
796 };
798 sec_jr1: jr1@2000 {
799 compatible = "fsl,sec-v4.0-job-ring";
800 reg = <0x2000 0x1000>;
801 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
802 };
804 sec_jr2: jr2@3000 {
805 compatible = "fsl,sec-v4.0-job-ring";
806 reg = <0x3000 0x1000>;
807 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
808 };
809 };
811 usbotg1: usb@2184000 {
812 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
813 reg = <0x02184000 0x200>;
814 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
815 clocks = <&clks IMX6UL_CLK_USBOH3>;
816 fsl,usbphy = <&usbphy1>;
817 fsl,usbmisc = <&usbmisc 0>;
818 fsl,anatop = <&anatop>;
819 ahb-burst-config = <0x0>;
820 tx-burst-size-dword = <0x10>;
821 rx-burst-size-dword = <0x10>;
822 status = "disabled";
823 };
825 usbotg2: usb@2184200 {
826 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
827 reg = <0x02184200 0x200>;
828 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
829 clocks = <&clks IMX6UL_CLK_USBOH3>;
830 fsl,usbphy = <&usbphy2>;
831 fsl,usbmisc = <&usbmisc 1>;
832 ahb-burst-config = <0x0>;
833 tx-burst-size-dword = <0x10>;
834 rx-burst-size-dword = <0x10>;
835 status = "disabled";
836 };
838 usbmisc: usbmisc@2184800 {
839 #index-cells = <1>;
840 compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
841 reg = <0x02184800 0x200>;
842 };
844 fec1: ethernet@2188000 {
845 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
846 reg = <0x02188000 0x4000>;
847 interrupt-names = "int0", "pps";
848 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
849 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
850 clocks = <&clks IMX6UL_CLK_ENET>,
851 <&clks IMX6UL_CLK_ENET_AHB>,
852 <&clks IMX6UL_CLK_ENET_PTP>,
853 <&clks IMX6UL_CLK_ENET_REF>,
854 <&clks IMX6UL_CLK_ENET_REF>;
855 clock-names = "ipg", "ahb", "ptp",
856 "enet_clk_ref", "enet_out";
857 fsl,num-tx-queues = <1>;
858 fsl,num-rx-queues = <1>;
859 status = "disabled";
860 };
862 usdhc1: usdhc@2190000 {
863 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
864 reg = <0x02190000 0x4000>;
865 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
866 clocks = <&clks IMX6UL_CLK_USDHC1>,
867 <&clks IMX6UL_CLK_USDHC1>,
868 <&clks IMX6UL_CLK_USDHC1>;
869 clock-names = "ipg", "ahb", "per";
870 fsl,tuning-step = <2>;
871 fsl,tuning-start-tap = <20>;
872 bus-width = <4>;
873 status = "disabled";
874 };
876 usdhc2: usdhc@2194000 {
877 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
878 reg = <0x02194000 0x4000>;
879 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
880 clocks = <&clks IMX6UL_CLK_USDHC2>,
881 <&clks IMX6UL_CLK_USDHC2>,
882 <&clks IMX6UL_CLK_USDHC2>;
883 clock-names = "ipg", "ahb", "per";
884 bus-width = <4>;
885 fsl,tuning-step = <2>;
886 fsl,tuning-start-tap = <20>;
887 status = "disabled";
888 };
890 adc1: adc@2198000 {
891 compatible = "fsl,imx6ul-adc", "fsl,vf610-adc";
892 reg = <0x02198000 0x4000>;
893 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
894 clocks = <&clks IMX6UL_CLK_ADC1>;
895 num-channels = <2>;
896 clock-names = "adc";
897 fsl,adck-max-frequency = <30000000>, <40000000>,
898 <20000000>;
899 status = "disabled";
900 };
902 i2c1: i2c@21a0000 {
903 #address-cells = <1>;
904 #size-cells = <0>;
905 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
906 reg = <0x021a0000 0x4000>;
907 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
908 clocks = <&clks IMX6UL_CLK_I2C1>;
909 status = "disabled";
910 };
912 i2c2: i2c@21a4000 {
913 #address-cells = <1>;
914 #size-cells = <0>;
915 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
916 reg = <0x021a4000 0x4000>;
917 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
918 clocks = <&clks IMX6UL_CLK_I2C2>;
919 status = "disabled";
920 };
922 i2c3: i2c@21a8000 {
923 #address-cells = <1>;
924 #size-cells = <0>;
925 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
926 reg = <0x021a8000 0x4000>;
927 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
928 clocks = <&clks IMX6UL_CLK_I2C3>;
929 status = "disabled";
930 };
932 memory-controller@21b0000 {
933 compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
934 reg = <0x021b0000 0x4000>;
935 clocks = <&clks IMX6UL_CLK_MMDC_P0_IPG>;
936 };
938 weim: weim@21b8000 {
939 #address-cells = <2>;
940 #size-cells = <1>;
941 compatible = "fsl,imx6ul-weim", "fsl,imx6q-weim";
942 reg = <0x021b8000 0x4000>;
943 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
944 clocks = <&clks IMX6UL_CLK_EIM>;
945 fsl,weim-cs-gpr = <&gpr>;
946 status = "disabled";
947 };
949 ocotp: ocotp-ctrl@21bc000 {
950 #address-cells = <1>;
951 #size-cells = <1>;
952 compatible = "fsl,imx6ul-ocotp", "syscon";
953 reg = <0x021bc000 0x4000>;
954 clocks = <&clks IMX6UL_CLK_OCOTP>;
956 tempmon_calib: calib@38 {
957 reg = <0x38 4>;
958 };
960 tempmon_temp_grade: temp-grade@20 {
961 reg = <0x20 4>;
962 };
964 cpu_speed_grade: speed-grade@10 {
965 reg = <0x10 4>;
966 };
967 };
969 csi: csi@21c4000 {
970 compatible = "fsl,imx6ul-csi", "fsl,imx7-csi";
971 reg = <0x021c4000 0x4000>;
972 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
973 clocks = <&clks IMX6UL_CLK_CSI>;
974 clock-names = "mclk";
975 status = "disabled";
976 };
978 lcdif: lcdif@21c8000 {
979 compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";
980 reg = <0x021c8000 0x4000>;
981 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
982 clocks = <&clks IMX6UL_CLK_LCDIF_PIX>,
983 <&clks IMX6UL_CLK_LCDIF_APB>,
984 <&clks IMX6UL_CLK_DUMMY>;
985 clock-names = "pix", "axi", "disp_axi";
986 status = "disabled";
987 };
989 pxp: pxp@21cc000 {
990 compatible = "fsl,imx6ul-pxp";
991 reg = <0x021cc000 0x4000>;
992 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
993 clocks = <&clks IMX6UL_CLK_PXP>;
994 clock-names = "axi";
995 };
997 qspi: spi@21e0000 {
998 #address-cells = <1>;
999 #size-cells = <0>;
1000 compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";
1001 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
1002 reg-names = "QuadSPI", "QuadSPI-memory";
1003 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1004 clocks = <&clks IMX6UL_CLK_QSPI>,
1005 <&clks IMX6UL_CLK_QSPI>;
1006 clock-names = "qspi_en", "qspi";
1007 status = "disabled";
1008 };
1010 wdog3: wdog@21e4000 {
1011 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
1012 reg = <0x021e4000 0x4000>;
1013 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1014 clocks = <&clks IMX6UL_CLK_WDOG3>;
1015 status = "disabled";
1016 };
1018 uart2: serial@21e8000 {
1019 compatible = "fsl,imx6ul-uart",
1020 "fsl,imx6q-uart";
1021 reg = <0x021e8000 0x4000>;
1022 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1023 clocks = <&clks IMX6UL_CLK_UART2_IPG>,
1024 <&clks IMX6UL_CLK_UART2_SERIAL>;
1025 clock-names = "ipg", "per";
1026 status = "disabled";
1027 };
1029 uart3: serial@21ec000 {
1030 compatible = "fsl,imx6ul-uart",
1031 "fsl,imx6q-uart";
1032 reg = <0x021ec000 0x4000>;
1033 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1034 clocks = <&clks IMX6UL_CLK_UART3_IPG>,
1035 <&clks IMX6UL_CLK_UART3_SERIAL>;
1036 clock-names = "ipg", "per";
1037 status = "disabled";
1038 };
1040 uart4: serial@21f0000 {
1041 compatible = "fsl,imx6ul-uart",
1042 "fsl,imx6q-uart";
1043 reg = <0x021f0000 0x4000>;
1044 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1045 clocks = <&clks IMX6UL_CLK_UART4_IPG>,
1046 <&clks IMX6UL_CLK_UART4_SERIAL>;
1047 clock-names = "ipg", "per";
1048 status = "disabled";
1049 };
1051 uart5: serial@21f4000 {
1052 compatible = "fsl,imx6ul-uart",
1053 "fsl,imx6q-uart";
1054 reg = <0x021f4000 0x4000>;
1055 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1056 clocks = <&clks IMX6UL_CLK_UART5_IPG>,
1057 <&clks IMX6UL_CLK_UART5_SERIAL>;
1058 clock-names = "ipg", "per";
1059 status = "disabled";
1060 };
1062 i2c4: i2c@21f8000 {
1063 #address-cells = <1>;
1064 #size-cells = <0>;
1065 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
1066 reg = <0x021f8000 0x4000>;
1067 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1068 clocks = <&clks IMX6UL_CLK_I2C4>;
1069 status = "disabled";
1070 };
1072 uart6: serial@21fc000 {
1073 compatible = "fsl,imx6ul-uart",
1074 "fsl,imx6q-uart";
1075 reg = <0x021fc000 0x4000>;
1076 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1077 clocks = <&clks IMX6UL_CLK_UART6_IPG>,
1078 <&clks IMX6UL_CLK_UART6_SERIAL>;
1079 clock-names = "ipg", "per";
1080 status = "disabled";
1081 };
1082 };
1083 };
1084 };