| blob | 2ec04d7972efce1bbc25e2913a6ce2c4188f66ce |
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
2 //
3 // Device Tree Source for UniPhier Pro4 SoC
4 //
5 // Copyright (C) 2015-2016 Socionext Inc.
6 // Author: Masahiro Yamada <yamada.masahiro@socionext.com>
8 #include <dt-bindings/gpio/uniphier-gpio.h>
10 / {
11 compatible = "socionext,uniphier-pro4";
12 #address-cells = <1>;
13 #size-cells = <1>;
15 cpus {
16 #address-cells = <1>;
17 #size-cells = <0>;
19 cpu@0 {
20 device_type = "cpu";
21 compatible = "arm,cortex-a9";
22 reg = <0>;
23 enable-method = "psci";
24 next-level-cache = <&l2>;
25 };
27 cpu@1 {
28 device_type = "cpu";
29 compatible = "arm,cortex-a9";
30 reg = <1>;
31 enable-method = "psci";
32 next-level-cache = <&l2>;
33 };
34 };
36 psci {
37 compatible = "arm,psci-0.2";
38 method = "smc";
39 };
41 clocks {
42 refclk: ref {
43 compatible = "fixed-clock";
44 #clock-cells = <0>;
45 clock-frequency = <25000000>;
46 };
48 arm_timer_clk: arm-timer {
49 #clock-cells = <0>;
50 compatible = "fixed-clock";
51 clock-frequency = <50000000>;
52 };
53 };
55 soc {
56 compatible = "simple-bus";
57 #address-cells = <1>;
58 #size-cells = <1>;
59 ranges;
60 interrupt-parent = <&intc>;
62 l2: l2-cache@500c0000 {
63 compatible = "socionext,uniphier-system-cache";
64 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
65 <0x506c0000 0x400>;
66 interrupts = <0 174 4>, <0 175 4>;
67 cache-unified;
68 cache-size = <(768 * 1024)>;
69 cache-sets = <256>;
70 cache-line-size = <128>;
71 cache-level = <2>;
72 };
74 spi0: spi@54006000 {
75 compatible = "socionext,uniphier-scssi";
76 status = "disabled";
77 reg = <0x54006000 0x100>;
78 interrupts = <0 39 4>;
79 pinctrl-names = "default";
80 pinctrl-0 = <&pinctrl_spi0>;
81 clocks = <&peri_clk 11>;
82 resets = <&peri_rst 11>;
83 };
85 serial0: serial@54006800 {
86 compatible = "socionext,uniphier-uart";
87 status = "disabled";
88 reg = <0x54006800 0x40>;
89 interrupts = <0 33 4>;
90 pinctrl-names = "default";
91 pinctrl-0 = <&pinctrl_uart0>;
92 clocks = <&peri_clk 0>;
93 resets = <&peri_rst 0>;
94 };
96 serial1: serial@54006900 {
97 compatible = "socionext,uniphier-uart";
98 status = "disabled";
99 reg = <0x54006900 0x40>;
100 interrupts = <0 35 4>;
101 pinctrl-names = "default";
102 pinctrl-0 = <&pinctrl_uart1>;
103 clocks = <&peri_clk 1>;
104 resets = <&peri_rst 1>;
105 };
107 serial2: serial@54006a00 {
108 compatible = "socionext,uniphier-uart";
109 status = "disabled";
110 reg = <0x54006a00 0x40>;
111 interrupts = <0 37 4>;
112 pinctrl-names = "default";
113 pinctrl-0 = <&pinctrl_uart2>;
114 clocks = <&peri_clk 2>;
115 resets = <&peri_rst 2>;
116 };
118 serial3: serial@54006b00 {
119 compatible = "socionext,uniphier-uart";
120 status = "disabled";
121 reg = <0x54006b00 0x40>;
122 interrupts = <0 177 4>;
123 pinctrl-names = "default";
124 pinctrl-0 = <&pinctrl_uart3>;
125 clocks = <&peri_clk 3>;
126 resets = <&peri_rst 3>;
127 };
129 gpio: gpio@55000000 {
130 compatible = "socionext,uniphier-gpio";
131 reg = <0x55000000 0x200>;
132 interrupt-parent = <&aidet>;
133 interrupt-controller;
134 #interrupt-cells = <2>;
135 gpio-controller;
136 #gpio-cells = <2>;
137 gpio-ranges = <&pinctrl 0 0 0>;
138 gpio-ranges-group-names = "gpio_range";
139 ngpios = <248>;
140 socionext,interrupt-ranges = <0 48 16>, <16 154 5>;
141 };
143 i2c0: i2c@58780000 {
144 compatible = "socionext,uniphier-fi2c";
145 status = "disabled";
146 reg = <0x58780000 0x80>;
147 #address-cells = <1>;
148 #size-cells = <0>;
149 interrupts = <0 41 4>;
150 pinctrl-names = "default";
151 pinctrl-0 = <&pinctrl_i2c0>;
152 clocks = <&peri_clk 4>;
153 resets = <&peri_rst 4>;
154 clock-frequency = <100000>;
155 };
157 i2c1: i2c@58781000 {
158 compatible = "socionext,uniphier-fi2c";
159 status = "disabled";
160 reg = <0x58781000 0x80>;
161 #address-cells = <1>;
162 #size-cells = <0>;
163 interrupts = <0 42 4>;
164 pinctrl-names = "default";
165 pinctrl-0 = <&pinctrl_i2c1>;
166 clocks = <&peri_clk 5>;
167 resets = <&peri_rst 5>;
168 clock-frequency = <100000>;
169 };
171 i2c2: i2c@58782000 {
172 compatible = "socionext,uniphier-fi2c";
173 status = "disabled";
174 reg = <0x58782000 0x80>;
175 #address-cells = <1>;
176 #size-cells = <0>;
177 interrupts = <0 43 4>;
178 pinctrl-names = "default";
179 pinctrl-0 = <&pinctrl_i2c2>;
180 clocks = <&peri_clk 6>;
181 resets = <&peri_rst 6>;
182 clock-frequency = <100000>;
183 };
185 i2c3: i2c@58783000 {
186 compatible = "socionext,uniphier-fi2c";
187 status = "disabled";
188 reg = <0x58783000 0x80>;
189 #address-cells = <1>;
190 #size-cells = <0>;
191 interrupts = <0 44 4>;
192 pinctrl-names = "default";
193 pinctrl-0 = <&pinctrl_i2c3>;
194 clocks = <&peri_clk 7>;
195 resets = <&peri_rst 7>;
196 clock-frequency = <100000>;
197 };
199 /* i2c4 does not exist */
201 /* chip-internal connection for DMD */
202 i2c5: i2c@58785000 {
203 compatible = "socionext,uniphier-fi2c";
204 reg = <0x58785000 0x80>;
205 #address-cells = <1>;
206 #size-cells = <0>;
207 interrupts = <0 25 4>;
208 clocks = <&peri_clk 9>;
209 resets = <&peri_rst 9>;
210 clock-frequency = <400000>;
211 };
213 /* chip-internal connection for HDMI */
214 i2c6: i2c@58786000 {
215 compatible = "socionext,uniphier-fi2c";
216 reg = <0x58786000 0x80>;
217 #address-cells = <1>;
218 #size-cells = <0>;
219 interrupts = <0 26 4>;
220 clocks = <&peri_clk 10>;
221 resets = <&peri_rst 10>;
222 clock-frequency = <400000>;
223 };
225 system_bus: system-bus@58c00000 {
226 compatible = "socionext,uniphier-system-bus";
227 status = "disabled";
228 reg = <0x58c00000 0x400>;
229 #address-cells = <2>;
230 #size-cells = <1>;
231 pinctrl-names = "default";
232 pinctrl-0 = <&pinctrl_system_bus>;
233 };
235 smpctrl@59801000 {
236 compatible = "socionext,uniphier-smpctrl";
237 reg = <0x59801000 0x400>;
238 };
240 mioctrl@59810000 {
241 compatible = "socionext,uniphier-pro4-mioctrl",
242 "simple-mfd", "syscon";
243 reg = <0x59810000 0x800>;
245 mio_clk: clock {
246 compatible = "socionext,uniphier-pro4-mio-clock";
247 #clock-cells = <1>;
248 };
250 mio_rst: reset {
251 compatible = "socionext,uniphier-pro4-mio-reset";
252 #reset-cells = <1>;
253 };
254 };
256 perictrl@59820000 {
257 compatible = "socionext,uniphier-pro4-perictrl",
258 "simple-mfd", "syscon";
259 reg = <0x59820000 0x200>;
261 peri_clk: clock {
262 compatible = "socionext,uniphier-pro4-peri-clock";
263 #clock-cells = <1>;
264 };
266 peri_rst: reset {
267 compatible = "socionext,uniphier-pro4-peri-reset";
268 #reset-cells = <1>;
269 };
270 };
272 dmac: dma-controller@5a000000 {
273 compatible = "socionext,uniphier-mio-dmac";
274 reg = <0x5a000000 0x1000>;
275 interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
276 <0 71 4>, <0 72 4>, <0 73 4>, <0 74 4>;
277 clocks = <&mio_clk 7>;
278 resets = <&mio_rst 7>;
279 #dma-cells = <1>;
280 };
282 sd: sdhc@5a400000 {
283 compatible = "socionext,uniphier-sd-v2.91";
284 status = "disabled";
285 reg = <0x5a400000 0x200>;
286 interrupts = <0 76 4>;
287 pinctrl-names = "default", "uhs";
288 pinctrl-0 = <&pinctrl_sd>;
289 pinctrl-1 = <&pinctrl_sd_uhs>;
290 clocks = <&mio_clk 0>;
291 reset-names = "host", "bridge";
292 resets = <&mio_rst 0>, <&mio_rst 3>;
293 dma-names = "rx-tx";
294 dmas = <&dmac 4>;
295 bus-width = <4>;
296 cap-sd-highspeed;
297 sd-uhs-sdr12;
298 sd-uhs-sdr25;
299 sd-uhs-sdr50;
300 };
302 emmc: sdhc@5a500000 {
303 compatible = "socionext,uniphier-sd-v2.91";
304 status = "disabled";
305 reg = <0x5a500000 0x200>;
306 interrupts = <0 78 4>;
307 pinctrl-names = "default";
308 pinctrl-0 = <&pinctrl_emmc>;
309 clocks = <&mio_clk 1>;
310 reset-names = "host", "bridge", "hw";
311 resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
312 dma-names = "rx-tx";
313 dmas = <&dmac 5>;
314 bus-width = <8>;
315 cap-mmc-highspeed;
316 cap-mmc-hw-reset;
317 non-removable;
318 };
320 sd1: sdhc@5a600000 {
321 compatible = "socionext,uniphier-sd-v2.91";
322 status = "disabled";
323 reg = <0x5a600000 0x200>;
324 interrupts = <0 85 4>;
325 pinctrl-names = "default";
326 pinctrl-0 = <&pinctrl_sd1>;
327 clocks = <&mio_clk 2>;
328 reset-names = "host", "bridge";
329 resets = <&mio_rst 2>, <&mio_rst 5>;
330 dma-names = "rx-tx";
331 dmas = <&dmac 6>;
332 bus-width = <4>;
333 cap-sd-highspeed;
334 };
336 usb2: usb@5a800100 {
337 compatible = "socionext,uniphier-ehci", "generic-ehci";
338 status = "disabled";
339 reg = <0x5a800100 0x100>;
340 interrupts = <0 80 4>;
341 pinctrl-names = "default";
342 pinctrl-0 = <&pinctrl_usb2>;
343 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
344 <&mio_clk 12>;
345 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
346 <&mio_rst 12>;
347 phy-names = "usb";
348 phys = <&usb_phy0>;
349 has-transaction-translator;
350 };
352 usb3: usb@5a810100 {
353 compatible = "socionext,uniphier-ehci", "generic-ehci";
354 status = "disabled";
355 reg = <0x5a810100 0x100>;
356 interrupts = <0 81 4>;
357 pinctrl-names = "default";
358 pinctrl-0 = <&pinctrl_usb3>;
359 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
360 <&mio_clk 13>;
361 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
362 <&mio_rst 13>;
363 phy-names = "usb";
364 phys = <&usb_phy1>;
365 has-transaction-translator;
366 };
368 soc_glue: soc-glue@5f800000 {
369 compatible = "socionext,uniphier-pro4-soc-glue",
370 "simple-mfd", "syscon";
371 reg = <0x5f800000 0x2000>;
373 pinctrl: pinctrl {
374 compatible = "socionext,uniphier-pro4-pinctrl";
375 };
377 usb-phy {
378 compatible = "socionext,uniphier-pro4-usb2-phy";
379 #address-cells = <1>;
380 #size-cells = <0>;
382 usb_phy0: phy@0 {
383 reg = <0>;
384 #phy-cells = <0>;
385 };
387 usb_phy1: phy@1 {
388 reg = <1>;
389 #phy-cells = <0>;
390 };
392 usb_phy2: phy@2 {
393 reg = <2>;
394 #phy-cells = <0>;
395 vbus-supply = <&usb0_vbus>;
396 };
398 usb_phy3: phy@3 {
399 reg = <3>;
400 #phy-cells = <0>;
401 vbus-supply = <&usb1_vbus>;
402 };
403 };
404 };
406 soc-glue@5f900000 {
407 compatible = "socionext,uniphier-pro4-soc-glue-debug",
408 "simple-mfd";
409 #address-cells = <1>;
410 #size-cells = <1>;
411 ranges = <0 0x5f900000 0x2000>;
413 efuse@100 {
414 compatible = "socionext,uniphier-efuse";
415 reg = <0x100 0x28>;
416 };
418 efuse@130 {
419 compatible = "socionext,uniphier-efuse";
420 reg = <0x130 0x8>;
421 };
423 efuse@200 {
424 compatible = "socionext,uniphier-efuse";
425 reg = <0x200 0x14>;
426 };
427 };
429 aidet: aidet@5fc20000 {
430 compatible = "socionext,uniphier-pro4-aidet";
431 reg = <0x5fc20000 0x200>;
432 interrupt-controller;
433 #interrupt-cells = <2>;
434 };
436 timer@60000200 {
437 compatible = "arm,cortex-a9-global-timer";
438 reg = <0x60000200 0x20>;
439 interrupts = <1 11 0x304>;
440 clocks = <&arm_timer_clk>;
441 };
443 timer@60000600 {
444 compatible = "arm,cortex-a9-twd-timer";
445 reg = <0x60000600 0x20>;
446 interrupts = <1 13 0x304>;
447 clocks = <&arm_timer_clk>;
448 };
450 intc: interrupt-controller@60001000 {
451 compatible = "arm,cortex-a9-gic";
452 reg = <0x60001000 0x1000>,
453 <0x60000100 0x100>;
454 #interrupt-cells = <3>;
455 interrupt-controller;
456 };
458 sysctrl@61840000 {
459 compatible = "socionext,uniphier-pro4-sysctrl",
460 "simple-mfd", "syscon";
461 reg = <0x61840000 0x10000>;
463 sys_clk: clock {
464 compatible = "socionext,uniphier-pro4-clock";
465 #clock-cells = <1>;
466 };
468 sys_rst: reset {
469 compatible = "socionext,uniphier-pro4-reset";
470 #reset-cells = <1>;
471 };
472 };
474 eth: ethernet@65000000 {
475 compatible = "socionext,uniphier-pro4-ave4";
476 status = "disabled";
477 reg = <0x65000000 0x8500>;
478 interrupts = <0 66 4>;
479 pinctrl-names = "default";
480 pinctrl-0 = <&pinctrl_ether_rgmii>;
481 clock-names = "gio", "ether", "ether-gb", "ether-phy";
482 clocks = <&sys_clk 12>, <&sys_clk 6>, <&sys_clk 7>,
483 <&sys_clk 10>;
484 reset-names = "gio", "ether";
485 resets = <&sys_rst 12>, <&sys_rst 6>;
486 phy-mode = "rgmii";
487 local-mac-address = [00 00 00 00 00 00];
488 socionext,syscon-phy-mode = <&soc_glue 0>;
490 mdio: mdio {
491 #address-cells = <1>;
492 #size-cells = <0>;
493 };
494 };
496 usb0: usb@65a00000 {
497 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
498 status = "disabled";
499 reg = <0x65a00000 0xcd00>;
500 interrupt-names = "host", "peripheral";
501 interrupts = <0 134 4>, <0 135 4>;
502 pinctrl-names = "default";
503 pinctrl-0 = <&pinctrl_usb0>;
504 clock-names = "ref", "bus_early", "suspend";
505 clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
506 resets = <&usb0_rst 4>;
507 phys = <&usb_phy2>, <&usb0_ssphy>;
508 dr_mode = "host";
509 };
511 usb-glue@65b00000 {
512 compatible = "socionext,uniphier-pro4-dwc3-glue",
513 "simple-mfd";
514 #address-cells = <1>;
515 #size-cells = <1>;
516 ranges = <0 0x65b00000 0x100>;
518 usb0_vbus: regulator@0 {
519 compatible = "socionext,uniphier-pro4-usb3-regulator";
520 reg = <0 0x10>;
521 clock-names = "gio", "link";
522 clocks = <&sys_clk 12>, <&sys_clk 14>;
523 reset-names = "gio", "link";
524 resets = <&sys_rst 12>, <&sys_rst 14>;
525 };
527 usb0_ssphy: ss-phy@10 {
528 compatible = "socionext,uniphier-pro4-usb3-ssphy";
529 reg = <0x10 0x10>;
530 #phy-cells = <0>;
531 clock-names = "gio", "link";
532 clocks = <&sys_clk 12>, <&sys_clk 14>;
533 reset-names = "gio", "link";
534 resets = <&sys_rst 12>, <&sys_rst 14>;
535 vbus-supply = <&usb0_vbus>;
536 };
538 usb0_rst: reset@40 {
539 compatible = "socionext,uniphier-pro4-usb3-reset";
540 reg = <0x40 0x4>;
541 #reset-cells = <1>;
542 clock-names = "gio", "link";
543 clocks = <&sys_clk 12>, <&sys_clk 14>;
544 reset-names = "gio", "link";
545 resets = <&sys_rst 12>, <&sys_rst 14>;
546 };
547 };
549 usb1: usb@65c00000 {
550 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
551 status = "disabled";
552 reg = <0x65c00000 0xcd00>;
553 interrupt-names = "host", "peripheral";
554 interrupts = <0 137 4>, <0 138 4>;
555 pinctrl-names = "default";
556 pinctrl-0 = <&pinctrl_usb1>;
557 clock-names = "ref", "bus_early", "suspend";
558 clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
559 resets = <&usb1_rst 4>;
560 phys = <&usb_phy3>;
561 dr_mode = "host";
562 };
564 usb-glue@65d00000 {
565 compatible = "socionext,uniphier-pro4-dwc3-glue",
566 "simple-mfd";
567 #address-cells = <1>;
568 #size-cells = <1>;
569 ranges = <0 0x65d00000 0x100>;
571 usb1_vbus: regulator@0 {
572 compatible = "socionext,uniphier-pro4-usb3-regulator";
573 reg = <0 0x10>;
574 clock-names = "gio", "link";
575 clocks = <&sys_clk 12>, <&sys_clk 15>;
576 reset-names = "gio", "link";
577 resets = <&sys_rst 12>, <&sys_rst 15>;
578 };
580 usb1_rst: reset@40 {
581 compatible = "socionext,uniphier-pro4-usb3-reset";
582 reg = <0x40 0x4>;
583 #reset-cells = <1>;
584 clock-names = "gio", "link";
585 clocks = <&sys_clk 12>, <&sys_clk 15>;
586 reset-names = "gio", "link";
587 resets = <&sys_rst 12>, <&sys_rst 15>;
588 };
589 };
591 nand: nand@68000000 {
592 compatible = "socionext,uniphier-denali-nand-v5a";
593 status = "disabled";
594 reg-names = "nand_data", "denali_reg";
595 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
596 #address-cells = <1>;
597 #size-cells = <0>;
598 interrupts = <0 65 4>;
599 pinctrl-names = "default";
600 pinctrl-0 = <&pinctrl_nand>;
601 clock-names = "nand", "nand_x", "ecc";
602 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
603 reset-names = "nand", "reg";
604 resets = <&sys_rst 2>, <&sys_rst 2>;
605 };
606 };
607 };
609 #include "uniphier-pinctrl.dtsi"