Linux 5.6.13
[linux/fpc-iii.git] / include / soc / mscc / ocelot.h
blobf8e1955c86f14c805f0fd7bfdbccceb87b460643
1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
2 /* Copyright (c) 2017 Microsemi Corporation
3 */
5 #ifndef _SOC_MSCC_OCELOT_H
6 #define _SOC_MSCC_OCELOT_H
8 #include <linux/ptp_clock_kernel.h>
9 #include <linux/net_tstamp.h>
10 #include <linux/if_vlan.h>
11 #include <linux/regmap.h>
12 #include <net/dsa.h>
14 #define IFH_INJ_BYPASS BIT(31)
15 #define IFH_INJ_POP_CNT_DISABLE (3 << 28)
17 #define IFH_TAG_TYPE_C 0
18 #define IFH_TAG_TYPE_S 1
20 #define IFH_REW_OP_NOOP 0x0
21 #define IFH_REW_OP_DSCP 0x1
22 #define IFH_REW_OP_ONE_STEP_PTP 0x2
23 #define IFH_REW_OP_TWO_STEP_PTP 0x3
24 #define IFH_REW_OP_ORIGIN_PTP 0x5
26 #define OCELOT_TAG_LEN 16
27 #define OCELOT_SHORT_PREFIX_LEN 4
28 #define OCELOT_LONG_PREFIX_LEN 16
30 #define OCELOT_SPEED_2500 0
31 #define OCELOT_SPEED_1000 1
32 #define OCELOT_SPEED_100 2
33 #define OCELOT_SPEED_10 3
35 #define TARGET_OFFSET 24
36 #define REG_MASK GENMASK(TARGET_OFFSET - 1, 0)
37 #define REG(reg, offset) [reg & REG_MASK] = offset
39 #define REG_RESERVED_ADDR 0xffffffff
40 #define REG_RESERVED(reg) REG(reg, REG_RESERVED_ADDR)
42 enum ocelot_target {
43 ANA = 1,
44 QS,
45 QSYS,
46 REW,
47 SYS,
48 S2,
49 HSIO,
50 PTP,
51 GCB,
52 TARGET_MAX,
55 enum ocelot_reg {
56 ANA_ADVLEARN = ANA << TARGET_OFFSET,
57 ANA_VLANMASK,
58 ANA_PORT_B_DOMAIN,
59 ANA_ANAGEFIL,
60 ANA_ANEVENTS,
61 ANA_STORMLIMIT_BURST,
62 ANA_STORMLIMIT_CFG,
63 ANA_ISOLATED_PORTS,
64 ANA_COMMUNITY_PORTS,
65 ANA_AUTOAGE,
66 ANA_MACTOPTIONS,
67 ANA_LEARNDISC,
68 ANA_AGENCTRL,
69 ANA_MIRRORPORTS,
70 ANA_EMIRRORPORTS,
71 ANA_FLOODING,
72 ANA_FLOODING_IPMC,
73 ANA_SFLOW_CFG,
74 ANA_PORT_MODE,
75 ANA_CUT_THRU_CFG,
76 ANA_PGID_PGID,
77 ANA_TABLES_ANMOVED,
78 ANA_TABLES_MACHDATA,
79 ANA_TABLES_MACLDATA,
80 ANA_TABLES_STREAMDATA,
81 ANA_TABLES_MACACCESS,
82 ANA_TABLES_MACTINDX,
83 ANA_TABLES_VLANACCESS,
84 ANA_TABLES_VLANTIDX,
85 ANA_TABLES_ISDXACCESS,
86 ANA_TABLES_ISDXTIDX,
87 ANA_TABLES_ENTRYLIM,
88 ANA_TABLES_PTP_ID_HIGH,
89 ANA_TABLES_PTP_ID_LOW,
90 ANA_TABLES_STREAMACCESS,
91 ANA_TABLES_STREAMTIDX,
92 ANA_TABLES_SEQ_HISTORY,
93 ANA_TABLES_SEQ_MASK,
94 ANA_TABLES_SFID_MASK,
95 ANA_TABLES_SFIDACCESS,
96 ANA_TABLES_SFIDTIDX,
97 ANA_MSTI_STATE,
98 ANA_OAM_UPM_LM_CNT,
99 ANA_SG_ACCESS_CTRL,
100 ANA_SG_CONFIG_REG_1,
101 ANA_SG_CONFIG_REG_2,
102 ANA_SG_CONFIG_REG_3,
103 ANA_SG_CONFIG_REG_4,
104 ANA_SG_CONFIG_REG_5,
105 ANA_SG_GCL_GS_CONFIG,
106 ANA_SG_GCL_TI_CONFIG,
107 ANA_SG_STATUS_REG_1,
108 ANA_SG_STATUS_REG_2,
109 ANA_SG_STATUS_REG_3,
110 ANA_PORT_VLAN_CFG,
111 ANA_PORT_DROP_CFG,
112 ANA_PORT_QOS_CFG,
113 ANA_PORT_VCAP_CFG,
114 ANA_PORT_VCAP_S1_KEY_CFG,
115 ANA_PORT_VCAP_S2_CFG,
116 ANA_PORT_PCP_DEI_MAP,
117 ANA_PORT_CPU_FWD_CFG,
118 ANA_PORT_CPU_FWD_BPDU_CFG,
119 ANA_PORT_CPU_FWD_GARP_CFG,
120 ANA_PORT_CPU_FWD_CCM_CFG,
121 ANA_PORT_PORT_CFG,
122 ANA_PORT_POL_CFG,
123 ANA_PORT_PTP_CFG,
124 ANA_PORT_PTP_DLY1_CFG,
125 ANA_PORT_PTP_DLY2_CFG,
126 ANA_PORT_SFID_CFG,
127 ANA_PFC_PFC_CFG,
128 ANA_PFC_PFC_TIMER,
129 ANA_IPT_OAM_MEP_CFG,
130 ANA_IPT_IPT,
131 ANA_PPT_PPT,
132 ANA_FID_MAP_FID_MAP,
133 ANA_AGGR_CFG,
134 ANA_CPUQ_CFG,
135 ANA_CPUQ_CFG2,
136 ANA_CPUQ_8021_CFG,
137 ANA_DSCP_CFG,
138 ANA_DSCP_REWR_CFG,
139 ANA_VCAP_RNG_TYPE_CFG,
140 ANA_VCAP_RNG_VAL_CFG,
141 ANA_VRAP_CFG,
142 ANA_VRAP_HDR_DATA,
143 ANA_VRAP_HDR_MASK,
144 ANA_DISCARD_CFG,
145 ANA_FID_CFG,
146 ANA_POL_PIR_CFG,
147 ANA_POL_CIR_CFG,
148 ANA_POL_MODE_CFG,
149 ANA_POL_PIR_STATE,
150 ANA_POL_CIR_STATE,
151 ANA_POL_STATE,
152 ANA_POL_FLOWC,
153 ANA_POL_HYST,
154 ANA_POL_MISC_CFG,
155 QS_XTR_GRP_CFG = QS << TARGET_OFFSET,
156 QS_XTR_RD,
157 QS_XTR_FRM_PRUNING,
158 QS_XTR_FLUSH,
159 QS_XTR_DATA_PRESENT,
160 QS_XTR_CFG,
161 QS_INJ_GRP_CFG,
162 QS_INJ_WR,
163 QS_INJ_CTRL,
164 QS_INJ_STATUS,
165 QS_INJ_ERR,
166 QS_INH_DBG,
167 QSYS_PORT_MODE = QSYS << TARGET_OFFSET,
168 QSYS_SWITCH_PORT_MODE,
169 QSYS_STAT_CNT_CFG,
170 QSYS_EEE_CFG,
171 QSYS_EEE_THRES,
172 QSYS_IGR_NO_SHARING,
173 QSYS_EGR_NO_SHARING,
174 QSYS_SW_STATUS,
175 QSYS_EXT_CPU_CFG,
176 QSYS_PAD_CFG,
177 QSYS_CPU_GROUP_MAP,
178 QSYS_QMAP,
179 QSYS_ISDX_SGRP,
180 QSYS_TIMED_FRAME_ENTRY,
181 QSYS_TFRM_MISC,
182 QSYS_TFRM_PORT_DLY,
183 QSYS_TFRM_TIMER_CFG_1,
184 QSYS_TFRM_TIMER_CFG_2,
185 QSYS_TFRM_TIMER_CFG_3,
186 QSYS_TFRM_TIMER_CFG_4,
187 QSYS_TFRM_TIMER_CFG_5,
188 QSYS_TFRM_TIMER_CFG_6,
189 QSYS_TFRM_TIMER_CFG_7,
190 QSYS_TFRM_TIMER_CFG_8,
191 QSYS_RED_PROFILE,
192 QSYS_RES_QOS_MODE,
193 QSYS_RES_CFG,
194 QSYS_RES_STAT,
195 QSYS_EGR_DROP_MODE,
196 QSYS_EQ_CTRL,
197 QSYS_EVENTS_CORE,
198 QSYS_QMAXSDU_CFG_0,
199 QSYS_QMAXSDU_CFG_1,
200 QSYS_QMAXSDU_CFG_2,
201 QSYS_QMAXSDU_CFG_3,
202 QSYS_QMAXSDU_CFG_4,
203 QSYS_QMAXSDU_CFG_5,
204 QSYS_QMAXSDU_CFG_6,
205 QSYS_QMAXSDU_CFG_7,
206 QSYS_PREEMPTION_CFG,
207 QSYS_CIR_CFG,
208 QSYS_EIR_CFG,
209 QSYS_SE_CFG,
210 QSYS_SE_DWRR_CFG,
211 QSYS_SE_CONNECT,
212 QSYS_SE_DLB_SENSE,
213 QSYS_CIR_STATE,
214 QSYS_EIR_STATE,
215 QSYS_SE_STATE,
216 QSYS_HSCH_MISC_CFG,
217 QSYS_TAG_CONFIG,
218 QSYS_TAS_PARAM_CFG_CTRL,
219 QSYS_PORT_MAX_SDU,
220 QSYS_PARAM_CFG_REG_1,
221 QSYS_PARAM_CFG_REG_2,
222 QSYS_PARAM_CFG_REG_3,
223 QSYS_PARAM_CFG_REG_4,
224 QSYS_PARAM_CFG_REG_5,
225 QSYS_GCL_CFG_REG_1,
226 QSYS_GCL_CFG_REG_2,
227 QSYS_PARAM_STATUS_REG_1,
228 QSYS_PARAM_STATUS_REG_2,
229 QSYS_PARAM_STATUS_REG_3,
230 QSYS_PARAM_STATUS_REG_4,
231 QSYS_PARAM_STATUS_REG_5,
232 QSYS_PARAM_STATUS_REG_6,
233 QSYS_PARAM_STATUS_REG_7,
234 QSYS_PARAM_STATUS_REG_8,
235 QSYS_PARAM_STATUS_REG_9,
236 QSYS_GCL_STATUS_REG_1,
237 QSYS_GCL_STATUS_REG_2,
238 REW_PORT_VLAN_CFG = REW << TARGET_OFFSET,
239 REW_TAG_CFG,
240 REW_PORT_CFG,
241 REW_DSCP_CFG,
242 REW_PCP_DEI_QOS_MAP_CFG,
243 REW_PTP_CFG,
244 REW_PTP_DLY1_CFG,
245 REW_RED_TAG_CFG,
246 REW_DSCP_REMAP_DP1_CFG,
247 REW_DSCP_REMAP_CFG,
248 REW_STAT_CFG,
249 REW_REW_STICKY,
250 REW_PPT,
251 SYS_COUNT_RX_OCTETS = SYS << TARGET_OFFSET,
252 SYS_COUNT_RX_UNICAST,
253 SYS_COUNT_RX_MULTICAST,
254 SYS_COUNT_RX_BROADCAST,
255 SYS_COUNT_RX_SHORTS,
256 SYS_COUNT_RX_FRAGMENTS,
257 SYS_COUNT_RX_JABBERS,
258 SYS_COUNT_RX_CRC_ALIGN_ERRS,
259 SYS_COUNT_RX_SYM_ERRS,
260 SYS_COUNT_RX_64,
261 SYS_COUNT_RX_65_127,
262 SYS_COUNT_RX_128_255,
263 SYS_COUNT_RX_256_1023,
264 SYS_COUNT_RX_1024_1526,
265 SYS_COUNT_RX_1527_MAX,
266 SYS_COUNT_RX_PAUSE,
267 SYS_COUNT_RX_CONTROL,
268 SYS_COUNT_RX_LONGS,
269 SYS_COUNT_RX_CLASSIFIED_DROPS,
270 SYS_COUNT_TX_OCTETS,
271 SYS_COUNT_TX_UNICAST,
272 SYS_COUNT_TX_MULTICAST,
273 SYS_COUNT_TX_BROADCAST,
274 SYS_COUNT_TX_COLLISION,
275 SYS_COUNT_TX_DROPS,
276 SYS_COUNT_TX_PAUSE,
277 SYS_COUNT_TX_64,
278 SYS_COUNT_TX_65_127,
279 SYS_COUNT_TX_128_511,
280 SYS_COUNT_TX_512_1023,
281 SYS_COUNT_TX_1024_1526,
282 SYS_COUNT_TX_1527_MAX,
283 SYS_COUNT_TX_AGING,
284 SYS_RESET_CFG,
285 SYS_SR_ETYPE_CFG,
286 SYS_VLAN_ETYPE_CFG,
287 SYS_PORT_MODE,
288 SYS_FRONT_PORT_MODE,
289 SYS_FRM_AGING,
290 SYS_STAT_CFG,
291 SYS_SW_STATUS,
292 SYS_MISC_CFG,
293 SYS_REW_MAC_HIGH_CFG,
294 SYS_REW_MAC_LOW_CFG,
295 SYS_TIMESTAMP_OFFSET,
296 SYS_CMID,
297 SYS_PAUSE_CFG,
298 SYS_PAUSE_TOT_CFG,
299 SYS_ATOP,
300 SYS_ATOP_TOT_CFG,
301 SYS_MAC_FC_CFG,
302 SYS_MMGT,
303 SYS_MMGT_FAST,
304 SYS_EVENTS_DIF,
305 SYS_EVENTS_CORE,
306 SYS_CNT,
307 SYS_PTP_STATUS,
308 SYS_PTP_TXSTAMP,
309 SYS_PTP_NXT,
310 SYS_PTP_CFG,
311 SYS_RAM_INIT,
312 SYS_CM_ADDR,
313 SYS_CM_DATA_WR,
314 SYS_CM_DATA_RD,
315 SYS_CM_OP,
316 SYS_CM_DATA,
317 S2_CORE_UPDATE_CTRL = S2 << TARGET_OFFSET,
318 S2_CORE_MV_CFG,
319 S2_CACHE_ENTRY_DAT,
320 S2_CACHE_MASK_DAT,
321 S2_CACHE_ACTION_DAT,
322 S2_CACHE_CNT_DAT,
323 S2_CACHE_TG_DAT,
324 PTP_PIN_CFG = PTP << TARGET_OFFSET,
325 PTP_PIN_TOD_SEC_MSB,
326 PTP_PIN_TOD_SEC_LSB,
327 PTP_PIN_TOD_NSEC,
328 PTP_CFG_MISC,
329 PTP_CLK_CFG_ADJ_CFG,
330 PTP_CLK_CFG_ADJ_FREQ,
331 GCB_SOFT_RST = GCB << TARGET_OFFSET,
334 enum ocelot_regfield {
335 ANA_ADVLEARN_VLAN_CHK,
336 ANA_ADVLEARN_LEARN_MIRROR,
337 ANA_ANEVENTS_FLOOD_DISCARD,
338 ANA_ANEVENTS_MSTI_DROP,
339 ANA_ANEVENTS_ACLKILL,
340 ANA_ANEVENTS_ACLUSED,
341 ANA_ANEVENTS_AUTOAGE,
342 ANA_ANEVENTS_VS2TTL1,
343 ANA_ANEVENTS_STORM_DROP,
344 ANA_ANEVENTS_LEARN_DROP,
345 ANA_ANEVENTS_AGED_ENTRY,
346 ANA_ANEVENTS_CPU_LEARN_FAILED,
347 ANA_ANEVENTS_AUTO_LEARN_FAILED,
348 ANA_ANEVENTS_LEARN_REMOVE,
349 ANA_ANEVENTS_AUTO_LEARNED,
350 ANA_ANEVENTS_AUTO_MOVED,
351 ANA_ANEVENTS_DROPPED,
352 ANA_ANEVENTS_CLASSIFIED_DROP,
353 ANA_ANEVENTS_CLASSIFIED_COPY,
354 ANA_ANEVENTS_VLAN_DISCARD,
355 ANA_ANEVENTS_FWD_DISCARD,
356 ANA_ANEVENTS_MULTICAST_FLOOD,
357 ANA_ANEVENTS_UNICAST_FLOOD,
358 ANA_ANEVENTS_DEST_KNOWN,
359 ANA_ANEVENTS_BUCKET3_MATCH,
360 ANA_ANEVENTS_BUCKET2_MATCH,
361 ANA_ANEVENTS_BUCKET1_MATCH,
362 ANA_ANEVENTS_BUCKET0_MATCH,
363 ANA_ANEVENTS_CPU_OPERATION,
364 ANA_ANEVENTS_DMAC_LOOKUP,
365 ANA_ANEVENTS_SMAC_LOOKUP,
366 ANA_ANEVENTS_SEQ_GEN_ERR_0,
367 ANA_ANEVENTS_SEQ_GEN_ERR_1,
368 ANA_TABLES_MACACCESS_B_DOM,
369 ANA_TABLES_MACTINDX_BUCKET,
370 ANA_TABLES_MACTINDX_M_INDEX,
371 QSYS_TIMED_FRAME_ENTRY_TFRM_VLD,
372 QSYS_TIMED_FRAME_ENTRY_TFRM_FP,
373 QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO,
374 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL,
375 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T,
376 SYS_RESET_CFG_CORE_ENA,
377 SYS_RESET_CFG_MEM_ENA,
378 SYS_RESET_CFG_MEM_INIT,
379 GCB_SOFT_RST_SWC_RST,
380 REGFIELD_MAX
383 enum ocelot_clk_pins {
384 ALT_PPS_PIN = 1,
385 EXT_CLK_PIN,
386 ALT_LDST_PIN,
387 TOD_ACC_PIN
390 struct ocelot_stat_layout {
391 u32 offset;
392 char name[ETH_GSTRING_LEN];
395 enum ocelot_tag_prefix {
396 OCELOT_TAG_PREFIX_DISABLED = 0,
397 OCELOT_TAG_PREFIX_NONE,
398 OCELOT_TAG_PREFIX_SHORT,
399 OCELOT_TAG_PREFIX_LONG,
402 struct ocelot;
404 struct ocelot_ops {
405 void (*pcs_init)(struct ocelot *ocelot, int port);
406 int (*reset)(struct ocelot *ocelot);
409 struct ocelot_port {
410 struct ocelot *ocelot;
412 void __iomem *regs;
414 bool vlan_aware;
416 /* Ingress default VLAN (pvid) */
417 u16 pvid;
419 /* Egress default VLAN (vid) */
420 u16 vid;
422 u8 ptp_cmd;
423 struct sk_buff_head tx_skbs;
424 u8 ts_id;
426 phy_interface_t phy_mode;
429 struct ocelot {
430 struct device *dev;
432 const struct ocelot_ops *ops;
433 struct regmap *targets[TARGET_MAX];
434 struct regmap_field *regfields[REGFIELD_MAX];
435 const u32 *const *map;
436 const struct ocelot_stat_layout *stats_layout;
437 unsigned int num_stats;
439 int shared_queue_sz;
441 struct net_device *hw_bridge_dev;
442 u16 bridge_mask;
443 u16 bridge_fwd_mask;
445 struct ocelot_port **ports;
447 u8 base_mac[ETH_ALEN];
449 /* Keep track of the vlan port masks */
450 u32 vlan_mask[VLAN_N_VID];
452 u8 num_phys_ports;
453 u8 num_cpu_ports;
454 u8 cpu;
456 u32 *lags;
458 struct list_head multicast;
460 /* Workqueue to check statistics for overflow with its lock */
461 struct mutex stats_lock;
462 u64 *stats;
463 struct delayed_work stats_work;
464 struct workqueue_struct *stats_queue;
466 u8 ptp:1;
467 struct ptp_clock *ptp_clock;
468 struct ptp_clock_info ptp_info;
469 struct hwtstamp_config hwtstamp_config;
470 /* Protects the PTP interface state */
471 struct mutex ptp_lock;
472 /* Protects the PTP clock */
473 spinlock_t ptp_clock_lock;
475 void (*port_pcs_init)(struct ocelot_port *port);
478 #define ocelot_read_ix(ocelot, reg, gi, ri) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
479 #define ocelot_read_gix(ocelot, reg, gi) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi))
480 #define ocelot_read_rix(ocelot, reg, ri) __ocelot_read_ix(ocelot, reg, reg##_RSZ * (ri))
481 #define ocelot_read(ocelot, reg) __ocelot_read_ix(ocelot, reg, 0)
483 #define ocelot_write_ix(ocelot, val, reg, gi, ri) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
484 #define ocelot_write_gix(ocelot, val, reg, gi) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi))
485 #define ocelot_write_rix(ocelot, val, reg, ri) __ocelot_write_ix(ocelot, val, reg, reg##_RSZ * (ri))
486 #define ocelot_write(ocelot, val, reg) __ocelot_write_ix(ocelot, val, reg, 0)
488 #define ocelot_rmw_ix(ocelot, val, m, reg, gi, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
489 #define ocelot_rmw_gix(ocelot, val, m, reg, gi) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi))
490 #define ocelot_rmw_rix(ocelot, val, m, reg, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_RSZ * (ri))
491 #define ocelot_rmw(ocelot, val, m, reg) __ocelot_rmw_ix(ocelot, val, m, reg, 0)
493 /* I/O */
494 u32 ocelot_port_readl(struct ocelot_port *port, u32 reg);
495 void ocelot_port_writel(struct ocelot_port *port, u32 val, u32 reg);
496 u32 __ocelot_read_ix(struct ocelot *ocelot, u32 reg, u32 offset);
497 void __ocelot_write_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 offset);
498 void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 mask, u32 reg,
499 u32 offset);
501 /* Hardware initialization */
502 int ocelot_regfields_init(struct ocelot *ocelot,
503 const struct reg_field *const regfields);
504 struct regmap *ocelot_regmap_init(struct ocelot *ocelot, struct resource *res);
505 void ocelot_set_cpu_port(struct ocelot *ocelot, int cpu,
506 enum ocelot_tag_prefix injection,
507 enum ocelot_tag_prefix extraction);
508 int ocelot_init(struct ocelot *ocelot);
509 void ocelot_deinit(struct ocelot *ocelot);
510 void ocelot_init_port(struct ocelot *ocelot, int port);
512 /* DSA callbacks */
513 void ocelot_port_enable(struct ocelot *ocelot, int port,
514 struct phy_device *phy);
515 void ocelot_port_disable(struct ocelot *ocelot, int port);
516 void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data);
517 void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data);
518 int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset);
519 int ocelot_get_ts_info(struct ocelot *ocelot, int port,
520 struct ethtool_ts_info *info);
521 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs);
522 void ocelot_adjust_link(struct ocelot *ocelot, int port,
523 struct phy_device *phydev);
524 void ocelot_port_vlan_filtering(struct ocelot *ocelot, int port,
525 bool vlan_aware);
526 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state);
527 int ocelot_port_bridge_join(struct ocelot *ocelot, int port,
528 struct net_device *bridge);
529 int ocelot_port_bridge_leave(struct ocelot *ocelot, int port,
530 struct net_device *bridge);
531 int ocelot_fdb_dump(struct ocelot *ocelot, int port,
532 dsa_fdb_dump_cb_t *cb, void *data);
533 int ocelot_fdb_add(struct ocelot *ocelot, int port,
534 const unsigned char *addr, u16 vid);
535 int ocelot_fdb_del(struct ocelot *ocelot, int port,
536 const unsigned char *addr, u16 vid);
537 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid,
538 bool untagged);
539 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid);
540 int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr);
541 int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr);
542 int ocelot_ptp_gettime64(struct ptp_clock_info *ptp, struct timespec64 *ts);
543 int ocelot_port_add_txtstamp_skb(struct ocelot_port *ocelot_port,
544 struct sk_buff *skb);
545 void ocelot_get_txtstamp(struct ocelot *ocelot);
547 #endif