arch/arm64/boot/dts/rockchip/rk3328.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
   4  */
   5
   6 #include <dt-bindings/clock/rk3328-cru.h>
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/interrupt-controller/irq.h>
  10 #include <dt-bindings/pinctrl/rockchip.h>
  11 #include <dt-bindings/power/rk3328-power.h>
  12 #include <dt-bindings/soc/rockchip,boot-mode.h>
  13 #include <dt-bindings/thermal/thermal.h>
  14
  15 / {
  16         compatible = "rockchip,rk3328";
  17
  18         interrupt-parent = <&gic>;
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         aliases {
  23                 serial0 = &uart0;
  24                 serial1 = &uart1;
  25                 serial2 = &uart2;
  26                 i2c0 = &i2c0;
  27                 i2c1 = &i2c1;
  28                 i2c2 = &i2c2;
  29                 i2c3 = &i2c3;
  30                 ethernet0 = &gmac2io;
  31                 ethernet1 = &gmac2phy;
  32         };
  33
  34         cpus {
  35                 #address-cells = <2>;
  36                 #size-cells = <0>;
  37
  38                 cpu0: cpu@0 {
  39                         device_type = "cpu";
  40                         compatible = "arm,cortex-a53";
  41                         reg = <0x0 0x0>;
  42                         clocks = <&cru ARMCLK>;
  43                         #cooling-cells = <2>;
  44                         dynamic-power-coefficient = <120>;
  45                         enable-method = "psci";
  46                         next-level-cache = <&l2>;
  47                         operating-points-v2 = <&cpu0_opp_table>;
  48                 };
  49
  50                 cpu1: cpu@1 {
  51                         device_type = "cpu";
  52                         compatible = "arm,cortex-a53";
  53                         reg = <0x0 0x1>;
  54                         clocks = <&cru ARMCLK>;
  55                         #cooling-cells = <2>;
  56                         dynamic-power-coefficient = <120>;
  57                         enable-method = "psci";
  58                         next-level-cache = <&l2>;
  59                         operating-points-v2 = <&cpu0_opp_table>;
  60                 };
  61
  62                 cpu2: cpu@2 {
  63                         device_type = "cpu";
  64                         compatible = "arm,cortex-a53";
  65                         reg = <0x0 0x2>;
  66                         clocks = <&cru ARMCLK>;
  67                         #cooling-cells = <2>;
  68                         dynamic-power-coefficient = <120>;
  69                         enable-method = "psci";
  70                         next-level-cache = <&l2>;
  71                         operating-points-v2 = <&cpu0_opp_table>;
  72                 };
  73
  74                 cpu3: cpu@3 {
  75                         device_type = "cpu";
  76                         compatible = "arm,cortex-a53";
  77                         reg = <0x0 0x3>;
  78                         clocks = <&cru ARMCLK>;
  79                         #cooling-cells = <2>;
  80                         dynamic-power-coefficient = <120>;
  81                         enable-method = "psci";
  82                         next-level-cache = <&l2>;
  83                         operating-points-v2 = <&cpu0_opp_table>;
  84                 };
  85
  86                 l2: l2-cache0 {
  87                         compatible = "cache";
  88                 };
  89         };
  90
  91         cpu0_opp_table: opp_table0 {
  92                 compatible = "operating-points-v2";
  93                 opp-shared;
  94
  95                 opp-408000000 {
  96                         opp-hz = /bits/ 64 <408000000>;
  97                         opp-microvolt = <950000>;
  98                         clock-latency-ns = <40000>;
  99                         opp-suspend;
 100                 };
 101                 opp-600000000 {
 102                         opp-hz = /bits/ 64 <600000000>;
 103                         opp-microvolt = <950000>;
 104                         clock-latency-ns = <40000>;
 105                 };
 106                 opp-816000000 {
 107                         opp-hz = /bits/ 64 <816000000>;
 108                         opp-microvolt = <1000000>;
 109                         clock-latency-ns = <40000>;
 110                 };
 111                 opp-1008000000 {
 112                         opp-hz = /bits/ 64 <1008000000>;
 113                         opp-microvolt = <1100000>;
 114                         clock-latency-ns = <40000>;
 115                 };
 116                 opp-1200000000 {
 117                         opp-hz = /bits/ 64 <1200000000>;
 118                         opp-microvolt = <1225000>;
 119                         clock-latency-ns = <40000>;
 120                 };
 121                 opp-1296000000 {
 122                         opp-hz = /bits/ 64 <1296000000>;
 123                         opp-microvolt = <1300000>;
 124                         clock-latency-ns = <40000>;
 125                 };
 126         };
 127
 128         amba {
 129                 compatible = "simple-bus";
 130                 #address-cells = <2>;
 131                 #size-cells = <2>;
 132                 ranges;
 133
 134                 dmac: dmac@ff1f0000 {
 135                         compatible = "arm,pl330", "arm,primecell";
 136                         reg = <0x0 0xff1f0000 0x0 0x4000>;
 137                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 138                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 139                         clocks = <&cru ACLK_DMAC>;
 140                         clock-names = "apb_pclk";
 141                         #dma-cells = <1>;
 142                 };
 143         };
 144
 145         arm-pmu {
 146                 compatible = "arm,cortex-a53-pmu";
 147                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 148                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 149                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 150                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 151                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 152         };
 153
 154         display_subsystem: display-subsystem {
 155                 compatible = "rockchip,display-subsystem";
 156                 ports = <&vop_out>;
 157         };
 158
 159         psci {
 160                 compatible = "arm,psci-1.0", "arm,psci-0.2";
 161                 method = "smc";
 162         };
 163
 164         timer {
 165                 compatible = "arm,armv8-timer";
 166                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 167                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 168                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 169                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 170         };
 171
 172         xin24m: xin24m {
 173                 compatible = "fixed-clock";
 174                 #clock-cells = <0>;
 175                 clock-frequency = <24000000>;
 176                 clock-output-names = "xin24m";
 177         };
 178
 179         i2s0: i2s@ff000000 {
 180                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 181                 reg = <0x0 0xff000000 0x0 0x1000>;
 182                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 183                 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
 184                 clock-names = "i2s_clk", "i2s_hclk";
 185                 dmas = <&dmac 11>, <&dmac 12>;
 186                 dma-names = "tx", "rx";
 187                 #sound-dai-cells = <0>;
 188                 status = "disabled";
 189         };
 190
 191         i2s1: i2s@ff010000 {
 192                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 193                 reg = <0x0 0xff010000 0x0 0x1000>;
 194                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 195                 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
 196                 clock-names = "i2s_clk", "i2s_hclk";
 197                 dmas = <&dmac 14>, <&dmac 15>;
 198                 dma-names = "tx", "rx";
 199                 #sound-dai-cells = <0>;
 200                 status = "disabled";
 201         };
 202
 203         i2s2: i2s@ff020000 {
 204                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 205                 reg = <0x0 0xff020000 0x0 0x1000>;
 206                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 207                 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
 208                 clock-names = "i2s_clk", "i2s_hclk";
 209                 dmas = <&dmac 0>, <&dmac 1>;
 210                 dma-names = "tx", "rx";
 211                 #sound-dai-cells = <0>;
 212                 status = "disabled";
 213         };
 214
 215         spdif: spdif@ff030000 {
 216                 compatible = "rockchip,rk3328-spdif";
 217                 reg = <0x0 0xff030000 0x0 0x1000>;
 218                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 219                 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
 220                 clock-names = "mclk", "hclk";
 221                 dmas = <&dmac 10>;
 222                 dma-names = "tx";
 223                 pinctrl-names = "default";
 224                 pinctrl-0 = <&spdifm2_tx>;
 225                 #sound-dai-cells = <0>;
 226                 status = "disabled";
 227         };
 228
 229         pdm: pdm@ff040000 {
 230                 compatible = "rockchip,pdm";
 231                 reg = <0x0 0xff040000 0x0 0x1000>;
 232                 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
 233                 clock-names = "pdm_clk", "pdm_hclk";
 234                 dmas = <&dmac 16>;
 235                 dma-names = "rx";
 236                 pinctrl-names = "default", "sleep";
 237                 pinctrl-0 = <&pdmm0_clk
 238                              &pdmm0_sdi0
 239                              &pdmm0_sdi1
 240                              &pdmm0_sdi2
 241                              &pdmm0_sdi3>;
 242                 pinctrl-1 = <&pdmm0_clk_sleep
 243                              &pdmm0_sdi0_sleep
 244                              &pdmm0_sdi1_sleep
 245                              &pdmm0_sdi2_sleep
 246                              &pdmm0_sdi3_sleep>;
 247                 status = "disabled";
 248         };
 249
 250         grf: syscon@ff100000 {
 251                 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
 252                 reg = <0x0 0xff100000 0x0 0x1000>;
 253                 #address-cells = <1>;
 254                 #size-cells = <1>;
 255
 256                 io_domains: io-domains {
 257                         compatible = "rockchip,rk3328-io-voltage-domain";
 258                         status = "disabled";
 259                 };
 260
 261                 grf_gpio: grf-gpio {
 262                         compatible = "rockchip,rk3328-grf-gpio";
 263                         gpio-controller;
 264                         #gpio-cells = <2>;
 265                 };
 266
 267                 power: power-controller {
 268                         compatible = "rockchip,rk3328-power-controller";
 269                         #power-domain-cells = <1>;
 270                         #address-cells = <1>;
 271                         #size-cells = <0>;
 272
 273                         pd_hevc@RK3328_PD_HEVC {
 274                                 reg = <RK3328_PD_HEVC>;
 275                         };
 276                         pd_video@RK3328_PD_VIDEO {
 277                                 reg = <RK3328_PD_VIDEO>;
 278                         };
 279                         pd_vpu@RK3328_PD_VPU {
 280                                 reg = <RK3328_PD_VPU>;
 281                         };
 282                 };
 283
 284                 reboot-mode {
 285                         compatible = "syscon-reboot-mode";
 286                         offset = <0x5c8>;
 287                         mode-normal = <BOOT_NORMAL>;
 288                         mode-recovery = <BOOT_RECOVERY>;
 289                         mode-bootloader = <BOOT_FASTBOOT>;
 290                         mode-loader = <BOOT_BL_DOWNLOAD>;
 291                 };
 292         };
 293
 294         uart0: serial@ff110000 {
 295                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 296                 reg = <0x0 0xff110000 0x0 0x100>;
 297                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 298                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 299                 clock-names = "baudclk", "apb_pclk";
 300                 dmas = <&dmac 2>, <&dmac 3>;
 301                 dma-names = "tx", "rx";
 302                 pinctrl-names = "default";
 303                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 304                 reg-io-width = <4>;
 305                 reg-shift = <2>;
 306                 status = "disabled";
 307         };
 308
 309         uart1: serial@ff120000 {
 310                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 311                 reg = <0x0 0xff120000 0x0 0x100>;
 312                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 313                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 314                 clock-names = "baudclk", "apb_pclk";
 315                 dmas = <&dmac 4>, <&dmac 5>;
 316                 dma-names = "tx", "rx";
 317                 pinctrl-names = "default";
 318                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 319                 reg-io-width = <4>;
 320                 reg-shift = <2>;
 321                 status = "disabled";
 322         };
 323
 324         uart2: serial@ff130000 {
 325                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 326                 reg = <0x0 0xff130000 0x0 0x100>;
 327                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 328                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 329                 clock-names = "baudclk", "apb_pclk";
 330                 dmas = <&dmac 6>, <&dmac 7>;
 331                 dma-names = "tx", "rx";
 332                 pinctrl-names = "default";
 333                 pinctrl-0 = <&uart2m1_xfer>;
 334                 reg-io-width = <4>;
 335                 reg-shift = <2>;
 336                 status = "disabled";
 337         };
 338
 339         i2c0: i2c@ff150000 {
 340                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 341                 reg = <0x0 0xff150000 0x0 0x1000>;
 342                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 343                 #address-cells = <1>;
 344                 #size-cells = <0>;
 345                 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
 346                 clock-names = "i2c", "pclk";
 347                 pinctrl-names = "default";
 348                 pinctrl-0 = <&i2c0_xfer>;
 349                 status = "disabled";
 350         };
 351
 352         i2c1: i2c@ff160000 {
 353                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 354                 reg = <0x0 0xff160000 0x0 0x1000>;
 355                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 356                 #address-cells = <1>;
 357                 #size-cells = <0>;
 358                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 359                 clock-names = "i2c", "pclk";
 360                 pinctrl-names = "default";
 361                 pinctrl-0 = <&i2c1_xfer>;
 362                 status = "disabled";
 363         };
 364
 365         i2c2: i2c@ff170000 {
 366                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 367                 reg = <0x0 0xff170000 0x0 0x1000>;
 368                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 369                 #address-cells = <1>;
 370                 #size-cells = <0>;
 371                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 372                 clock-names = "i2c", "pclk";
 373                 pinctrl-names = "default";
 374                 pinctrl-0 = <&i2c2_xfer>;
 375                 status = "disabled";
 376         };
 377
 378         i2c3: i2c@ff180000 {
 379                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 380                 reg = <0x0 0xff180000 0x0 0x1000>;
 381                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 382                 #address-cells = <1>;
 383                 #size-cells = <0>;
 384                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 385                 clock-names = "i2c", "pclk";
 386                 pinctrl-names = "default";
 387                 pinctrl-0 = <&i2c3_xfer>;
 388                 status = "disabled";
 389         };
 390
 391         spi0: spi@ff190000 {
 392                 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
 393                 reg = <0x0 0xff190000 0x0 0x1000>;
 394                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 395                 #address-cells = <1>;
 396                 #size-cells = <0>;
 397                 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
 398                 clock-names = "spiclk", "apb_pclk";
 399                 dmas = <&dmac 8>, <&dmac 9>;
 400                 dma-names = "tx", "rx";
 401                 pinctrl-names = "default";
 402                 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
 403                 status = "disabled";
 404         };
 405
 406         wdt: watchdog@ff1a0000 {
 407                 compatible = "snps,dw-wdt";
 408                 reg = <0x0 0xff1a0000 0x0 0x100>;
 409                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 410                 clocks = <&cru PCLK_WDT>;
 411         };
 412
 413         pwm0: pwm@ff1b0000 {
 414                 compatible = "rockchip,rk3328-pwm";
 415                 reg = <0x0 0xff1b0000 0x0 0x10>;
 416                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 417                 clock-names = "pwm", "pclk";
 418                 pinctrl-names = "default";
 419                 pinctrl-0 = <&pwm0_pin>;
 420                 #pwm-cells = <3>;
 421                 status = "disabled";
 422         };
 423
 424         pwm1: pwm@ff1b0010 {
 425                 compatible = "rockchip,rk3328-pwm";
 426                 reg = <0x0 0xff1b0010 0x0 0x10>;
 427                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 428                 clock-names = "pwm", "pclk";
 429                 pinctrl-names = "default";
 430                 pinctrl-0 = <&pwm1_pin>;
 431                 #pwm-cells = <3>;
 432                 status = "disabled";
 433         };
 434
 435         pwm2: pwm@ff1b0020 {
 436                 compatible = "rockchip,rk3328-pwm";
 437                 reg = <0x0 0xff1b0020 0x0 0x10>;
 438                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 439                 clock-names = "pwm", "pclk";
 440                 pinctrl-names = "default";
 441                 pinctrl-0 = <&pwm2_pin>;
 442                 #pwm-cells = <3>;
 443                 status = "disabled";
 444         };
 445
 446         pwm3: pwm@ff1b0030 {
 447                 compatible = "rockchip,rk3328-pwm";
 448                 reg = <0x0 0xff1b0030 0x0 0x10>;
 449                 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 450                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 451                 clock-names = "pwm", "pclk";
 452                 pinctrl-names = "default";
 453                 pinctrl-0 = <&pwmir_pin>;
 454                 #pwm-cells = <3>;
 455                 status = "disabled";
 456         };
 457
 458         thermal-zones {
 459                 soc_thermal: soc-thermal {
 460                         polling-delay-passive = <20>;
 461                         polling-delay = <1000>;
 462                         sustainable-power = <1000>;
 463
 464                         thermal-sensors = <&tsadc 0>;
 465
 466                         trips {
 467                                 threshold: trip-point0 {
 468                                         temperature = <70000>;
 469                                         hysteresis = <2000>;
 470                                         type = "passive";
 471                                 };
 472                                 target: trip-point1 {
 473                                         temperature = <85000>;
 474                                         hysteresis = <2000>;
 475                                         type = "passive";
 476                                 };
 477                                 soc_crit: soc-crit {
 478                                         temperature = <95000>;
 479                                         hysteresis = <2000>;
 480                                         type = "critical";
 481                                 };
 482                         };
 483
 484                         cooling-maps {
 485                                 map0 {
 486                                         trip = <&target>;
 487                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 488                                                          <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 489                                                          <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 490                                                          <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 491                                         contribution = <4096>;
 492                                 };
 493                         };
 494                 };
 495
 496         };
 497
 498         tsadc: tsadc@ff250000 {
 499                 compatible = "rockchip,rk3328-tsadc";
 500                 reg = <0x0 0xff250000 0x0 0x100>;
 501                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 502                 assigned-clocks = <&cru SCLK_TSADC>;
 503                 assigned-clock-rates = <50000>;
 504                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 505                 clock-names = "tsadc", "apb_pclk";
 506                 pinctrl-names = "init", "default", "sleep";
 507                 pinctrl-0 = <&otp_gpio>;
 508                 pinctrl-1 = <&otp_out>;
 509                 pinctrl-2 = <&otp_gpio>;
 510                 resets = <&cru SRST_TSADC>;
 511                 reset-names = "tsadc-apb";
 512                 rockchip,grf = <&grf>;
 513                 rockchip,hw-tshut-temp = <100000>;
 514                 #thermal-sensor-cells = <1>;
 515                 status = "disabled";
 516         };
 517
 518         efuse: efuse@ff260000 {
 519                 compatible = "rockchip,rk3328-efuse";
 520                 reg = <0x0 0xff260000 0x0 0x50>;
 521                 #address-cells = <1>;
 522                 #size-cells = <1>;
 523                 clocks = <&cru SCLK_EFUSE>;
 524                 clock-names = "pclk_efuse";
 525                 rockchip,efuse-size = <0x20>;
 526
 527                 /* Data cells */
 528                 efuse_id: id@7 {
 529                         reg = <0x07 0x10>;
 530                 };
 531                 cpu_leakage: cpu-leakage@17 {
 532                         reg = <0x17 0x1>;
 533                 };
 534                 logic_leakage: logic-leakage@19 {
 535                         reg = <0x19 0x1>;
 536                 };
 537                 efuse_cpu_version: cpu-version@1a {
 538                         reg = <0x1a 0x1>;
 539                         bits = <3 3>;
 540                 };
 541         };
 542
 543         saradc: adc@ff280000 {
 544                 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
 545                 reg = <0x0 0xff280000 0x0 0x100>;
 546                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 547                 #io-channel-cells = <1>;
 548                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 549                 clock-names = "saradc", "apb_pclk";
 550                 resets = <&cru SRST_SARADC_P>;
 551                 reset-names = "saradc-apb";
 552                 status = "disabled";
 553         };
 554
 555         gpu: gpu@ff300000 {
 556                 compatible = "rockchip,rk3328-mali", "arm,mali-450";
 557                 reg = <0x0 0xff300000 0x0 0x40000>;
 558                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
 559                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 560                              <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
 561                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
 562                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 563                              <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
 564                              <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 565                 interrupt-names = "gp",
 566                                   "gpmmu",
 567                                   "pp",
 568                                   "pp0",
 569                                   "ppmmu0",
 570                                   "pp1",
 571                                   "ppmmu1";
 572                 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
 573                 clock-names = "bus", "core";
 574                 resets = <&cru SRST_GPU_A>;
 575         };
 576
 577         h265e_mmu: iommu@ff330200 {
 578                 compatible = "rockchip,iommu";
 579                 reg = <0x0 0xff330200 0 0x100>;
 580                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 581                 interrupt-names = "h265e_mmu";
 582                 clocks = <&cru ACLK_H265>, <&cru PCLK_H265>;
 583                 clock-names = "aclk", "iface";
 584                 #iommu-cells = <0>;
 585                 status = "disabled";
 586         };
 587
 588         vepu_mmu: iommu@ff340800 {
 589                 compatible = "rockchip,iommu";
 590                 reg = <0x0 0xff340800 0x0 0x40>;
 591                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 592                 interrupt-names = "vepu_mmu";
 593                 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
 594                 clock-names = "aclk", "iface";
 595                 #iommu-cells = <0>;
 596                 status = "disabled";
 597         };
 598
 599         vpu_mmu: iommu@ff350800 {
 600                 compatible = "rockchip,iommu";
 601                 reg = <0x0 0xff350800 0x0 0x40>;
 602                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 603                 interrupt-names = "vpu_mmu";
 604                 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
 605                 clock-names = "aclk", "iface";
 606                 #iommu-cells = <0>;
 607                 status = "disabled";
 608         };
 609
 610         rkvdec_mmu: iommu@ff360480 {
 611                 compatible = "rockchip,iommu";
 612                 reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>;
 613                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 614                 interrupt-names = "rkvdec_mmu";
 615                 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
 616                 clock-names = "aclk", "iface";
 617                 #iommu-cells = <0>;
 618                 status = "disabled";
 619         };
 620
 621         vop: vop@ff370000 {
 622                 compatible = "rockchip,rk3328-vop";
 623                 reg = <0x0 0xff370000 0x0 0x3efc>;
 624                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 625                 clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>;
 626                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 627                 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
 628                 reset-names = "axi", "ahb", "dclk";
 629                 iommus = <&vop_mmu>;
 630                 status = "disabled";
 631
 632                 vop_out: port {
 633                         #address-cells = <1>;
 634                         #size-cells = <0>;
 635
 636                         vop_out_hdmi: endpoint@0 {
 637                                 reg = <0>;
 638                                 remote-endpoint = <&hdmi_in_vop>;
 639                         };
 640                 };
 641         };
 642
 643         vop_mmu: iommu@ff373f00 {
 644                 compatible = "rockchip,iommu";
 645                 reg = <0x0 0xff373f00 0x0 0x100>;
 646                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 647                 interrupt-names = "vop_mmu";
 648                 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
 649                 clock-names = "aclk", "iface";
 650                 #iommu-cells = <0>;
 651                 status = "disabled";
 652         };
 653
 654         hdmi: hdmi@ff3c0000 {
 655                 compatible = "rockchip,rk3328-dw-hdmi";
 656                 reg = <0x0 0xff3c0000 0x0 0x20000>;
 657                 reg-io-width = <4>;
 658                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 659                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 660                 clocks = <&cru PCLK_HDMI>,
 661                          <&cru SCLK_HDMI_SFC>,
 662                          <&cru SCLK_RTC32K>;
 663                 clock-names = "iahb",
 664                               "isfr",
 665                               "cec";
 666                 phys = <&hdmiphy>;
 667                 phy-names = "hdmi";
 668                 pinctrl-names = "default";
 669                 pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>;
 670                 rockchip,grf = <&grf>;
 671                 #sound-dai-cells = <0>;
 672                 status = "disabled";
 673
 674                 ports {
 675                         hdmi_in: port {
 676                                 hdmi_in_vop: endpoint {
 677                                         remote-endpoint = <&vop_out_hdmi>;
 678                                 };
 679                         };
 680                 };
 681         };
 682
 683         codec: codec@ff410000 {
 684                 compatible = "rockchip,rk3328-codec";
 685                 reg = <0x0 0xff410000 0x0 0x1000>;
 686                 clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>;
 687                 clock-names = "pclk", "mclk";
 688                 rockchip,grf = <&grf>;
 689                 #sound-dai-cells = <0>;
 690                 status = "disabled";
 691         };
 692
 693         hdmiphy: phy@ff430000 {
 694                 compatible = "rockchip,rk3328-hdmi-phy";
 695                 reg = <0x0 0xff430000 0x0 0x10000>;
 696                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 697                 clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>;
 698                 clock-names = "sysclk", "refoclk", "refpclk";
 699                 clock-output-names = "hdmi_phy";
 700                 #clock-cells = <0>;
 701                 nvmem-cells = <&efuse_cpu_version>;
 702                 nvmem-cell-names = "cpu-version";
 703                 #phy-cells = <0>;
 704                 status = "disabled";
 705         };
 706
 707         cru: clock-controller@ff440000 {
 708                 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
 709                 reg = <0x0 0xff440000 0x0 0x1000>;
 710                 rockchip,grf = <&grf>;
 711                 #clock-cells = <1>;
 712                 #reset-cells = <1>;
 713                 assigned-clocks =
 714                         /*
 715                          * CPLL should run at 1200, but that is to high for
 716                          * the initial dividers of most of its children.
 717                          * We need set cpll child clk div first,
 718                          * and then set the cpll frequency.
 719                          */
 720                         <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
 721                         <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
 722                         <&cru SCLK_UART1>, <&cru SCLK_UART2>,
 723                         <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 724                         <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
 725                         <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
 726                         <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
 727                         <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
 728                         <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
 729                         <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
 730                         <&cru SCLK_WIFI>, <&cru ARMCLK>,
 731                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 732                         <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
 733                         <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 734                         <&cru HCLK_PERI>, <&cru PCLK_PERI>,
 735                         <&cru SCLK_RTC32K>;
 736                 assigned-clock-parents =
 737                         <&cru HDMIPHY>, <&cru PLL_APLL>,
 738                         <&cru PLL_GPLL>, <&xin24m>,
 739                         <&xin24m>, <&xin24m>;
 740                 assigned-clock-rates =
 741                         <0>, <61440000>,
 742                         <0>, <24000000>,
 743                         <24000000>, <24000000>,
 744                         <15000000>, <15000000>,
 745                         <100000000>, <100000000>,
 746                         <100000000>, <100000000>,
 747                         <50000000>, <100000000>,
 748                         <100000000>, <100000000>,
 749                         <50000000>, <50000000>,
 750                         <50000000>, <50000000>,
 751                         <24000000>, <600000000>,
 752                         <491520000>, <1200000000>,
 753                         <150000000>, <75000000>,
 754                         <75000000>, <150000000>,
 755                         <75000000>, <75000000>,
 756                         <32768>;
 757         };
 758
 759         usb2phy_grf: syscon@ff450000 {
 760                 compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
 761                              "simple-mfd";
 762                 reg = <0x0 0xff450000 0x0 0x10000>;
 763                 #address-cells = <1>;
 764                 #size-cells = <1>;
 765
 766                 u2phy: usb2-phy@100 {
 767                         compatible = "rockchip,rk3328-usb2phy";
 768                         reg = <0x100 0x10>;
 769                         clocks = <&xin24m>;
 770                         clock-names = "phyclk";
 771                         clock-output-names = "usb480m_phy";
 772                         #clock-cells = <0>;
 773                         assigned-clocks = <&cru USB480M>;
 774                         assigned-clock-parents = <&u2phy>;
 775                         status = "disabled";
 776
 777                         u2phy_otg: otg-port {
 778                                 #phy-cells = <0>;
 779                                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 780                                              <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 781                                              <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 782                                 interrupt-names = "otg-bvalid", "otg-id",
 783                                                   "linestate";
 784                                 status = "disabled";
 785                         };
 786
 787                         u2phy_host: host-port {
 788                                 #phy-cells = <0>;
 789                                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 790                                 interrupt-names = "linestate";
 791                                 status = "disabled";
 792                         };
 793                 };
 794         };
 795
 796         sdmmc: dwmmc@ff500000 {
 797                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 798                 reg = <0x0 0xff500000 0x0 0x4000>;
 799                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 800                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 801                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 802                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 803                 fifo-depth = <0x100>;
 804                 status = "disabled";
 805         };
 806
 807         sdio: dwmmc@ff510000 {
 808                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 809                 reg = <0x0 0xff510000 0x0 0x4000>;
 810                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 811                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 812                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 813                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 814                 fifo-depth = <0x100>;
 815                 status = "disabled";
 816         };
 817
 818         emmc: dwmmc@ff520000 {
 819                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 820                 reg = <0x0 0xff520000 0x0 0x4000>;
 821                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 822                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 823                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 824                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 825                 fifo-depth = <0x100>;
 826                 status = "disabled";
 827         };
 828
 829         gmac2io: ethernet@ff540000 {
 830                 compatible = "rockchip,rk3328-gmac";
 831                 reg = <0x0 0xff540000 0x0 0x10000>;
 832                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 833                 interrupt-names = "macirq";
 834                 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
 835                          <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
 836                          <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
 837                          <&cru PCLK_MAC2IO>;
 838                 clock-names = "stmmaceth", "mac_clk_rx",
 839                               "mac_clk_tx", "clk_mac_ref",
 840                               "clk_mac_refout", "aclk_mac",
 841                               "pclk_mac";
 842                 resets = <&cru SRST_GMAC2IO_A>;
 843                 reset-names = "stmmaceth";
 844                 rockchip,grf = <&grf>;
 845                 status = "disabled";
 846         };
 847
 848         gmac2phy: ethernet@ff550000 {
 849                 compatible = "rockchip,rk3328-gmac";
 850                 reg = <0x0 0xff550000 0x0 0x10000>;
 851                 rockchip,grf = <&grf>;
 852                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 853                 interrupt-names = "macirq";
 854                 clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>,
 855                          <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>,
 856                          <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>,
 857                          <&cru SCLK_MAC2PHY_OUT>;
 858                 clock-names = "stmmaceth", "mac_clk_rx",
 859                               "mac_clk_tx", "clk_mac_ref",
 860                               "aclk_mac", "pclk_mac",
 861                               "clk_macphy";
 862                 resets = <&cru SRST_GMAC2PHY_A>, <&cru SRST_MACPHY>;
 863                 reset-names = "stmmaceth", "mac-phy";
 864                 phy-mode = "rmii";
 865                 phy-handle = <&phy>;
 866                 status = "disabled";
 867
 868                 mdio {
 869                         compatible = "snps,dwmac-mdio";
 870                         #address-cells = <1>;
 871                         #size-cells = <0>;
 872
 873                         phy: phy@0 {
 874                                 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
 875                                 reg = <0>;
 876                                 clocks = <&cru SCLK_MAC2PHY_OUT>;
 877                                 resets = <&cru SRST_MACPHY>;
 878                                 pinctrl-names = "default";
 879                                 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;
 880                                 phy-is-integrated;
 881                         };
 882                 };
 883         };
 884
 885         usb20_otg: usb@ff580000 {
 886                 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
 887                              "snps,dwc2";
 888                 reg = <0x0 0xff580000 0x0 0x40000>;
 889                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 890                 clocks = <&cru HCLK_OTG>;
 891                 clock-names = "otg";
 892                 dr_mode = "otg";
 893                 g-np-tx-fifo-size = <16>;
 894                 g-rx-fifo-size = <280>;
 895                 g-tx-fifo-size = <256 128 128 64 32 16>;
 896                 g-use-dma;
 897                 phys = <&u2phy_otg>;
 898                 phy-names = "usb2-phy";
 899                 status = "disabled";
 900         };
 901
 902         usb_host0_ehci: usb@ff5c0000 {
 903                 compatible = "generic-ehci";
 904                 reg = <0x0 0xff5c0000 0x0 0x10000>;
 905                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 906                 clocks = <&cru HCLK_HOST0>, <&u2phy>;
 907                 clock-names = "usbhost", "utmi";
 908                 phys = <&u2phy_host>;
 909                 phy-names = "usb";
 910                 status = "disabled";
 911         };
 912
 913         usb_host0_ohci: usb@ff5d0000 {
 914                 compatible = "generic-ohci";
 915                 reg = <0x0 0xff5d0000 0x0 0x10000>;
 916                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 917                 clocks = <&cru HCLK_HOST0>, <&u2phy>;
 918                 clock-names = "usbhost", "utmi";
 919                 phys = <&u2phy_host>;
 920                 phy-names = "usb";
 921                 status = "disabled";
 922         };
 923
 924         gic: interrupt-controller@ff811000 {
 925                 compatible = "arm,gic-400";
 926                 #interrupt-cells = <3>;
 927                 #address-cells = <0>;
 928                 interrupt-controller;
 929                 reg = <0x0 0xff811000 0 0x1000>,
 930                       <0x0 0xff812000 0 0x2000>,
 931                       <0x0 0xff814000 0 0x2000>,
 932                       <0x0 0xff816000 0 0x2000>;
 933                 interrupts = <GIC_PPI 9
 934                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 935         };
 936
 937         pinctrl: pinctrl {
 938                 compatible = "rockchip,rk3328-pinctrl";
 939                 rockchip,grf = <&grf>;
 940                 #address-cells = <2>;
 941                 #size-cells = <2>;
 942                 ranges;
 943
 944                 gpio0: gpio0@ff210000 {
 945                         compatible = "rockchip,gpio-bank";
 946                         reg = <0x0 0xff210000 0x0 0x100>;
 947                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 948                         clocks = <&cru PCLK_GPIO0>;
 949
 950                         gpio-controller;
 951                         #gpio-cells = <2>;
 952
 953                         interrupt-controller;
 954                         #interrupt-cells = <2>;
 955                 };
 956
 957                 gpio1: gpio1@ff220000 {
 958                         compatible = "rockchip,gpio-bank";
 959                         reg = <0x0 0xff220000 0x0 0x100>;
 960                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 961                         clocks = <&cru PCLK_GPIO1>;
 962
 963                         gpio-controller;
 964                         #gpio-cells = <2>;
 965
 966                         interrupt-controller;
 967                         #interrupt-cells = <2>;
 968                 };
 969
 970                 gpio2: gpio2@ff230000 {
 971                         compatible = "rockchip,gpio-bank";
 972                         reg = <0x0 0xff230000 0x0 0x100>;
 973                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 974                         clocks = <&cru PCLK_GPIO2>;
 975
 976                         gpio-controller;
 977                         #gpio-cells = <2>;
 978
 979                         interrupt-controller;
 980                         #interrupt-cells = <2>;
 981                 };
 982
 983                 gpio3: gpio3@ff240000 {
 984                         compatible = "rockchip,gpio-bank";
 985                         reg = <0x0 0xff240000 0x0 0x100>;
 986                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 987                         clocks = <&cru PCLK_GPIO3>;
 988
 989                         gpio-controller;
 990                         #gpio-cells = <2>;
 991
 992                         interrupt-controller;
 993                         #interrupt-cells = <2>;
 994                 };
 995
 996                 pcfg_pull_up: pcfg-pull-up {
 997                         bias-pull-up;
 998                 };
 999
1000                 pcfg_pull_down: pcfg-pull-down {
1001                         bias-pull-down;
1002                 };
1003
1004                 pcfg_pull_none: pcfg-pull-none {
1005                         bias-disable;
1006                 };
1007
1008                 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
1009                         bias-disable;
1010                         drive-strength = <2>;
1011                 };
1012
1013                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1014                         bias-pull-up;
1015                         drive-strength = <2>;
1016                 };
1017
1018                 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1019                         bias-pull-up;
1020                         drive-strength = <4>;
1021                 };
1022
1023                 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1024                         bias-disable;
1025                         drive-strength = <4>;
1026                 };
1027
1028                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1029                         bias-pull-down;
1030                         drive-strength = <4>;
1031                 };
1032
1033                 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1034                         bias-disable;
1035                         drive-strength = <8>;
1036                 };
1037
1038                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1039                         bias-pull-up;
1040                         drive-strength = <8>;
1041                 };
1042
1043                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1044                         bias-disable;
1045                         drive-strength = <12>;
1046                 };
1047
1048                 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1049                         bias-pull-up;
1050                         drive-strength = <12>;
1051                 };
1052
1053                 pcfg_output_high: pcfg-output-high {
1054                         output-high;
1055                 };
1056
1057                 pcfg_output_low: pcfg-output-low {
1058                         output-low;
1059                 };
1060
1061                 pcfg_input_high: pcfg-input-high {
1062                         bias-pull-up;
1063                         input-enable;
1064                 };
1065
1066                 pcfg_input: pcfg-input {
1067                         input-enable;
1068                 };
1069
1070                 i2c0 {
1071                         i2c0_xfer: i2c0-xfer {
1072                                 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>,
1073                                                 <2 RK_PD1 1 &pcfg_pull_none>;
1074                         };
1075                 };
1076
1077                 i2c1 {
1078                         i2c1_xfer: i2c1-xfer {
1079                                 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>,
1080                                                 <2 RK_PA5 2 &pcfg_pull_none>;
1081                         };
1082                 };
1083
1084                 i2c2 {
1085                         i2c2_xfer: i2c2-xfer {
1086                                 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>,
1087                                                 <2 RK_PB6 1 &pcfg_pull_none>;
1088                         };
1089                 };
1090
1091                 i2c3 {
1092                         i2c3_xfer: i2c3-xfer {
1093                                 rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>,
1094                                                 <0 RK_PA6 2 &pcfg_pull_none>;
1095                         };
1096                         i2c3_gpio: i2c3-gpio {
1097                                 rockchip,pins =
1098                                         <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>,
1099                                         <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1100                         };
1101                 };
1102
1103                 hdmi_i2c {
1104                         hdmii2c_xfer: hdmii2c-xfer {
1105                                 rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>,
1106                                                 <0 RK_PA6 1 &pcfg_pull_none>;
1107                         };
1108                 };
1109
1110                 pdm-0 {
1111                         pdmm0_clk: pdmm0-clk {
1112                                 rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>;
1113                         };
1114
1115                         pdmm0_fsync: pdmm0-fsync {
1116                                 rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>;
1117                         };
1118
1119                         pdmm0_sdi0: pdmm0-sdi0 {
1120                                 rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>;
1121                         };
1122
1123                         pdmm0_sdi1: pdmm0-sdi1 {
1124                                 rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>;
1125                         };
1126
1127                         pdmm0_sdi2: pdmm0-sdi2 {
1128                                 rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>;
1129                         };
1130
1131                         pdmm0_sdi3: pdmm0-sdi3 {
1132                                 rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>;
1133                         };
1134
1135                         pdmm0_clk_sleep: pdmm0-clk-sleep {
1136                                 rockchip,pins =
1137                                         <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>;
1138                         };
1139
1140                         pdmm0_sdi0_sleep: pdmm0-sdi0-sleep {
1141                                 rockchip,pins =
1142                                         <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>;
1143                         };
1144
1145                         pdmm0_sdi1_sleep: pdmm0-sdi1-sleep {
1146                                 rockchip,pins =
1147                                         <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>;
1148                         };
1149
1150                         pdmm0_sdi2_sleep: pdmm0-sdi2-sleep {
1151                                 rockchip,pins =
1152                                         <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>;
1153                         };
1154
1155                         pdmm0_sdi3_sleep: pdmm0-sdi3-sleep {
1156                                 rockchip,pins =
1157                                         <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1158                         };
1159
1160                         pdmm0_fsync_sleep: pdmm0-fsync-sleep {
1161                                 rockchip,pins =
1162                                         <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1163                         };
1164                 };
1165
1166                 tsadc {
1167                         otp_gpio: otp-gpio {
1168                                 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1169                         };
1170
1171                         otp_out: otp-out {
1172                                 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>;
1173                         };
1174                 };
1175
1176                 uart0 {
1177                         uart0_xfer: uart0-xfer {
1178                                 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_up>,
1179                                                 <1 RK_PB0 1 &pcfg_pull_none>;
1180                         };
1181
1182                         uart0_cts: uart0-cts {
1183                                 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;
1184                         };
1185
1186                         uart0_rts: uart0-rts {
1187                                 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>;
1188                         };
1189
1190                         uart0_rts_gpio: uart0-rts-gpio {
1191                                 rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
1192                         };
1193                 };
1194
1195                 uart1 {
1196                         uart1_xfer: uart1-xfer {
1197                                 rockchip,pins = <3 RK_PA4 4 &pcfg_pull_up>,
1198                                                 <3 RK_PA6 4 &pcfg_pull_none>;
1199                         };
1200
1201                         uart1_cts: uart1-cts {
1202                                 rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>;
1203                         };
1204
1205                         uart1_rts: uart1-rts {
1206                                 rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>;
1207                         };
1208
1209                         uart1_rts_gpio: uart1-rts-gpio {
1210                                 rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
1211                         };
1212                 };
1213
1214                 uart2-0 {
1215                         uart2m0_xfer: uart2m0-xfer {
1216                                 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_up>,
1217                                                 <1 RK_PA1 2 &pcfg_pull_none>;
1218                         };
1219                 };
1220
1221                 uart2-1 {
1222                         uart2m1_xfer: uart2m1-xfer {
1223                                 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_up>,
1224                                                 <2 RK_PA1 1 &pcfg_pull_none>;
1225                         };
1226                 };
1227
1228                 spi0-0 {
1229                         spi0m0_clk: spi0m0-clk {
1230                                 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>;
1231                         };
1232
1233                         spi0m0_cs0: spi0m0-cs0 {
1234                                 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>;
1235                         };
1236
1237                         spi0m0_tx: spi0m0-tx {
1238                                 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>;
1239                         };
1240
1241                         spi0m0_rx: spi0m0-rx {
1242                                 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>;
1243                         };
1244
1245                         spi0m0_cs1: spi0m0-cs1 {
1246                                 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>;
1247                         };
1248                 };
1249
1250                 spi0-1 {
1251                         spi0m1_clk: spi0m1-clk {
1252                                 rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>;
1253                         };
1254
1255                         spi0m1_cs0: spi0m1-cs0 {
1256                                 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>;
1257                         };
1258
1259                         spi0m1_tx: spi0m1-tx {
1260                                 rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>;
1261                         };
1262
1263                         spi0m1_rx: spi0m1-rx {
1264                                 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>;
1265                         };
1266
1267                         spi0m1_cs1: spi0m1-cs1 {
1268                                 rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>;
1269                         };
1270                 };
1271
1272                 spi0-2 {
1273                         spi0m2_clk: spi0m2-clk {
1274                                 rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>;
1275                         };
1276
1277                         spi0m2_cs0: spi0m2-cs0 {
1278                                 rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>;
1279                         };
1280
1281                         spi0m2_tx: spi0m2-tx {
1282                                 rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>;
1283                         };
1284
1285                         spi0m2_rx: spi0m2-rx {
1286                                 rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>;
1287                         };
1288                 };
1289
1290                 i2s1 {
1291                         i2s1_mclk: i2s1-mclk {
1292                                 rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>;
1293                         };
1294
1295                         i2s1_sclk: i2s1-sclk {
1296                                 rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>;
1297                         };
1298
1299                         i2s1_lrckrx: i2s1-lrckrx {
1300                                 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>;
1301                         };
1302
1303                         i2s1_lrcktx: i2s1-lrcktx {
1304                                 rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>;
1305                         };
1306
1307                         i2s1_sdi: i2s1-sdi {
1308                                 rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>;
1309                         };
1310
1311                         i2s1_sdo: i2s1-sdo {
1312                                 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>;
1313                         };
1314
1315                         i2s1_sdio1: i2s1-sdio1 {
1316                                 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>;
1317                         };
1318
1319                         i2s1_sdio2: i2s1-sdio2 {
1320                                 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>;
1321                         };
1322
1323                         i2s1_sdio3: i2s1-sdio3 {
1324                                 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>;
1325                         };
1326
1327                         i2s1_sleep: i2s1-sleep {
1328                                 rockchip,pins =
1329                                         <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>,
1330                                         <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>,
1331                                         <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>,
1332                                         <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>,
1333                                         <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>,
1334                                         <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>,
1335                                         <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1336                                         <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1337                                         <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1338                         };
1339                 };
1340
1341                 i2s2-0 {
1342                         i2s2m0_mclk: i2s2m0-mclk {
1343                                 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
1344                         };
1345
1346                         i2s2m0_sclk: i2s2m0-sclk {
1347                                 rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>;
1348                         };
1349
1350                         i2s2m0_lrckrx: i2s2m0-lrckrx {
1351                                 rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>;
1352                         };
1353
1354                         i2s2m0_lrcktx: i2s2m0-lrcktx {
1355                                 rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>;
1356                         };
1357
1358                         i2s2m0_sdi: i2s2m0-sdi {
1359                                 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>;
1360                         };
1361
1362                         i2s2m0_sdo: i2s2m0-sdo {
1363                                 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>;
1364                         };
1365
1366                         i2s2m0_sleep: i2s2m0-sleep {
1367                                 rockchip,pins =
1368                                         <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1369                                         <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1370                                         <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>,
1371                                         <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>,
1372                                         <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>,
1373                                         <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
1374                         };
1375                 };
1376
1377                 i2s2-1 {
1378                         i2s2m1_mclk: i2s2m1-mclk {
1379                                 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
1380                         };
1381
1382                         i2s2m1_sclk: i2s2m1-sclk {
1383                                 rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>;
1384                         };
1385
1386                         i2s2m1_lrckrx: i2sm1-lrckrx {
1387                                 rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>;
1388                         };
1389
1390                         i2s2m1_lrcktx: i2s2m1-lrcktx {
1391                                 rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>;
1392                         };
1393
1394                         i2s2m1_sdi: i2s2m1-sdi {
1395                                 rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>;
1396                         };
1397
1398                         i2s2m1_sdo: i2s2m1-sdo {
1399                                 rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>;
1400                         };
1401
1402                         i2s2m1_sleep: i2s2m1-sleep {
1403                                 rockchip,pins =
1404                                         <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1405                                         <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>,
1406                                         <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>,
1407                                         <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>,
1408                                         <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>;
1409                         };
1410                 };
1411
1412                 spdif-0 {
1413                         spdifm0_tx: spdifm0-tx {
1414                                 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
1415                         };
1416                 };
1417
1418                 spdif-1 {
1419                         spdifm1_tx: spdifm1-tx {
1420                                 rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>;
1421                         };
1422                 };
1423
1424                 spdif-2 {
1425                         spdifm2_tx: spdifm2-tx {
1426                                 rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>;
1427                         };
1428                 };
1429
1430                 sdmmc0-0 {
1431                         sdmmc0m0_pwren: sdmmc0m0-pwren {
1432                                 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>;
1433                         };
1434
1435                         sdmmc0m0_gpio: sdmmc0m0-gpio {
1436                                 rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1437                         };
1438                 };
1439
1440                 sdmmc0-1 {
1441                         sdmmc0m1_pwren: sdmmc0m1-pwren {
1442                                 rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>;
1443                         };
1444
1445                         sdmmc0m1_gpio: sdmmc0m1-gpio {
1446                                 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1447                         };
1448                 };
1449
1450                 sdmmc0 {
1451                         sdmmc0_clk: sdmmc0-clk {
1452                                 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_8ma>;
1453                         };
1454
1455                         sdmmc0_cmd: sdmmc0-cmd {
1456                                 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_8ma>;
1457                         };
1458
1459                         sdmmc0_dectn: sdmmc0-dectn {
1460                                 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>;
1461                         };
1462
1463                         sdmmc0_wrprt: sdmmc0-wrprt {
1464                                 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>;
1465                         };
1466
1467                         sdmmc0_bus1: sdmmc0-bus1 {
1468                                 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>;
1469                         };
1470
1471                         sdmmc0_bus4: sdmmc0-bus4 {
1472                                 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>,
1473                                                 <1 RK_PA1 1 &pcfg_pull_up_8ma>,
1474                                                 <1 RK_PA2 1 &pcfg_pull_up_8ma>,
1475                                                 <1 RK_PA3 1 &pcfg_pull_up_8ma>;
1476                         };
1477
1478                         sdmmc0_gpio: sdmmc0-gpio {
1479                                 rockchip,pins =
1480                                         <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1481                                         <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1482                                         <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1483                                         <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1484                                         <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1485                                         <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1486                                         <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1487                                         <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1488                         };
1489                 };
1490
1491                 sdmmc0ext {
1492                         sdmmc0ext_clk: sdmmc0ext-clk {
1493                                 rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>;
1494                         };
1495
1496                         sdmmc0ext_cmd: sdmmc0ext-cmd {
1497                                 rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>;
1498                         };
1499
1500                         sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1501                                 rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>;
1502                         };
1503
1504                         sdmmc0ext_dectn: sdmmc0ext-dectn {
1505                                 rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>;
1506                         };
1507
1508                         sdmmc0ext_bus1: sdmmc0ext-bus1 {
1509                                 rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>;
1510                         };
1511
1512                         sdmmc0ext_bus4: sdmmc0ext-bus4 {
1513                                 rockchip,pins =
1514                                         <3 RK_PA4 3 &pcfg_pull_up_4ma>,
1515                                         <3 RK_PA5 3 &pcfg_pull_up_4ma>,
1516                                         <3 RK_PA6 3 &pcfg_pull_up_4ma>,
1517                                         <3 RK_PA7 3 &pcfg_pull_up_4ma>;
1518                         };
1519
1520                         sdmmc0ext_gpio: sdmmc0ext-gpio {
1521                                 rockchip,pins =
1522                                         <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1523                                         <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1524                                         <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1525                                         <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1526                                         <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1527                                         <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1528                                         <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1529                                         <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1530                         };
1531                 };
1532
1533                 sdmmc1 {
1534                         sdmmc1_clk: sdmmc1-clk {
1535                                 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>;
1536                         };
1537
1538                         sdmmc1_cmd: sdmmc1-cmd {
1539                                 rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>;
1540                         };
1541
1542                         sdmmc1_pwren: sdmmc1-pwren {
1543                                 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>;
1544                         };
1545
1546                         sdmmc1_wrprt: sdmmc1-wrprt {
1547                                 rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>;
1548                         };
1549
1550                         sdmmc1_dectn: sdmmc1-dectn {
1551                                 rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>;
1552                         };
1553
1554                         sdmmc1_bus1: sdmmc1-bus1 {
1555                                 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>;
1556                         };
1557
1558                         sdmmc1_bus4: sdmmc1-bus4 {
1559                                 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>,
1560                                                 <1 RK_PB7 1 &pcfg_pull_up_8ma>,
1561                                                 <1 RK_PC0 1 &pcfg_pull_up_8ma>,
1562                                                 <1 RK_PC1 1 &pcfg_pull_up_8ma>;
1563                         };
1564
1565                         sdmmc1_gpio: sdmmc1-gpio {
1566                                 rockchip,pins =
1567                                         <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1568                                         <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1569                                         <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1570                                         <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1571                                         <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1572                                         <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1573                                         <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1574                                         <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1575                                         <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1576                         };
1577                 };
1578
1579                 emmc {
1580                         emmc_clk: emmc-clk {
1581                                 rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>;
1582                         };
1583
1584                         emmc_cmd: emmc-cmd {
1585                                 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>;
1586                         };
1587
1588                         emmc_pwren: emmc-pwren {
1589                                 rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>;
1590                         };
1591
1592                         emmc_rstnout: emmc-rstnout {
1593                                 rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>;
1594                         };
1595
1596                         emmc_bus1: emmc-bus1 {
1597                                 rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>;
1598                         };
1599
1600                         emmc_bus4: emmc-bus4 {
1601                                 rockchip,pins =
1602                                         <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1603                                         <2 RK_PD4 2 &pcfg_pull_up_12ma>,
1604                                         <2 RK_PD5 2 &pcfg_pull_up_12ma>,
1605                                         <2 RK_PD6 2 &pcfg_pull_up_12ma>;
1606                         };
1607
1608                         emmc_bus8: emmc-bus8 {
1609                                 rockchip,pins =
1610                                         <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1611                                         <2 RK_PD4 2 &pcfg_pull_up_12ma>,
1612                                         <2 RK_PD5 2 &pcfg_pull_up_12ma>,
1613                                         <2 RK_PD6 2 &pcfg_pull_up_12ma>,
1614                                         <2 RK_PD7 2 &pcfg_pull_up_12ma>,
1615                                         <3 RK_PC0 2 &pcfg_pull_up_12ma>,
1616                                         <3 RK_PC1 2 &pcfg_pull_up_12ma>,
1617                                         <3 RK_PC2 2 &pcfg_pull_up_12ma>;
1618                         };
1619                 };
1620
1621                 pwm0 {
1622                         pwm0_pin: pwm0-pin {
1623                                 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>;
1624                         };
1625                 };
1626
1627                 pwm1 {
1628                         pwm1_pin: pwm1-pin {
1629                                 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>;
1630                         };
1631                 };
1632
1633                 pwm2 {
1634                         pwm2_pin: pwm2-pin {
1635                                 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>;
1636                         };
1637                 };
1638
1639                 pwmir {
1640                         pwmir_pin: pwmir-pin {
1641                                 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>;
1642                         };
1643                 };
1644
1645                 gmac-1 {
1646                         rgmiim1_pins: rgmiim1-pins {
1647                                 rockchip,pins =
1648                                         /* mac_txclk */
1649                                         <1 RK_PB4 2 &pcfg_pull_none_8ma>,
1650                                         /* mac_rxclk */
1651                                         <1 RK_PB5 2 &pcfg_pull_none_4ma>,
1652                                         /* mac_mdio */
1653                                         <1 RK_PC3 2 &pcfg_pull_none_4ma>,
1654                                         /* mac_txen */
1655                                         <1 RK_PD1 2 &pcfg_pull_none_8ma>,
1656                                         /* mac_clk */
1657                                         <1 RK_PC5 2 &pcfg_pull_none_4ma>,
1658                                         /* mac_rxdv */
1659                                         <1 RK_PC6 2 &pcfg_pull_none_4ma>,
1660                                         /* mac_mdc */
1661                                         <1 RK_PC7 2 &pcfg_pull_none_4ma>,
1662                                         /* mac_rxd1 */
1663                                         <1 RK_PB2 2 &pcfg_pull_none_4ma>,
1664                                         /* mac_rxd0 */
1665                                         <1 RK_PB3 2 &pcfg_pull_none_4ma>,
1666                                         /* mac_txd1 */
1667                                         <1 RK_PB0 2 &pcfg_pull_none_8ma>,
1668                                         /* mac_txd0 */
1669                                         <1 RK_PB1 2 &pcfg_pull_none_8ma>,
1670                                         /* mac_rxd3 */
1671                                         <1 RK_PB6 2 &pcfg_pull_none_4ma>,
1672                                         /* mac_rxd2 */
1673                                         <1 RK_PB7 2 &pcfg_pull_none_4ma>,
1674                                         /* mac_txd3 */
1675                                         <1 RK_PC0 2 &pcfg_pull_none_8ma>,
1676                                         /* mac_txd2 */
1677                                         <1 RK_PC1 2 &pcfg_pull_none_8ma>,
1678
1679                                         /* mac_txclk */
1680                                         <0 RK_PB0 1 &pcfg_pull_none_8ma>,
1681                                         /* mac_txen */
1682                                         <0 RK_PB4 1 &pcfg_pull_none_8ma>,
1683                                         /* mac_clk */
1684                                         <0 RK_PD0 1 &pcfg_pull_none_4ma>,
1685                                         /* mac_txd1 */
1686                                         <0 RK_PC0 1 &pcfg_pull_none_8ma>,
1687                                         /* mac_txd0 */
1688                                         <0 RK_PC1 1 &pcfg_pull_none_8ma>,
1689                                         /* mac_txd3 */
1690                                         <0 RK_PC7 1 &pcfg_pull_none_8ma>,
1691                                         /* mac_txd2 */
1692                                         <0 RK_PC6 1 &pcfg_pull_none_8ma>;
1693                         };
1694
1695                         rmiim1_pins: rmiim1-pins {
1696                                 rockchip,pins =
1697                                         /* mac_mdio */
1698                                         <1 RK_PC3 2 &pcfg_pull_none_2ma>,
1699                                         /* mac_txen */
1700                                         <1 RK_PD1 2 &pcfg_pull_none_12ma>,
1701                                         /* mac_clk */
1702                                         <1 RK_PC5 2 &pcfg_pull_none_2ma>,
1703                                         /* mac_rxer */
1704                                         <1 RK_PD0 2 &pcfg_pull_none_2ma>,
1705                                         /* mac_rxdv */
1706                                         <1 RK_PC6 2 &pcfg_pull_none_2ma>,
1707                                         /* mac_mdc */
1708                                         <1 RK_PC7 2 &pcfg_pull_none_2ma>,
1709                                         /* mac_rxd1 */
1710                                         <1 RK_PB2 2 &pcfg_pull_none_2ma>,
1711                                         /* mac_rxd0 */
1712                                         <1 RK_PB3 2 &pcfg_pull_none_2ma>,
1713                                         /* mac_txd1 */
1714                                         <1 RK_PB0 2 &pcfg_pull_none_12ma>,
1715                                         /* mac_txd0 */
1716                                         <1 RK_PB1 2 &pcfg_pull_none_12ma>,
1717
1718                                         /* mac_mdio */
1719                                         <0 RK_PB3 1 &pcfg_pull_none>,
1720                                         /* mac_txen */
1721                                         <0 RK_PB4 1 &pcfg_pull_none>,
1722                                         /* mac_clk */
1723                                         <0 RK_PD0 1 &pcfg_pull_none>,
1724                                         /* mac_mdc */
1725                                         <0 RK_PC3 1 &pcfg_pull_none>,
1726                                         /* mac_txd1 */
1727                                         <0 RK_PC0 1 &pcfg_pull_none>,
1728                                         /* mac_txd0 */
1729                                         <0 RK_PC1 1 &pcfg_pull_none>;
1730                         };
1731                 };
1732
1733                 gmac2phy {
1734                         fephyled_speed100: fephyled-speed100 {
1735                                 rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>;
1736                         };
1737
1738                         fephyled_speed10: fephyled-speed10 {
1739                                 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>;
1740                         };
1741
1742                         fephyled_duplex: fephyled-duplex {
1743                                 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
1744                         };
1745
1746                         fephyled_rxm0: fephyled-rxm0 {
1747                                 rockchip,pins = <0 RK_PD5 1 &pcfg_pull_none>;
1748                         };
1749
1750                         fephyled_txm0: fephyled-txm0 {
1751                                 rockchip,pins = <0 RK_PD5 2 &pcfg_pull_none>;
1752                         };
1753
1754                         fephyled_linkm0: fephyled-linkm0 {
1755                                 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>;
1756                         };
1757
1758                         fephyled_rxm1: fephyled-rxm1 {
1759                                 rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>;
1760                         };
1761
1762                         fephyled_txm1: fephyled-txm1 {
1763                                 rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>;
1764                         };
1765
1766                         fephyled_linkm1: fephyled-linkm1 {
1767                                 rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>;
1768                         };
1769                 };
1770
1771                 tsadc_pin {
1772                         tsadc_int: tsadc-int {
1773                                 rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>;
1774                         };
1775                         tsadc_gpio: tsadc-gpio {
1776                                 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1777                         };
1778                 };
1779
1780                 hdmi_pin {
1781                         hdmi_cec: hdmi-cec {
1782                                 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
1783                         };
1784
1785                         hdmi_hpd: hdmi-hpd {
1786                                 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>;
1787                         };
1788                 };
1789
1790                 cif-0 {
1791                         dvp_d2d9_m0:dvp-d2d9-m0 {
1792                                 rockchip,pins =
1793                                         /* cif_d0 */
1794                                         <3 RK_PA4 2 &pcfg_pull_none>,
1795                                         /* cif_d1 */
1796                                         <3 RK_PA5 2 &pcfg_pull_none>,
1797                                         /* cif_d2 */
1798                                         <3 RK_PA6 2 &pcfg_pull_none>,
1799                                         /* cif_d3 */
1800                                         <3 RK_PA7 2 &pcfg_pull_none>,
1801                                         /* cif_d4 */
1802                                         <3 RK_PB0 2 &pcfg_pull_none>,
1803                                         /* cif_d5m0 */
1804                                         <3 RK_PB1 2 &pcfg_pull_none>,
1805                                         /* cif_d6m0 */
1806                                         <3 RK_PB2 2 &pcfg_pull_none>,
1807                                         /* cif_d7m0 */
1808                                         <3 RK_PB3 2 &pcfg_pull_none>,
1809                                         /* cif_href */
1810                                         <3 RK_PA1 2 &pcfg_pull_none>,
1811                                         /* cif_vsync */
1812                                         <3 RK_PA0 2 &pcfg_pull_none>,
1813                                         /* cif_clkoutm0 */
1814                                         <3 RK_PA3 2 &pcfg_pull_none>,
1815                                         /* cif_clkin */
1816                                         <3 RK_PA2 2 &pcfg_pull_none>;
1817                         };
1818                 };
1819
1820                 cif-1 {
1821                         dvp_d2d9_m1:dvp-d2d9-m1 {
1822                                 rockchip,pins =
1823                                         /* cif_d0 */
1824                                         <3 RK_PA4 2 &pcfg_pull_none>,
1825                                         /* cif_d1 */
1826                                         <3 RK_PA5 2 &pcfg_pull_none>,
1827                                         /* cif_d2 */
1828                                         <3 RK_PA6 2 &pcfg_pull_none>,
1829                                         /* cif_d3 */
1830                                         <3 RK_PA7 2 &pcfg_pull_none>,
1831                                         /* cif_d4 */
1832                                         <3 RK_PB0 2 &pcfg_pull_none>,
1833                                         /* cif_d5m1 */
1834                                         <2 RK_PC0 4 &pcfg_pull_none>,
1835                                         /* cif_d6m1 */
1836                                         <2 RK_PC1 4 &pcfg_pull_none>,
1837                                         /* cif_d7m1 */
1838                                         <2 RK_PC2 4 &pcfg_pull_none>,
1839                                         /* cif_href */
1840                                         <3 RK_PA1 2 &pcfg_pull_none>,
1841                                         /* cif_vsync */
1842                                         <3 RK_PA0 2 &pcfg_pull_none>,
1843                                         /* cif_clkoutm1 */
1844                                         <2 RK_PB7 4 &pcfg_pull_none>,
1845                                         /* cif_clkin */
1846                                         <3 RK_PA2 2 &pcfg_pull_none>;
1847                         };
1848                 };
1849         };
1850 };