arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * dts file for Xilinx ZynqMP ZCU102 RevA
   4  *
   5  * (C) Copyright 2015 - 2018, Xilinx, Inc.
   6  *
   7  * Michal Simek <michal.simek@xilinx.com>
   8  */
   9
  10 /dts-v1/;
  11
  12 #include "zynqmp.dtsi"
  13 #include "zynqmp-clk.dtsi"
  14 #include <dt-bindings/input/input.h>
  15 #include <dt-bindings/gpio/gpio.h>
  16
  17 / {
  18         model = "ZynqMP ZCU102 RevA";
  19         compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
  20
  21         aliases {
  22                 ethernet0 = &gem3;
  23                 i2c0 = &i2c0;
  24                 i2c1 = &i2c1;
  25                 mmc0 = &sdhci1;
  26                 rtc0 = &rtc;
  27                 serial0 = &uart0;
  28                 serial1 = &uart1;
  29                 serial2 = &dcc;
  30         };
  31
  32         chosen {
  33                 bootargs = "earlycon";
  34                 stdout-path = "serial0:115200n8";
  35         };
  36
  37         memory@0 {
  38                 device_type = "memory";
  39                 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
  40         };
  41
  42         gpio-keys {
  43                 compatible = "gpio-keys";
  44                 autorepeat;
  45                 sw19 {
  46                         label = "sw19";
  47                         gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
  48                         linux,code = <KEY_DOWN>;
  49                         wakeup-source;
  50                         autorepeat;
  51                 };
  52         };
  53
  54         leds {
  55                 compatible = "gpio-leds";
  56                 heartbeat-led {
  57                         label = "heartbeat";
  58                         gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
  59                         linux,default-trigger = "heartbeat";
  60                 };
  61         };
  62 };
  63
  64 &can1 {
  65         status = "okay";
  66 };
  67
  68 &dcc {
  69         status = "okay";
  70 };
  71
  72 &fpd_dma_chan1 {
  73         status = "okay";
  74 };
  75
  76 &fpd_dma_chan2 {
  77         status = "okay";
  78 };
  79
  80 &fpd_dma_chan3 {
  81         status = "okay";
  82 };
  83
  84 &fpd_dma_chan4 {
  85         status = "okay";
  86 };
  87
  88 &fpd_dma_chan5 {
  89         status = "okay";
  90 };
  91
  92 &fpd_dma_chan6 {
  93         status = "okay";
  94 };
  95
  96 &fpd_dma_chan7 {
  97         status = "okay";
  98 };
  99
 100 &fpd_dma_chan8 {
 101         status = "okay";
 102 };
 103
 104 &gem3 {
 105         status = "okay";
 106         phy-handle = <&phy0>;
 107         phy-mode = "rgmii-id";
 108         phy0: phy@21 {
 109                 reg = <21>;
 110                 ti,rx-internal-delay = <0x8>;
 111                 ti,tx-internal-delay = <0xa>;
 112                 ti,fifo-depth = <0x1>;
 113                 ti,dp83867-rxctrl-strap-quirk;
 114         };
 115 };
 116
 117 &gpio {
 118         status = "okay";
 119 };
 120
 121 &i2c0 {
 122         status = "okay";
 123         clock-frequency = <400000>;
 124
 125         tca6416_u97: gpio@20 {
 126                 compatible = "ti,tca6416";
 127                 reg = <0x20>;
 128                 gpio-controller;
 129                 #gpio-cells = <2>;
 130                 /*
 131                  * IRQ not connected
 132                  * Lines:
 133                  * 0 - PS_GTR_LAN_SEL0
 134                  * 1 - PS_GTR_LAN_SEL1
 135                  * 2 - PS_GTR_LAN_SEL2
 136                  * 3 - PS_GTR_LAN_SEL3
 137                  * 4 - PCI_CLK_DIR_SEL
 138                  * 5 - IIC_MUX_RESET_B
 139                  * 6 - GEM3_EXP_RESET_B
 140                  * 7, 10 - 17 - not connected
 141                  */
 142
 143                 gtr-sel0 {
 144                         gpio-hog;
 145                         gpios = <0 0>;
 146                         output-low; /* PCIE = 0, DP = 1 */
 147                         line-name = "sel0";
 148                 };
 149                 gtr-sel1 {
 150                         gpio-hog;
 151                         gpios = <1 0>;
 152                         output-high; /* PCIE = 0, DP = 1 */
 153                         line-name = "sel1";
 154                 };
 155                 gtr-sel2 {
 156                         gpio-hog;
 157                         gpios = <2 0>;
 158                         output-high; /* PCIE = 0, USB0 = 1 */
 159                         line-name = "sel2";
 160                 };
 161                 gtr-sel3 {
 162                         gpio-hog;
 163                         gpios = <3 0>;
 164                         output-high; /* PCIE = 0, SATA = 1 */
 165                         line-name = "sel3";
 166                 };
 167         };
 168
 169         tca6416_u61: gpio@21 {
 170                 compatible = "ti,tca6416";
 171                 reg = <0x21>;
 172                 gpio-controller;
 173                 #gpio-cells = <2>;
 174                 /*
 175                  * IRQ not connected
 176                  * Lines:
 177                  * 0 - VCCPSPLL_EN
 178                  * 1 - MGTRAVCC_EN
 179                  * 2 - MGTRAVTT_EN
 180                  * 3 - VCCPSDDRPLL_EN
 181                  * 4 - MIO26_PMU_INPUT_LS
 182                  * 5 - PL_PMBUS_ALERT
 183                  * 6 - PS_PMBUS_ALERT
 184                  * 7 - MAXIM_PMBUS_ALERT
 185                  * 10 - PL_DDR4_VTERM_EN
 186                  * 11 - PL_DDR4_VPP_2V5_EN
 187                  * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
 188                  * 13 - PS_DIMM_SUSPEND_EN
 189                  * 14 - PS_DDR4_VTERM_EN
 190                  * 15 - PS_DDR4_VPP_2V5_EN
 191                  * 16 - 17 - not connected
 192                  */
 193         };
 194
 195         i2c-mux@75 { /* u60 */
 196                 compatible = "nxp,pca9544";
 197                 #address-cells = <1>;
 198                 #size-cells = <0>;
 199                 reg = <0x75>;
 200                 i2c@0 {
 201                         #address-cells = <1>;
 202                         #size-cells = <0>;
 203                         reg = <0>;
 204                         /* PS_PMBUS */
 205                         ina226@40 { /* u76 */
 206                                 compatible = "ti,ina226";
 207                                 reg = <0x40>;
 208                                 shunt-resistor = <5000>;
 209                         };
 210                         ina226@41 { /* u77 */
 211                                 compatible = "ti,ina226";
 212                                 reg = <0x41>;
 213                                 shunt-resistor = <5000>;
 214                         };
 215                         ina226@42 { /* u78 */
 216                                 compatible = "ti,ina226";
 217                                 reg = <0x42>;
 218                                 shunt-resistor = <5000>;
 219                         };
 220                         ina226@43 { /* u87 */
 221                                 compatible = "ti,ina226";
 222                                 reg = <0x43>;
 223                                 shunt-resistor = <5000>;
 224                         };
 225                         ina226@44 { /* u85 */
 226                                 compatible = "ti,ina226";
 227                                 reg = <0x44>;
 228                                 shunt-resistor = <5000>;
 229                         };
 230                         ina226@45 { /* u86 */
 231                                 compatible = "ti,ina226";
 232                                 reg = <0x45>;
 233                                 shunt-resistor = <5000>;
 234                         };
 235                         ina226@46 { /* u93 */
 236                                 compatible = "ti,ina226";
 237                                 reg = <0x46>;
 238                                 shunt-resistor = <5000>;
 239                         };
 240                         ina226@47 { /* u88 */
 241                                 compatible = "ti,ina226";
 242                                 reg = <0x47>;
 243                                 shunt-resistor = <5000>;
 244                         };
 245                         ina226@4a { /* u15 */
 246                                 compatible = "ti,ina226";
 247                                 reg = <0x4a>;
 248                                 shunt-resistor = <5000>;
 249                         };
 250                         ina226@4b { /* u92 */
 251                                 compatible = "ti,ina226";
 252                                 reg = <0x4b>;
 253                                 shunt-resistor = <5000>;
 254                         };
 255                 };
 256                 i2c@1 {
 257                         #address-cells = <1>;
 258                         #size-cells = <0>;
 259                         reg = <1>;
 260                         /* PL_PMBUS */
 261                         ina226@40 { /* u79 */
 262                                 compatible = "ti,ina226";
 263                                 reg = <0x40>;
 264                                 shunt-resistor = <2000>;
 265                         };
 266                         ina226@41 { /* u81 */
 267                                 compatible = "ti,ina226";
 268                                 reg = <0x41>;
 269                                 shunt-resistor = <5000>;
 270                         };
 271                         ina226@42 { /* u80 */
 272                                 compatible = "ti,ina226";
 273                                 reg = <0x42>;
 274                                 shunt-resistor = <5000>;
 275                         };
 276                         ina226@43 { /* u84 */
 277                                 compatible = "ti,ina226";
 278                                 reg = <0x43>;
 279                                 shunt-resistor = <5000>;
 280                         };
 281                         ina226@44 { /* u16 */
 282                                 compatible = "ti,ina226";
 283                                 reg = <0x44>;
 284                                 shunt-resistor = <5000>;
 285                         };
 286                         ina226@45 { /* u65 */
 287                                 compatible = "ti,ina226";
 288                                 reg = <0x45>;
 289                                 shunt-resistor = <5000>;
 290                         };
 291                         ina226@46 { /* u74 */
 292                                 compatible = "ti,ina226";
 293                                 reg = <0x46>;
 294                                 shunt-resistor = <5000>;
 295                         };
 296                         ina226@47 { /* u75 */
 297                                 compatible = "ti,ina226";
 298                                 reg = <0x47>;
 299                                 shunt-resistor = <5000>;
 300                         };
 301                 };
 302                 i2c@2 {
 303                         #address-cells = <1>;
 304                         #size-cells = <0>;
 305                         reg = <2>;
 306                         /* MAXIM_PMBUS - 00 */
 307                         max15301@a { /* u46 */
 308                                 compatible = "maxim,max15301";
 309                                 reg = <0xa>;
 310                         };
 311                         max15303@b { /* u4 */
 312                                 compatible = "maxim,max15303";
 313                                 reg = <0xb>;
 314                         };
 315                         max15303@10 { /* u13 */
 316                                 compatible = "maxim,max15303";
 317                                 reg = <0x10>;
 318                         };
 319                         max15301@13 { /* u47 */
 320                                 compatible = "maxim,max15301";
 321                                 reg = <0x13>;
 322                         };
 323                         max15303@14 { /* u7 */
 324                                 compatible = "maxim,max15303";
 325                                 reg = <0x14>;
 326                         };
 327                         max15303@15 { /* u6 */
 328                                 compatible = "maxim,max15303";
 329                                 reg = <0x15>;
 330                         };
 331                         max15303@16 { /* u10 */
 332                                 compatible = "maxim,max15303";
 333                                 reg = <0x16>;
 334                         };
 335                         max15303@17 { /* u9 */
 336                                 compatible = "maxim,max15303";
 337                                 reg = <0x17>;
 338                         };
 339                         max15301@18 { /* u63 */
 340                                 compatible = "maxim,max15301";
 341                                 reg = <0x18>;
 342                         };
 343                         max15303@1a { /* u49 */
 344                                 compatible = "maxim,max15303";
 345                                 reg = <0x1a>;
 346                         };
 347                         max15303@1d { /* u18 */
 348                                 compatible = "maxim,max15303";
 349                                 reg = <0x1d>;
 350                         };
 351                         max15303@20 { /* u8 */
 352                                 compatible = "maxim,max15303";
 353                                 status = "disabled"; /* unreachable */
 354                                 reg = <0x20>;
 355                         };
 356
 357                         max20751@72 { /* u95 */
 358                                 compatible = "maxim,max20751";
 359                                 reg = <0x72>;
 360                         };
 361                         max20751@73 { /* u96 */
 362                                 compatible = "maxim,max20751";
 363                                 reg = <0x73>;
 364                         };
 365                 };
 366                 /* Bus 3 is not connected */
 367         };
 368 };
 369
 370 &i2c1 {
 371         status = "okay";
 372         clock-frequency = <400000>;
 373
 374         /* PL i2c via PCA9306 - u45 */
 375         i2c-mux@74 { /* u34 */
 376                 compatible = "nxp,pca9548";
 377                 #address-cells = <1>;
 378                 #size-cells = <0>;
 379                 reg = <0x74>;
 380                 i2c@0 {
 381                         #address-cells = <1>;
 382                         #size-cells = <0>;
 383                         reg = <0>;
 384                         /*
 385                          * IIC_EEPROM 1kB memory which uses 256B blocks
 386                          * where every block has different address.
 387                          *    0 - 256B address 0x54
 388                          * 256B - 512B address 0x55
 389                          * 512B - 768B address 0x56
 390                          * 768B - 1024B address 0x57
 391                          */
 392                         eeprom: eeprom@54 { /* u23 */
 393                                 compatible = "atmel,24c08";
 394                                 reg = <0x54>;
 395                         };
 396                 };
 397                 i2c@1 {
 398                         #address-cells = <1>;
 399                         #size-cells = <0>;
 400                         reg = <1>;
 401                         si5341: clock-generator@36 { /* SI5341 - u69 */
 402                                 reg = <0x36>;
 403                         };
 404
 405                 };
 406                 i2c@2 {
 407                         #address-cells = <1>;
 408                         #size-cells = <0>;
 409                         reg = <2>;
 410                         si570_1: clock-generator@5d { /* USER SI570 - u42 */
 411                                 #clock-cells = <0>;
 412                                 compatible = "silabs,si570";
 413                                 reg = <0x5d>;
 414                                 temperature-stability = <50>;
 415                                 factory-fout = <300000000>;
 416                                 clock-frequency = <300000000>;
 417                         };
 418                 };
 419                 i2c@3 {
 420                         #address-cells = <1>;
 421                         #size-cells = <0>;
 422                         reg = <3>;
 423                         si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
 424                                 #clock-cells = <0>;
 425                                 compatible = "silabs,si570";
 426                                 reg = <0x5d>;
 427                                 temperature-stability = <50>; /* copy from zc702 */
 428                                 factory-fout = <156250000>;
 429                                 clock-frequency = <148500000>;
 430                         };
 431                 };
 432                 i2c@4 {
 433                         #address-cells = <1>;
 434                         #size-cells = <0>;
 435                         reg = <4>;
 436                         si5328: clock-generator@69 {/* SI5328 - u20 */
 437                                 reg = <0x69>;
 438                                 /*
 439                                  * Chip has interrupt present connected to PL
 440                                  * interrupt-parent = <&>;
 441                                  * interrupts = <>;
 442                                  */
 443                         };
 444                 };
 445                 /* 5 - 7 unconnected */
 446         };
 447
 448         i2c-mux@75 {
 449                 compatible = "nxp,pca9548"; /* u135 */
 450                 #address-cells = <1>;
 451                 #size-cells = <0>;
 452                 reg = <0x75>;
 453
 454                 i2c@0 {
 455                         #address-cells = <1>;
 456                         #size-cells = <0>;
 457                         reg = <0>;
 458                         /* HPC0_IIC */
 459                 };
 460                 i2c@1 {
 461                         #address-cells = <1>;
 462                         #size-cells = <0>;
 463                         reg = <1>;
 464                         /* HPC1_IIC */
 465                 };
 466                 i2c@2 {
 467                         #address-cells = <1>;
 468                         #size-cells = <0>;
 469                         reg = <2>;
 470                         /* SYSMON */
 471                 };
 472                 i2c@3 {
 473                         #address-cells = <1>;
 474                         #size-cells = <0>;
 475                         reg = <3>;
 476                         /* DDR4 SODIMM */
 477                 };
 478                 i2c@4 {
 479                         #address-cells = <1>;
 480                         #size-cells = <0>;
 481                         reg = <4>;
 482                         /* SEP 3 */
 483                 };
 484                 i2c@5 {
 485                         #address-cells = <1>;
 486                         #size-cells = <0>;
 487                         reg = <5>;
 488                         /* SEP 2 */
 489                 };
 490                 i2c@6 {
 491                         #address-cells = <1>;
 492                         #size-cells = <0>;
 493                         reg = <6>;
 494                         /* SEP 1 */
 495                 };
 496                 i2c@7 {
 497                         #address-cells = <1>;
 498                         #size-cells = <0>;
 499                         reg = <7>;
 500                         /* SEP 0 */
 501                 };
 502         };
 503 };
 504
 505 &pcie {
 506         status = "okay";
 507 };
 508
 509 &rtc {
 510         status = "okay";
 511 };
 512
 513 &sata {
 514         status = "okay";
 515         /* SATA OOB timing settings */
 516         ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 517         ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 518         ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 519         ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 520         ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 521         ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 522         ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 523         ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 524 };
 525
 526 /* SD1 with level shifter */
 527 &sdhci1 {
 528         status = "okay";
 529         no-1-8-v;
 530 };
 531
 532 &uart0 {
 533         status = "okay";
 534 };
 535
 536 &uart1 {
 537         status = "okay";
 538 };
 539
 540 /* ULPI SMSC USB3320 */
 541 &usb0 {
 542         status = "okay";
 543 };
 544
 545 &watchdog0 {
 546         status = "okay";
 547 };