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perf bpf: Move perf_event_output() from stdio.h to bpf.h
[linux/fpc-iii.git] / drivers / spi / spi-sh-msiof.c
blobadf384323934a6e432183bb16bcad27090b29881
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * SuperH MSIOF SPI Master Interface
4 *
5 * Copyright (c) 2009 Magnus Damm
6 * Copyright (C) 2014 Renesas Electronics Corporation
7 * Copyright (C) 2014-2017 Glider bvba
8 */
9
10 #include <linux/bitmap.h>
11 #include <linux/clk.h>
12 #include <linux/completion.h>
13 #include <linux/delay.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/dmaengine.h>
16 #include <linux/err.h>
17 #include <linux/gpio.h>
18 #include <linux/gpio/consumer.h>
19 #include <linux/interrupt.h>
20 #include <linux/io.h>
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/of.h>
24 #include <linux/of_device.h>
25 #include <linux/platform_device.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/sh_dma.h>
28
29 #include <linux/spi/sh_msiof.h>
30 #include <linux/spi/spi.h>
31
32 #include <asm/unaligned.h>
33
34 struct sh_msiof_chipdata {
35 u16 tx_fifo_size;
36 u16 rx_fifo_size;
37 u16 master_flags;
38 u16 min_div_pow;
39 };
40
41 struct sh_msiof_spi_priv {
42 struct spi_master *master;
43 void __iomem *mapbase;
44 struct clk *clk;
45 struct platform_device *pdev;
46 struct sh_msiof_spi_info *info;
47 struct completion done;
48 struct completion done_txdma;
49 unsigned int tx_fifo_size;
50 unsigned int rx_fifo_size;
51 unsigned int min_div_pow;
52 void *tx_dma_page;
53 void *rx_dma_page;
54 dma_addr_t tx_dma_addr;
55 dma_addr_t rx_dma_addr;
56 unsigned short unused_ss;
57 bool native_cs_inited;
58 bool native_cs_high;
59 bool slave_aborted;
60 };
61
62 #define MAX_SS 3 /* Maximum number of native chip selects */
63
64 #define TMDR1 0x00 /* Transmit Mode Register 1 */
65 #define TMDR2 0x04 /* Transmit Mode Register 2 */
66 #define TMDR3 0x08 /* Transmit Mode Register 3 */
67 #define RMDR1 0x10 /* Receive Mode Register 1 */
68 #define RMDR2 0x14 /* Receive Mode Register 2 */
69 #define RMDR3 0x18 /* Receive Mode Register 3 */
70 #define TSCR 0x20 /* Transmit Clock Select Register */
71 #define RSCR 0x22 /* Receive Clock Select Register (SH, A1, APE6) */
72 #define CTR 0x28 /* Control Register */
73 #define FCTR 0x30 /* FIFO Control Register */
74 #define STR 0x40 /* Status Register */
75 #define IER 0x44 /* Interrupt Enable Register */
76 #define TDR1 0x48 /* Transmit Control Data Register 1 (SH, A1) */
77 #define TDR2 0x4c /* Transmit Control Data Register 2 (SH, A1) */
78 #define TFDR 0x50 /* Transmit FIFO Data Register */
79 #define RDR1 0x58 /* Receive Control Data Register 1 (SH, A1) */
80 #define RDR2 0x5c /* Receive Control Data Register 2 (SH, A1) */
81 #define RFDR 0x60 /* Receive FIFO Data Register */
82
83 /* TMDR1 and RMDR1 */
84 #define MDR1_TRMD 0x80000000 /* Transfer Mode (1 = Master mode) */
85 #define MDR1_SYNCMD_MASK 0x30000000 /* SYNC Mode */
86 #define MDR1_SYNCMD_SPI 0x20000000 /* Level mode/SPI */
87 #define MDR1_SYNCMD_LR 0x30000000 /* L/R mode */
88 #define MDR1_SYNCAC_SHIFT 25 /* Sync Polarity (1 = Active-low) */
89 #define MDR1_BITLSB_SHIFT 24 /* MSB/LSB First (1 = LSB first) */
90 #define MDR1_DTDL_SHIFT 20 /* Data Pin Bit Delay for MSIOF_SYNC */
91 #define MDR1_SYNCDL_SHIFT 16 /* Frame Sync Signal Timing Delay */
92 #define MDR1_FLD_MASK 0x0000000c /* Frame Sync Signal Interval (0-3) */
93 #define MDR1_FLD_SHIFT 2
94 #define MDR1_XXSTP 0x00000001 /* Transmission/Reception Stop on FIFO */
95 /* TMDR1 */
96 #define TMDR1_PCON 0x40000000 /* Transfer Signal Connection */
97 #define TMDR1_SYNCCH_MASK 0xc000000 /* Synchronization Signal Channel Select */
98 #define TMDR1_SYNCCH_SHIFT 26 /* 0=MSIOF_SYNC, 1=MSIOF_SS1, 2=MSIOF_SS2 */
99
100 /* TMDR2 and RMDR2 */
101 #define MDR2_BITLEN1(i) (((i) - 1) << 24) /* Data Size (8-32 bits) */
102 #define MDR2_WDLEN1(i) (((i) - 1) << 16) /* Word Count (1-64/256 (SH, A1))) */
103 #define MDR2_GRPMASK1 0x00000001 /* Group Output Mask 1 (SH, A1) */
104
105 /* TSCR and RSCR */
106 #define SCR_BRPS_MASK 0x1f00 /* Prescaler Setting (1-32) */
107 #define SCR_BRPS(i) (((i) - 1) << 8)
108 #define SCR_BRDV_MASK 0x0007 /* Baud Rate Generator's Division Ratio */
109 #define SCR_BRDV_DIV_2 0x0000
110 #define SCR_BRDV_DIV_4 0x0001
111 #define SCR_BRDV_DIV_8 0x0002
112 #define SCR_BRDV_DIV_16 0x0003
113 #define SCR_BRDV_DIV_32 0x0004
114 #define SCR_BRDV_DIV_1 0x0007
115
116 /* CTR */
117 #define CTR_TSCKIZ_MASK 0xc0000000 /* Transmit Clock I/O Polarity Select */
118 #define CTR_TSCKIZ_SCK 0x80000000 /* Disable SCK when TX disabled */
119 #define CTR_TSCKIZ_POL_SHIFT 30 /* Transmit Clock Polarity */
120 #define CTR_RSCKIZ_MASK 0x30000000 /* Receive Clock Polarity Select */
121 #define CTR_RSCKIZ_SCK 0x20000000 /* Must match CTR_TSCKIZ_SCK */
122 #define CTR_RSCKIZ_POL_SHIFT 28 /* Receive Clock Polarity */
123 #define CTR_TEDG_SHIFT 27 /* Transmit Timing (1 = falling edge) */
124 #define CTR_REDG_SHIFT 26 /* Receive Timing (1 = falling edge) */
125 #define CTR_TXDIZ_MASK 0x00c00000 /* Pin Output When TX is Disabled */
126 #define CTR_TXDIZ_LOW 0x00000000 /* 0 */
127 #define CTR_TXDIZ_HIGH 0x00400000 /* 1 */
128 #define CTR_TXDIZ_HIZ 0x00800000 /* High-impedance */
129 #define CTR_TSCKE 0x00008000 /* Transmit Serial Clock Output Enable */
130 #define CTR_TFSE 0x00004000 /* Transmit Frame Sync Signal Output Enable */
131 #define CTR_TXE 0x00000200 /* Transmit Enable */
132 #define CTR_RXE 0x00000100 /* Receive Enable */
133
134 /* FCTR */
135 #define FCTR_TFWM_MASK 0xe0000000 /* Transmit FIFO Watermark */
136 #define FCTR_TFWM_64 0x00000000 /* Transfer Request when 64 empty stages */
137 #define FCTR_TFWM_32 0x20000000 /* Transfer Request when 32 empty stages */
138 #define FCTR_TFWM_24 0x40000000 /* Transfer Request when 24 empty stages */
139 #define FCTR_TFWM_16 0x60000000 /* Transfer Request when 16 empty stages */
140 #define FCTR_TFWM_12 0x80000000 /* Transfer Request when 12 empty stages */
141 #define FCTR_TFWM_8 0xa0000000 /* Transfer Request when 8 empty stages */
142 #define FCTR_TFWM_4 0xc0000000 /* Transfer Request when 4 empty stages */
143 #define FCTR_TFWM_1 0xe0000000 /* Transfer Request when 1 empty stage */
144 #define FCTR_TFUA_MASK 0x07f00000 /* Transmit FIFO Usable Area */
145 #define FCTR_TFUA_SHIFT 20
146 #define FCTR_TFUA(i) ((i) << FCTR_TFUA_SHIFT)
147 #define FCTR_RFWM_MASK 0x0000e000 /* Receive FIFO Watermark */
148 #define FCTR_RFWM_1 0x00000000 /* Transfer Request when 1 valid stages */
149 #define FCTR_RFWM_4 0x00002000 /* Transfer Request when 4 valid stages */
150 #define FCTR_RFWM_8 0x00004000 /* Transfer Request when 8 valid stages */
151 #define FCTR_RFWM_16 0x00006000 /* Transfer Request when 16 valid stages */
152 #define FCTR_RFWM_32 0x00008000 /* Transfer Request when 32 valid stages */
153 #define FCTR_RFWM_64 0x0000a000 /* Transfer Request when 64 valid stages */
154 #define FCTR_RFWM_128 0x0000c000 /* Transfer Request when 128 valid stages */
155 #define FCTR_RFWM_256 0x0000e000 /* Transfer Request when 256 valid stages */
156 #define FCTR_RFUA_MASK 0x00001ff0 /* Receive FIFO Usable Area (0x40 = full) */
157 #define FCTR_RFUA_SHIFT 4
158 #define FCTR_RFUA(i) ((i) << FCTR_RFUA_SHIFT)
159
160 /* STR */
161 #define STR_TFEMP 0x20000000 /* Transmit FIFO Empty */
162 #define STR_TDREQ 0x10000000 /* Transmit Data Transfer Request */
163 #define STR_TEOF 0x00800000 /* Frame Transmission End */
164 #define STR_TFSERR 0x00200000 /* Transmit Frame Synchronization Error */
165 #define STR_TFOVF 0x00100000 /* Transmit FIFO Overflow */
166 #define STR_TFUDF 0x00080000 /* Transmit FIFO Underflow */
167 #define STR_RFFUL 0x00002000 /* Receive FIFO Full */
168 #define STR_RDREQ 0x00001000 /* Receive Data Transfer Request */
169 #define STR_REOF 0x00000080 /* Frame Reception End */
170 #define STR_RFSERR 0x00000020 /* Receive Frame Synchronization Error */
171 #define STR_RFUDF 0x00000010 /* Receive FIFO Underflow */
172 #define STR_RFOVF 0x00000008 /* Receive FIFO Overflow */
173
174 /* IER */
175 #define IER_TDMAE 0x80000000 /* Transmit Data DMA Transfer Req. Enable */
176 #define IER_TFEMPE 0x20000000 /* Transmit FIFO Empty Enable */
177 #define IER_TDREQE 0x10000000 /* Transmit Data Transfer Request Enable */
178 #define IER_TEOFE 0x00800000 /* Frame Transmission End Enable */
179 #define IER_TFSERRE 0x00200000 /* Transmit Frame Sync Error Enable */
180 #define IER_TFOVFE 0x00100000 /* Transmit FIFO Overflow Enable */
181 #define IER_TFUDFE 0x00080000 /* Transmit FIFO Underflow Enable */
182 #define IER_RDMAE 0x00008000 /* Receive Data DMA Transfer Req. Enable */
183 #define IER_RFFULE 0x00002000 /* Receive FIFO Full Enable */
184 #define IER_RDREQE 0x00001000 /* Receive Data Transfer Request Enable */
185 #define IER_REOFE 0x00000080 /* Frame Reception End Enable */
186 #define IER_RFSERRE 0x00000020 /* Receive Frame Sync Error Enable */
187 #define IER_RFUDFE 0x00000010 /* Receive FIFO Underflow Enable */
188 #define IER_RFOVFE 0x00000008 /* Receive FIFO Overflow Enable */
189
190
191 static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs)
192 {
193 switch (reg_offs) {
194 case TSCR:
195 case RSCR:
196 return ioread16(p->mapbase + reg_offs);
197 default:
198 return ioread32(p->mapbase + reg_offs);
199 }
200 }
201
202 static void sh_msiof_write(struct sh_msiof_spi_priv *p, int reg_offs,
203 u32 value)
204 {
205 switch (reg_offs) {
206 case TSCR:
207 case RSCR:
208 iowrite16(value, p->mapbase + reg_offs);
209 break;
210 default:
211 iowrite32(value, p->mapbase + reg_offs);
212 break;
213 }
214 }
215
216 static int sh_msiof_modify_ctr_wait(struct sh_msiof_spi_priv *p,
217 u32 clr, u32 set)
218 {
219 u32 mask = clr | set;
220 u32 data;
221 int k;
222
223 data = sh_msiof_read(p, CTR);
224 data &= ~clr;
225 data |= set;
226 sh_msiof_write(p, CTR, data);
227
228 for (k = 100; k > 0; k--) {
229 if ((sh_msiof_read(p, CTR) & mask) == set)
230 break;
231
232 udelay(10);
233 }
234
235 return k > 0 ? 0 : -ETIMEDOUT;
236 }
237
238 static irqreturn_t sh_msiof_spi_irq(int irq, void *data)
239 {
240 struct sh_msiof_spi_priv *p = data;
241
242 /* just disable the interrupt and wake up */
243 sh_msiof_write(p, IER, 0);
244 complete(&p->done);
245
246 return IRQ_HANDLED;
247 }
248
249 static const u32 sh_msiof_spi_div_array[] = {
250 SCR_BRDV_DIV_1, SCR_BRDV_DIV_2, SCR_BRDV_DIV_4,
251 SCR_BRDV_DIV_8, SCR_BRDV_DIV_16, SCR_BRDV_DIV_32,
252 };
253
254 static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
255 unsigned long parent_rate, u32 spi_hz)
256 {
257 unsigned long div;
258 u32 brps, scr;
259 unsigned int div_pow = p->min_div_pow;
260
261 if (!spi_hz || !parent_rate) {
262 WARN(1, "Invalid clock rate parameters %lu and %u\n",
263 parent_rate, spi_hz);
264 return;
265 }
266
267 div = DIV_ROUND_UP(parent_rate, spi_hz);
268 if (div <= 1024) {
269 /* SCR_BRDV_DIV_1 is valid only if BRPS is x 1/1 or x 1/2 */
270 if (!div_pow && div <= 32 && div > 2)
271 div_pow = 1;
272
273 if (div_pow)
274 brps = (div + 1) >> div_pow;
275 else
276 brps = div;
277
278 for (; brps > 32; div_pow++)
279 brps = (brps + 1) >> 1;
280 } else {
281 /* Set transfer rate composite divisor to 2^5 * 32 = 1024 */
282 dev_err(&p->pdev->dev,
283 "Requested SPI transfer rate %d is too low\n", spi_hz);
284 div_pow = 5;
285 brps = 32;
286 }
287
288 scr = sh_msiof_spi_div_array[div_pow] | SCR_BRPS(brps);
289 sh_msiof_write(p, TSCR, scr);
290 if (!(p->master->flags & SPI_MASTER_MUST_TX))
291 sh_msiof_write(p, RSCR, scr);
292 }
293
294 static u32 sh_msiof_get_delay_bit(u32 dtdl_or_syncdl)
295 {
296 /*
297 * DTDL/SYNCDL bit : p->info->dtdl or p->info->syncdl
298 * b'000 : 0
299 * b'001 : 100
300 * b'010 : 200
301 * b'011 (SYNCDL only) : 300
302 * b'101 : 50
303 * b'110 : 150
304 */
305 if (dtdl_or_syncdl % 100)
306 return dtdl_or_syncdl / 100 + 5;
307 else
308 return dtdl_or_syncdl / 100;
309 }
310
311 static u32 sh_msiof_spi_get_dtdl_and_syncdl(struct sh_msiof_spi_priv *p)
312 {
313 u32 val;
314
315 if (!p->info)
316 return 0;
317
318 /* check if DTDL and SYNCDL is allowed value */
319 if (p->info->dtdl > 200 || p->info->syncdl > 300) {
320 dev_warn(&p->pdev->dev, "DTDL or SYNCDL is too large\n");
321 return 0;
322 }
323
324 /* check if the sum of DTDL and SYNCDL becomes an integer value */
325 if ((p->info->dtdl + p->info->syncdl) % 100) {
326 dev_warn(&p->pdev->dev, "the sum of DTDL/SYNCDL is not good\n");
327 return 0;
328 }
329
330 val = sh_msiof_get_delay_bit(p->info->dtdl) << MDR1_DTDL_SHIFT;
331 val |= sh_msiof_get_delay_bit(p->info->syncdl) << MDR1_SYNCDL_SHIFT;
332
333 return val;
334 }
335
336 static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p, u32 ss,
337 u32 cpol, u32 cpha,
338 u32 tx_hi_z, u32 lsb_first, u32 cs_high)
339 {
340 u32 tmp;
341 int edge;
342
343 /*
344 * CPOL CPHA TSCKIZ RSCKIZ TEDG REDG
345 * 0 0 10 10 1 1
346 * 0 1 10 10 0 0
347 * 1 0 11 11 0 0
348 * 1 1 11 11 1 1
349 */
350 tmp = MDR1_SYNCMD_SPI | 1 << MDR1_FLD_SHIFT | MDR1_XXSTP;
351 tmp |= !cs_high << MDR1_SYNCAC_SHIFT;
352 tmp |= lsb_first << MDR1_BITLSB_SHIFT;
353 tmp |= sh_msiof_spi_get_dtdl_and_syncdl(p);
354 if (spi_controller_is_slave(p->master)) {
355 sh_msiof_write(p, TMDR1, tmp | TMDR1_PCON);
356 } else {
357 sh_msiof_write(p, TMDR1,
358 tmp | MDR1_TRMD | TMDR1_PCON |
359 (ss < MAX_SS ? ss : 0) << TMDR1_SYNCCH_SHIFT);
360 }
361 if (p->master->flags & SPI_MASTER_MUST_TX) {
362 /* These bits are reserved if RX needs TX */
363 tmp &= ~0x0000ffff;
364 }
365 sh_msiof_write(p, RMDR1, tmp);
366
367 tmp = 0;
368 tmp |= CTR_TSCKIZ_SCK | cpol << CTR_TSCKIZ_POL_SHIFT;
369 tmp |= CTR_RSCKIZ_SCK | cpol << CTR_RSCKIZ_POL_SHIFT;
370
371 edge = cpol ^ !cpha;
372
373 tmp |= edge << CTR_TEDG_SHIFT;
374 tmp |= edge << CTR_REDG_SHIFT;
375 tmp |= tx_hi_z ? CTR_TXDIZ_HIZ : CTR_TXDIZ_LOW;
376 sh_msiof_write(p, CTR, tmp);
377 }
378
379 static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p,
380 const void *tx_buf, void *rx_buf,
381 u32 bits, u32 words)
382 {
383 u32 dr2 = MDR2_BITLEN1(bits) | MDR2_WDLEN1(words);
384
385 if (tx_buf || (p->master->flags & SPI_MASTER_MUST_TX))
386 sh_msiof_write(p, TMDR2, dr2);
387 else
388 sh_msiof_write(p, TMDR2, dr2 | MDR2_GRPMASK1);
389
390 if (rx_buf)
391 sh_msiof_write(p, RMDR2, dr2);
392 }
393
394 static void sh_msiof_reset_str(struct sh_msiof_spi_priv *p)
395 {
396 sh_msiof_write(p, STR,
397 sh_msiof_read(p, STR) & ~(STR_TDREQ | STR_RDREQ));
398 }
399
400 static void sh_msiof_spi_write_fifo_8(struct sh_msiof_spi_priv *p,
401 const void *tx_buf, int words, int fs)
402 {
403 const u8 *buf_8 = tx_buf;
404 int k;
405
406 for (k = 0; k < words; k++)
407 sh_msiof_write(p, TFDR, buf_8[k] << fs);
408 }
409
410 static void sh_msiof_spi_write_fifo_16(struct sh_msiof_spi_priv *p,
411 const void *tx_buf, int words, int fs)
412 {
413 const u16 *buf_16 = tx_buf;
414 int k;
415
416 for (k = 0; k < words; k++)
417 sh_msiof_write(p, TFDR, buf_16[k] << fs);
418 }
419
420 static void sh_msiof_spi_write_fifo_16u(struct sh_msiof_spi_priv *p,
421 const void *tx_buf, int words, int fs)
422 {
423 const u16 *buf_16 = tx_buf;
424 int k;
425
426 for (k = 0; k < words; k++)
427 sh_msiof_write(p, TFDR, get_unaligned(&buf_16[k]) << fs);
428 }
429
430 static void sh_msiof_spi_write_fifo_32(struct sh_msiof_spi_priv *p,
431 const void *tx_buf, int words, int fs)
432 {
433 const u32 *buf_32 = tx_buf;
434 int k;
435
436 for (k = 0; k < words; k++)
437 sh_msiof_write(p, TFDR, buf_32[k] << fs);
438 }
439
440 static void sh_msiof_spi_write_fifo_32u(struct sh_msiof_spi_priv *p,
441 const void *tx_buf, int words, int fs)
442 {
443 const u32 *buf_32 = tx_buf;
444 int k;
445
446 for (k = 0; k < words; k++)
447 sh_msiof_write(p, TFDR, get_unaligned(&buf_32[k]) << fs);
448 }
449
450 static void sh_msiof_spi_write_fifo_s32(struct sh_msiof_spi_priv *p,
451 const void *tx_buf, int words, int fs)
452 {
453 const u32 *buf_32 = tx_buf;
454 int k;
455
456 for (k = 0; k < words; k++)
457 sh_msiof_write(p, TFDR, swab32(buf_32[k] << fs));
458 }
459
460 static void sh_msiof_spi_write_fifo_s32u(struct sh_msiof_spi_priv *p,
461 const void *tx_buf, int words, int fs)
462 {
463 const u32 *buf_32 = tx_buf;
464 int k;
465
466 for (k = 0; k < words; k++)
467 sh_msiof_write(p, TFDR, swab32(get_unaligned(&buf_32[k]) << fs));
468 }
469
470 static void sh_msiof_spi_read_fifo_8(struct sh_msiof_spi_priv *p,
471 void *rx_buf, int words, int fs)
472 {
473 u8 *buf_8 = rx_buf;
474 int k;
475
476 for (k = 0; k < words; k++)
477 buf_8[k] = sh_msiof_read(p, RFDR) >> fs;
478 }
479
480 static void sh_msiof_spi_read_fifo_16(struct sh_msiof_spi_priv *p,
481 void *rx_buf, int words, int fs)
482 {
483 u16 *buf_16 = rx_buf;
484 int k;
485
486 for (k = 0; k < words; k++)
487 buf_16[k] = sh_msiof_read(p, RFDR) >> fs;
488 }
489
490 static void sh_msiof_spi_read_fifo_16u(struct sh_msiof_spi_priv *p,
491 void *rx_buf, int words, int fs)
492 {
493 u16 *buf_16 = rx_buf;
494 int k;
495
496 for (k = 0; k < words; k++)
497 put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_16[k]);
498 }
499
500 static void sh_msiof_spi_read_fifo_32(struct sh_msiof_spi_priv *p,
501 void *rx_buf, int words, int fs)
502 {
503 u32 *buf_32 = rx_buf;
504 int k;
505
506 for (k = 0; k < words; k++)
507 buf_32[k] = sh_msiof_read(p, RFDR) >> fs;
508 }
509
510 static void sh_msiof_spi_read_fifo_32u(struct sh_msiof_spi_priv *p,
511 void *rx_buf, int words, int fs)
512 {
513 u32 *buf_32 = rx_buf;
514 int k;
515
516 for (k = 0; k < words; k++)
517 put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_32[k]);
518 }
519
520 static void sh_msiof_spi_read_fifo_s32(struct sh_msiof_spi_priv *p,
521 void *rx_buf, int words, int fs)
522 {
523 u32 *buf_32 = rx_buf;
524 int k;
525
526 for (k = 0; k < words; k++)
527 buf_32[k] = swab32(sh_msiof_read(p, RFDR) >> fs);
528 }
529
530 static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv *p,
531 void *rx_buf, int words, int fs)
532 {
533 u32 *buf_32 = rx_buf;
534 int k;
535
536 for (k = 0; k < words; k++)
537 put_unaligned(swab32(sh_msiof_read(p, RFDR) >> fs), &buf_32[k]);
538 }
539
540 static int sh_msiof_spi_setup(struct spi_device *spi)
541 {
542 struct device_node *np = spi->master->dev.of_node;
543 struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master);
544 u32 clr, set, tmp;
545
546 if (!np) {
547 /*
548 * Use spi->controller_data for CS (same strategy as spi_gpio),
549 * if any. otherwise let HW control CS
550 */
551 spi->cs_gpio = (uintptr_t)spi->controller_data;
552 }
553
554 if (gpio_is_valid(spi->cs_gpio)) {
555 gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
556 return 0;
557 }
558
559 if (spi_controller_is_slave(p->master))
560 return 0;
561
562 if (p->native_cs_inited &&
563 (p->native_cs_high == !!(spi->mode & SPI_CS_HIGH)))
564 return 0;
565
566 /* Configure native chip select mode/polarity early */
567 clr = MDR1_SYNCMD_MASK;
568 set = MDR1_SYNCMD_SPI;
569 if (spi->mode & SPI_CS_HIGH)
570 clr |= BIT(MDR1_SYNCAC_SHIFT);
571 else
572 set |= BIT(MDR1_SYNCAC_SHIFT);
573 pm_runtime_get_sync(&p->pdev->dev);
574 tmp = sh_msiof_read(p, TMDR1) & ~clr;
575 sh_msiof_write(p, TMDR1, tmp | set | MDR1_TRMD | TMDR1_PCON);
576 tmp = sh_msiof_read(p, RMDR1) & ~clr;
577 sh_msiof_write(p, RMDR1, tmp | set);
578 pm_runtime_put(&p->pdev->dev);
579 p->native_cs_high = spi->mode & SPI_CS_HIGH;
580 p->native_cs_inited = true;
581 return 0;
582 }
583
584 static int sh_msiof_prepare_message(struct spi_master *master,
585 struct spi_message *msg)
586 {
587 struct sh_msiof_spi_priv *p = spi_master_get_devdata(master);
588 const struct spi_device *spi = msg->spi;
589 u32 ss, cs_high;
590
591 /* Configure pins before asserting CS */
592 if (gpio_is_valid(spi->cs_gpio)) {
593 ss = p->unused_ss;
594 cs_high = p->native_cs_high;
595 } else {
596 ss = spi->chip_select;
597 cs_high = !!(spi->mode & SPI_CS_HIGH);
598 }
599 sh_msiof_spi_set_pin_regs(p, ss, !!(spi->mode & SPI_CPOL),
600 !!(spi->mode & SPI_CPHA),
601 !!(spi->mode & SPI_3WIRE),
602 !!(spi->mode & SPI_LSB_FIRST), cs_high);
603 return 0;
604 }
605
606 static int sh_msiof_spi_start(struct sh_msiof_spi_priv *p, void *rx_buf)
607 {
608 bool slave = spi_controller_is_slave(p->master);
609 int ret = 0;
610
611 /* setup clock and rx/tx signals */
612 if (!slave)
613 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TSCKE);
614 if (rx_buf && !ret)
615 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_RXE);
616 if (!ret)
617 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TXE);
618
619 /* start by setting frame bit */
620 if (!ret && !slave)
621 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TFSE);
622
623 return ret;
624 }
625
626 static int sh_msiof_spi_stop(struct sh_msiof_spi_priv *p, void *rx_buf)
627 {
628 bool slave = spi_controller_is_slave(p->master);
629 int ret = 0;
630
631 /* shut down frame, rx/tx and clock signals */
632 if (!slave)
633 ret = sh_msiof_modify_ctr_wait(p, CTR_TFSE, 0);
634 if (!ret)
635 ret = sh_msiof_modify_ctr_wait(p, CTR_TXE, 0);
636 if (rx_buf && !ret)
637 ret = sh_msiof_modify_ctr_wait(p, CTR_RXE, 0);
638 if (!ret && !slave)
639 ret = sh_msiof_modify_ctr_wait(p, CTR_TSCKE, 0);
640
641 return ret;
642 }
643
644 static int sh_msiof_slave_abort(struct spi_master *master)
645 {
646 struct sh_msiof_spi_priv *p = spi_master_get_devdata(master);
647
648 p->slave_aborted = true;
649 complete(&p->done);
650 complete(&p->done_txdma);
651 return 0;
652 }
653
654 static int sh_msiof_wait_for_completion(struct sh_msiof_spi_priv *p,
655 struct completion *x)
656 {
657 if (spi_controller_is_slave(p->master)) {
658 if (wait_for_completion_interruptible(x) ||
659 p->slave_aborted) {
660 dev_dbg(&p->pdev->dev, "interrupted\n");
661 return -EINTR;
662 }
663 } else {
664 if (!wait_for_completion_timeout(x, HZ)) {
665 dev_err(&p->pdev->dev, "timeout\n");
666 return -ETIMEDOUT;
667 }
668 }
669
670 return 0;
671 }
672
673 static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p,
674 void (*tx_fifo)(struct sh_msiof_spi_priv *,
675 const void *, int, int),
676 void (*rx_fifo)(struct sh_msiof_spi_priv *,
677 void *, int, int),
678 const void *tx_buf, void *rx_buf,
679 int words, int bits)
680 {
681 int fifo_shift;
682 int ret;
683
684 /* limit maximum word transfer to rx/tx fifo size */
685 if (tx_buf)
686 words = min_t(int, words, p->tx_fifo_size);
687 if (rx_buf)
688 words = min_t(int, words, p->rx_fifo_size);
689
690 /* the fifo contents need shifting */
691 fifo_shift = 32 - bits;
692
693 /* default FIFO watermarks for PIO */
694 sh_msiof_write(p, FCTR, 0);
695
696 /* setup msiof transfer mode registers */
697 sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words);
698 sh_msiof_write(p, IER, IER_TEOFE | IER_REOFE);
699
700 /* write tx fifo */
701 if (tx_buf)
702 tx_fifo(p, tx_buf, words, fifo_shift);
703
704 reinit_completion(&p->done);
705 p->slave_aborted = false;
706
707 ret = sh_msiof_spi_start(p, rx_buf);
708 if (ret) {
709 dev_err(&p->pdev->dev, "failed to start hardware\n");
710 goto stop_ier;
711 }
712
713 /* wait for tx fifo to be emptied / rx fifo to be filled */
714 ret = sh_msiof_wait_for_completion(p, &p->done);
715 if (ret)
716 goto stop_reset;
717
718 /* read rx fifo */
719 if (rx_buf)
720 rx_fifo(p, rx_buf, words, fifo_shift);
721
722 /* clear status bits */
723 sh_msiof_reset_str(p);
724
725 ret = sh_msiof_spi_stop(p, rx_buf);
726 if (ret) {
727 dev_err(&p->pdev->dev, "failed to shut down hardware\n");
728 return ret;
729 }
730
731 return words;
732
733 stop_reset:
734 sh_msiof_reset_str(p);
735 sh_msiof_spi_stop(p, rx_buf);
736 stop_ier:
737 sh_msiof_write(p, IER, 0);
738 return ret;
739 }
740
741 static void sh_msiof_dma_complete(void *arg)
742 {
743 complete(arg);
744 }
745
746 static int sh_msiof_dma_once(struct sh_msiof_spi_priv *p, const void *tx,
747 void *rx, unsigned int len)
748 {
749 u32 ier_bits = 0;
750 struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL;
751 dma_cookie_t cookie;
752 int ret;
753
754 /* First prepare and submit the DMA request(s), as this may fail */
755 if (rx) {
756 ier_bits |= IER_RDREQE | IER_RDMAE;
757 desc_rx = dmaengine_prep_slave_single(p->master->dma_rx,
758 p->rx_dma_addr, len, DMA_DEV_TO_MEM,
759 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
760 if (!desc_rx)
761 return -EAGAIN;
762
763 desc_rx->callback = sh_msiof_dma_complete;
764 desc_rx->callback_param = &p->done;
765 cookie = dmaengine_submit(desc_rx);
766 if (dma_submit_error(cookie))
767 return cookie;
768 }
769
770 if (tx) {
771 ier_bits |= IER_TDREQE | IER_TDMAE;
772 dma_sync_single_for_device(p->master->dma_tx->device->dev,
773 p->tx_dma_addr, len, DMA_TO_DEVICE);
774 desc_tx = dmaengine_prep_slave_single(p->master->dma_tx,
775 p->tx_dma_addr, len, DMA_MEM_TO_DEV,
776 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
777 if (!desc_tx) {
778 ret = -EAGAIN;
779 goto no_dma_tx;
780 }
781
782 desc_tx->callback = sh_msiof_dma_complete;
783 desc_tx->callback_param = &p->done_txdma;
784 cookie = dmaengine_submit(desc_tx);
785 if (dma_submit_error(cookie)) {
786 ret = cookie;
787 goto no_dma_tx;
788 }
789 }
790
791 /* 1 stage FIFO watermarks for DMA */
792 sh_msiof_write(p, FCTR, FCTR_TFWM_1 | FCTR_RFWM_1);
793
794 /* setup msiof transfer mode registers (32-bit words) */
795 sh_msiof_spi_set_mode_regs(p, tx, rx, 32, len / 4);
796
797 sh_msiof_write(p, IER, ier_bits);
798
799 reinit_completion(&p->done);
800 if (tx)
801 reinit_completion(&p->done_txdma);
802 p->slave_aborted = false;
803
804 /* Now start DMA */
805 if (rx)
806 dma_async_issue_pending(p->master->dma_rx);
807 if (tx)
808 dma_async_issue_pending(p->master->dma_tx);
809
810 ret = sh_msiof_spi_start(p, rx);
811 if (ret) {
812 dev_err(&p->pdev->dev, "failed to start hardware\n");
813 goto stop_dma;
814 }
815
816 if (tx) {
817 /* wait for tx DMA completion */
818 ret = sh_msiof_wait_for_completion(p, &p->done_txdma);
819 if (ret)
820 goto stop_reset;
821 }
822
823 if (rx) {
824 /* wait for rx DMA completion */
825 ret = sh_msiof_wait_for_completion(p, &p->done);
826 if (ret)
827 goto stop_reset;
828
829 sh_msiof_write(p, IER, 0);
830 } else {
831 /* wait for tx fifo to be emptied */
832 sh_msiof_write(p, IER, IER_TEOFE);
833 ret = sh_msiof_wait_for_completion(p, &p->done);
834 if (ret)
835 goto stop_reset;
836 }
837
838 /* clear status bits */
839 sh_msiof_reset_str(p);
840
841 ret = sh_msiof_spi_stop(p, rx);
842 if (ret) {
843 dev_err(&p->pdev->dev, "failed to shut down hardware\n");
844 return ret;
845 }
846
847 if (rx)
848 dma_sync_single_for_cpu(p->master->dma_rx->device->dev,
849 p->rx_dma_addr, len,
850 DMA_FROM_DEVICE);
851
852 return 0;
853
854 stop_reset:
855 sh_msiof_reset_str(p);
856 sh_msiof_spi_stop(p, rx);
857 stop_dma:
858 if (tx)
859 dmaengine_terminate_all(p->master->dma_tx);
860 no_dma_tx:
861 if (rx)
862 dmaengine_terminate_all(p->master->dma_rx);
863 sh_msiof_write(p, IER, 0);
864 return ret;
865 }
866
867 static void copy_bswap32(u32 *dst, const u32 *src, unsigned int words)
868 {
869 /* src or dst can be unaligned, but not both */
870 if ((unsigned long)src & 3) {
871 while (words--) {
872 *dst++ = swab32(get_unaligned(src));
873 src++;
874 }
875 } else if ((unsigned long)dst & 3) {
876 while (words--) {
877 put_unaligned(swab32(*src++), dst);
878 dst++;
879 }
880 } else {
881 while (words--)
882 *dst++ = swab32(*src++);
883 }
884 }
885
886 static void copy_wswap32(u32 *dst, const u32 *src, unsigned int words)
887 {
888 /* src or dst can be unaligned, but not both */
889 if ((unsigned long)src & 3) {
890 while (words--) {
891 *dst++ = swahw32(get_unaligned(src));
892 src++;
893 }
894 } else if ((unsigned long)dst & 3) {
895 while (words--) {
896 put_unaligned(swahw32(*src++), dst);
897 dst++;
898 }
899 } else {
900 while (words--)
901 *dst++ = swahw32(*src++);
902 }
903 }
904
905 static void copy_plain32(u32 *dst, const u32 *src, unsigned int words)
906 {
907 memcpy(dst, src, words * 4);
908 }
909
910 static int sh_msiof_transfer_one(struct spi_master *master,
911 struct spi_device *spi,
912 struct spi_transfer *t)
913 {
914 struct sh_msiof_spi_priv *p = spi_master_get_devdata(master);
915 void (*copy32)(u32 *, const u32 *, unsigned int);
916 void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int);
917 void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int);
918 const void *tx_buf = t->tx_buf;
919 void *rx_buf = t->rx_buf;
920 unsigned int len = t->len;
921 unsigned int bits = t->bits_per_word;
922 unsigned int bytes_per_word;
923 unsigned int words;
924 int n;
925 bool swab;
926 int ret;
927
928 /* setup clocks (clock already enabled in chipselect()) */
929 if (!spi_controller_is_slave(p->master))
930 sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk), t->speed_hz);
931
932 while (master->dma_tx && len > 15) {
933 /*
934 * DMA supports 32-bit words only, hence pack 8-bit and 16-bit
935 * words, with byte resp. word swapping.
936 */
937 unsigned int l = 0;
938
939 if (tx_buf)
940 l = min(len, p->tx_fifo_size * 4);
941 if (rx_buf)
942 l = min(len, p->rx_fifo_size * 4);
943
944 if (bits <= 8) {
945 if (l & 3)
946 break;
947 copy32 = copy_bswap32;
948 } else if (bits <= 16) {
949 if (l & 3)
950 break;
951 copy32 = copy_wswap32;
952 } else {
953 copy32 = copy_plain32;
954 }
955
956 if (tx_buf)
957 copy32(p->tx_dma_page, tx_buf, l / 4);
958
959 ret = sh_msiof_dma_once(p, tx_buf, rx_buf, l);
960 if (ret == -EAGAIN) {
961 dev_warn_once(&p->pdev->dev,
962 "DMA not available, falling back to PIO\n");
963 break;
964 }
965 if (ret)
966 return ret;
967
968 if (rx_buf) {
969 copy32(rx_buf, p->rx_dma_page, l / 4);
970 rx_buf += l;
971 }
972 if (tx_buf)
973 tx_buf += l;
974
975 len -= l;
976 if (!len)
977 return 0;
978 }
979
980 if (bits <= 8 && len > 15 && !(len & 3)) {
981 bits = 32;
982 swab = true;
983 } else {
984 swab = false;
985 }
986
987 /* setup bytes per word and fifo read/write functions */
988 if (bits <= 8) {
989 bytes_per_word = 1;
990 tx_fifo = sh_msiof_spi_write_fifo_8;
991 rx_fifo = sh_msiof_spi_read_fifo_8;
992 } else if (bits <= 16) {
993 bytes_per_word = 2;
994 if ((unsigned long)tx_buf & 0x01)
995 tx_fifo = sh_msiof_spi_write_fifo_16u;
996 else
997 tx_fifo = sh_msiof_spi_write_fifo_16;
998
999 if ((unsigned long)rx_buf & 0x01)
1000 rx_fifo = sh_msiof_spi_read_fifo_16u;
1001 else
1002 rx_fifo = sh_msiof_spi_read_fifo_16;
1003 } else if (swab) {
1004 bytes_per_word = 4;
1005 if ((unsigned long)tx_buf & 0x03)
1006 tx_fifo = sh_msiof_spi_write_fifo_s32u;
1007 else
1008 tx_fifo = sh_msiof_spi_write_fifo_s32;
1009
1010 if ((unsigned long)rx_buf & 0x03)
1011 rx_fifo = sh_msiof_spi_read_fifo_s32u;
1012 else
1013 rx_fifo = sh_msiof_spi_read_fifo_s32;
1014 } else {
1015 bytes_per_word = 4;
1016 if ((unsigned long)tx_buf & 0x03)
1017 tx_fifo = sh_msiof_spi_write_fifo_32u;
1018 else
1019 tx_fifo = sh_msiof_spi_write_fifo_32;
1020
1021 if ((unsigned long)rx_buf & 0x03)
1022 rx_fifo = sh_msiof_spi_read_fifo_32u;
1023 else
1024 rx_fifo = sh_msiof_spi_read_fifo_32;
1025 }
1026
1027 /* transfer in fifo sized chunks */
1028 words = len / bytes_per_word;
1029
1030 while (words > 0) {
1031 n = sh_msiof_spi_txrx_once(p, tx_fifo, rx_fifo, tx_buf, rx_buf,
1032 words, bits);
1033 if (n < 0)
1034 return n;
1035
1036 if (tx_buf)
1037 tx_buf += n * bytes_per_word;
1038 if (rx_buf)
1039 rx_buf += n * bytes_per_word;
1040 words -= n;
1041 }
1042
1043 return 0;
1044 }
1045
1046 static const struct sh_msiof_chipdata sh_data = {
1047 .tx_fifo_size = 64,
1048 .rx_fifo_size = 64,
1049 .master_flags = 0,
1050 .min_div_pow = 0,
1051 };
1052
1053 static const struct sh_msiof_chipdata rcar_gen2_data = {
1054 .tx_fifo_size = 64,
1055 .rx_fifo_size = 64,
1056 .master_flags = SPI_MASTER_MUST_TX,
1057 .min_div_pow = 0,
1058 };
1059
1060 static const struct sh_msiof_chipdata rcar_gen3_data = {
1061 .tx_fifo_size = 64,
1062 .rx_fifo_size = 64,
1063 .master_flags = SPI_MASTER_MUST_TX,
1064 .min_div_pow = 1,
1065 };
1066
1067 static const struct of_device_id sh_msiof_match[] = {
1068 { .compatible = "renesas,sh-mobile-msiof", .data = &sh_data },
1069 { .compatible = "renesas,msiof-r8a7743", .data = &rcar_gen2_data },
1070 { .compatible = "renesas,msiof-r8a7745", .data = &rcar_gen2_data },
1071 { .compatible = "renesas,msiof-r8a7790", .data = &rcar_gen2_data },
1072 { .compatible = "renesas,msiof-r8a7791", .data = &rcar_gen2_data },
1073 { .compatible = "renesas,msiof-r8a7792", .data = &rcar_gen2_data },
1074 { .compatible = "renesas,msiof-r8a7793", .data = &rcar_gen2_data },
1075 { .compatible = "renesas,msiof-r8a7794", .data = &rcar_gen2_data },
1076 { .compatible = "renesas,rcar-gen2-msiof", .data = &rcar_gen2_data },
1077 { .compatible = "renesas,msiof-r8a7796", .data = &rcar_gen3_data },
1078 { .compatible = "renesas,rcar-gen3-msiof", .data = &rcar_gen3_data },
1079 { .compatible = "renesas,sh-msiof", .data = &sh_data }, /* Deprecated */
1080 {},
1081 };
1082 MODULE_DEVICE_TABLE(of, sh_msiof_match);
1083
1084 #ifdef CONFIG_OF
1085 static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev)
1086 {
1087 struct sh_msiof_spi_info *info;
1088 struct device_node *np = dev->of_node;
1089 u32 num_cs = 1;
1090
1091 info = devm_kzalloc(dev, sizeof(struct sh_msiof_spi_info), GFP_KERNEL);
1092 if (!info)
1093 return NULL;
1094
1095 info->mode = of_property_read_bool(np, "spi-slave") ? MSIOF_SPI_SLAVE
1096 : MSIOF_SPI_MASTER;
1097
1098 /* Parse the MSIOF properties */
1099 if (info->mode == MSIOF_SPI_MASTER)
1100 of_property_read_u32(np, "num-cs", &num_cs);
1101 of_property_read_u32(np, "renesas,tx-fifo-size",
1102 &info->tx_fifo_override);
1103 of_property_read_u32(np, "renesas,rx-fifo-size",
1104 &info->rx_fifo_override);
1105 of_property_read_u32(np, "renesas,dtdl", &info->dtdl);
1106 of_property_read_u32(np, "renesas,syncdl", &info->syncdl);
1107
1108 info->num_chipselect = num_cs;
1109
1110 return info;
1111 }
1112 #else
1113 static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev)
1114 {
1115 return NULL;
1116 }
1117 #endif
1118
1119 static int sh_msiof_get_cs_gpios(struct sh_msiof_spi_priv *p)
1120 {
1121 struct device *dev = &p->pdev->dev;
1122 unsigned int used_ss_mask = 0;
1123 unsigned int cs_gpios = 0;
1124 unsigned int num_cs, i;
1125 int ret;
1126
1127 ret = gpiod_count(dev, "cs");
1128 if (ret <= 0)
1129 return 0;
1130
1131 num_cs = max_t(unsigned int, ret, p->master->num_chipselect);
1132 for (i = 0; i < num_cs; i++) {
1133 struct gpio_desc *gpiod;
1134
1135 gpiod = devm_gpiod_get_index(dev, "cs", i, GPIOD_ASIS);
1136 if (!IS_ERR(gpiod)) {
1137 cs_gpios++;
1138 continue;
1139 }
1140
1141 if (PTR_ERR(gpiod) != -ENOENT)
1142 return PTR_ERR(gpiod);
1143
1144 if (i >= MAX_SS) {
1145 dev_err(dev, "Invalid native chip select %d\n", i);
1146 return -EINVAL;
1147 }
1148 used_ss_mask |= BIT(i);
1149 }
1150 p->unused_ss = ffz(used_ss_mask);
1151 if (cs_gpios && p->unused_ss >= MAX_SS) {
1152 dev_err(dev, "No unused native chip select available\n");
1153 return -EINVAL;
1154 }
1155 return 0;
1156 }
1157
1158 static struct dma_chan *sh_msiof_request_dma_chan(struct device *dev,
1159 enum dma_transfer_direction dir, unsigned int id, dma_addr_t port_addr)
1160 {
1161 dma_cap_mask_t mask;
1162 struct dma_chan *chan;
1163 struct dma_slave_config cfg;
1164 int ret;
1165
1166 dma_cap_zero(mask);
1167 dma_cap_set(DMA_SLAVE, mask);
1168
1169 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
1170 (void *)(unsigned long)id, dev,
1171 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1172 if (!chan) {
1173 dev_warn(dev, "dma_request_slave_channel_compat failed\n");
1174 return NULL;
1175 }
1176
1177 memset(&cfg, 0, sizeof(cfg));
1178 cfg.direction = dir;
1179 if (dir == DMA_MEM_TO_DEV) {
1180 cfg.dst_addr = port_addr;
1181 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1182 } else {
1183 cfg.src_addr = port_addr;
1184 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1185 }
1186
1187 ret = dmaengine_slave_config(chan, &cfg);
1188 if (ret) {
1189 dev_warn(dev, "dmaengine_slave_config failed %d\n", ret);
1190 dma_release_channel(chan);
1191 return NULL;
1192 }
1193
1194 return chan;
1195 }
1196
1197 static int sh_msiof_request_dma(struct sh_msiof_spi_priv *p)
1198 {
1199 struct platform_device *pdev = p->pdev;
1200 struct device *dev = &pdev->dev;
1201 const struct sh_msiof_spi_info *info = dev_get_platdata(dev);
1202 unsigned int dma_tx_id, dma_rx_id;
1203 const struct resource *res;
1204 struct spi_master *master;
1205 struct device *tx_dev, *rx_dev;
1206
1207 if (dev->of_node) {
1208 /* In the OF case we will get the slave IDs from the DT */
1209 dma_tx_id = 0;
1210 dma_rx_id = 0;
1211 } else if (info && info->dma_tx_id && info->dma_rx_id) {
1212 dma_tx_id = info->dma_tx_id;
1213 dma_rx_id = info->dma_rx_id;
1214 } else {
1215 /* The driver assumes no error */
1216 return 0;
1217 }
1218
1219 /* The DMA engine uses the second register set, if present */
1220 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1221 if (!res)
1222 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1223
1224 master = p->master;
1225 master->dma_tx = sh_msiof_request_dma_chan(dev, DMA_MEM_TO_DEV,
1226 dma_tx_id,
1227 res->start + TFDR);
1228 if (!master->dma_tx)
1229 return -ENODEV;
1230
1231 master->dma_rx = sh_msiof_request_dma_chan(dev, DMA_DEV_TO_MEM,
1232 dma_rx_id,
1233 res->start + RFDR);
1234 if (!master->dma_rx)
1235 goto free_tx_chan;
1236
1237 p->tx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
1238 if (!p->tx_dma_page)
1239 goto free_rx_chan;
1240
1241 p->rx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
1242 if (!p->rx_dma_page)
1243 goto free_tx_page;
1244
1245 tx_dev = master->dma_tx->device->dev;
1246 p->tx_dma_addr = dma_map_single(tx_dev, p->tx_dma_page, PAGE_SIZE,
1247 DMA_TO_DEVICE);
1248 if (dma_mapping_error(tx_dev, p->tx_dma_addr))
1249 goto free_rx_page;
1250
1251 rx_dev = master->dma_rx->device->dev;
1252 p->rx_dma_addr = dma_map_single(rx_dev, p->rx_dma_page, PAGE_SIZE,
1253 DMA_FROM_DEVICE);
1254 if (dma_mapping_error(rx_dev, p->rx_dma_addr))
1255 goto unmap_tx_page;
1256
1257 dev_info(dev, "DMA available");
1258 return 0;
1259
1260 unmap_tx_page:
1261 dma_unmap_single(tx_dev, p->tx_dma_addr, PAGE_SIZE, DMA_TO_DEVICE);
1262 free_rx_page:
1263 free_page((unsigned long)p->rx_dma_page);
1264 free_tx_page:
1265 free_page((unsigned long)p->tx_dma_page);
1266 free_rx_chan:
1267 dma_release_channel(master->dma_rx);
1268 free_tx_chan:
1269 dma_release_channel(master->dma_tx);
1270 master->dma_tx = NULL;
1271 return -ENODEV;
1272 }
1273
1274 static void sh_msiof_release_dma(struct sh_msiof_spi_priv *p)
1275 {
1276 struct spi_master *master = p->master;
1277
1278 if (!master->dma_tx)
1279 return;
1280
1281 dma_unmap_single(master->dma_rx->device->dev, p->rx_dma_addr,
1282 PAGE_SIZE, DMA_FROM_DEVICE);
1283 dma_unmap_single(master->dma_tx->device->dev, p->tx_dma_addr,
1284 PAGE_SIZE, DMA_TO_DEVICE);
1285 free_page((unsigned long)p->rx_dma_page);
1286 free_page((unsigned long)p->tx_dma_page);
1287 dma_release_channel(master->dma_rx);
1288 dma_release_channel(master->dma_tx);
1289 }
1290
1291 static int sh_msiof_spi_probe(struct platform_device *pdev)
1292 {
1293 struct resource *r;
1294 struct spi_master *master;
1295 const struct sh_msiof_chipdata *chipdata;
1296 struct sh_msiof_spi_info *info;
1297 struct sh_msiof_spi_priv *p;
1298 int i;
1299 int ret;
1300
1301 chipdata = of_device_get_match_data(&pdev->dev);
1302 if (chipdata) {
1303 info = sh_msiof_spi_parse_dt(&pdev->dev);
1304 } else {
1305 chipdata = (const void *)pdev->id_entry->driver_data;
1306 info = dev_get_platdata(&pdev->dev);
1307 }
1308
1309 if (!info) {
1310 dev_err(&pdev->dev, "failed to obtain device info\n");
1311 return -ENXIO;
1312 }
1313
1314 if (info->mode == MSIOF_SPI_SLAVE)
1315 master = spi_alloc_slave(&pdev->dev,
1316 sizeof(struct sh_msiof_spi_priv));
1317 else
1318 master = spi_alloc_master(&pdev->dev,
1319 sizeof(struct sh_msiof_spi_priv));
1320 if (master == NULL)
1321 return -ENOMEM;
1322
1323 p = spi_master_get_devdata(master);
1324
1325 platform_set_drvdata(pdev, p);
1326 p->master = master;
1327 p->info = info;
1328 p->min_div_pow = chipdata->min_div_pow;
1329
1330 init_completion(&p->done);
1331 init_completion(&p->done_txdma);
1332
1333 p->clk = devm_clk_get(&pdev->dev, NULL);
1334 if (IS_ERR(p->clk)) {
1335 dev_err(&pdev->dev, "cannot get clock\n");
1336 ret = PTR_ERR(p->clk);
1337 goto err1;
1338 }
1339
1340 i = platform_get_irq(pdev, 0);
1341 if (i < 0) {
1342 dev_err(&pdev->dev, "cannot get IRQ\n");
1343 ret = i;
1344 goto err1;
1345 }
1346
1347 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1348 p->mapbase = devm_ioremap_resource(&pdev->dev, r);
1349 if (IS_ERR(p->mapbase)) {
1350 ret = PTR_ERR(p->mapbase);
1351 goto err1;
1352 }
1353
1354 ret = devm_request_irq(&pdev->dev, i, sh_msiof_spi_irq, 0,
1355 dev_name(&pdev->dev), p);
1356 if (ret) {
1357 dev_err(&pdev->dev, "unable to request irq\n");
1358 goto err1;
1359 }
1360
1361 p->pdev = pdev;
1362 pm_runtime_enable(&pdev->dev);
1363
1364 /* Platform data may override FIFO sizes */
1365 p->tx_fifo_size = chipdata->tx_fifo_size;
1366 p->rx_fifo_size = chipdata->rx_fifo_size;
1367 if (p->info->tx_fifo_override)
1368 p->tx_fifo_size = p->info->tx_fifo_override;
1369 if (p->info->rx_fifo_override)
1370 p->rx_fifo_size = p->info->rx_fifo_override;
1371
1372 /* Setup GPIO chip selects */
1373 master->num_chipselect = p->info->num_chipselect;
1374 ret = sh_msiof_get_cs_gpios(p);
1375 if (ret)
1376 goto err1;
1377
1378 /* init master code */
1379 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1380 master->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE;
1381 master->flags = chipdata->master_flags;
1382 master->bus_num = pdev->id;
1383 master->dev.of_node = pdev->dev.of_node;
1384 master->setup = sh_msiof_spi_setup;
1385 master->prepare_message = sh_msiof_prepare_message;
1386 master->slave_abort = sh_msiof_slave_abort;
1387 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32);
1388 master->auto_runtime_pm = true;
1389 master->transfer_one = sh_msiof_transfer_one;
1390
1391 ret = sh_msiof_request_dma(p);
1392 if (ret < 0)
1393 dev_warn(&pdev->dev, "DMA not available, using PIO\n");
1394
1395 ret = devm_spi_register_master(&pdev->dev, master);
1396 if (ret < 0) {
1397 dev_err(&pdev->dev, "spi_register_master error.\n");
1398 goto err2;
1399 }
1400
1401 return 0;
1402
1403 err2:
1404 sh_msiof_release_dma(p);
1405 pm_runtime_disable(&pdev->dev);
1406 err1:
1407 spi_master_put(master);
1408 return ret;
1409 }
1410
1411 static int sh_msiof_spi_remove(struct platform_device *pdev)
1412 {
1413 struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev);
1414
1415 sh_msiof_release_dma(p);
1416 pm_runtime_disable(&pdev->dev);
1417 return 0;
1418 }
1419
1420 static const struct platform_device_id spi_driver_ids[] = {
1421 { "spi_sh_msiof", (kernel_ulong_t)&sh_data },
1422 {},
1423 };
1424 MODULE_DEVICE_TABLE(platform, spi_driver_ids);
1425
1426 #ifdef CONFIG_PM_SLEEP
1427 static int sh_msiof_spi_suspend(struct device *dev)
1428 {
1429 struct platform_device *pdev = to_platform_device(dev);
1430 struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev);
1431
1432 return spi_master_suspend(p->master);
1433 }
1434
1435 static int sh_msiof_spi_resume(struct device *dev)
1436 {
1437 struct platform_device *pdev = to_platform_device(dev);
1438 struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev);
1439
1440 return spi_master_resume(p->master);
1441 }
1442
1443 static SIMPLE_DEV_PM_OPS(sh_msiof_spi_pm_ops, sh_msiof_spi_suspend,
1444 sh_msiof_spi_resume);
1445 #define DEV_PM_OPS &sh_msiof_spi_pm_ops
1446 #else
1447 #define DEV_PM_OPS NULL
1448 #endif /* CONFIG_PM_SLEEP */
1449
1450 static struct platform_driver sh_msiof_spi_drv = {
1451 .probe = sh_msiof_spi_probe,
1452 .remove = sh_msiof_spi_remove,
1453 .id_table = spi_driver_ids,
1454 .driver = {
1455 .name = "spi_sh_msiof",
1456 .pm = DEV_PM_OPS,
1457 .of_match_table = of_match_ptr(sh_msiof_match),
1458 },
1459 };
1460 module_platform_driver(sh_msiof_spi_drv);
1461
1462 MODULE_DESCRIPTION("SuperH MSIOF SPI Master Interface Driver");
1463 MODULE_AUTHOR("Magnus Damm");
1464 MODULE_LICENSE("GPL v2");
1465 MODULE_ALIAS("platform:spi_sh_msiof");
Linux with added FPC-III support