| blob | ea0349f6358658065b52aa1473e877ee4fa8f5ba |
1 /*
2 * linux/arch/arm/vfp/vfphw.S
3 *
4 * Copyright (C) 2004 ARM Limited.
5 * Written by Deep Blue Solutions Limited.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This code is called from the kernel's undefined instruction trap.
12 * r9 holds the return address for successful handling.
13 * lr holds the return address for unrecognised instructions.
14 * r10 points at the start of the private FP workspace in the thread structure
15 * sp points to a struct pt_regs (as defined in include/asm/proc/ptrace.h)
16 */
17 #include <asm/thread_info.h>
18 #include <asm/vfpmacros.h>
19 #include <linux/kern_levels.h>
20 #include "../kernel/entry-header.S"
22 .macro DBGSTR, str
23 #ifdef DEBUG
24 stmfd sp!, {r0-r3, ip, lr}
25 add r0, pc, #4
26 bl printk
27 b 1f
28 .asciz KERN_DEBUG "VFP: \str\n"
29 .balign 4
30 1: ldmfd sp!, {r0-r3, ip, lr}
31 #endif
32 .endm
34 .macro DBGSTR1, str, arg
35 #ifdef DEBUG
36 stmfd sp!, {r0-r3, ip, lr}
37 mov r1, \arg
38 add r0, pc, #4
39 bl printk
40 b 1f
41 .asciz KERN_DEBUG "VFP: \str\n"
42 .balign 4
43 1: ldmfd sp!, {r0-r3, ip, lr}
44 #endif
45 .endm
47 .macro DBGSTR3, str, arg1, arg2, arg3
48 #ifdef DEBUG
49 stmfd sp!, {r0-r3, ip, lr}
50 mov r3, \arg3
51 mov r2, \arg2
52 mov r1, \arg1
53 add r0, pc, #4
54 bl printk
55 b 1f
56 .asciz KERN_DEBUG "VFP: \str\n"
57 .balign 4
58 1: ldmfd sp!, {r0-r3, ip, lr}
59 #endif
60 .endm
63 @ VFP hardware support entry point.
64 @
65 @ r0 = instruction opcode (32-bit ARM or two 16-bit Thumb)
66 @ r2 = PC value to resume execution after successful emulation
67 @ r9 = normal "successful" return address
68 @ r10 = vfp_state union
69 @ r11 = CPU number
70 @ lr = unrecognised instruction return address
71 @ IRQs enabled.
72 ENTRY(vfp_support_entry)
73 DBGSTR3 "instr %08x pc %08x state %p", r0, r2, r10
75 VFPFMRX r1, FPEXC @ Is the VFP enabled?
76 DBGSTR1 "fpexc %08x", r1
77 tst r1, #FPEXC_EN
78 bne look_for_VFP_exceptions @ VFP is already enabled
80 DBGSTR1 "enable %x", r10
81 ldr r3, vfp_current_hw_state_address
82 orr r1, r1, #FPEXC_EN @ user FPEXC has the enable bit set
83 ldr r4, [r3, r11, lsl #2] @ vfp_current_hw_state pointer
84 bic r5, r1, #FPEXC_EX @ make sure exceptions are disabled
85 cmp r4, r10 @ this thread owns the hw context?
86 #ifndef CONFIG_SMP
87 @ For UP, checking that this thread owns the hw context is
88 @ sufficient to determine that the hardware state is valid.
89 beq vfp_hw_state_valid
91 @ On UP, we lazily save the VFP context. As a different
92 @ thread wants ownership of the VFP hardware, save the old
93 @ state if there was a previous (valid) owner.
95 VFPFMXR FPEXC, r5 @ enable VFP, disable any pending
96 @ exceptions, so we can get at the
97 @ rest of it
99 DBGSTR1 "save old state %p", r4
100 cmp r4, #0 @ if the vfp_current_hw_state is NULL
101 beq vfp_reload_hw @ then the hw state needs reloading
102 VFPFSTMIA r4, r5 @ save the working registers
103 VFPFMRX r5, FPSCR @ current status
104 #ifndef CONFIG_CPU_FEROCEON
105 tst r1, #FPEXC_EX @ is there additional state to save?
106 beq 1f
107 VFPFMRX r6, FPINST @ FPINST (only if FPEXC.EX is set)
108 tst r1, #FPEXC_FP2V @ is there an FPINST2 to read?
109 beq 1f
110 VFPFMRX r8, FPINST2 @ FPINST2 if needed (and present)
111 1:
112 #endif
113 stmia r4, {r1, r5, r6, r8} @ save FPEXC, FPSCR, FPINST, FPINST2
114 vfp_reload_hw:
116 #else
117 @ For SMP, if this thread does not own the hw context, then we
118 @ need to reload it. No need to save the old state as on SMP,
119 @ we always save the state when we switch away from a thread.
120 bne vfp_reload_hw
122 @ This thread has ownership of the current hardware context.
123 @ However, it may have been migrated to another CPU, in which
124 @ case the saved state is newer than the hardware context.
125 @ Check this by looking at the CPU number which the state was
126 @ last loaded onto.
127 ldr ip, [r10, #VFP_CPU]
128 teq ip, r11
129 beq vfp_hw_state_valid
131 vfp_reload_hw:
132 @ We're loading this threads state into the VFP hardware. Update
133 @ the CPU number which contains the most up to date VFP context.
134 str r11, [r10, #VFP_CPU]
136 VFPFMXR FPEXC, r5 @ enable VFP, disable any pending
137 @ exceptions, so we can get at the
138 @ rest of it
139 #endif
141 DBGSTR1 "load state %p", r10
142 str r10, [r3, r11, lsl #2] @ update the vfp_current_hw_state pointer
143 @ Load the saved state back into the VFP
144 VFPFLDMIA r10, r5 @ reload the working registers while
145 @ FPEXC is in a safe state
146 ldmia r10, {r1, r5, r6, r8} @ load FPEXC, FPSCR, FPINST, FPINST2
147 #ifndef CONFIG_CPU_FEROCEON
148 tst r1, #FPEXC_EX @ is there additional state to restore?
149 beq 1f
150 VFPFMXR FPINST, r6 @ restore FPINST (only if FPEXC.EX is set)
151 tst r1, #FPEXC_FP2V @ is there an FPINST2 to write?
152 beq 1f
153 VFPFMXR FPINST2, r8 @ FPINST2 if needed (and present)
154 1:
155 #endif
156 VFPFMXR FPSCR, r5 @ restore status
158 @ The context stored in the VFP hardware is up to date with this thread
159 vfp_hw_state_valid:
160 tst r1, #FPEXC_EX
161 bne process_exception @ might as well handle the pending
162 @ exception before retrying branch
163 @ out before setting an FPEXC that
164 @ stops us reading stuff
165 VFPFMXR FPEXC, r1 @ Restore FPEXC last
166 sub r2, r2, #4 @ Retry current instruction - if Thumb
167 str r2, [sp, #S_PC] @ mode it's two 16-bit instructions,
168 @ else it's one 32-bit instruction, so
169 @ always subtract 4 from the following
170 @ instruction address.
171 #ifdef CONFIG_PREEMPT
172 get_thread_info r10
173 ldr r4, [r10, #TI_PREEMPT] @ get preempt count
174 sub r11, r4, #1 @ decrement it
175 str r11, [r10, #TI_PREEMPT]
176 #endif
177 mov pc, r9 @ we think we have handled things
180 look_for_VFP_exceptions:
181 @ Check for synchronous or asynchronous exception
182 tst r1, #FPEXC_EX | FPEXC_DEX
183 bne process_exception
184 @ On some implementations of the VFP subarch 1, setting FPSCR.IXE
185 @ causes all the CDP instructions to be bounced synchronously without
186 @ setting the FPEXC.EX bit
187 VFPFMRX r5, FPSCR
188 tst r5, #FPSCR_IXE
189 bne process_exception
191 @ Fall into hand on to next handler - appropriate coproc instr
192 @ not recognised by VFP
194 DBGSTR "not VFP"
195 #ifdef CONFIG_PREEMPT
196 get_thread_info r10
197 ldr r4, [r10, #TI_PREEMPT] @ get preempt count
198 sub r11, r4, #1 @ decrement it
199 str r11, [r10, #TI_PREEMPT]
200 #endif
201 mov pc, lr
203 process_exception:
204 DBGSTR "bounce"
205 mov r2, sp @ nothing stacked - regdump is at TOS
206 mov lr, r9 @ setup for a return to the user code.
208 @ Now call the C code to package up the bounce to the support code
209 @ r0 holds the trigger instruction
210 @ r1 holds the FPEXC value
211 @ r2 pointer to register dump
212 b VFP_bounce @ we have handled this - the support
213 @ code will raise an exception if
214 @ required. If not, the user code will
215 @ retry the faulted instruction
216 ENDPROC(vfp_support_entry)
218 ENTRY(vfp_save_state)
219 @ Save the current VFP state
220 @ r0 - save location
221 @ r1 - FPEXC
222 DBGSTR1 "save VFP state %p", r0
223 VFPFSTMIA r0, r2 @ save the working registers
224 VFPFMRX r2, FPSCR @ current status
225 tst r1, #FPEXC_EX @ is there additional state to save?
226 beq 1f
227 VFPFMRX r3, FPINST @ FPINST (only if FPEXC.EX is set)
228 tst r1, #FPEXC_FP2V @ is there an FPINST2 to read?
229 beq 1f
230 VFPFMRX r12, FPINST2 @ FPINST2 if needed (and present)
231 1:
232 stmia r0, {r1, r2, r3, r12} @ save FPEXC, FPSCR, FPINST, FPINST2
233 mov pc, lr
234 ENDPROC(vfp_save_state)
236 .align
237 vfp_current_hw_state_address:
238 .word vfp_current_hw_state
240 .macro tbl_branch, base, tmp, shift
241 #ifdef CONFIG_THUMB2_KERNEL
242 adr \tmp, 1f
243 add \tmp, \tmp, \base, lsl \shift
244 mov pc, \tmp
245 #else
246 add pc, pc, \base, lsl \shift
247 mov r0, r0
248 #endif
249 1:
250 .endm
252 ENTRY(vfp_get_float)
253 tbl_branch r0, r3, #3
254 .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
255 1: mrc p10, 0, r0, c\dr, c0, 0 @ fmrs r0, s0
256 mov pc, lr
257 .org 1b + 8
258 1: mrc p10, 0, r0, c\dr, c0, 4 @ fmrs r0, s1
259 mov pc, lr
260 .org 1b + 8
261 .endr
262 ENDPROC(vfp_get_float)
264 ENTRY(vfp_put_float)
265 tbl_branch r1, r3, #3
266 .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
267 1: mcr p10, 0, r0, c\dr, c0, 0 @ fmsr r0, s0
268 mov pc, lr
269 .org 1b + 8
270 1: mcr p10, 0, r0, c\dr, c0, 4 @ fmsr r0, s1
271 mov pc, lr
272 .org 1b + 8
273 .endr
274 ENDPROC(vfp_put_float)
276 ENTRY(vfp_get_double)
277 tbl_branch r0, r3, #3
278 .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
279 1: fmrrd r0, r1, d\dr
280 mov pc, lr
281 .org 1b + 8
282 .endr
283 #ifdef CONFIG_VFPv3
284 @ d16 - d31 registers
285 .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
286 1: mrrc p11, 3, r0, r1, c\dr @ fmrrd r0, r1, d\dr
287 mov pc, lr
288 .org 1b + 8
289 .endr
290 #endif
292 @ virtual register 16 (or 32 if VFPv3) for compare with zero
293 mov r0, #0
294 mov r1, #0
295 mov pc, lr
296 ENDPROC(vfp_get_double)
298 ENTRY(vfp_put_double)
299 tbl_branch r2, r3, #3
300 .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
301 1: fmdrr d\dr, r0, r1
302 mov pc, lr
303 .org 1b + 8
304 .endr
305 #ifdef CONFIG_VFPv3
306 @ d16 - d31 registers
307 .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
308 1: mcrr p11, 3, r0, r1, c\dr @ fmdrr r0, r1, d\dr
309 mov pc, lr
310 .org 1b + 8
311 .endr
312 #endif
313 ENDPROC(vfp_put_double)