arch/arm/boot/dts/imx6q.dtsi

   1
   2 /*
   3  * Copyright 2013 Freescale Semiconductor, Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  */
  10
  11 #include <dt-bindings/interrupt-controller/irq.h>
  12 #include "imx6q-pinfunc.h"
  13 #include "imx6qdl.dtsi"
  14
  15 / {
  16         aliases {
  17                 ipu1 = &ipu2;
  18                 spi4 = &ecspi5;
  19         };
  20
  21         cpus {
  22                 #address-cells = <1>;
  23                 #size-cells = <0>;
  24
  25                 cpu0: cpu@0 {
  26                         compatible = "arm,cortex-a9";
  27                         device_type = "cpu";
  28                         reg = <0>;
  29                         next-level-cache = <&L2>;
  30                         operating-points = <
  31                                 /* kHz    uV */
  32                                 1200000 1275000
  33                                 996000  1250000
  34                                 852000  1250000
  35                                 792000  1175000
  36                                 396000  975000
  37                         >;
  38                         fsl,soc-operating-points = <
  39                                 /* ARM kHz  SOC-PU uV */
  40                                 1200000 1275000
  41                                 996000  1250000
  42                                 852000  1250000
  43                                 792000  1175000
  44                                 396000  1175000
  45                         >;
  46                         clock-latency = <61036>; /* two CLK32 periods */
  47                         clocks = <&clks IMX6QDL_CLK_ARM>,
  48                                  <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
  49                                  <&clks IMX6QDL_CLK_STEP>,
  50                                  <&clks IMX6QDL_CLK_PLL1_SW>,
  51                                  <&clks IMX6QDL_CLK_PLL1_SYS>;
  52                         clock-names = "arm", "pll2_pfd2_396m", "step",
  53                                       "pll1_sw", "pll1_sys";
  54                         arm-supply = <&reg_arm>;
  55                         pu-supply = <&reg_pu>;
  56                         soc-supply = <&reg_soc>;
  57                 };
  58
  59                 cpu@1 {
  60                         compatible = "arm,cortex-a9";
  61                         device_type = "cpu";
  62                         reg = <1>;
  63                         next-level-cache = <&L2>;
  64                 };
  65
  66                 cpu@2 {
  67                         compatible = "arm,cortex-a9";
  68                         device_type = "cpu";
  69                         reg = <2>;
  70                         next-level-cache = <&L2>;
  71                 };
  72
  73                 cpu@3 {
  74                         compatible = "arm,cortex-a9";
  75                         device_type = "cpu";
  76                         reg = <3>;
  77                         next-level-cache = <&L2>;
  78                 };
  79         };
  80
  81         soc {
  82                 ocram: sram@00900000 {
  83                         compatible = "mmio-sram";
  84                         reg = <0x00900000 0x40000>;
  85                         clocks = <&clks IMX6QDL_CLK_OCRAM>;
  86                 };
  87
  88                 aips-bus@02000000 { /* AIPS1 */
  89                         spba-bus@02000000 {
  90                                 ecspi5: ecspi@02018000 {
  91                                         #address-cells = <1>;
  92                                         #size-cells = <0>;
  93                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
  94                                         reg = <0x02018000 0x4000>;
  95                                         interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
  96                                         clocks = <&clks IMX6Q_CLK_ECSPI5>,
  97                                                  <&clks IMX6Q_CLK_ECSPI5>;
  98                                         clock-names = "ipg", "per";
  99                                         dmas = <&sdma 11 7 1>, <&sdma 12 7 2>;
 100                                         dma-names = "rx", "tx";
 101                                         status = "disabled";
 102                                 };
 103                         };
 104
 105                         iomuxc: iomuxc@020e0000 {
 106                                 compatible = "fsl,imx6q-iomuxc";
 107                         };
 108                 };
 109
 110                 sata: sata@02200000 {
 111                         compatible = "fsl,imx6q-ahci";
 112                         reg = <0x02200000 0x4000>;
 113                         interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
 114                         clocks = <&clks IMX6QDL_CLK_SATA>,
 115                                  <&clks IMX6QDL_CLK_SATA_REF_100M>,
 116                                  <&clks IMX6QDL_CLK_AHB>;
 117                         clock-names = "sata", "sata_ref", "ahb";
 118                         status = "disabled";
 119                 };
 120
 121                 gpu_vg: gpu@02204000 {
 122                         compatible = "vivante,gc";
 123                         reg = <0x02204000 0x4000>;
 124                         interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
 125                         clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>,
 126                                  <&clks IMX6QDL_CLK_GPU2D_CORE>;
 127                         clock-names = "bus", "core";
 128                         power-domains = <&pd_pu>;
 129                 };
 130
 131                 ipu2: ipu@02800000 {
 132                         #address-cells = <1>;
 133                         #size-cells = <0>;
 134                         compatible = "fsl,imx6q-ipu";
 135                         reg = <0x02800000 0x400000>;
 136                         interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
 137                                      <0 7 IRQ_TYPE_LEVEL_HIGH>;
 138                         clocks = <&clks IMX6QDL_CLK_IPU2>,
 139                                  <&clks IMX6QDL_CLK_IPU2_DI0>,
 140                                  <&clks IMX6QDL_CLK_IPU2_DI1>;
 141                         clock-names = "bus", "di0", "di1";
 142                         resets = <&src 4>;
 143
 144                         ipu2_csi0: port@0 {
 145                                 reg = <0>;
 146
 147                                 ipu2_csi0_from_mipi_vc2: endpoint {
 148                                         remote-endpoint = <&mipi_vc2_to_ipu2_csi0>;
 149                                 };
 150                         };
 151
 152                         ipu2_csi1: port@1 {
 153                                 reg = <1>;
 154
 155                                 ipu2_csi1_from_ipu2_csi1_mux: endpoint {
 156                                         remote-endpoint = <&ipu2_csi1_mux_to_ipu2_csi1>;
 157                                 };
 158                         };
 159
 160                         ipu2_di0: port@2 {
 161                                 #address-cells = <1>;
 162                                 #size-cells = <0>;
 163                                 reg = <2>;
 164
 165                                 ipu2_di0_disp0: disp0-endpoint {
 166                                 };
 167
 168                                 ipu2_di0_hdmi: hdmi-endpoint {
 169                                         remote-endpoint = <&hdmi_mux_2>;
 170                                 };
 171
 172                                 ipu2_di0_mipi: mipi-endpoint {
 173                                         remote-endpoint = <&mipi_mux_2>;
 174                                 };
 175
 176                                 ipu2_di0_lvds0: lvds0-endpoint {
 177                                         remote-endpoint = <&lvds0_mux_2>;
 178                                 };
 179
 180                                 ipu2_di0_lvds1: lvds1-endpoint {
 181                                         remote-endpoint = <&lvds1_mux_2>;
 182                                 };
 183                         };
 184
 185                         ipu2_di1: port@3 {
 186                                 #address-cells = <1>;
 187                                 #size-cells = <0>;
 188                                 reg = <3>;
 189
 190                                 ipu2_di1_hdmi: hdmi-endpoint {
 191                                         remote-endpoint = <&hdmi_mux_3>;
 192                                 };
 193
 194                                 ipu2_di1_mipi: mipi-endpoint {
 195                                         remote-endpoint = <&mipi_mux_3>;
 196                                 };
 197
 198                                 ipu2_di1_lvds0: lvds0-endpoint {
 199                                         remote-endpoint = <&lvds0_mux_3>;
 200                                 };
 201
 202                                 ipu2_di1_lvds1: lvds1-endpoint {
 203                                         remote-endpoint = <&lvds1_mux_3>;
 204                                 };
 205                         };
 206                 };
 207         };
 208
 209         capture-subsystem {
 210                 compatible = "fsl,imx-capture-subsystem";
 211                 ports = <&ipu1_csi0>, <&ipu1_csi1>, <&ipu2_csi0>, <&ipu2_csi1>;
 212         };
 213
 214         display-subsystem {
 215                 compatible = "fsl,imx-display-subsystem";
 216                 ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
 217         };
 218
 219         gpu-subsystem {
 220                 compatible = "fsl,imx-gpu-subsystem";
 221                 cores = <&gpu_2d>, <&gpu_3d>, <&gpu_vg>;
 222         };
 223 };
 224
 225 &gpio1 {
 226         gpio-ranges = <&iomuxc  0 136  2>, <&iomuxc  2 141 1>, <&iomuxc  3 139 1>,
 227                       <&iomuxc  4 142  2>, <&iomuxc  6 140 1>, <&iomuxc  7 144 2>,
 228                       <&iomuxc  9 138  1>, <&iomuxc 10 213 3>, <&iomuxc 13  20 1>,
 229                       <&iomuxc 14  19  1>, <&iomuxc 15  21 1>, <&iomuxc 16 208 1>,
 230                       <&iomuxc 17 207  1>, <&iomuxc 18 210 3>, <&iomuxc 21 209 1>,
 231                       <&iomuxc 22 116 10>;
 232 };
 233
 234 &gpio2 {
 235         gpio-ranges = <&iomuxc  0 191 16>, <&iomuxc 16 55 14>, <&iomuxc 30 35 1>,
 236                       <&iomuxc 31  44  1>;
 237 };
 238
 239 &gpio3 {
 240         gpio-ranges = <&iomuxc 0 69 16>, <&iomuxc 16 36 8>, <&iomuxc 24 45 8>;
 241 };
 242
 243 &gpio4 {
 244         gpio-ranges = <&iomuxc 5 149 1>, <&iomuxc 6 126 10>, <&iomuxc 16 87 16>;
 245 };
 246
 247 &gpio5 {
 248         gpio-ranges = <&iomuxc 0  85  1>, <&iomuxc  2  34  1>, <&iomuxc 4 53 1>,
 249                       <&iomuxc 5 103 13>, <&iomuxc 18 150 14>;
 250 };
 251
 252 &gpio6 {
 253         gpio-ranges = <&iomuxc  0 164 6>, <&iomuxc  6  54 1>, <&iomuxc  7 181  5>,
 254                       <&iomuxc 14 186 3>, <&iomuxc 17 170 2>, <&iomuxc 19  22 12>,
 255                       <&iomuxc 31  86 1>;
 256 };
 257
 258 &gpio7 {
 259         gpio-ranges = <&iomuxc 0 172 9>, <&iomuxc 9 189 2>, <&iomuxc 11 146 3>;
 260 };
 261
 262 &gpr {
 263         ipu1_csi0_mux {
 264                 compatible = "video-mux";
 265                 mux-controls = <&mux 0>;
 266                 #address-cells = <1>;
 267                 #size-cells = <0>;
 268
 269                 port@0 {
 270                         reg = <0>;
 271
 272                         ipu1_csi0_mux_from_mipi_vc0: endpoint {
 273                                 remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
 274                         };
 275                 };
 276
 277                 port@1 {
 278                         reg = <1>;
 279
 280                         ipu1_csi0_mux_from_parallel_sensor: endpoint {
 281                         };
 282                 };
 283
 284                 port@2 {
 285                         reg = <2>;
 286
 287                         ipu1_csi0_mux_to_ipu1_csi0: endpoint {
 288                                 remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
 289                         };
 290                 };
 291         };
 292
 293         ipu2_csi1_mux {
 294                 compatible = "video-mux";
 295                 mux-controls = <&mux 1>;
 296                 #address-cells = <1>;
 297                 #size-cells = <0>;
 298
 299                 port@0 {
 300                         reg = <0>;
 301
 302                         ipu2_csi1_mux_from_mipi_vc3: endpoint {
 303                                 remote-endpoint = <&mipi_vc3_to_ipu2_csi1_mux>;
 304                         };
 305                 };
 306
 307                 port@1 {
 308                         reg = <1>;
 309
 310                         ipu2_csi1_mux_from_parallel_sensor: endpoint {
 311                         };
 312                 };
 313
 314                 port@2 {
 315                         reg = <2>;
 316
 317                         ipu2_csi1_mux_to_ipu2_csi1: endpoint {
 318                                 remote-endpoint = <&ipu2_csi1_from_ipu2_csi1_mux>;
 319                         };
 320                 };
 321         };
 322 };
 323
 324 &hdmi {
 325         compatible = "fsl,imx6q-hdmi";
 326
 327         port@2 {
 328                 reg = <2>;
 329
 330                 hdmi_mux_2: endpoint {
 331                         remote-endpoint = <&ipu2_di0_hdmi>;
 332                 };
 333         };
 334
 335         port@3 {
 336                 reg = <3>;
 337
 338                 hdmi_mux_3: endpoint {
 339                         remote-endpoint = <&ipu2_di1_hdmi>;
 340                 };
 341         };
 342 };
 343
 344 &ipu1_csi1 {
 345         ipu1_csi1_from_mipi_vc1: endpoint {
 346                 remote-endpoint = <&mipi_vc1_to_ipu1_csi1>;
 347         };
 348 };
 349
 350 &ldb {
 351         clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
 352                  <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
 353                  <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
 354                  <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
 355         clock-names = "di0_pll", "di1_pll",
 356                       "di0_sel", "di1_sel", "di2_sel", "di3_sel",
 357                       "di0", "di1";
 358
 359         lvds-channel@0 {
 360                 port@2 {
 361                         reg = <2>;
 362
 363                         lvds0_mux_2: endpoint {
 364                                 remote-endpoint = <&ipu2_di0_lvds0>;
 365                         };
 366                 };
 367
 368                 port@3 {
 369                         reg = <3>;
 370
 371                         lvds0_mux_3: endpoint {
 372                                 remote-endpoint = <&ipu2_di1_lvds0>;
 373                         };
 374                 };
 375         };
 376
 377         lvds-channel@1 {
 378                 port@2 {
 379                         reg = <2>;
 380
 381                         lvds1_mux_2: endpoint {
 382                                 remote-endpoint = <&ipu2_di0_lvds1>;
 383                         };
 384                 };
 385
 386                 port@3 {
 387                         reg = <3>;
 388
 389                         lvds1_mux_3: endpoint {
 390                                 remote-endpoint = <&ipu2_di1_lvds1>;
 391                         };
 392                 };
 393         };
 394 };
 395
 396 &mipi_csi {
 397         port@1 {
 398                 reg = <1>;
 399
 400                 mipi_vc0_to_ipu1_csi0_mux: endpoint {
 401                         remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
 402                 };
 403         };
 404
 405         port@2 {
 406                 reg = <2>;
 407
 408                 mipi_vc1_to_ipu1_csi1: endpoint {
 409                         remote-endpoint = <&ipu1_csi1_from_mipi_vc1>;
 410                 };
 411         };
 412
 413         port@3 {
 414                 reg = <3>;
 415
 416                 mipi_vc2_to_ipu2_csi0: endpoint {
 417                         remote-endpoint = <&ipu2_csi0_from_mipi_vc2>;
 418                 };
 419         };
 420
 421         port@4 {
 422                 reg = <4>;
 423
 424                 mipi_vc3_to_ipu2_csi1_mux: endpoint {
 425                         remote-endpoint = <&ipu2_csi1_mux_from_mipi_vc3>;
 426                 };
 427         };
 428 };
 429
 430 &mipi_dsi {
 431         ports {
 432                 port@2 {
 433                         reg = <2>;
 434
 435                         mipi_mux_2: endpoint {
 436                                 remote-endpoint = <&ipu2_di0_mipi>;
 437                         };
 438                 };
 439
 440                 port@3 {
 441                         reg = <3>;
 442
 443                         mipi_mux_3: endpoint {
 444                                 remote-endpoint = <&ipu2_di1_mipi>;
 445                         };
 446                 };
 447         };
 448 };
 449
 450 &mux {
 451         mux-reg-masks = <0x04 0x00080000>, /* MIPI_IPU1_MUX */
 452                         <0x04 0x00100000>, /* MIPI_IPU2_MUX */
 453                         <0x0c 0x0000000c>, /* HDMI_MUX_CTL */
 454                         <0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
 455                         <0x0c 0x00000300>, /* LVDS1_MUX_CTL */
 456                         <0x28 0x00000003>, /* DCIC1_MUX_CTL */
 457                         <0x28 0x0000000c>; /* DCIC2_MUX_CTL */
 458 };
 459
 460 &vpu {
 461         compatible = "fsl,imx6q-vpu", "cnm,coda960";
 462 };