arch/arm/boot/dts/rk3066a.dtsi

   1 /*
   2  * Copyright (c) 2013 MundoReader S.L.
   3  * Author: Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * This file is dual-licensed: you can use it either under the terms
   6  * of the GPL or the X11 license, at your option. Note that this dual
   7  * licensing only applies to this file, and not this project as a
   8  * whole.
   9  *
  10  *  a) This file is free software; you can redistribute it and/or
  11  *     modify it under the terms of the GNU General Public License as
  12  *     published by the Free Software Foundation; either version 2 of the
  13  *     License, or (at your option) any later version.
  14  *
  15  *     This file is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  * Or, alternatively,
  21  *
  22  *  b) Permission is hereby granted, free of charge, to any person
  23  *     obtaining a copy of this software and associated documentation
  24  *     files (the "Software"), to deal in the Software without
  25  *     restriction, including without limitation the rights to use,
  26  *     copy, modify, merge, publish, distribute, sublicense, and/or
  27  *     sell copies of the Software, and to permit persons to whom the
  28  *     Software is furnished to do so, subject to the following
  29  *     conditions:
  30  *
  31  *     The above copyright notice and this permission notice shall be
  32  *     included in all copies or substantial portions of the Software.
  33  *
  34  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  36  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  38  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  40  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  41  *     OTHER DEALINGS IN THE SOFTWARE.
  42  */
  43
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/pinctrl/rockchip.h>
  46 #include <dt-bindings/clock/rk3066a-cru.h>
  47 #include "rk3xxx.dtsi"
  48
  49 / {
  50         compatible = "rockchip,rk3066a";
  51
  52         cpus {
  53                 #address-cells = <1>;
  54                 #size-cells = <0>;
  55                 enable-method = "rockchip,rk3066-smp";
  56
  57                 cpu0: cpu@0 {
  58                         device_type = "cpu";
  59                         compatible = "arm,cortex-a9";
  60                         next-level-cache = <&L2>;
  61                         reg = <0x0>;
  62                         operating-points = <
  63                                 /* kHz    uV */
  64                                 1416000 1300000
  65                                 1200000 1175000
  66                                 1008000 1125000
  67                                 816000  1125000
  68                                 600000  1100000
  69                                 504000  1100000
  70                                 312000  1075000
  71                         >;
  72                         clock-latency = <40000>;
  73                         clocks = <&cru ARMCLK>;
  74                 };
  75                 cpu@1 {
  76                         device_type = "cpu";
  77                         compatible = "arm,cortex-a9";
  78                         next-level-cache = <&L2>;
  79                         reg = <0x1>;
  80                 };
  81         };
  82
  83         sram: sram@10080000 {
  84                 compatible = "mmio-sram";
  85                 reg = <0x10080000 0x10000>;
  86                 #address-cells = <1>;
  87                 #size-cells = <1>;
  88                 ranges = <0 0x10080000 0x10000>;
  89
  90                 smp-sram@0 {
  91                         compatible = "rockchip,rk3066-smp-sram";
  92                         reg = <0x0 0x50>;
  93                 };
  94         };
  95
  96         i2s0: i2s@10118000 {
  97                 compatible = "rockchip,rk3066-i2s";
  98                 reg = <0x10118000 0x2000>;
  99                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 100                 #address-cells = <1>;
 101                 #size-cells = <0>;
 102                 pinctrl-names = "default";
 103                 pinctrl-0 = <&i2s0_bus>;
 104                 dmas = <&dmac1_s 4>, <&dmac1_s 5>;
 105                 dma-names = "tx", "rx";
 106                 clock-names = "i2s_hclk", "i2s_clk";
 107                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
 108                 rockchip,playback-channels = <8>;
 109                 rockchip,capture-channels = <2>;
 110                 status = "disabled";
 111         };
 112
 113         i2s1: i2s@1011a000 {
 114                 compatible = "rockchip,rk3066-i2s";
 115                 reg = <0x1011a000 0x2000>;
 116                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 117                 #address-cells = <1>;
 118                 #size-cells = <0>;
 119                 pinctrl-names = "default";
 120                 pinctrl-0 = <&i2s1_bus>;
 121                 dmas = <&dmac1_s 6>, <&dmac1_s 7>;
 122                 dma-names = "tx", "rx";
 123                 clock-names = "i2s_hclk", "i2s_clk";
 124                 clocks = <&cru HCLK_I2S1>, <&cru SCLK_I2S1>;
 125                 rockchip,playback-channels = <2>;
 126                 rockchip,capture-channels = <2>;
 127                 status = "disabled";
 128         };
 129
 130         i2s2: i2s@1011c000 {
 131                 compatible = "rockchip,rk3066-i2s";
 132                 reg = <0x1011c000 0x2000>;
 133                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 134                 #address-cells = <1>;
 135                 #size-cells = <0>;
 136                 pinctrl-names = "default";
 137                 pinctrl-0 = <&i2s2_bus>;
 138                 dmas = <&dmac1_s 9>, <&dmac1_s 10>;
 139                 dma-names = "tx", "rx";
 140                 clock-names = "i2s_hclk", "i2s_clk";
 141                 clocks = <&cru HCLK_I2S2>, <&cru SCLK_I2S2>;
 142                 rockchip,playback-channels = <2>;
 143                 rockchip,capture-channels = <2>;
 144                 status = "disabled";
 145         };
 146
 147         cru: clock-controller@20000000 {
 148                 compatible = "rockchip,rk3066a-cru";
 149                 reg = <0x20000000 0x1000>;
 150                 rockchip,grf = <&grf>;
 151
 152                 #clock-cells = <1>;
 153                 #reset-cells = <1>;
 154                 assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>,
 155                                   <&cru ACLK_CPU>, <&cru HCLK_CPU>,
 156                                   <&cru PCLK_CPU>, <&cru ACLK_PERI>,
 157                                   <&cru HCLK_PERI>, <&cru PCLK_PERI>;
 158                 assigned-clock-rates = <400000000>, <594000000>,
 159                                        <300000000>, <150000000>,
 160                                        <75000000>, <300000000>,
 161                                        <150000000>, <75000000>;
 162         };
 163
 164         timer@2000e000 {
 165                 compatible = "snps,dw-apb-timer-osc";
 166                 reg = <0x2000e000 0x100>;
 167                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 168                 clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
 169                 clock-names = "timer", "pclk";
 170         };
 171
 172         efuse: efuse@20010000 {
 173                 compatible = "rockchip,rk3066a-efuse";
 174                 reg = <0x20010000 0x4000>;
 175                 #address-cells = <1>;
 176                 #size-cells = <1>;
 177                 clocks = <&cru PCLK_EFUSE>;
 178                 clock-names = "pclk_efuse";
 179
 180                 cpu_leakage: cpu_leakage@17 {
 181                         reg = <0x17 0x1>;
 182                 };
 183         };
 184
 185         timer@20038000 {
 186                 compatible = "snps,dw-apb-timer-osc";
 187                 reg = <0x20038000 0x100>;
 188                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 189                 clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
 190                 clock-names = "timer", "pclk";
 191         };
 192
 193         timer@2003a000 {
 194                 compatible = "snps,dw-apb-timer-osc";
 195                 reg = <0x2003a000 0x100>;
 196                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 197                 clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
 198                 clock-names = "timer", "pclk";
 199         };
 200
 201         tsadc: tsadc@20060000 {
 202                 compatible = "rockchip,rk3066-tsadc";
 203                 reg = <0x20060000 0x100>;
 204                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 205                 clock-names = "saradc", "apb_pclk";
 206                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 207                 #io-channel-cells = <1>;
 208                 resets = <&cru SRST_TSADC>;
 209                 reset-names = "saradc-apb";
 210                 status = "disabled";
 211         };
 212
 213         usbphy: phy {
 214                 compatible = "rockchip,rk3066a-usb-phy", "rockchip,rk3288-usb-phy";
 215                 rockchip,grf = <&grf>;
 216                 #address-cells = <1>;
 217                 #size-cells = <0>;
 218                 status = "disabled";
 219
 220                 usbphy0: usb-phy@17c {
 221                         #phy-cells = <0>;
 222                         reg = <0x17c>;
 223                         clocks = <&cru SCLK_OTGPHY0>;
 224                         clock-names = "phyclk";
 225                         #clock-cells = <0>;
 226                 };
 227
 228                 usbphy1: usb-phy@188 {
 229                         #phy-cells = <0>;
 230                         reg = <0x188>;
 231                         clocks = <&cru SCLK_OTGPHY1>;
 232                         clock-names = "phyclk";
 233                         #clock-cells = <0>;
 234                 };
 235         };
 236
 237         pinctrl: pinctrl {
 238                 compatible = "rockchip,rk3066a-pinctrl";
 239                 rockchip,grf = <&grf>;
 240                 #address-cells = <1>;
 241                 #size-cells = <1>;
 242                 ranges;
 243
 244                 gpio0: gpio0@20034000 {
 245                         compatible = "rockchip,gpio-bank";
 246                         reg = <0x20034000 0x100>;
 247                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 248                         clocks = <&cru PCLK_GPIO0>;
 249
 250                         gpio-controller;
 251                         #gpio-cells = <2>;
 252
 253                         interrupt-controller;
 254                         #interrupt-cells = <2>;
 255                 };
 256
 257                 gpio1: gpio1@2003c000 {
 258                         compatible = "rockchip,gpio-bank";
 259                         reg = <0x2003c000 0x100>;
 260                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 261                         clocks = <&cru PCLK_GPIO1>;
 262
 263                         gpio-controller;
 264                         #gpio-cells = <2>;
 265
 266                         interrupt-controller;
 267                         #interrupt-cells = <2>;
 268                 };
 269
 270                 gpio2: gpio2@2003e000 {
 271                         compatible = "rockchip,gpio-bank";
 272                         reg = <0x2003e000 0x100>;
 273                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 274                         clocks = <&cru PCLK_GPIO2>;
 275
 276                         gpio-controller;
 277                         #gpio-cells = <2>;
 278
 279                         interrupt-controller;
 280                         #interrupt-cells = <2>;
 281                 };
 282
 283                 gpio3: gpio3@20080000 {
 284                         compatible = "rockchip,gpio-bank";
 285                         reg = <0x20080000 0x100>;
 286                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 287                         clocks = <&cru PCLK_GPIO3>;
 288
 289                         gpio-controller;
 290                         #gpio-cells = <2>;
 291
 292                         interrupt-controller;
 293                         #interrupt-cells = <2>;
 294                 };
 295
 296                 gpio4: gpio4@20084000 {
 297                         compatible = "rockchip,gpio-bank";
 298                         reg = <0x20084000 0x100>;
 299                         interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 300                         clocks = <&cru PCLK_GPIO4>;
 301
 302                         gpio-controller;
 303                         #gpio-cells = <2>;
 304
 305                         interrupt-controller;
 306                         #interrupt-cells = <2>;
 307                 };
 308
 309                 gpio6: gpio6@2000a000 {
 310                         compatible = "rockchip,gpio-bank";
 311                         reg = <0x2000a000 0x100>;
 312                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 313                         clocks = <&cru PCLK_GPIO6>;
 314
 315                         gpio-controller;
 316                         #gpio-cells = <2>;
 317
 318                         interrupt-controller;
 319                         #interrupt-cells = <2>;
 320                 };
 321
 322                 pcfg_pull_default: pcfg_pull_default {
 323                         bias-pull-pin-default;
 324                 };
 325
 326                 pcfg_pull_none: pcfg_pull_none {
 327                         bias-disable;
 328                 };
 329
 330                 emac {
 331                         emac_xfer: emac-xfer {
 332                                 rockchip,pins = <RK_GPIO1 16 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
 333                                                 <RK_GPIO1 17 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
 334                                                 <RK_GPIO1 18 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
 335                                                 <RK_GPIO1 19 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
 336                                                 <RK_GPIO1 20 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
 337                                                 <RK_GPIO1 21 RK_FUNC_2 &pcfg_pull_none>, /* crs_dvalid */
 338                                                 <RK_GPIO1 22 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
 339                                                 <RK_GPIO1 23 RK_FUNC_2 &pcfg_pull_none>; /* rxd0 */
 340                         };
 341
 342                         emac_mdio: emac-mdio {
 343                                 rockchip,pins = <RK_GPIO1 24 RK_FUNC_2 &pcfg_pull_none>, /* mac_md */
 344                                                 <RK_GPIO1 25 RK_FUNC_2 &pcfg_pull_none>; /* mac_mdclk */
 345                         };
 346                 };
 347
 348                 emmc {
 349                         emmc_clk: emmc-clk {
 350                                 rockchip,pins = <RK_GPIO3 31 RK_FUNC_2 &pcfg_pull_default>;
 351                         };
 352
 353                         emmc_cmd: emmc-cmd {
 354                                 rockchip,pins = <RK_GPIO4 9 RK_FUNC_2 &pcfg_pull_default>;
 355                         };
 356
 357                         emmc_rst: emmc-rst {
 358                                 rockchip,pins = <RK_GPIO4 10 RK_FUNC_2 &pcfg_pull_default>;
 359                         };
 360
 361                         /*
 362                          * The data pins are shared between nandc and emmc and
 363                          * not accessible through pinctrl. Also they should've
 364                          * been already set correctly by firmware, as
 365                          * flash/emmc is the boot-device.
 366                          */
 367                 };
 368
 369                 i2c0 {
 370                         i2c0_xfer: i2c0-xfer {
 371                                 rockchip,pins = <RK_GPIO2 28 RK_FUNC_1 &pcfg_pull_none>,
 372                                                 <RK_GPIO2 29 RK_FUNC_1 &pcfg_pull_none>;
 373                         };
 374                 };
 375
 376                 i2c1 {
 377                         i2c1_xfer: i2c1-xfer {
 378                                 rockchip,pins = <RK_GPIO2 30 RK_FUNC_1 &pcfg_pull_none>,
 379                                                 <RK_GPIO2 31 RK_FUNC_1 &pcfg_pull_none>;
 380                         };
 381                 };
 382
 383                 i2c2 {
 384                         i2c2_xfer: i2c2-xfer {
 385                                 rockchip,pins = <RK_GPIO3 0 RK_FUNC_1 &pcfg_pull_none>,
 386                                                 <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
 387                         };
 388                 };
 389
 390                 i2c3 {
 391                         i2c3_xfer: i2c3-xfer {
 392                                 rockchip,pins = <RK_GPIO3 2 RK_FUNC_2 &pcfg_pull_none>,
 393                                                 <RK_GPIO3 3 RK_FUNC_2 &pcfg_pull_none>;
 394                         };
 395                 };
 396
 397                 i2c4 {
 398                         i2c4_xfer: i2c4-xfer {
 399                                 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
 400                                                 <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>;
 401                         };
 402                 };
 403
 404                 pwm0 {
 405                         pwm0_out: pwm0-out {
 406                                 rockchip,pins = <RK_GPIO0 3 RK_FUNC_1 &pcfg_pull_none>;
 407                         };
 408                 };
 409
 410                 pwm1 {
 411                         pwm1_out: pwm1-out {
 412                                 rockchip,pins = <RK_GPIO0 4 RK_FUNC_1 &pcfg_pull_none>;
 413                         };
 414                 };
 415
 416                 pwm2 {
 417                         pwm2_out: pwm2-out {
 418                                 rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_none>;
 419                         };
 420                 };
 421
 422                 pwm3 {
 423                         pwm3_out: pwm3-out {
 424                                 rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_none>;
 425                         };
 426                 };
 427
 428                 spi0 {
 429                         spi0_clk: spi0-clk {
 430                                 rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_default>;
 431                         };
 432                         spi0_cs0: spi0-cs0 {
 433                                 rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_default>;
 434                         };
 435                         spi0_tx: spi0-tx {
 436                                 rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_default>;
 437                         };
 438                         spi0_rx: spi0-rx {
 439                                 rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_default>;
 440                         };
 441                         spi0_cs1: spi0-cs1 {
 442                                 rockchip,pins = <RK_GPIO4 15 RK_FUNC_1 &pcfg_pull_default>;
 443                         };
 444                 };
 445
 446                 spi1 {
 447                         spi1_clk: spi1-clk {
 448                                 rockchip,pins = <RK_GPIO2 19 RK_FUNC_2 &pcfg_pull_default>;
 449                         };
 450                         spi1_cs0: spi1-cs0 {
 451                                 rockchip,pins = <RK_GPIO2 20 RK_FUNC_2 &pcfg_pull_default>;
 452                         };
 453                         spi1_rx: spi1-rx {
 454                                 rockchip,pins = <RK_GPIO2 22 RK_FUNC_2 &pcfg_pull_default>;
 455                         };
 456                         spi1_tx: spi1-tx {
 457                                 rockchip,pins = <RK_GPIO2 21 RK_FUNC_2 &pcfg_pull_default>;
 458                         };
 459                         spi1_cs1: spi1-cs1 {
 460                                 rockchip,pins = <RK_GPIO2 23 RK_FUNC_2 &pcfg_pull_default>;
 461                         };
 462                 };
 463
 464                 uart0 {
 465                         uart0_xfer: uart0-xfer {
 466                                 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
 467                                                 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>;
 468                         };
 469
 470                         uart0_cts: uart0-cts {
 471                                 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>;
 472                         };
 473
 474                         uart0_rts: uart0-rts {
 475                                 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>;
 476                         };
 477                 };
 478
 479                 uart1 {
 480                         uart1_xfer: uart1-xfer {
 481                                 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>,
 482                                                 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>;
 483                         };
 484
 485                         uart1_cts: uart1-cts {
 486                                 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>;
 487                         };
 488
 489                         uart1_rts: uart1-rts {
 490                                 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>;
 491                         };
 492                 };
 493
 494                 uart2 {
 495                         uart2_xfer: uart2-xfer {
 496                                 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>,
 497                                                 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>;
 498                         };
 499                         /* no rts / cts for uart2 */
 500                 };
 501
 502                 uart3 {
 503                         uart3_xfer: uart3-xfer {
 504                                 rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>,
 505                                                 <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>;
 506                         };
 507
 508                         uart3_cts: uart3-cts {
 509                                 rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>;
 510                         };
 511
 512                         uart3_rts: uart3-rts {
 513                                 rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>;
 514                         };
 515                 };
 516
 517                 sd0 {
 518                         sd0_clk: sd0-clk {
 519                                 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>;
 520                         };
 521
 522                         sd0_cmd: sd0-cmd {
 523                                 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>;
 524                         };
 525
 526                         sd0_cd: sd0-cd {
 527                                 rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>;
 528                         };
 529
 530                         sd0_wp: sd0-wp {
 531                                 rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>;
 532                         };
 533
 534                         sd0_bus1: sd0-bus-width1 {
 535                                 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>;
 536                         };
 537
 538                         sd0_bus4: sd0-bus-width4 {
 539                                 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>,
 540                                                 <RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>,
 541                                                 <RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>,
 542                                                 <RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>;
 543                         };
 544                 };
 545
 546                 sd1 {
 547                         sd1_clk: sd1-clk {
 548                                 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>;
 549                         };
 550
 551                         sd1_cmd: sd1-cmd {
 552                                 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>;
 553                         };
 554
 555                         sd1_cd: sd1-cd {
 556                                 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>;
 557                         };
 558
 559                         sd1_wp: sd1-wp {
 560                                 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>;
 561                         };
 562
 563                         sd1_bus1: sd1-bus-width1 {
 564                                 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>;
 565                         };
 566
 567                         sd1_bus4: sd1-bus-width4 {
 568                                 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>,
 569                                                 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>,
 570                                                 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>,
 571                                                 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
 572                         };
 573                 };
 574
 575                 i2s0 {
 576                         i2s0_bus: i2s0-bus {
 577                                 rockchip,pins = <RK_GPIO0 7 RK_FUNC_1 &pcfg_pull_default>,
 578                                                 <RK_GPIO0 8 RK_FUNC_1 &pcfg_pull_default>,
 579                                                 <RK_GPIO0 9 RK_FUNC_1 &pcfg_pull_default>,
 580                                                 <RK_GPIO0 10 RK_FUNC_1 &pcfg_pull_default>,
 581                                                 <RK_GPIO0 11 RK_FUNC_1 &pcfg_pull_default>,
 582                                                 <RK_GPIO0 12 RK_FUNC_1 &pcfg_pull_default>,
 583                                                 <RK_GPIO0 13 RK_FUNC_1 &pcfg_pull_default>,
 584                                                 <RK_GPIO0 14 RK_FUNC_1 &pcfg_pull_default>,
 585                                                 <RK_GPIO0 15 RK_FUNC_1 &pcfg_pull_default>;
 586                         };
 587                 };
 588
 589                 i2s1 {
 590                         i2s1_bus: i2s1-bus {
 591                                 rockchip,pins = <RK_GPIO0 16 RK_FUNC_1 &pcfg_pull_default>,
 592                                                 <RK_GPIO0 17 RK_FUNC_1 &pcfg_pull_default>,
 593                                                 <RK_GPIO0 18 RK_FUNC_1 &pcfg_pull_default>,
 594                                                 <RK_GPIO0 19 RK_FUNC_1 &pcfg_pull_default>,
 595                                                 <RK_GPIO0 20 RK_FUNC_1 &pcfg_pull_default>,
 596                                                 <RK_GPIO0 21 RK_FUNC_1 &pcfg_pull_default>;
 597                         };
 598                 };
 599
 600                 i2s2 {
 601                         i2s2_bus: i2s2-bus {
 602                                 rockchip,pins = <RK_GPIO0 24 RK_FUNC_1 &pcfg_pull_default>,
 603                                                 <RK_GPIO0 25 RK_FUNC_1 &pcfg_pull_default>,
 604                                                 <RK_GPIO0 26 RK_FUNC_1 &pcfg_pull_default>,
 605                                                 <RK_GPIO0 27 RK_FUNC_1 &pcfg_pull_default>,
 606                                                 <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_default>,
 607                                                 <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_default>;
 608                         };
 609                 };
 610         };
 611 };
 612
 613 &i2c0 {
 614         pinctrl-names = "default";
 615         pinctrl-0 = <&i2c0_xfer>;
 616 };
 617
 618 &i2c1 {
 619         pinctrl-names = "default";
 620         pinctrl-0 = <&i2c1_xfer>;
 621 };
 622
 623 &i2c2 {
 624         pinctrl-names = "default";
 625         pinctrl-0 = <&i2c2_xfer>;
 626 };
 627
 628 &i2c3 {
 629         pinctrl-names = "default";
 630         pinctrl-0 = <&i2c3_xfer>;
 631 };
 632
 633 &i2c4 {
 634         pinctrl-names = "default";
 635         pinctrl-0 = <&i2c4_xfer>;
 636 };
 637
 638 &mmc0 {
 639         clock-frequency = <50000000>;
 640         dmas = <&dmac2 1>;
 641         dma-names = "rx-tx";
 642         max-frequency = <50000000>;
 643         pinctrl-names = "default";
 644         pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
 645 };
 646
 647 &mmc1 {
 648         dmas = <&dmac2 3>;
 649         dma-names = "rx-tx";
 650         pinctrl-names = "default";
 651         pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
 652 };
 653
 654 &emmc {
 655         dmas = <&dmac2 4>;
 656         dma-names = "rx-tx";
 657 };
 658
 659 &pwm0 {
 660         pinctrl-names = "default";
 661         pinctrl-0 = <&pwm0_out>;
 662 };
 663
 664 &pwm1 {
 665         pinctrl-names = "default";
 666         pinctrl-0 = <&pwm1_out>;
 667 };
 668
 669 &pwm2 {
 670         pinctrl-names = "default";
 671         pinctrl-0 = <&pwm2_out>;
 672 };
 673
 674 &pwm3 {
 675         pinctrl-names = "default";
 676         pinctrl-0 = <&pwm3_out>;
 677 };
 678
 679 &spi0 {
 680         pinctrl-names = "default";
 681         pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 682 };
 683
 684 &spi1 {
 685         pinctrl-names = "default";
 686         pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 687 };
 688
 689 &uart0 {
 690         compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
 691         dmas = <&dmac1_s 0>, <&dmac1_s 1>;
 692         dma-names = "tx", "rx";
 693         pinctrl-names = "default";
 694         pinctrl-0 = <&uart0_xfer>;
 695 };
 696
 697 &uart1 {
 698         compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
 699         dmas = <&dmac1_s 2>, <&dmac1_s 3>;
 700         dma-names = "tx", "rx";
 701         pinctrl-names = "default";
 702         pinctrl-0 = <&uart1_xfer>;
 703 };
 704
 705 &uart2 {
 706         compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
 707         dmas = <&dmac2 6>, <&dmac2 7>;
 708         dma-names = "tx", "rx";
 709         pinctrl-names = "default";
 710         pinctrl-0 = <&uart2_xfer>;
 711 };
 712
 713 &uart3 {
 714         compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
 715         dmas = <&dmac2 8>, <&dmac2 9>;
 716         dma-names = "tx", "rx";
 717         pinctrl-names = "default";
 718         pinctrl-0 = <&uart3_xfer>;
 719 };
 720
 721 &wdt {
 722         compatible = "rockchip,rk3066-wdt", "snps,dw-wdt";
 723 };
 724
 725 &emac {
 726         compatible = "rockchip,rk3066-emac";
 727 };