drivers/pci/hotplug/pciehp_hpc.c

   1 /*
   2  * PCI Express PCI Hot Plug Driver
   3  *
   4  * Copyright (C) 1995,2001 Compaq Computer Corporation
   5  * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
   6  * Copyright (C) 2001 IBM Corp.
   7  * Copyright (C) 2003-2004 Intel Corporation
   8  *
   9  * All rights reserved.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or (at
  14  * your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful, but
  17  * WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  19  * NON INFRINGEMENT.  See the GNU General Public License for more
  20  * details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  25  *
  26  * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
  27  *
  28  */
  29
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/types.h>
  33 #include <linux/signal.h>
  34 #include <linux/jiffies.h>
  35 #include <linux/timer.h>
  36 #include <linux/pci.h>
  37 #include <linux/interrupt.h>
  38 #include <linux/time.h>
  39 #include <linux/slab.h>
  40
  41 #include "../pci.h"
  42 #include "pciehp.h"
  43
  44 static atomic_t pciehp_num_controllers = ATOMIC_INIT(0);
  45
  46 static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value)
  47 {
  48         struct pci_dev *dev = ctrl->pcie->port;
  49         return pci_read_config_word(dev, pci_pcie_cap(dev) + reg, value);
  50 }
  51
  52 static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value)
  53 {
  54         struct pci_dev *dev = ctrl->pcie->port;
  55         return pci_read_config_dword(dev, pci_pcie_cap(dev) + reg, value);
  56 }
  57
  58 static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value)
  59 {
  60         struct pci_dev *dev = ctrl->pcie->port;
  61         return pci_write_config_word(dev, pci_pcie_cap(dev) + reg, value);
  62 }
  63
  64 static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value)
  65 {
  66         struct pci_dev *dev = ctrl->pcie->port;
  67         return pci_write_config_dword(dev, pci_pcie_cap(dev) + reg, value);
  68 }
  69
  70 /* Power Control Command */
  71 #define POWER_ON        0
  72 #define POWER_OFF       PCI_EXP_SLTCTL_PCC
  73
  74 static irqreturn_t pcie_isr(int irq, void *dev_id);
  75 static void start_int_poll_timer(struct controller *ctrl, int sec);
  76
  77 /* This is the interrupt polling timeout function. */
  78 static void int_poll_timeout(unsigned long data)
  79 {
  80         struct controller *ctrl = (struct controller *)data;
  81
  82         /* Poll for interrupt events.  regs == NULL => polling */
  83         pcie_isr(0, ctrl);
  84
  85         init_timer(&ctrl->poll_timer);
  86         if (!pciehp_poll_time)
  87                 pciehp_poll_time = 2; /* default polling interval is 2 sec */
  88
  89         start_int_poll_timer(ctrl, pciehp_poll_time);
  90 }
  91
  92 /* This function starts the interrupt polling timer. */
  93 static void start_int_poll_timer(struct controller *ctrl, int sec)
  94 {
  95         /* Clamp to sane value */
  96         if ((sec <= 0) || (sec > 60))
  97                 sec = 2;
  98
  99         ctrl->poll_timer.function = &int_poll_timeout;
 100         ctrl->poll_timer.data = (unsigned long)ctrl;
 101         ctrl->poll_timer.expires = jiffies + sec * HZ;
 102         add_timer(&ctrl->poll_timer);
 103 }
 104
 105 static inline int pciehp_request_irq(struct controller *ctrl)
 106 {
 107         int retval, irq = ctrl->pcie->irq;
 108
 109         /* Install interrupt polling timer. Start with 10 sec delay */
 110         if (pciehp_poll_mode) {
 111                 init_timer(&ctrl->poll_timer);
 112                 start_int_poll_timer(ctrl, 10);
 113                 return 0;
 114         }
 115
 116         /* Installs the interrupt handler */
 117         retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl);
 118         if (retval)
 119                 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
 120                          irq);
 121         return retval;
 122 }
 123
 124 static inline void pciehp_free_irq(struct controller *ctrl)
 125 {
 126         if (pciehp_poll_mode)
 127                 del_timer_sync(&ctrl->poll_timer);
 128         else
 129                 free_irq(ctrl->pcie->irq, ctrl);
 130 }
 131
 132 static int pcie_poll_cmd(struct controller *ctrl)
 133 {
 134         u16 slot_status;
 135         int err, timeout = 1000;
 136
 137         err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
 138         if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) {
 139                 pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC);
 140                 return 1;
 141         }
 142         while (timeout > 0) {
 143                 msleep(10);
 144                 timeout -= 10;
 145                 err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
 146                 if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) {
 147                         pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC);
 148                         return 1;
 149                 }
 150         }
 151         return 0;       /* timeout */
 152 }
 153
 154 static void pcie_wait_cmd(struct controller *ctrl, int poll)
 155 {
 156         unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
 157         unsigned long timeout = msecs_to_jiffies(msecs);
 158         int rc;
 159
 160         if (poll)
 161                 rc = pcie_poll_cmd(ctrl);
 162         else
 163                 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
 164         if (!rc)
 165                 ctrl_dbg(ctrl, "Command not completed in 1000 msec\n");
 166 }
 167
 168 /**
 169  * pcie_write_cmd - Issue controller command
 170  * @ctrl: controller to which the command is issued
 171  * @cmd:  command value written to slot control register
 172  * @mask: bitmask of slot control register to be modified
 173  */
 174 static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
 175 {
 176         int retval = 0;
 177         u16 slot_status;
 178         u16 slot_ctrl;
 179
 180         mutex_lock(&ctrl->ctrl_lock);
 181
 182         retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
 183         if (retval) {
 184                 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
 185                          __func__);
 186                 goto out;
 187         }
 188
 189         if (slot_status & PCI_EXP_SLTSTA_CC) {
 190                 if (!ctrl->no_cmd_complete) {
 191                         /*
 192                          * After 1 sec and CMD_COMPLETED still not set, just
 193                          * proceed forward to issue the next command according
 194                          * to spec. Just print out the error message.
 195                          */
 196                         ctrl_dbg(ctrl, "CMD_COMPLETED not clear after 1 sec\n");
 197                 } else if (!NO_CMD_CMPL(ctrl)) {
 198                         /*
 199                          * This controller semms to notify of command completed
 200                          * event even though it supports none of power
 201                          * controller, attention led, power led and EMI.
 202                          */
 203                         ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Need to "
 204                                  "wait for command completed event.\n");
 205                         ctrl->no_cmd_complete = 0;
 206                 } else {
 207                         ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Maybe "
 208                                  "the controller is broken.\n");
 209                 }
 210         }
 211
 212         retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
 213         if (retval) {
 214                 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
 215                 goto out;
 216         }
 217
 218         slot_ctrl &= ~mask;
 219         slot_ctrl |= (cmd & mask);
 220         ctrl->cmd_busy = 1;
 221         smp_mb();
 222         retval = pciehp_writew(ctrl, PCI_EXP_SLTCTL, slot_ctrl);
 223         if (retval)
 224                 ctrl_err(ctrl, "Cannot write to SLOTCTRL register\n");
 225
 226         /*
 227          * Wait for command completion.
 228          */
 229         if (!retval && !ctrl->no_cmd_complete) {
 230                 int poll = 0;
 231                 /*
 232                  * if hotplug interrupt is not enabled or command
 233                  * completed interrupt is not enabled, we need to poll
 234                  * command completed event.
 235                  */
 236                 if (!(slot_ctrl & PCI_EXP_SLTCTL_HPIE) ||
 237                     !(slot_ctrl & PCI_EXP_SLTCTL_CCIE))
 238                         poll = 1;
 239                 pcie_wait_cmd(ctrl, poll);
 240         }
 241  out:
 242         mutex_unlock(&ctrl->ctrl_lock);
 243         return retval;
 244 }
 245
 246 static inline int check_link_active(struct controller *ctrl)
 247 {
 248         u16 link_status;
 249
 250         if (pciehp_readw(ctrl, PCI_EXP_LNKSTA, &link_status))
 251                 return 0;
 252         return !!(link_status & PCI_EXP_LNKSTA_DLLLA);
 253 }
 254
 255 static void pcie_wait_link_active(struct controller *ctrl)
 256 {
 257         int timeout = 1000;
 258
 259         if (check_link_active(ctrl))
 260                 return;
 261         while (timeout > 0) {
 262                 msleep(10);
 263                 timeout -= 10;
 264                 if (check_link_active(ctrl))
 265                         return;
 266         }
 267         ctrl_dbg(ctrl, "Data Link Layer Link Active not set in 1000 msec\n");
 268 }
 269
 270 int pciehp_check_link_status(struct controller *ctrl)
 271 {
 272         u16 lnk_status;
 273         int retval = 0;
 274
 275         /*
 276          * Data Link Layer Link Active Reporting must be capable for
 277          * hot-plug capable downstream port. But old controller might
 278          * not implement it. In this case, we wait for 1000 ms.
 279          */
 280         if (ctrl->link_active_reporting){
 281                 /* Wait for Data Link Layer Link Active bit to be set */
 282                 pcie_wait_link_active(ctrl);
 283                 /*
 284                  * We must wait for 100 ms after the Data Link Layer
 285                  * Link Active bit reads 1b before initiating a
 286                  * configuration access to the hot added device.
 287                  */
 288                 msleep(100);
 289         } else
 290                 msleep(1000);
 291
 292         retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
 293         if (retval) {
 294                 ctrl_err(ctrl, "Cannot read LNKSTATUS register\n");
 295                 return retval;
 296         }
 297
 298         ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
 299         if ((lnk_status & PCI_EXP_LNKSTA_LT) ||
 300             !(lnk_status & PCI_EXP_LNKSTA_NLW)) {
 301                 ctrl_err(ctrl, "Link Training Error occurs \n");
 302                 retval = -1;
 303                 return retval;
 304         }
 305
 306         return retval;
 307 }
 308
 309 int pciehp_get_attention_status(struct slot *slot, u8 *status)
 310 {
 311         struct controller *ctrl = slot->ctrl;
 312         u16 slot_ctrl;
 313         u8 atten_led_state;
 314         int retval = 0;
 315
 316         retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
 317         if (retval) {
 318                 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
 319                 return retval;
 320         }
 321
 322         ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__,
 323                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
 324
 325         atten_led_state = (slot_ctrl & PCI_EXP_SLTCTL_AIC) >> 6;
 326
 327         switch (atten_led_state) {
 328         case 0:
 329                 *status = 0xFF; /* Reserved */
 330                 break;
 331         case 1:
 332                 *status = 1;    /* On */
 333                 break;
 334         case 2:
 335                 *status = 2;    /* Blink */
 336                 break;
 337         case 3:
 338                 *status = 0;    /* Off */
 339                 break;
 340         default:
 341                 *status = 0xFF;
 342                 break;
 343         }
 344
 345         return 0;
 346 }
 347
 348 int pciehp_get_power_status(struct slot *slot, u8 *status)
 349 {
 350         struct controller *ctrl = slot->ctrl;
 351         u16 slot_ctrl;
 352         u8 pwr_state;
 353         int     retval = 0;
 354
 355         retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
 356         if (retval) {
 357                 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
 358                 return retval;
 359         }
 360         ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__,
 361                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
 362
 363         pwr_state = (slot_ctrl & PCI_EXP_SLTCTL_PCC) >> 10;
 364
 365         switch (pwr_state) {
 366         case 0:
 367                 *status = 1;
 368                 break;
 369         case 1:
 370                 *status = 0;
 371                 break;
 372         default:
 373                 *status = 0xFF;
 374                 break;
 375         }
 376
 377         return retval;
 378 }
 379
 380 int pciehp_get_latch_status(struct slot *slot, u8 *status)
 381 {
 382         struct controller *ctrl = slot->ctrl;
 383         u16 slot_status;
 384         int retval;
 385
 386         retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
 387         if (retval) {
 388                 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
 389                          __func__);
 390                 return retval;
 391         }
 392         *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);
 393         return 0;
 394 }
 395
 396 int pciehp_get_adapter_status(struct slot *slot, u8 *status)
 397 {
 398         struct controller *ctrl = slot->ctrl;
 399         u16 slot_status;
 400         int retval;
 401
 402         retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
 403         if (retval) {
 404                 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
 405                          __func__);
 406                 return retval;
 407         }
 408         *status = !!(slot_status & PCI_EXP_SLTSTA_PDS);
 409         return 0;
 410 }
 411
 412 int pciehp_query_power_fault(struct slot *slot)
 413 {
 414         struct controller *ctrl = slot->ctrl;
 415         u16 slot_status;
 416         int retval;
 417
 418         retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
 419         if (retval) {
 420                 ctrl_err(ctrl, "Cannot check for power fault\n");
 421                 return retval;
 422         }
 423         return !!(slot_status & PCI_EXP_SLTSTA_PFD);
 424 }
 425
 426 int pciehp_set_attention_status(struct slot *slot, u8 value)
 427 {
 428         struct controller *ctrl = slot->ctrl;
 429         u16 slot_cmd;
 430         u16 cmd_mask;
 431
 432         cmd_mask = PCI_EXP_SLTCTL_AIC;
 433         switch (value) {
 434         case 0 :        /* turn off */
 435                 slot_cmd = 0x00C0;
 436                 break;
 437         case 1:         /* turn on */
 438                 slot_cmd = 0x0040;
 439                 break;
 440         case 2:         /* turn blink */
 441                 slot_cmd = 0x0080;
 442                 break;
 443         default:
 444                 return -EINVAL;
 445         }
 446         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 447                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
 448         return pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
 449 }
 450
 451 void pciehp_green_led_on(struct slot *slot)
 452 {
 453         struct controller *ctrl = slot->ctrl;
 454         u16 slot_cmd;
 455         u16 cmd_mask;
 456
 457         slot_cmd = 0x0100;
 458         cmd_mask = PCI_EXP_SLTCTL_PIC;
 459         pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
 460         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 461                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
 462 }
 463
 464 void pciehp_green_led_off(struct slot *slot)
 465 {
 466         struct controller *ctrl = slot->ctrl;
 467         u16 slot_cmd;
 468         u16 cmd_mask;
 469
 470         slot_cmd = 0x0300;
 471         cmd_mask = PCI_EXP_SLTCTL_PIC;
 472         pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
 473         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 474                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
 475 }
 476
 477 void pciehp_green_led_blink(struct slot *slot)
 478 {
 479         struct controller *ctrl = slot->ctrl;
 480         u16 slot_cmd;
 481         u16 cmd_mask;
 482
 483         slot_cmd = 0x0200;
 484         cmd_mask = PCI_EXP_SLTCTL_PIC;
 485         pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
 486         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 487                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
 488 }
 489
 490 int pciehp_power_on_slot(struct slot * slot)
 491 {
 492         struct controller *ctrl = slot->ctrl;
 493         u16 slot_cmd;
 494         u16 cmd_mask;
 495         u16 slot_status;
 496         u16 lnk_status;
 497         int retval = 0;
 498
 499         /* Clear sticky power-fault bit from previous power failures */
 500         retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
 501         if (retval) {
 502                 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
 503                          __func__);
 504                 return retval;
 505         }
 506         slot_status &= PCI_EXP_SLTSTA_PFD;
 507         if (slot_status) {
 508                 retval = pciehp_writew(ctrl, PCI_EXP_SLTSTA, slot_status);
 509                 if (retval) {
 510                         ctrl_err(ctrl,
 511                                  "%s: Cannot write to SLOTSTATUS register\n",
 512                                  __func__);
 513                         return retval;
 514                 }
 515         }
 516         ctrl->power_fault_detected = 0;
 517
 518         slot_cmd = POWER_ON;
 519         cmd_mask = PCI_EXP_SLTCTL_PCC;
 520         retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
 521         if (retval) {
 522                 ctrl_err(ctrl, "Write %x command failed!\n", slot_cmd);
 523                 return retval;
 524         }
 525         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 526                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
 527
 528         retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
 529         if (retval) {
 530                 ctrl_err(ctrl, "%s: Cannot read LNKSTA register\n",
 531                                 __func__);
 532                 return retval;
 533         }
 534         pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
 535
 536         return retval;
 537 }
 538
 539 int pciehp_power_off_slot(struct slot * slot)
 540 {
 541         struct controller *ctrl = slot->ctrl;
 542         u16 slot_cmd;
 543         u16 cmd_mask;
 544         int retval;
 545
 546         slot_cmd = POWER_OFF;
 547         cmd_mask = PCI_EXP_SLTCTL_PCC;
 548         retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
 549         if (retval) {
 550                 ctrl_err(ctrl, "Write command failed!\n");
 551                 return retval;
 552         }
 553         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 554                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
 555         return 0;
 556 }
 557
 558 static irqreturn_t pcie_isr(int irq, void *dev_id)
 559 {
 560         struct controller *ctrl = (struct controller *)dev_id;
 561         struct slot *slot = ctrl->slot;
 562         u16 detected, intr_loc;
 563
 564         /*
 565          * In order to guarantee that all interrupt events are
 566          * serviced, we need to re-inspect Slot Status register after
 567          * clearing what is presumed to be the last pending interrupt.
 568          */
 569         intr_loc = 0;
 570         do {
 571                 if (pciehp_readw(ctrl, PCI_EXP_SLTSTA, &detected)) {
 572                         ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS\n",
 573                                  __func__);
 574                         return IRQ_NONE;
 575                 }
 576
 577                 detected &= (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
 578                              PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
 579                              PCI_EXP_SLTSTA_CC);
 580                 detected &= ~intr_loc;
 581                 intr_loc |= detected;
 582                 if (!intr_loc)
 583                         return IRQ_NONE;
 584                 if (detected && pciehp_writew(ctrl, PCI_EXP_SLTSTA, intr_loc)) {
 585                         ctrl_err(ctrl, "%s: Cannot write to SLOTSTATUS\n",
 586                                  __func__);
 587                         return IRQ_NONE;
 588                 }
 589         } while (detected);
 590
 591         ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc);
 592
 593         /* Check Command Complete Interrupt Pending */
 594         if (intr_loc & PCI_EXP_SLTSTA_CC) {
 595                 ctrl->cmd_busy = 0;
 596                 smp_mb();
 597                 wake_up(&ctrl->queue);
 598         }
 599
 600         if (!(intr_loc & ~PCI_EXP_SLTSTA_CC))
 601                 return IRQ_HANDLED;
 602
 603         /* Check MRL Sensor Changed */
 604         if (intr_loc & PCI_EXP_SLTSTA_MRLSC)
 605                 pciehp_handle_switch_change(slot);
 606
 607         /* Check Attention Button Pressed */
 608         if (intr_loc & PCI_EXP_SLTSTA_ABP)
 609                 pciehp_handle_attention_button(slot);
 610
 611         /* Check Presence Detect Changed */
 612         if (intr_loc & PCI_EXP_SLTSTA_PDC)
 613                 pciehp_handle_presence_change(slot);
 614
 615         /* Check Power Fault Detected */
 616         if ((intr_loc & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) {
 617                 ctrl->power_fault_detected = 1;
 618                 pciehp_handle_power_fault(slot);
 619         }
 620         return IRQ_HANDLED;
 621 }
 622
 623 int pciehp_get_max_lnk_width(struct slot *slot,
 624                                  enum pcie_link_width *value)
 625 {
 626         struct controller *ctrl = slot->ctrl;
 627         enum pcie_link_width lnk_wdth;
 628         u32     lnk_cap;
 629         int retval = 0;
 630
 631         retval = pciehp_readl(ctrl, PCI_EXP_LNKCAP, &lnk_cap);
 632         if (retval) {
 633                 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__);
 634                 return retval;
 635         }
 636
 637         switch ((lnk_cap & PCI_EXP_LNKSTA_NLW) >> 4){
 638         case 0:
 639                 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
 640                 break;
 641         case 1:
 642                 lnk_wdth = PCIE_LNK_X1;
 643                 break;
 644         case 2:
 645                 lnk_wdth = PCIE_LNK_X2;
 646                 break;
 647         case 4:
 648                 lnk_wdth = PCIE_LNK_X4;
 649                 break;
 650         case 8:
 651                 lnk_wdth = PCIE_LNK_X8;
 652                 break;
 653         case 12:
 654                 lnk_wdth = PCIE_LNK_X12;
 655                 break;
 656         case 16:
 657                 lnk_wdth = PCIE_LNK_X16;
 658                 break;
 659         case 32:
 660                 lnk_wdth = PCIE_LNK_X32;
 661                 break;
 662         default:
 663                 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
 664                 break;
 665         }
 666
 667         *value = lnk_wdth;
 668         ctrl_dbg(ctrl, "Max link width = %d\n", lnk_wdth);
 669
 670         return retval;
 671 }
 672
 673 int pciehp_get_cur_lnk_width(struct slot *slot,
 674                                  enum pcie_link_width *value)
 675 {
 676         struct controller *ctrl = slot->ctrl;
 677         enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
 678         int retval = 0;
 679         u16 lnk_status;
 680
 681         retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
 682         if (retval) {
 683                 ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n",
 684                          __func__);
 685                 return retval;
 686         }
 687
 688         switch ((lnk_status & PCI_EXP_LNKSTA_NLW) >> 4){
 689         case 0:
 690                 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
 691                 break;
 692         case 1:
 693                 lnk_wdth = PCIE_LNK_X1;
 694                 break;
 695         case 2:
 696                 lnk_wdth = PCIE_LNK_X2;
 697                 break;
 698         case 4:
 699                 lnk_wdth = PCIE_LNK_X4;
 700                 break;
 701         case 8:
 702                 lnk_wdth = PCIE_LNK_X8;
 703                 break;
 704         case 12:
 705                 lnk_wdth = PCIE_LNK_X12;
 706                 break;
 707         case 16:
 708                 lnk_wdth = PCIE_LNK_X16;
 709                 break;
 710         case 32:
 711                 lnk_wdth = PCIE_LNK_X32;
 712                 break;
 713         default:
 714                 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
 715                 break;
 716         }
 717
 718         *value = lnk_wdth;
 719         ctrl_dbg(ctrl, "Current link width = %d\n", lnk_wdth);
 720
 721         return retval;
 722 }
 723
 724 int pcie_enable_notification(struct controller *ctrl)
 725 {
 726         u16 cmd, mask;
 727
 728         /*
 729          * TBD: Power fault detected software notification support.
 730          *
 731          * Power fault detected software notification is not enabled
 732          * now, because it caused power fault detected interrupt storm
 733          * on some machines. On those machines, power fault detected
 734          * bit in the slot status register was set again immediately
 735          * when it is cleared in the interrupt service routine, and
 736          * next power fault detected interrupt was notified again.
 737          */
 738         cmd = PCI_EXP_SLTCTL_PDCE;
 739         if (ATTN_BUTTN(ctrl))
 740                 cmd |= PCI_EXP_SLTCTL_ABPE;
 741         if (MRL_SENS(ctrl))
 742                 cmd |= PCI_EXP_SLTCTL_MRLSCE;
 743         if (!pciehp_poll_mode)
 744                 cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE;
 745
 746         mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
 747                 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
 748                 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE);
 749
 750         if (pcie_write_cmd(ctrl, cmd, mask)) {
 751                 ctrl_err(ctrl, "Cannot enable software notification\n");
 752                 return -1;
 753         }
 754         return 0;
 755 }
 756
 757 static void pcie_disable_notification(struct controller *ctrl)
 758 {
 759         u16 mask;
 760         mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
 761                 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
 762                 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
 763                 PCI_EXP_SLTCTL_DLLSCE);
 764         if (pcie_write_cmd(ctrl, 0, mask))
 765                 ctrl_warn(ctrl, "Cannot disable software notification\n");
 766 }
 767
 768 int pcie_init_notification(struct controller *ctrl)
 769 {
 770         if (pciehp_request_irq(ctrl))
 771                 return -1;
 772         if (pcie_enable_notification(ctrl)) {
 773                 pciehp_free_irq(ctrl);
 774                 return -1;
 775         }
 776         ctrl->notification_enabled = 1;
 777         return 0;
 778 }
 779
 780 static void pcie_shutdown_notification(struct controller *ctrl)
 781 {
 782         if (ctrl->notification_enabled) {
 783                 pcie_disable_notification(ctrl);
 784                 pciehp_free_irq(ctrl);
 785                 ctrl->notification_enabled = 0;
 786         }
 787 }
 788
 789 static int pcie_init_slot(struct controller *ctrl)
 790 {
 791         struct slot *slot;
 792
 793         slot = kzalloc(sizeof(*slot), GFP_KERNEL);
 794         if (!slot)
 795                 return -ENOMEM;
 796
 797         slot->ctrl = ctrl;
 798         mutex_init(&slot->lock);
 799         INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work);
 800         ctrl->slot = slot;
 801         return 0;
 802 }
 803
 804 static void pcie_cleanup_slot(struct controller *ctrl)
 805 {
 806         struct slot *slot = ctrl->slot;
 807         cancel_delayed_work(&slot->work);
 808         flush_scheduled_work();
 809         flush_workqueue(pciehp_wq);
 810         kfree(slot);
 811 }
 812
 813 static inline void dbg_ctrl(struct controller *ctrl)
 814 {
 815         int i;
 816         u16 reg16;
 817         struct pci_dev *pdev = ctrl->pcie->port;
 818
 819         if (!pciehp_debug)
 820                 return;
 821
 822         ctrl_info(ctrl, "Hotplug Controller:\n");
 823         ctrl_info(ctrl, "  Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n",
 824                   pci_name(pdev), pdev->irq);
 825         ctrl_info(ctrl, "  Vendor ID            : 0x%04x\n", pdev->vendor);
 826         ctrl_info(ctrl, "  Device ID            : 0x%04x\n", pdev->device);
 827         ctrl_info(ctrl, "  Subsystem ID         : 0x%04x\n",
 828                   pdev->subsystem_device);
 829         ctrl_info(ctrl, "  Subsystem Vendor ID  : 0x%04x\n",
 830                   pdev->subsystem_vendor);
 831         ctrl_info(ctrl, "  PCIe Cap offset      : 0x%02x\n",
 832                   pci_pcie_cap(pdev));
 833         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
 834                 if (!pci_resource_len(pdev, i))
 835                         continue;
 836                 ctrl_info(ctrl, "  PCI resource [%d]     : %pR\n",
 837                           i, &pdev->resource[i]);
 838         }
 839         ctrl_info(ctrl, "Slot Capabilities      : 0x%08x\n", ctrl->slot_cap);
 840         ctrl_info(ctrl, "  Physical Slot Number : %d\n", PSN(ctrl));
 841         ctrl_info(ctrl, "  Attention Button     : %3s\n",
 842                   ATTN_BUTTN(ctrl) ? "yes" : "no");
 843         ctrl_info(ctrl, "  Power Controller     : %3s\n",
 844                   POWER_CTRL(ctrl) ? "yes" : "no");
 845         ctrl_info(ctrl, "  MRL Sensor           : %3s\n",
 846                   MRL_SENS(ctrl)   ? "yes" : "no");
 847         ctrl_info(ctrl, "  Attention Indicator  : %3s\n",
 848                   ATTN_LED(ctrl)   ? "yes" : "no");
 849         ctrl_info(ctrl, "  Power Indicator      : %3s\n",
 850                   PWR_LED(ctrl)    ? "yes" : "no");
 851         ctrl_info(ctrl, "  Hot-Plug Surprise    : %3s\n",
 852                   HP_SUPR_RM(ctrl) ? "yes" : "no");
 853         ctrl_info(ctrl, "  EMI Present          : %3s\n",
 854                   EMI(ctrl)        ? "yes" : "no");
 855         ctrl_info(ctrl, "  Command Completed    : %3s\n",
 856                   NO_CMD_CMPL(ctrl) ? "no" : "yes");
 857         pciehp_readw(ctrl, PCI_EXP_SLTSTA, &reg16);
 858         ctrl_info(ctrl, "Slot Status            : 0x%04x\n", reg16);
 859         pciehp_readw(ctrl, PCI_EXP_SLTCTL, &reg16);
 860         ctrl_info(ctrl, "Slot Control           : 0x%04x\n", reg16);
 861 }
 862
 863 struct controller *pcie_init(struct pcie_device *dev)
 864 {
 865         struct controller *ctrl;
 866         u32 slot_cap, link_cap;
 867         struct pci_dev *pdev = dev->port;
 868
 869         ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
 870         if (!ctrl) {
 871                 dev_err(&dev->device, "%s: Out of memory\n", __func__);
 872                 goto abort;
 873         }
 874         ctrl->pcie = dev;
 875         if (!pci_pcie_cap(pdev)) {
 876                 ctrl_err(ctrl, "Cannot find PCI Express capability\n");
 877                 goto abort_ctrl;
 878         }
 879         if (pciehp_readl(ctrl, PCI_EXP_SLTCAP, &slot_cap)) {
 880                 ctrl_err(ctrl, "Cannot read SLOTCAP register\n");
 881                 goto abort_ctrl;
 882         }
 883
 884         ctrl->slot_cap = slot_cap;
 885         mutex_init(&ctrl->ctrl_lock);
 886         init_waitqueue_head(&ctrl->queue);
 887         dbg_ctrl(ctrl);
 888         /*
 889          * Controller doesn't notify of command completion if the "No
 890          * Command Completed Support" bit is set in Slot Capability
 891          * register or the controller supports none of power
 892          * controller, attention led, power led and EMI.
 893          */
 894         if (NO_CMD_CMPL(ctrl) ||
 895             !(POWER_CTRL(ctrl) | ATTN_LED(ctrl) | PWR_LED(ctrl) | EMI(ctrl)))
 896             ctrl->no_cmd_complete = 1;
 897
 898         /* Check if Data Link Layer Link Active Reporting is implemented */
 899         if (pciehp_readl(ctrl, PCI_EXP_LNKCAP, &link_cap)) {
 900                 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__);
 901                 goto abort_ctrl;
 902         }
 903         if (link_cap & PCI_EXP_LNKCAP_DLLLARC) {
 904                 ctrl_dbg(ctrl, "Link Active Reporting supported\n");
 905                 ctrl->link_active_reporting = 1;
 906         }
 907
 908         /* Clear all remaining event bits in Slot Status register */
 909         if (pciehp_writew(ctrl, PCI_EXP_SLTSTA, 0x1f))
 910                 goto abort_ctrl;
 911
 912         /* Disable sotfware notification */
 913         pcie_disable_notification(ctrl);
 914
 915         /*
 916          * If this is the first controller to be initialized,
 917          * initialize the pciehp work queue
 918          */
 919         if (atomic_add_return(1, &pciehp_num_controllers) == 1) {
 920                 pciehp_wq = create_singlethread_workqueue("pciehpd");
 921                 if (!pciehp_wq)
 922                         goto abort_ctrl;
 923         }
 924
 925         ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",
 926                   pdev->vendor, pdev->device, pdev->subsystem_vendor,
 927                   pdev->subsystem_device);
 928
 929         if (pcie_init_slot(ctrl))
 930                 goto abort_ctrl;
 931
 932         return ctrl;
 933
 934 abort_ctrl:
 935         kfree(ctrl);
 936 abort:
 937         return NULL;
 938 }
 939
 940 void pciehp_release_ctrl(struct controller *ctrl)
 941 {
 942         pcie_shutdown_notification(ctrl);
 943         pcie_cleanup_slot(ctrl);
 944         /*
 945          * If this is the last controller to be released, destroy the
 946          * pciehp work queue
 947          */
 948         if (atomic_dec_and_test(&pciehp_num_controllers))
 949                 destroy_workqueue(pciehp_wq);
 950         kfree(ctrl);
 951 }