drivers/i2c/busses/i2c-octeon-core.c

   1 /*
   2  * (C) Copyright 2009-2010
   3  * Nokia Siemens Networks, michael.lawnick.ext@nsn.com
   4  *
   5  * Portions Copyright (C) 2010 - 2016 Cavium, Inc.
   6  *
   7  * This file contains the shared part of the driver for the i2c adapter in
   8  * Cavium Networks' OCTEON processors and ThunderX SOCs.
   9  *
  10  * This file is licensed under the terms of the GNU General Public
  11  * License version 2. This program is licensed "as is" without any
  12  * warranty of any kind, whether express or implied.
  13  */
  14
  15 #include <linux/delay.h>
  16 #include <linux/i2c.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/kernel.h>
  19 #include <linux/module.h>
  20
  21 #include "i2c-octeon-core.h"
  22
  23 /* interrupt service routine */
  24 irqreturn_t octeon_i2c_isr(int irq, void *dev_id)
  25 {
  26         struct octeon_i2c *i2c = dev_id;
  27
  28         i2c->int_disable(i2c);
  29         wake_up(&i2c->queue);
  30
  31         return IRQ_HANDLED;
  32 }
  33
  34 static bool octeon_i2c_test_iflg(struct octeon_i2c *i2c)
  35 {
  36         return (octeon_i2c_ctl_read(i2c) & TWSI_CTL_IFLG);
  37 }
  38
  39 static bool octeon_i2c_test_ready(struct octeon_i2c *i2c, bool *first)
  40 {
  41         if (octeon_i2c_test_iflg(i2c))
  42                 return true;
  43
  44         if (*first) {
  45                 *first = false;
  46                 return false;
  47         }
  48
  49         /*
  50          * IRQ has signaled an event but IFLG hasn't changed.
  51          * Sleep and retry once.
  52          */
  53         usleep_range(I2C_OCTEON_EVENT_WAIT, 2 * I2C_OCTEON_EVENT_WAIT);
  54         return octeon_i2c_test_iflg(i2c);
  55 }
  56
  57 /**
  58  * octeon_i2c_wait - wait for the IFLG to be set
  59  * @i2c: The struct octeon_i2c
  60  *
  61  * Returns 0 on success, otherwise a negative errno.
  62  */
  63 static int octeon_i2c_wait(struct octeon_i2c *i2c)
  64 {
  65         long time_left;
  66         bool first = true;
  67
  68         /*
  69          * Some chip revisions don't assert the irq in the interrupt
  70          * controller. So we must poll for the IFLG change.
  71          */
  72         if (i2c->broken_irq_mode) {
  73                 u64 end = get_jiffies_64() + i2c->adap.timeout;
  74
  75                 while (!octeon_i2c_test_iflg(i2c) &&
  76                        time_before64(get_jiffies_64(), end))
  77                         usleep_range(I2C_OCTEON_EVENT_WAIT / 2, I2C_OCTEON_EVENT_WAIT);
  78
  79                 return octeon_i2c_test_iflg(i2c) ? 0 : -ETIMEDOUT;
  80         }
  81
  82         i2c->int_enable(i2c);
  83         time_left = wait_event_timeout(i2c->queue, octeon_i2c_test_ready(i2c, &first),
  84                                        i2c->adap.timeout);
  85         i2c->int_disable(i2c);
  86
  87         if (i2c->broken_irq_check && !time_left &&
  88             octeon_i2c_test_iflg(i2c)) {
  89                 dev_err(i2c->dev, "broken irq connection detected, switching to polling mode.\n");
  90                 i2c->broken_irq_mode = true;
  91                 return 0;
  92         }
  93
  94         if (!time_left)
  95                 return -ETIMEDOUT;
  96
  97         return 0;
  98 }
  99
 100 static bool octeon_i2c_hlc_test_valid(struct octeon_i2c *i2c)
 101 {
 102         return (__raw_readq(i2c->twsi_base + SW_TWSI(i2c)) & SW_TWSI_V) == 0;
 103 }
 104
 105 static bool octeon_i2c_hlc_test_ready(struct octeon_i2c *i2c, bool *first)
 106 {
 107         /* check if valid bit is cleared */
 108         if (octeon_i2c_hlc_test_valid(i2c))
 109                 return true;
 110
 111         if (*first) {
 112                 *first = false;
 113                 return false;
 114         }
 115
 116         /*
 117          * IRQ has signaled an event but valid bit isn't cleared.
 118          * Sleep and retry once.
 119          */
 120         usleep_range(I2C_OCTEON_EVENT_WAIT, 2 * I2C_OCTEON_EVENT_WAIT);
 121         return octeon_i2c_hlc_test_valid(i2c);
 122 }
 123
 124 static void octeon_i2c_hlc_int_clear(struct octeon_i2c *i2c)
 125 {
 126         /* clear ST/TS events, listen for neither */
 127         octeon_i2c_write_int(i2c, TWSI_INT_ST_INT | TWSI_INT_TS_INT);
 128 }
 129
 130 /*
 131  * Cleanup low-level state & enable high-level controller.
 132  */
 133 static void octeon_i2c_hlc_enable(struct octeon_i2c *i2c)
 134 {
 135         int try = 0;
 136         u64 val;
 137
 138         if (i2c->hlc_enabled)
 139                 return;
 140         i2c->hlc_enabled = true;
 141
 142         while (1) {
 143                 val = octeon_i2c_ctl_read(i2c);
 144                 if (!(val & (TWSI_CTL_STA | TWSI_CTL_STP)))
 145                         break;
 146
 147                 /* clear IFLG event */
 148                 if (val & TWSI_CTL_IFLG)
 149                         octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
 150
 151                 if (try++ > 100) {
 152                         pr_err("%s: giving up\n", __func__);
 153                         break;
 154                 }
 155
 156                 /* spin until any start/stop has finished */
 157                 udelay(10);
 158         }
 159         octeon_i2c_ctl_write(i2c, TWSI_CTL_CE | TWSI_CTL_AAK | TWSI_CTL_ENAB);
 160 }
 161
 162 static void octeon_i2c_hlc_disable(struct octeon_i2c *i2c)
 163 {
 164         if (!i2c->hlc_enabled)
 165                 return;
 166
 167         i2c->hlc_enabled = false;
 168         octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
 169 }
 170
 171 /**
 172  * octeon_i2c_hlc_wait - wait for an HLC operation to complete
 173  * @i2c: The struct octeon_i2c
 174  *
 175  * Returns 0 on success, otherwise -ETIMEDOUT.
 176  */
 177 static int octeon_i2c_hlc_wait(struct octeon_i2c *i2c)
 178 {
 179         bool first = true;
 180         int time_left;
 181
 182         /*
 183          * Some cn38xx boards don't assert the irq in the interrupt
 184          * controller. So we must poll for the valid bit change.
 185          */
 186         if (i2c->broken_irq_mode) {
 187                 u64 end = get_jiffies_64() + i2c->adap.timeout;
 188
 189                 while (!octeon_i2c_hlc_test_valid(i2c) &&
 190                        time_before64(get_jiffies_64(), end))
 191                         usleep_range(I2C_OCTEON_EVENT_WAIT / 2, I2C_OCTEON_EVENT_WAIT);
 192
 193                 return octeon_i2c_hlc_test_valid(i2c) ? 0 : -ETIMEDOUT;
 194         }
 195
 196         i2c->hlc_int_enable(i2c);
 197         time_left = wait_event_timeout(i2c->queue,
 198                                        octeon_i2c_hlc_test_ready(i2c, &first),
 199                                        i2c->adap.timeout);
 200         i2c->hlc_int_disable(i2c);
 201         if (!time_left)
 202                 octeon_i2c_hlc_int_clear(i2c);
 203
 204         if (i2c->broken_irq_check && !time_left &&
 205             octeon_i2c_hlc_test_valid(i2c)) {
 206                 dev_err(i2c->dev, "broken irq connection detected, switching to polling mode.\n");
 207                 i2c->broken_irq_mode = true;
 208                 return 0;
 209         }
 210
 211         if (!time_left)
 212                 return -ETIMEDOUT;
 213         return 0;
 214 }
 215
 216 static int octeon_i2c_check_status(struct octeon_i2c *i2c, int final_read)
 217 {
 218         u8 stat;
 219
 220         /*
 221          * This is ugly... in HLC mode the status is not in the status register
 222          * but in the lower 8 bits of SW_TWSI.
 223          */
 224         if (i2c->hlc_enabled)
 225                 stat = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));
 226         else
 227                 stat = octeon_i2c_stat_read(i2c);
 228
 229         switch (stat) {
 230         /* Everything is fine */
 231         case STAT_IDLE:
 232         case STAT_AD2W_ACK:
 233         case STAT_RXADDR_ACK:
 234         case STAT_TXADDR_ACK:
 235         case STAT_TXDATA_ACK:
 236                 return 0;
 237
 238         /* ACK allowed on pre-terminal bytes only */
 239         case STAT_RXDATA_ACK:
 240                 if (!final_read)
 241                         return 0;
 242                 return -EIO;
 243
 244         /* NAK allowed on terminal byte only */
 245         case STAT_RXDATA_NAK:
 246                 if (final_read)
 247                         return 0;
 248                 return -EIO;
 249
 250         /* Arbitration lost */
 251         case STAT_LOST_ARB_38:
 252         case STAT_LOST_ARB_68:
 253         case STAT_LOST_ARB_78:
 254         case STAT_LOST_ARB_B0:
 255                 return -EAGAIN;
 256
 257         /* Being addressed as slave, should back off & listen */
 258         case STAT_SLAVE_60:
 259         case STAT_SLAVE_70:
 260         case STAT_GENDATA_ACK:
 261         case STAT_GENDATA_NAK:
 262                 return -EOPNOTSUPP;
 263
 264         /* Core busy as slave */
 265         case STAT_SLAVE_80:
 266         case STAT_SLAVE_88:
 267         case STAT_SLAVE_A0:
 268         case STAT_SLAVE_A8:
 269         case STAT_SLAVE_LOST:
 270         case STAT_SLAVE_NAK:
 271         case STAT_SLAVE_ACK:
 272                 return -EOPNOTSUPP;
 273
 274         case STAT_TXDATA_NAK:
 275                 return -EIO;
 276         case STAT_TXADDR_NAK:
 277         case STAT_RXADDR_NAK:
 278         case STAT_AD2W_NAK:
 279                 return -ENXIO;
 280         default:
 281                 dev_err(i2c->dev, "unhandled state: %d\n", stat);
 282                 return -EIO;
 283         }
 284 }
 285
 286 static int octeon_i2c_recovery(struct octeon_i2c *i2c)
 287 {
 288         int ret;
 289
 290         ret = i2c_recover_bus(&i2c->adap);
 291         if (ret)
 292                 /* recover failed, try hardware re-init */
 293                 ret = octeon_i2c_init_lowlevel(i2c);
 294         return ret;
 295 }
 296
 297 /**
 298  * octeon_i2c_start - send START to the bus
 299  * @i2c: The struct octeon_i2c
 300  *
 301  * Returns 0 on success, otherwise a negative errno.
 302  */
 303 static int octeon_i2c_start(struct octeon_i2c *i2c)
 304 {
 305         int ret;
 306         u8 stat;
 307
 308         octeon_i2c_hlc_disable(i2c);
 309
 310         octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB | TWSI_CTL_STA);
 311         ret = octeon_i2c_wait(i2c);
 312         if (ret)
 313                 goto error;
 314
 315         stat = octeon_i2c_stat_read(i2c);
 316         if (stat == STAT_START || stat == STAT_REP_START)
 317                 /* START successful, bail out */
 318                 return 0;
 319
 320 error:
 321         /* START failed, try to recover */
 322         ret = octeon_i2c_recovery(i2c);
 323         return (ret) ? ret : -EAGAIN;
 324 }
 325
 326 /* send STOP to the bus */
 327 static void octeon_i2c_stop(struct octeon_i2c *i2c)
 328 {
 329         octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB | TWSI_CTL_STP);
 330 }
 331
 332 /**
 333  * octeon_i2c_read - receive data from the bus via low-level controller
 334  * @i2c: The struct octeon_i2c
 335  * @target: Target address
 336  * @data: Pointer to the location to store the data
 337  * @rlength: Length of the data
 338  * @recv_len: flag for length byte
 339  *
 340  * The address is sent over the bus, then the data is read.
 341  *
 342  * Returns 0 on success, otherwise a negative errno.
 343  */
 344 static int octeon_i2c_read(struct octeon_i2c *i2c, int target,
 345                            u8 *data, u16 *rlength, bool recv_len)
 346 {
 347         int i, result, length = *rlength;
 348         bool final_read = false;
 349
 350         octeon_i2c_data_write(i2c, (target << 1) | 1);
 351         octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
 352
 353         result = octeon_i2c_wait(i2c);
 354         if (result)
 355                 return result;
 356
 357         /* address OK ? */
 358         result = octeon_i2c_check_status(i2c, false);
 359         if (result)
 360                 return result;
 361
 362         for (i = 0; i < length; i++) {
 363                 /*
 364                  * For the last byte to receive TWSI_CTL_AAK must not be set.
 365                  *
 366                  * A special case is I2C_M_RECV_LEN where we don't know the
 367                  * additional length yet. If recv_len is set we assume we're
 368                  * not reading the final byte and therefore need to set
 369                  * TWSI_CTL_AAK.
 370                  */
 371                 if ((i + 1 == length) && !(recv_len && i == 0))
 372                         final_read = true;
 373
 374                 /* clear iflg to allow next event */
 375                 if (final_read)
 376                         octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
 377                 else
 378                         octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB | TWSI_CTL_AAK);
 379
 380                 result = octeon_i2c_wait(i2c);
 381                 if (result)
 382                         return result;
 383
 384                 data[i] = octeon_i2c_data_read(i2c, &result);
 385                 if (result)
 386                         return result;
 387                 if (recv_len && i == 0) {
 388                         if (data[i] > I2C_SMBUS_BLOCK_MAX + 1)
 389                                 return -EPROTO;
 390                         length += data[i];
 391                 }
 392
 393                 result = octeon_i2c_check_status(i2c, final_read);
 394                 if (result)
 395                         return result;
 396         }
 397         *rlength = length;
 398         return 0;
 399 }
 400
 401 /**
 402  * octeon_i2c_write - send data to the bus via low-level controller
 403  * @i2c: The struct octeon_i2c
 404  * @target: Target address
 405  * @data: Pointer to the data to be sent
 406  * @length: Length of the data
 407  *
 408  * The address is sent over the bus, then the data.
 409  *
 410  * Returns 0 on success, otherwise a negative errno.
 411  */
 412 static int octeon_i2c_write(struct octeon_i2c *i2c, int target,
 413                             const u8 *data, int length)
 414 {
 415         int i, result;
 416
 417         octeon_i2c_data_write(i2c, target << 1);
 418         octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
 419
 420         result = octeon_i2c_wait(i2c);
 421         if (result)
 422                 return result;
 423
 424         for (i = 0; i < length; i++) {
 425                 result = octeon_i2c_check_status(i2c, false);
 426                 if (result)
 427                         return result;
 428
 429                 octeon_i2c_data_write(i2c, data[i]);
 430                 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
 431
 432                 result = octeon_i2c_wait(i2c);
 433                 if (result)
 434                         return result;
 435         }
 436
 437         return 0;
 438 }
 439
 440 /* high-level-controller pure read of up to 8 bytes */
 441 static int octeon_i2c_hlc_read(struct octeon_i2c *i2c, struct i2c_msg *msgs)
 442 {
 443         int i, j, ret = 0;
 444         u64 cmd;
 445
 446         octeon_i2c_hlc_enable(i2c);
 447         octeon_i2c_hlc_int_clear(i2c);
 448
 449         cmd = SW_TWSI_V | SW_TWSI_R | SW_TWSI_SOVR;
 450         /* SIZE */
 451         cmd |= (u64)(msgs[0].len - 1) << SW_TWSI_SIZE_SHIFT;
 452         /* A */
 453         cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;
 454
 455         if (msgs[0].flags & I2C_M_TEN)
 456                 cmd |= SW_TWSI_OP_10;
 457         else
 458                 cmd |= SW_TWSI_OP_7;
 459
 460         octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI(i2c));
 461         ret = octeon_i2c_hlc_wait(i2c);
 462         if (ret)
 463                 goto err;
 464
 465         cmd = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));
 466         if ((cmd & SW_TWSI_R) == 0)
 467                 return octeon_i2c_check_status(i2c, false);
 468
 469         for (i = 0, j = msgs[0].len - 1; i  < msgs[0].len && i < 4; i++, j--)
 470                 msgs[0].buf[j] = (cmd >> (8 * i)) & 0xff;
 471
 472         if (msgs[0].len > 4) {
 473                 cmd = __raw_readq(i2c->twsi_base + SW_TWSI_EXT(i2c));
 474                 for (i = 0; i  < msgs[0].len - 4 && i < 4; i++, j--)
 475                         msgs[0].buf[j] = (cmd >> (8 * i)) & 0xff;
 476         }
 477
 478 err:
 479         return ret;
 480 }
 481
 482 /* high-level-controller pure write of up to 8 bytes */
 483 static int octeon_i2c_hlc_write(struct octeon_i2c *i2c, struct i2c_msg *msgs)
 484 {
 485         int i, j, ret = 0;
 486         u64 cmd;
 487
 488         octeon_i2c_hlc_enable(i2c);
 489         octeon_i2c_hlc_int_clear(i2c);
 490
 491         cmd = SW_TWSI_V | SW_TWSI_SOVR;
 492         /* SIZE */
 493         cmd |= (u64)(msgs[0].len - 1) << SW_TWSI_SIZE_SHIFT;
 494         /* A */
 495         cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;
 496
 497         if (msgs[0].flags & I2C_M_TEN)
 498                 cmd |= SW_TWSI_OP_10;
 499         else
 500                 cmd |= SW_TWSI_OP_7;
 501
 502         for (i = 0, j = msgs[0].len - 1; i  < msgs[0].len && i < 4; i++, j--)
 503                 cmd |= (u64)msgs[0].buf[j] << (8 * i);
 504
 505         if (msgs[0].len > 4) {
 506                 u64 ext = 0;
 507
 508                 for (i = 0; i < msgs[0].len - 4 && i < 4; i++, j--)
 509                         ext |= (u64)msgs[0].buf[j] << (8 * i);
 510                 octeon_i2c_writeq_flush(ext, i2c->twsi_base + SW_TWSI_EXT(i2c));
 511         }
 512
 513         octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI(i2c));
 514         ret = octeon_i2c_hlc_wait(i2c);
 515         if (ret)
 516                 goto err;
 517
 518         cmd = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));
 519         if ((cmd & SW_TWSI_R) == 0)
 520                 return octeon_i2c_check_status(i2c, false);
 521
 522 err:
 523         return ret;
 524 }
 525
 526 /* high-level-controller composite write+read, msg0=addr, msg1=data */
 527 static int octeon_i2c_hlc_comp_read(struct octeon_i2c *i2c, struct i2c_msg *msgs)
 528 {
 529         int i, j, ret = 0;
 530         u64 cmd;
 531
 532         octeon_i2c_hlc_enable(i2c);
 533
 534         cmd = SW_TWSI_V | SW_TWSI_R | SW_TWSI_SOVR;
 535         /* SIZE */
 536         cmd |= (u64)(msgs[1].len - 1) << SW_TWSI_SIZE_SHIFT;
 537         /* A */
 538         cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;
 539
 540         if (msgs[0].flags & I2C_M_TEN)
 541                 cmd |= SW_TWSI_OP_10_IA;
 542         else
 543                 cmd |= SW_TWSI_OP_7_IA;
 544
 545         if (msgs[0].len == 2) {
 546                 u64 ext = 0;
 547
 548                 cmd |= SW_TWSI_EIA;
 549                 ext = (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT;
 550                 cmd |= (u64)msgs[0].buf[1] << SW_TWSI_IA_SHIFT;
 551                 octeon_i2c_writeq_flush(ext, i2c->twsi_base + SW_TWSI_EXT(i2c));
 552         } else {
 553                 cmd |= (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT;
 554         }
 555
 556         octeon_i2c_hlc_int_clear(i2c);
 557         octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI(i2c));
 558
 559         ret = octeon_i2c_hlc_wait(i2c);
 560         if (ret)
 561                 goto err;
 562
 563         cmd = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));
 564         if ((cmd & SW_TWSI_R) == 0)
 565                 return octeon_i2c_check_status(i2c, false);
 566
 567         for (i = 0, j = msgs[1].len - 1; i  < msgs[1].len && i < 4; i++, j--)
 568                 msgs[1].buf[j] = (cmd >> (8 * i)) & 0xff;
 569
 570         if (msgs[1].len > 4) {
 571                 cmd = __raw_readq(i2c->twsi_base + SW_TWSI_EXT(i2c));
 572                 for (i = 0; i  < msgs[1].len - 4 && i < 4; i++, j--)
 573                         msgs[1].buf[j] = (cmd >> (8 * i)) & 0xff;
 574         }
 575
 576 err:
 577         return ret;
 578 }
 579
 580 /* high-level-controller composite write+write, m[0]len<=2, m[1]len<=8 */
 581 static int octeon_i2c_hlc_comp_write(struct octeon_i2c *i2c, struct i2c_msg *msgs)
 582 {
 583         bool set_ext = false;
 584         int i, j, ret = 0;
 585         u64 cmd, ext = 0;
 586
 587         octeon_i2c_hlc_enable(i2c);
 588
 589         cmd = SW_TWSI_V | SW_TWSI_SOVR;
 590         /* SIZE */
 591         cmd |= (u64)(msgs[1].len - 1) << SW_TWSI_SIZE_SHIFT;
 592         /* A */
 593         cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;
 594
 595         if (msgs[0].flags & I2C_M_TEN)
 596                 cmd |= SW_TWSI_OP_10_IA;
 597         else
 598                 cmd |= SW_TWSI_OP_7_IA;
 599
 600         if (msgs[0].len == 2) {
 601                 cmd |= SW_TWSI_EIA;
 602                 ext |= (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT;
 603                 set_ext = true;
 604                 cmd |= (u64)msgs[0].buf[1] << SW_TWSI_IA_SHIFT;
 605         } else {
 606                 cmd |= (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT;
 607         }
 608
 609         for (i = 0, j = msgs[1].len - 1; i  < msgs[1].len && i < 4; i++, j--)
 610                 cmd |= (u64)msgs[1].buf[j] << (8 * i);
 611
 612         if (msgs[1].len > 4) {
 613                 for (i = 0; i < msgs[1].len - 4 && i < 4; i++, j--)
 614                         ext |= (u64)msgs[1].buf[j] << (8 * i);
 615                 set_ext = true;
 616         }
 617         if (set_ext)
 618                 octeon_i2c_writeq_flush(ext, i2c->twsi_base + SW_TWSI_EXT(i2c));
 619
 620         octeon_i2c_hlc_int_clear(i2c);
 621         octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI(i2c));
 622
 623         ret = octeon_i2c_hlc_wait(i2c);
 624         if (ret)
 625                 goto err;
 626
 627         cmd = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));
 628         if ((cmd & SW_TWSI_R) == 0)
 629                 return octeon_i2c_check_status(i2c, false);
 630
 631 err:
 632         return ret;
 633 }
 634
 635 /**
 636  * octeon_i2c_xfer - The driver's master_xfer function
 637  * @adap: Pointer to the i2c_adapter structure
 638  * @msgs: Pointer to the messages to be processed
 639  * @num: Length of the MSGS array
 640  *
 641  * Returns the number of messages processed, or a negative errno on failure.
 642  */
 643 int octeon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
 644 {
 645         struct octeon_i2c *i2c = i2c_get_adapdata(adap);
 646         int i, ret = 0;
 647
 648         if (num == 1) {
 649                 if (msgs[0].len > 0 && msgs[0].len <= 8) {
 650                         if (msgs[0].flags & I2C_M_RD)
 651                                 ret = octeon_i2c_hlc_read(i2c, msgs);
 652                         else
 653                                 ret = octeon_i2c_hlc_write(i2c, msgs);
 654                         goto out;
 655                 }
 656         } else if (num == 2) {
 657                 if ((msgs[0].flags & I2C_M_RD) == 0 &&
 658                     (msgs[1].flags & I2C_M_RECV_LEN) == 0 &&
 659                     msgs[0].len > 0 && msgs[0].len <= 2 &&
 660                     msgs[1].len > 0 && msgs[1].len <= 8 &&
 661                     msgs[0].addr == msgs[1].addr) {
 662                         if (msgs[1].flags & I2C_M_RD)
 663                                 ret = octeon_i2c_hlc_comp_read(i2c, msgs);
 664                         else
 665                                 ret = octeon_i2c_hlc_comp_write(i2c, msgs);
 666                         goto out;
 667                 }
 668         }
 669
 670         for (i = 0; ret == 0 && i < num; i++) {
 671                 struct i2c_msg *pmsg = &msgs[i];
 672
 673                 /* zero-length messages are not supported */
 674                 if (!pmsg->len) {
 675                         ret = -EOPNOTSUPP;
 676                         break;
 677                 }
 678
 679                 ret = octeon_i2c_start(i2c);
 680                 if (ret)
 681                         return ret;
 682
 683                 if (pmsg->flags & I2C_M_RD)
 684                         ret = octeon_i2c_read(i2c, pmsg->addr, pmsg->buf,
 685                                               &pmsg->len, pmsg->flags & I2C_M_RECV_LEN);
 686                 else
 687                         ret = octeon_i2c_write(i2c, pmsg->addr, pmsg->buf,
 688                                                pmsg->len);
 689         }
 690         octeon_i2c_stop(i2c);
 691 out:
 692         return (ret != 0) ? ret : num;
 693 }
 694
 695 /* calculate and set clock divisors */
 696 void octeon_i2c_set_clock(struct octeon_i2c *i2c)
 697 {
 698         int tclk, thp_base, inc, thp_idx, mdiv_idx, ndiv_idx, foscl, diff;
 699         int thp = 0x18, mdiv = 2, ndiv = 0, delta_hz = 1000000;
 700
 701         for (ndiv_idx = 0; ndiv_idx < 8 && delta_hz != 0; ndiv_idx++) {
 702                 /*
 703                  * An mdiv value of less than 2 seems to not work well
 704                  * with ds1337 RTCs, so we constrain it to larger values.
 705                  */
 706                 for (mdiv_idx = 15; mdiv_idx >= 2 && delta_hz != 0; mdiv_idx--) {
 707                         /*
 708                          * For given ndiv and mdiv values check the
 709                          * two closest thp values.
 710                          */
 711                         tclk = i2c->twsi_freq * (mdiv_idx + 1) * 10;
 712                         tclk *= (1 << ndiv_idx);
 713                         thp_base = (i2c->sys_freq / (tclk * 2)) - 1;
 714
 715                         for (inc = 0; inc <= 1; inc++) {
 716                                 thp_idx = thp_base + inc;
 717                                 if (thp_idx < 5 || thp_idx > 0xff)
 718                                         continue;
 719
 720                                 foscl = i2c->sys_freq / (2 * (thp_idx + 1));
 721                                 foscl = foscl / (1 << ndiv_idx);
 722                                 foscl = foscl / (mdiv_idx + 1) / 10;
 723                                 diff = abs(foscl - i2c->twsi_freq);
 724                                 if (diff < delta_hz) {
 725                                         delta_hz = diff;
 726                                         thp = thp_idx;
 727                                         mdiv = mdiv_idx;
 728                                         ndiv = ndiv_idx;
 729                                 }
 730                         }
 731                 }
 732         }
 733         octeon_i2c_reg_write(i2c, SW_TWSI_OP_TWSI_CLK, thp);
 734         octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CLKCTL, (mdiv << 3) | ndiv);
 735 }
 736
 737 int octeon_i2c_init_lowlevel(struct octeon_i2c *i2c)
 738 {
 739         u8 status = 0;
 740         int tries;
 741
 742         /* reset controller */
 743         octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_RST, 0);
 744
 745         for (tries = 10; tries && status != STAT_IDLE; tries--) {
 746                 udelay(1);
 747                 status = octeon_i2c_stat_read(i2c);
 748                 if (status == STAT_IDLE)
 749                         break;
 750         }
 751
 752         if (status != STAT_IDLE) {
 753                 dev_err(i2c->dev, "%s: TWSI_RST failed! (0x%x)\n",
 754                         __func__, status);
 755                 return -EIO;
 756         }
 757
 758         /* toggle twice to force both teardowns */
 759         octeon_i2c_hlc_enable(i2c);
 760         octeon_i2c_hlc_disable(i2c);
 761         return 0;
 762 }
 763
 764 static int octeon_i2c_get_scl(struct i2c_adapter *adap)
 765 {
 766         struct octeon_i2c *i2c = i2c_get_adapdata(adap);
 767         u64 state;
 768
 769         state = octeon_i2c_read_int(i2c);
 770         return state & TWSI_INT_SCL;
 771 }
 772
 773 static void octeon_i2c_set_scl(struct i2c_adapter *adap, int val)
 774 {
 775         struct octeon_i2c *i2c = i2c_get_adapdata(adap);
 776
 777         octeon_i2c_write_int(i2c, val ? 0 : TWSI_INT_SCL_OVR);
 778 }
 779
 780 static int octeon_i2c_get_sda(struct i2c_adapter *adap)
 781 {
 782         struct octeon_i2c *i2c = i2c_get_adapdata(adap);
 783         u64 state;
 784
 785         state = octeon_i2c_read_int(i2c);
 786         return state & TWSI_INT_SDA;
 787 }
 788
 789 static void octeon_i2c_prepare_recovery(struct i2c_adapter *adap)
 790 {
 791         struct octeon_i2c *i2c = i2c_get_adapdata(adap);
 792
 793         octeon_i2c_hlc_disable(i2c);
 794
 795         /*
 796          * Bring control register to a good state regardless
 797          * of HLC state.
 798          */
 799         octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
 800
 801         octeon_i2c_write_int(i2c, 0);
 802 }
 803
 804 static void octeon_i2c_unprepare_recovery(struct i2c_adapter *adap)
 805 {
 806         struct octeon_i2c *i2c = i2c_get_adapdata(adap);
 807
 808         /*
 809          * Generate STOP to finish the unfinished transaction.
 810          * Can't generate STOP via the TWSI CTL register
 811          * since it could bring the TWSI controller into an inoperable state.
 812          */
 813         octeon_i2c_write_int(i2c, TWSI_INT_SDA_OVR | TWSI_INT_SCL_OVR);
 814         udelay(5);
 815         octeon_i2c_write_int(i2c, TWSI_INT_SDA_OVR);
 816         udelay(5);
 817         octeon_i2c_write_int(i2c, 0);
 818 }
 819
 820 struct i2c_bus_recovery_info octeon_i2c_recovery_info = {
 821         .recover_bus = i2c_generic_scl_recovery,
 822         .get_scl = octeon_i2c_get_scl,
 823         .set_scl = octeon_i2c_set_scl,
 824         .get_sda = octeon_i2c_get_sda,
 825         .prepare_recovery = octeon_i2c_prepare_recovery,
 826         .unprepare_recovery = octeon_i2c_unprepare_recovery,
 827 };