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gpio: rcar: Fix runtime PM imbalance on error
[linux/fpc-iii.git] / drivers / net / ethernet / dec / tulip / media.c
blobdcf21a36a9cf4864adb5fa8ab284f96d65265a68
1 /*
2 drivers/net/ethernet/dec/tulip/media.c
3
4 Copyright 2000,2001 The Linux Kernel Team
5 Written/copyright 1994-2001 by Donald Becker.
6
7 This software may be used and distributed according to the terms
8 of the GNU General Public License, incorporated herein by reference.
9
10 Please submit bugs to http://bugzilla.kernel.org/ .
11 */
12
13 #include <linux/kernel.h>
14 #include <linux/mii.h>
15 #include <linux/delay.h>
16 #include <linux/pci.h>
17 #include "tulip.h"
18
19
20 /* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
21 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
22 "overclocking" issues or future 66Mhz PCI. */
23 #define mdio_delay() ioread32(mdio_addr)
24
25 /* Read and write the MII registers using software-generated serial
26 MDIO protocol. It is just different enough from the EEPROM protocol
27 to not share code. The maxium data clock rate is 2.5 Mhz. */
28 #define MDIO_SHIFT_CLK 0x10000
29 #define MDIO_DATA_WRITE0 0x00000
30 #define MDIO_DATA_WRITE1 0x20000
31 #define MDIO_ENB 0x00000 /* Ignore the 0x02000 databook setting. */
32 #define MDIO_ENB_IN 0x40000
33 #define MDIO_DATA_READ 0x80000
34
35 static const unsigned char comet_miireg2offset[32] = {
36 0xB4, 0xB8, 0xBC, 0xC0, 0xC4, 0xC8, 0xCC, 0, 0,0,0,0, 0,0,0,0,
37 0,0xD0,0,0, 0,0,0,0, 0,0,0,0, 0, 0xD4, 0xD8, 0xDC, };
38
39
40 /* MII transceiver control section.
41 Read and write the MII registers using software-generated serial
42 MDIO protocol.
43 See IEEE 802.3-2002.pdf (Section 2, Chapter "22.2.4 Management functions")
44 or DP83840A data sheet for more details.
45 */
46
47 int tulip_mdio_read(struct net_device *dev, int phy_id, int location)
48 {
49 struct tulip_private *tp = netdev_priv(dev);
50 int i;
51 int read_cmd = (0xf6 << 10) | ((phy_id & 0x1f) << 5) | location;
52 int retval = 0;
53 void __iomem *ioaddr = tp->base_addr;
54 void __iomem *mdio_addr = ioaddr + CSR9;
55 unsigned long flags;
56
57 if (location & ~0x1f)
58 return 0xffff;
59
60 if (tp->chip_id == COMET && phy_id == 30) {
61 if (comet_miireg2offset[location])
62 return ioread32(ioaddr + comet_miireg2offset[location]);
63 return 0xffff;
64 }
65
66 spin_lock_irqsave(&tp->mii_lock, flags);
67 if (tp->chip_id == LC82C168) {
68 iowrite32(0x60020000 + (phy_id<<23) + (location<<18), ioaddr + 0xA0);
69 ioread32(ioaddr + 0xA0);
70 ioread32(ioaddr + 0xA0);
71 for (i = 1000; i >= 0; --i) {
72 barrier();
73 if ( ! ((retval = ioread32(ioaddr + 0xA0)) & 0x80000000))
74 break;
75 }
76 spin_unlock_irqrestore(&tp->mii_lock, flags);
77 return retval & 0xffff;
78 }
79
80 /* Establish sync by sending at least 32 logic ones. */
81 for (i = 32; i >= 0; i--) {
82 iowrite32(MDIO_ENB | MDIO_DATA_WRITE1, mdio_addr);
83 mdio_delay();
84 iowrite32(MDIO_ENB | MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr);
85 mdio_delay();
86 }
87 /* Shift the read command bits out. */
88 for (i = 15; i >= 0; i--) {
89 int dataval = (read_cmd & (1 << i)) ? MDIO_DATA_WRITE1 : 0;
90
91 iowrite32(MDIO_ENB | dataval, mdio_addr);
92 mdio_delay();
93 iowrite32(MDIO_ENB | dataval | MDIO_SHIFT_CLK, mdio_addr);
94 mdio_delay();
95 }
96 /* Read the two transition, 16 data, and wire-idle bits. */
97 for (i = 19; i > 0; i--) {
98 iowrite32(MDIO_ENB_IN, mdio_addr);
99 mdio_delay();
100 retval = (retval << 1) | ((ioread32(mdio_addr) & MDIO_DATA_READ) ? 1 : 0);
101 iowrite32(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
102 mdio_delay();
103 }
104
105 spin_unlock_irqrestore(&tp->mii_lock, flags);
106 return (retval>>1) & 0xffff;
107 }
108
109 void tulip_mdio_write(struct net_device *dev, int phy_id, int location, int val)
110 {
111 struct tulip_private *tp = netdev_priv(dev);
112 int i;
113 int cmd = (0x5002 << 16) | ((phy_id & 0x1f) << 23) | (location<<18) | (val & 0xffff);
114 void __iomem *ioaddr = tp->base_addr;
115 void __iomem *mdio_addr = ioaddr + CSR9;
116 unsigned long flags;
117
118 if (location & ~0x1f)
119 return;
120
121 if (tp->chip_id == COMET && phy_id == 30) {
122 if (comet_miireg2offset[location])
123 iowrite32(val, ioaddr + comet_miireg2offset[location]);
124 return;
125 }
126
127 spin_lock_irqsave(&tp->mii_lock, flags);
128 if (tp->chip_id == LC82C168) {
129 iowrite32(cmd, ioaddr + 0xA0);
130 for (i = 1000; i >= 0; --i) {
131 barrier();
132 if ( ! (ioread32(ioaddr + 0xA0) & 0x80000000))
133 break;
134 }
135 spin_unlock_irqrestore(&tp->mii_lock, flags);
136 return;
137 }
138
139 /* Establish sync by sending 32 logic ones. */
140 for (i = 32; i >= 0; i--) {
141 iowrite32(MDIO_ENB | MDIO_DATA_WRITE1, mdio_addr);
142 mdio_delay();
143 iowrite32(MDIO_ENB | MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr);
144 mdio_delay();
145 }
146 /* Shift the command bits out. */
147 for (i = 31; i >= 0; i--) {
148 int dataval = (cmd & (1 << i)) ? MDIO_DATA_WRITE1 : 0;
149 iowrite32(MDIO_ENB | dataval, mdio_addr);
150 mdio_delay();
151 iowrite32(MDIO_ENB | dataval | MDIO_SHIFT_CLK, mdio_addr);
152 mdio_delay();
153 }
154 /* Clear out extra bits. */
155 for (i = 2; i > 0; i--) {
156 iowrite32(MDIO_ENB_IN, mdio_addr);
157 mdio_delay();
158 iowrite32(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
159 mdio_delay();
160 }
161
162 spin_unlock_irqrestore(&tp->mii_lock, flags);
163 }
164
165
166 /* Set up the transceiver control registers for the selected media type. */
167 void tulip_select_media(struct net_device *dev, int startup)
168 {
169 struct tulip_private *tp = netdev_priv(dev);
170 void __iomem *ioaddr = tp->base_addr;
171 struct mediatable *mtable = tp->mtable;
172 u32 new_csr6;
173 int i;
174
175 if (mtable) {
176 struct medialeaf *mleaf = &mtable->mleaf[tp->cur_index];
177 unsigned char *p = mleaf->leafdata;
178 switch (mleaf->type) {
179 case 0: /* 21140 non-MII xcvr. */
180 if (tulip_debug > 1)
181 netdev_dbg(dev, "Using a 21140 non-MII transceiver with control setting %02x\n",
182 p[1]);
183 dev->if_port = p[0];
184 if (startup)
185 iowrite32(mtable->csr12dir | 0x100, ioaddr + CSR12);
186 iowrite32(p[1], ioaddr + CSR12);
187 new_csr6 = 0x02000000 | ((p[2] & 0x71) << 18);
188 break;
189 case 2: case 4: {
190 u16 setup[5];
191 u32 csr13val, csr14val, csr15dir, csr15val;
192 for (i = 0; i < 5; i++)
193 setup[i] = get_u16(&p[i*2 + 1]);
194
195 dev->if_port = p[0] & MEDIA_MASK;
196 if (tulip_media_cap[dev->if_port] & MediaAlwaysFD)
197 tp->full_duplex = 1;
198
199 if (startup && mtable->has_reset) {
200 struct medialeaf *rleaf = &mtable->mleaf[mtable->has_reset];
201 unsigned char *rst = rleaf->leafdata;
202 if (tulip_debug > 1)
203 netdev_dbg(dev, "Resetting the transceiver\n");
204 for (i = 0; i < rst[0]; i++)
205 iowrite32(get_u16(rst + 1 + (i<<1)) << 16, ioaddr + CSR15);
206 }
207 if (tulip_debug > 1)
208 netdev_dbg(dev, "21143 non-MII %s transceiver control %04x/%04x\n",
209 medianame[dev->if_port],
210 setup[0], setup[1]);
211 if (p[0] & 0x40) { /* SIA (CSR13-15) setup values are provided. */
212 csr13val = setup[0];
213 csr14val = setup[1];
214 csr15dir = (setup[3]<<16) | setup[2];
215 csr15val = (setup[4]<<16) | setup[2];
216 iowrite32(0, ioaddr + CSR13);
217 iowrite32(csr14val, ioaddr + CSR14);
218 iowrite32(csr15dir, ioaddr + CSR15); /* Direction */
219 iowrite32(csr15val, ioaddr + CSR15); /* Data */
220 iowrite32(csr13val, ioaddr + CSR13);
221 } else {
222 csr13val = 1;
223 csr14val = 0;
224 csr15dir = (setup[0]<<16) | 0x0008;
225 csr15val = (setup[1]<<16) | 0x0008;
226 if (dev->if_port <= 4)
227 csr14val = t21142_csr14[dev->if_port];
228 if (startup) {
229 iowrite32(0, ioaddr + CSR13);
230 iowrite32(csr14val, ioaddr + CSR14);
231 }
232 iowrite32(csr15dir, ioaddr + CSR15); /* Direction */
233 iowrite32(csr15val, ioaddr + CSR15); /* Data */
234 if (startup) iowrite32(csr13val, ioaddr + CSR13);
235 }
236 if (tulip_debug > 1)
237 netdev_dbg(dev, "Setting CSR15 to %08x/%08x\n",
238 csr15dir, csr15val);
239 if (mleaf->type == 4)
240 new_csr6 = 0x82020000 | ((setup[2] & 0x71) << 18);
241 else
242 new_csr6 = 0x82420000;
243 break;
244 }
245 case 1: case 3: {
246 int phy_num = p[0];
247 int init_length = p[1];
248 u16 *misc_info, tmp_info;
249
250 dev->if_port = 11;
251 new_csr6 = 0x020E0000;
252 if (mleaf->type == 3) { /* 21142 */
253 u16 *init_sequence = (u16*)(p+2);
254 u16 *reset_sequence = &((u16*)(p+3))[init_length];
255 int reset_length = p[2 + init_length*2];
256 misc_info = reset_sequence + reset_length;
257 if (startup) {
258 int timeout = 10; /* max 1 ms */
259 for (i = 0; i < reset_length; i++)
260 iowrite32(get_u16(&reset_sequence[i]) << 16, ioaddr + CSR15);
261
262 /* flush posted writes */
263 ioread32(ioaddr + CSR15);
264
265 /* Sect 3.10.3 in DP83840A.pdf (p39) */
266 udelay(500);
267
268 /* Section 4.2 in DP83840A.pdf (p43) */
269 /* and IEEE 802.3 "22.2.4.1.1 Reset" */
270 while (timeout-- &&
271 (tulip_mdio_read (dev, phy_num, MII_BMCR) & BMCR_RESET))
272 udelay(100);
273 }
274 for (i = 0; i < init_length; i++)
275 iowrite32(get_u16(&init_sequence[i]) << 16, ioaddr + CSR15);
276
277 ioread32(ioaddr + CSR15); /* flush posted writes */
278 } else {
279 u8 *init_sequence = p + 2;
280 u8 *reset_sequence = p + 3 + init_length;
281 int reset_length = p[2 + init_length];
282 misc_info = (u16*)(reset_sequence + reset_length);
283 if (startup) {
284 int timeout = 10; /* max 1 ms */
285 iowrite32(mtable->csr12dir | 0x100, ioaddr + CSR12);
286 for (i = 0; i < reset_length; i++)
287 iowrite32(reset_sequence[i], ioaddr + CSR12);
288
289 /* flush posted writes */
290 ioread32(ioaddr + CSR12);
291
292 /* Sect 3.10.3 in DP83840A.pdf (p39) */
293 udelay(500);
294
295 /* Section 4.2 in DP83840A.pdf (p43) */
296 /* and IEEE 802.3 "22.2.4.1.1 Reset" */
297 while (timeout-- &&
298 (tulip_mdio_read (dev, phy_num, MII_BMCR) & BMCR_RESET))
299 udelay(100);
300 }
301 for (i = 0; i < init_length; i++)
302 iowrite32(init_sequence[i], ioaddr + CSR12);
303
304 ioread32(ioaddr + CSR12); /* flush posted writes */
305 }
306
307 tmp_info = get_u16(&misc_info[1]);
308 if (tmp_info)
309 tp->advertising[phy_num] = tmp_info | 1;
310 if (tmp_info && startup < 2) {
311 if (tp->mii_advertise == 0)
312 tp->mii_advertise = tp->advertising[phy_num];
313 if (tulip_debug > 1)
314 netdev_dbg(dev, " Advertising %04x on MII %d\n",
315 tp->mii_advertise,
316 tp->phys[phy_num]);
317 tulip_mdio_write(dev, tp->phys[phy_num], 4, tp->mii_advertise);
318 }
319 break;
320 }
321 case 5: case 6: {
322 u16 setup[5];
323
324 new_csr6 = 0; /* FIXME */
325
326 for (i = 0; i < 5; i++)
327 setup[i] = get_u16(&p[i*2 + 1]);
328
329 if (startup && mtable->has_reset) {
330 struct medialeaf *rleaf = &mtable->mleaf[mtable->has_reset];
331 unsigned char *rst = rleaf->leafdata;
332 if (tulip_debug > 1)
333 netdev_dbg(dev, "Resetting the transceiver\n");
334 for (i = 0; i < rst[0]; i++)
335 iowrite32(get_u16(rst + 1 + (i<<1)) << 16, ioaddr + CSR15);
336 }
337
338 break;
339 }
340 default:
341 netdev_dbg(dev, " Invalid media table selection %d\n",
342 mleaf->type);
343 new_csr6 = 0x020E0000;
344 }
345 if (tulip_debug > 1)
346 netdev_dbg(dev, "Using media type %s, CSR12 is %02x\n",
347 medianame[dev->if_port],
348 ioread32(ioaddr + CSR12) & 0xff);
349 } else if (tp->chip_id == LC82C168) {
350 if (startup && ! tp->medialock)
351 dev->if_port = tp->mii_cnt ? 11 : 0;
352 if (tulip_debug > 1)
353 netdev_dbg(dev, "PNIC PHY status is %3.3x, media %s\n",
354 ioread32(ioaddr + 0xB8),
355 medianame[dev->if_port]);
356 if (tp->mii_cnt) {
357 new_csr6 = 0x810C0000;
358 iowrite32(0x0001, ioaddr + CSR15);
359 iowrite32(0x0201B07A, ioaddr + 0xB8);
360 } else if (startup) {
361 /* Start with 10mbps to do autonegotiation. */
362 iowrite32(0x32, ioaddr + CSR12);
363 new_csr6 = 0x00420000;
364 iowrite32(0x0001B078, ioaddr + 0xB8);
365 iowrite32(0x0201B078, ioaddr + 0xB8);
366 } else if (dev->if_port == 3 || dev->if_port == 5) {
367 iowrite32(0x33, ioaddr + CSR12);
368 new_csr6 = 0x01860000;
369 /* Trigger autonegotiation. */
370 iowrite32(startup ? 0x0201F868 : 0x0001F868, ioaddr + 0xB8);
371 } else {
372 iowrite32(0x32, ioaddr + CSR12);
373 new_csr6 = 0x00420000;
374 iowrite32(0x1F078, ioaddr + 0xB8);
375 }
376 } else { /* Unknown chip type with no media table. */
377 if (tp->default_port == 0)
378 dev->if_port = tp->mii_cnt ? 11 : 3;
379 if (tulip_media_cap[dev->if_port] & MediaIsMII) {
380 new_csr6 = 0x020E0000;
381 } else if (tulip_media_cap[dev->if_port] & MediaIsFx) {
382 new_csr6 = 0x02860000;
383 } else
384 new_csr6 = 0x03860000;
385 if (tulip_debug > 1)
386 netdev_dbg(dev, "No media description table, assuming %s transceiver, CSR12 %02x\n",
387 medianame[dev->if_port],
388 ioread32(ioaddr + CSR12));
389 }
390
391 tp->csr6 = new_csr6 | (tp->csr6 & 0xfdff) | (tp->full_duplex ? 0x0200 : 0);
392
393 mdelay(1);
394 }
395
396 /*
397 Check the MII negotiated duplex and change the CSR6 setting if
398 required.
399 Return 0 if everything is OK.
400 Return < 0 if the transceiver is missing or has no link beat.
401 */
402 int tulip_check_duplex(struct net_device *dev)
403 {
404 struct tulip_private *tp = netdev_priv(dev);
405 unsigned int bmsr, lpa, negotiated, new_csr6;
406
407 bmsr = tulip_mdio_read(dev, tp->phys[0], MII_BMSR);
408 lpa = tulip_mdio_read(dev, tp->phys[0], MII_LPA);
409 if (tulip_debug > 1)
410 dev_info(&dev->dev, "MII status %04x, Link partner report %04x\n",
411 bmsr, lpa);
412 if (bmsr == 0xffff)
413 return -2;
414 if ((bmsr & BMSR_LSTATUS) == 0) {
415 int new_bmsr = tulip_mdio_read(dev, tp->phys[0], MII_BMSR);
416 if ((new_bmsr & BMSR_LSTATUS) == 0) {
417 if (tulip_debug > 1)
418 dev_info(&dev->dev,
419 "No link beat on the MII interface, status %04x\n",
420 new_bmsr);
421 return -1;
422 }
423 }
424 negotiated = lpa & tp->advertising[0];
425 tp->full_duplex = mii_duplex(tp->full_duplex_lock, negotiated);
426
427 new_csr6 = tp->csr6;
428
429 if (negotiated & LPA_100) new_csr6 &= ~TxThreshold;
430 else new_csr6 |= TxThreshold;
431 if (tp->full_duplex) new_csr6 |= FullDuplex;
432 else new_csr6 &= ~FullDuplex;
433
434 if (new_csr6 != tp->csr6) {
435 tp->csr6 = new_csr6;
436 tulip_restart_rxtx(tp);
437
438 if (tulip_debug > 0)
439 dev_info(&dev->dev,
440 "Setting %s-duplex based on MII#%d link partner capability of %04x\n",
441 tp->full_duplex ? "full" : "half",
442 tp->phys[0], lpa);
443 return 1;
444 }
445
446 return 0;
447 }
448
449 void tulip_find_mii(struct net_device *dev, int board_idx)
450 {
451 struct tulip_private *tp = netdev_priv(dev);
452 int phyn, phy_idx = 0;
453 int mii_reg0;
454 int mii_advert;
455 unsigned int to_advert, new_bmcr, ane_switch;
456
457 /* Find the connected MII xcvrs.
458 Doing this in open() would allow detecting external xcvrs later,
459 but takes much time. */
460 for (phyn = 1; phyn <= 32 && phy_idx < ARRAY_SIZE(tp->phys); phyn++) {
461 int phy = phyn & 0x1f;
462 int mii_status = tulip_mdio_read (dev, phy, MII_BMSR);
463 if ((mii_status & 0x8301) == 0x8001 ||
464 ((mii_status & BMSR_100BASE4) == 0 &&
465 (mii_status & 0x7800) != 0)) {
466 /* preserve Becker logic, gain indentation level */
467 } else {
468 continue;
469 }
470
471 mii_reg0 = tulip_mdio_read (dev, phy, MII_BMCR);
472 mii_advert = tulip_mdio_read (dev, phy, MII_ADVERTISE);
473 ane_switch = 0;
474
475 /* if not advertising at all, gen an
476 * advertising value from the capability
477 * bits in BMSR
478 */
479 if ((mii_advert & ADVERTISE_ALL) == 0) {
480 unsigned int tmpadv = tulip_mdio_read (dev, phy, MII_BMSR);
481 mii_advert = ((tmpadv >> 6) & 0x3e0) | 1;
482 }
483
484 if (tp->mii_advertise) {
485 tp->advertising[phy_idx] =
486 to_advert = tp->mii_advertise;
487 } else if (tp->advertising[phy_idx]) {
488 to_advert = tp->advertising[phy_idx];
489 } else {
490 tp->advertising[phy_idx] =
491 tp->mii_advertise =
492 to_advert = mii_advert;
493 }
494
495 tp->phys[phy_idx++] = phy;
496
497 pr_info("tulip%d: MII transceiver #%d config %04x status %04x advertising %04x\n",
498 board_idx, phy, mii_reg0, mii_status, mii_advert);
499
500 /* Fixup for DLink with miswired PHY. */
501 if (mii_advert != to_advert) {
502 pr_debug("tulip%d: Advertising %04x on PHY %d, previously advertising %04x\n",
503 board_idx, to_advert, phy, mii_advert);
504 tulip_mdio_write (dev, phy, 4, to_advert);
505 }
506
507 /* Enable autonegotiation: some boards default to off. */
508 if (tp->default_port == 0) {
509 new_bmcr = mii_reg0 | BMCR_ANENABLE;
510 if (new_bmcr != mii_reg0) {
511 new_bmcr |= BMCR_ANRESTART;
512 ane_switch = 1;
513 }
514 }
515 /* ...or disable nway, if forcing media */
516 else {
517 new_bmcr = mii_reg0 & ~BMCR_ANENABLE;
518 if (new_bmcr != mii_reg0)
519 ane_switch = 1;
520 }
521
522 /* clear out bits we never want at this point */
523 new_bmcr &= ~(BMCR_CTST | BMCR_FULLDPLX | BMCR_ISOLATE |
524 BMCR_PDOWN | BMCR_SPEED100 | BMCR_LOOPBACK |
525 BMCR_RESET);
526
527 if (tp->full_duplex)
528 new_bmcr |= BMCR_FULLDPLX;
529 if (tulip_media_cap[tp->default_port] & MediaIs100)
530 new_bmcr |= BMCR_SPEED100;
531
532 if (new_bmcr != mii_reg0) {
533 /* some phys need the ANE switch to
534 * happen before forced media settings
535 * will "take." However, we write the
536 * same value twice in order not to
537 * confuse the sane phys.
538 */
539 if (ane_switch) {
540 tulip_mdio_write (dev, phy, MII_BMCR, new_bmcr);
541 udelay (10);
542 }
543 tulip_mdio_write (dev, phy, MII_BMCR, new_bmcr);
544 }
545 }
546 tp->mii_cnt = phy_idx;
547 if (tp->mtable && tp->mtable->has_mii && phy_idx == 0) {
548 pr_info("tulip%d: ***WARNING***: No MII transceiver found!\n",
549 board_idx);
550 tp->phys[0] = 1;
551 }
552 }
Linux with added FPC-III support