| blob | 177c6da80c576f06b73c7754d4a68a350379c22c |
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
6 #include <linux/module.h>
7 #include <linux/types.h>
8 #include <linux/init.h>
9 #include <linux/pci.h>
10 #include <linux/vmalloc.h>
11 #include <linux/pagemap.h>
12 #include <linux/delay.h>
13 #include <linux/netdevice.h>
14 #include <linux/interrupt.h>
15 #include <linux/tcp.h>
16 #include <linux/ipv6.h>
17 #include <linux/slab.h>
18 #include <net/checksum.h>
19 #include <net/ip6_checksum.h>
20 #include <linux/ethtool.h>
21 #include <linux/if_vlan.h>
22 #include <linux/cpu.h>
23 #include <linux/smp.h>
24 #include <linux/pm_qos.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/aer.h>
27 #include <linux/prefetch.h>
37 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
57 };
60 u32 ofs;
62 };
65 /* General Registers */
70 /* Interrupt Registers */
73 /* Rx Registers */
89 /* Tx Registers */
106 /* List Terminator */
108 };
110 /**
111 * __ew32_prepare - prepare to write to MAC CSR register on certain parts
112 * @hw: pointer to the HW structure
113 *
114 * When updating the MAC CSR registers, the Manageability Engine (ME) could
115 * be accessing the registers at the same time. Normally, this is handled in
116 * h/w by an arbiter but on some parts there is a bug that acknowledges Host
117 * accesses later than it should which could result in the register to have
118 * an incorrect value. Workaround this by checking the FWSM register which
119 * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set
120 * and try again a number of times.
121 **/
123 {
130 }
133 {
138 }
140 /**
141 * e1000_regdump - register printout routine
142 * @hw: pointer to the HW structure
143 * @reginfo: pointer to the register info table
144 **/
146 {
168 }
172 }
176 {
188 }
189 }
190 }
192 /**
193 * e1000e_dump - Print registers, Tx-ring and Rx-ring
194 * @adapter: board private structure
195 **/
197 {
204 __le64 a;
205 __le64 b;
212 __le64 a;
213 __le64 b;
214 __le64 c;
215 __le64 d;
217 u32 staterr;
223 /* Print netdevice Info */
229 }
231 /* Print Registers */
237 }
239 /* Print Tx Ring Summary */
253 /* Print Tx Ring */
259 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended)
260 *
261 * Legacy Transmit Descriptor
262 * +--------------------------------------------------------------+
263 * 0 | Buffer Address [63:0] (Reserved on Write Back) |
264 * +--------------------------------------------------------------+
265 * 8 | Special | CSS | Status | CMD | CSO | Length |
266 * +--------------------------------------------------------------+
267 * 63 48 47 36 35 32 31 24 23 16 15 0
268 *
269 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload
270 * 63 48 47 40 39 32 31 16 15 8 7 0
271 * +----------------------------------------------------------------+
272 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS |
273 * +----------------------------------------------------------------+
274 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN |
275 * +----------------------------------------------------------------+
276 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
277 *
278 * Extended Data Descriptor (DTYP=0x1)
279 * +----------------------------------------------------------------+
280 * 0 | Buffer Address [63:0] |
281 * +----------------------------------------------------------------+
282 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN |
283 * +----------------------------------------------------------------+
284 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
285 */
286 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n");
287 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n");
288 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n");
300 else
305 i,
317 }
319 /* Print Rx Ring Summary */
320 rx_ring_summary:
326 /* Print Rx Ring */
335 /* [Extended] Packet Split Receive Descriptor Format
336 *
337 * +-----------------------------------------------------+
338 * 0 | Buffer Address 0 [63:0] |
339 * +-----------------------------------------------------+
340 * 8 | Buffer Address 1 [63:0] |
341 * +-----------------------------------------------------+
342 * 16 | Buffer Address 2 [63:0] |
343 * +-----------------------------------------------------+
344 * 24 | Buffer Address 3 [63:0] |
345 * +-----------------------------------------------------+
346 */
347 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n");
348 /* [Extended] Receive Descriptor (Write-Back) Format
349 *
350 * 63 48 47 32 31 13 12 8 7 4 3 0
351 * +------------------------------------------------------+
352 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS |
353 * | Checksum | Ident | | Queue | | Type |
354 * +------------------------------------------------------+
355 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
356 * +------------------------------------------------------+
357 * 63 48 47 32 31 20 19 0
358 */
359 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n");
365 staterr =
372 else
376 /* Descriptor Done */
396 buffer_info);
397 }
398 }
402 /* Extended Receive Descriptor (Read) Format
403 *
404 * +-----------------------------------------------------+
405 * 0 | Buffer Address [63:0] |
406 * +-----------------------------------------------------+
407 * 8 | Reserved |
408 * +-----------------------------------------------------+
409 */
410 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n");
411 /* Extended Receive Descriptor (Write-Back) Format
412 *
413 * 63 48 47 32 31 24 23 4 3 0
414 * +------------------------------------------------------+
415 * | RSS Hash | | | |
416 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS |
417 * | Packet | IP | | | Type |
418 * | Checksum | Ident | | | |
419 * +------------------------------------------------------+
420 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
421 * +------------------------------------------------------+
422 * 63 48 47 32 31 20 19 0
423 */
438 else
442 /* Descriptor Done */
464 }
465 }
466 }
467 }
469 /**
470 * e1000_desc_unused - calculate if we have unused descriptors
471 **/
473 {
478 }
480 /**
481 * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp
482 * @adapter: board private structure
483 * @hwtstamps: time stamp structure to update
484 * @systim: unsigned 64bit system time value.
485 *
486 * Convert the system time value stored in the RX/TXSTMP registers into a
487 * hwtstamp which can be used by the upper level time stamping functions.
488 *
489 * The 'systim_lock' spinlock is used to protect the consistency of the
490 * system time value. This is needed because reading the 64 bit time
491 * value involves reading two 32 bit registers. The first read latches the
492 * value.
493 **/
496 u64 systim)
497 {
498 u64 ns;
507 }
509 /**
510 * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp
511 * @adapter: board private structure
512 * @status: descriptor extended error and status field
513 * @skb: particular skb to include time stamp
514 *
515 * If the time stamp is valid, convert it into the timecounter ns value
516 * and store that result into the shhwtstamps structure which is passed
517 * up the network stack.
518 **/
521 {
523 u64 rxstmp;
530 /* The Rx time stamp registers contain the time stamp. No other
531 * received packet will be time stamped until the Rx time stamp
532 * registers are read. Because only one packet can be time stamped
533 * at a time, the register values must belong to this packet and
534 * therefore none of the other additional attributes need to be
535 * compared.
536 */
542 }
544 /**
545 * e1000_receive_skb - helper function to handle Rx indications
546 * @adapter: board private structure
547 * @staterr: descriptor extended error and status field as written by hardware
548 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
549 * @skb: pointer to sk_buff to be indicated to stack
550 **/
554 {
565 }
567 /**
568 * e1000_rx_checksum - Receive Checksum Offload
569 * @adapter: board private structure
570 * @status_err: receive descriptor status and error fields
571 * @csum: receive descriptor csum field
572 * @sk_buff: socket buffer with received data
573 **/
576 {
582 /* Rx checksum disabled */
586 /* Ignore Checksum bit is set */
590 /* TCP/UDP checksum error bit or IP checksum error bit is set */
592 /* let the stack verify checksum errors */
595 }
597 /* TCP/UDP Checksum has not been calculated */
601 /* It must be a TCP or UDP packet with a valid checksum */
604 }
607 {
620 }
621 }
624 {
637 }
638 }
640 /**
641 * e1000_alloc_rx_buffers - Replace used receive buffers
642 * @rx_ring: Rx descriptor ring
643 **/
646 {
664 }
668 /* Better luck next round */
671 }
674 map_skb:
677 DMA_FROM_DEVICE);
682 }
688 /* Force memory writes to complete before letting h/w
689 * know there are new descriptors to fetch. (Only
690 * applicable for weak-ordered memory model archs,
691 * such as IA-64).
692 */
696 else
698 }
699 i++;
703 }
706 }
708 /**
709 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
710 * @rx_ring: Rx descriptor ring
711 **/
714 {
733 /* all unused desc entries get hw null ptr */
737 }
743 }
747 DMA_FROM_DEVICE);
754 }
755 }
756 /* Refresh the desc even if buffer_addrs
757 * didn't change because each write-back
758 * erases this info.
759 */
762 }
765 gfp);
770 }
775 DMA_FROM_DEVICE);
779 /* cleanup skb */
783 }
788 /* Force memory writes to complete before letting h/w
789 * know there are new descriptors to fetch. (Only
790 * applicable for weak-ordered memory model archs,
791 * such as IA-64).
792 */
796 else
798 }
800 i++;
804 }
806 no_buffers:
808 }
810 /**
811 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers
812 * @rx_ring: Rx descriptor ring
813 * @cleaned_count: number of buffers to allocate this pass
814 **/
818 {
836 }
840 /* Better luck next round */
843 }
846 check_page:
847 /* allocate a new page if necessary */
853 }
854 }
859 PAGE_SIZE,
860 DMA_FROM_DEVICE);
864 }
865 }
873 }
880 /* Force memory writes to complete before letting h/w
881 * know there are new descriptors to fetch. (Only
882 * applicable for weak-ordered memory model archs,
883 * such as IA-64).
884 */
888 else
890 }
891 }
895 {
898 }
900 /**
901 * e1000_clean_rx_irq - Send received data up the network stack
902 * @rx_ring: Rx descriptor ring
903 *
904 * the return value indicates whether actual cleaning was done, there
905 * is no guarantee that everything was cleaned
906 **/
909 {
940 i++;
949 cleaned_count++;
956 /* !EOP means multiple descriptors were used to store a single
957 * packet, if that's the case we need to toss it. In fact, we
958 * need to toss every packet with the EOP bit clear and the
959 * next frame that _does_ have the EOP bit set, as it is by
960 * definition only a frame fragment
961 */
966 /* All receives must fit into a single buffer */
968 /* recycle */
973 }
977 /* recycle */
980 }
982 /* adjust length to remove Ethernet CRC */
984 /* If configured to store CRC, don't subtract FCS,
985 * but keep the FCS bytes out of the total_rx_bytes
986 * counter
987 */
990 else
992 }
995 total_rx_packets++;
997 /* code added for copybreak, this should improve
998 * performance for small packets with large amounts
999 * of reassembly being done in the stack
1000 */
1008 NET_IP_ALIGN),
1010 NET_IP_ALIGN));
1011 /* save the skb in buffer_info as good */
1014 }
1015 /* else just continue with the old one */
1016 }
1017 /* end copybreak code */
1020 /* Receive Checksum Offload */
1028 next_desc:
1031 /* return some buffers to hardware, one at a time is too slow */
1034 GFP_ATOMIC);
1036 }
1038 /* use prefetched values */
1043 }
1053 }
1058 {
1065 else
1069 }
1073 else
1076 }
1078 }
1081 {
1084 print_hang_task);
1092 u16 pci_status;
1098 /* May be block on write-back, flush and detect again
1099 * flush pending descriptor writebacks to memory
1100 */
1102 /* execute the writes immediately */
1104 /* Due to rare timing issues, write to TIDV again to ensure
1105 * the write is successful
1106 */
1108 /* execute the writes immediately */
1112 }
1118 }
1120 /* Real hang detected */
1129 /* detected Hardware unit hang */
1152 /* Suggest workaround for known h/w issue */
1155 }
1157 /**
1158 * e1000e_tx_hwtstamp_work - check for Tx time stamp
1159 * @work: pointer to work struct
1160 *
1161 * This work function polls the TSYNCTXCTL valid bit to determine when a
1162 * timestamp has been taken for the current stored skb. The timestamp must
1163 * be for this skb because only one such packet is allowed in the queue.
1164 */
1166 {
1168 tx_hwtstamp_work);
1174 u64 txstmp;
1181 /* Clear the global tx_hwtstamp_skb pointer and force writes
1182 * prior to notifying the stack of a Tx timestamp.
1183 */
1196 /* reschedule to check later */
1198 }
1199 }
1201 /**
1202 * e1000_clean_tx_irq - Reclaim resources after transmit completes
1203 * @tx_ring: Tx descriptor ring
1204 *
1205 * the return value indicates whether actual cleaning was done, there
1206 * is no guarantee that everything was cleaned
1207 **/
1209 {
1239 pkts_compl++;
1240 }
1241 }
1246 i++;
1249 }
1255 }
1261 #define TX_WAKE_THRESHOLD 32
1264 /* Make sure that anybody stopping the queue after this
1265 * sees the new next_to_clean.
1266 */
1273 }
1274 }
1277 /* Detect a transmit hang in hardware, this serializes the
1278 * check with the clearing of time_stamp and movement of i
1279 */
1286 else
1288 }
1292 }
1294 /**
1295 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
1296 * @rx_ring: Rx descriptor ring
1297 *
1298 * the return value indicates whether actual cleaning was done, there
1299 * is no guarantee that everything was cleaned
1300 **/
1303 {
1330 /* in the packet split case this is header only */
1333 i++;
1342 cleaned_count++;
1347 /* see !EOP comment in other Rx routine */
1357 }
1363 }
1371 }
1373 /* Good Receive */
1376 {
1377 /* this looks ugly, but it seems compiler issues make
1378 * it more efficient than reusing j
1379 */
1382 /* page alloc/put takes too long and effects small
1383 * packet throughput, so unsplit small packets and
1384 * save the alloc/put only valid in softirq (napi)
1385 * context to call kmap_*
1386 */
1393 /* there is no documentation about how to call
1394 * kmap_atomic, so we can't hold the mapping
1395 * very long
1396 */
1399 PAGE_SIZE,
1400 DMA_FROM_DEVICE);
1406 PAGE_SIZE,
1407 DMA_FROM_DEVICE);
1409 /* remove the CRC */
1413 }
1418 }
1427 DMA_FROM_DEVICE);
1434 }
1436 /* strip the ethernet crc, problem is we're using pages now so
1437 * this whole operation can get a little cpu intensive
1438 */
1442 }
1444 copydone:
1446 total_rx_packets++;
1459 next_desc:
1463 /* return some buffers to hardware, one at a time is too slow */
1466 GFP_ATOMIC);
1468 }
1470 /* use prefetched values */
1475 }
1485 }
1487 /**
1488 * e1000_consume_page - helper function
1489 **/
1491 u16 length)
1492 {
1497 }
1499 /**
1500 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy
1501 * @adapter: board private structure
1502 *
1503 * the return value indicates whether actual cleaning was done, there
1504 * is no guarantee that everything was cleaned
1505 **/
1508 {
1546 cleaned_count++;
1548 DMA_FROM_DEVICE);
1553 /* errors is only valid for DD + EOP descriptors */
1557 /* recycle both page and skb */
1559 /* an error means any chain goes out the window too */
1564 }
1565 #define rxtop (rx_ring->rx_skb_top)
1567 /* this descriptor is only the beginning (or middle) */
1569 /* this is the beginning of a chain */
1574 /* this is the middle of a chain */
1578 length);
1579 /* re-use the skb, only consumed the page */
1581 }
1586 /* end of the chain */
1590 length);
1591 /* re-use the current skb, we only consumed the
1592 * page
1593 */
1599 /* no chain, got EOP, this buf is the packet
1600 * copybreak to save the put_page/alloc_page
1601 */
1607 length);
1609 /* re-use the page, so don't erase
1610 * buffer_info->page
1611 */
1616 length);
1618 length);
1619 }
1620 }
1621 }
1623 /* Receive Checksum Offload */
1628 /* probably a little skewed due to removing CRC */
1630 total_rx_packets++;
1632 /* eth type trans needs skb->data to point to something */
1637 }
1642 next_desc:
1645 /* return some buffers to hardware, one at a time is too slow */
1648 GFP_ATOMIC);
1650 }
1652 /* use prefetched values */
1657 }
1667 }
1669 /**
1670 * e1000_clean_rx_ring - Free Rx Buffers per Queue
1671 * @rx_ring: Rx descriptor ring
1672 **/
1674 {
1681 /* Free all the Rx ring sk_buffs */
1688 DMA_FROM_DEVICE);
1695 DMA_FROM_DEVICE);
1697 }
1702 }
1707 }
1714 DMA_FROM_DEVICE);
1718 }
1719 }
1721 /* there also may be some cached data from a chained receive */
1725 }
1727 /* Zero out the descriptor ring */
1733 }
1736 {
1739 downshift_task);
1745 }
1747 /**
1748 * e1000_intr_msi - Interrupt Handler
1749 * @irq: interrupt number
1750 * @data: pointer to a network interface device structure
1751 **/
1753 {
1759 /* read ICR disables interrupts using IAM */
1762 /* ICH8 workaround-- Call gig speed drop workaround on cable
1763 * disconnect (LSC) before accessing any PHY registers
1764 */
1769 /* 80003ES2LAN workaround-- For packet buffer work-around on
1770 * link down event; disable receives here in the ISR and reset
1771 * adapter in watchdog
1772 */
1775 /* disable receives */
1780 }
1781 /* guard against interrupt when we're going down */
1784 }
1786 /* Reset on uncorrectable ECC error */
1794 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1796 /* Do the reset outside of interrupt context */
1799 /* return immediately since reset is imminent */
1801 }
1809 }
1812 }
1814 /**
1815 * e1000_intr - Interrupt Handler
1816 * @irq: interrupt number
1817 * @data: pointer to a network interface device structure
1818 **/
1820 {
1829 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
1830 * not set, then the adapter didn't send an interrupt
1831 */
1835 /* Interrupt Auto-Mask...upon reading ICR,
1836 * interrupts are masked. No need for the
1837 * IMC write
1838 */
1842 /* ICH8 workaround-- Call gig speed drop workaround on cable
1843 * disconnect (LSC) before accessing any PHY registers
1844 */
1849 /* 80003ES2LAN workaround--
1850 * For packet buffer work-around on link down event;
1851 * disable receives here in the ISR and
1852 * reset adapter in watchdog
1853 */
1856 /* disable receives */
1860 }
1861 /* guard against interrupt when we're going down */
1864 }
1866 /* Reset on uncorrectable ECC error */
1874 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1876 /* Do the reset outside of interrupt context */
1879 /* return immediately since reset is imminent */
1881 }
1889 }
1892 }
1895 {
1906 /* guard against interrupt when we're going down */
1909 }
1915 }
1918 {
1928 /* Ring was not completely cleaned, so fire another interrupt */
1935 }
1938 {
1943 /* Write the ITR value calculated at the end of the
1944 * previous interrupt.
1945 */
1952 }
1958 }
1960 }
1962 /**
1963 * e1000_configure_msix - Configure MSI-X hardware
1964 *
1965 * e1000_configure_msix sets up the hardware to properly
1966 * generate MSI-X interrupts.
1967 **/
1969 {
1978 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */
1984 }
1986 /* Configure Rx vector */
1992 else
1996 /* Configure Tx vector */
1998 vector++;
2002 else
2007 /* set vector for Other Causes, e.g. link changes */
2008 vector++;
2013 else
2016 /* Cause Tx interrupts on every write back */
2021 /* enable MSI-X PBA support */
2026 }
2029 {
2037 }
2038 }
2040 /**
2041 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported
2042 *
2043 * Attempt to configure interrupts using the best available
2044 * capabilities of the hardware and kernel.
2045 **/
2047 {
2057 msix_entry),
2058 GFP_KERNEL);
2071 }
2072 /* MSI-X failed, so fall through and try MSI */
2075 }
2077 /* Fall through */
2084 }
2085 /* Fall through */
2087 /* Don't do anything; this is the system default */
2089 }
2091 /* store the number of vectors being used */
2093 }
2095 /**
2096 * e1000_request_msix - Initialize MSI-X interrupts
2097 *
2098 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the
2099 * kernel.
2100 **/
2102 {
2110 else
2114 netdev);
2120 vector++;
2126 else
2130 netdev);
2136 vector++;
2146 }
2148 /**
2149 * e1000_request_irq - initialize interrupts
2150 *
2151 * Attempts to configure interrupts using the best available
2152 * capabilities of the hardware and kernel.
2153 **/
2155 {
2163 /* fall back to MSI */
2167 }
2174 /* fall back to legacy interrupt */
2177 }
2185 }
2188 {
2195 vector++;
2198 vector++;
2200 /* Other Causes interrupt vector */
2203 }
2206 }
2208 /**
2209 * e1000_irq_disable - Mask off interrupt generation on the NIC
2210 **/
2212 {
2227 }
2228 }
2230 /**
2231 * e1000_irq_enable - Enable default interrupt generation settings
2232 **/
2234 {
2240 IMS_OTHER_MASK);
2245 }
2247 }
2249 /**
2250 * e1000e_get_hw_control - get control of the h/w from f/w
2251 * @adapter: address of board private structure
2252 *
2253 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
2254 * For ASF and Pass Through versions of f/w this means that
2255 * the driver is loaded. For AMT version (only with 82573)
2256 * of the f/w this means that the network i/f is open.
2257 **/
2259 {
2261 u32 ctrl_ext;
2262 u32 swsm;
2264 /* Let firmware know the driver has taken over */
2271 }
2272 }
2274 /**
2275 * e1000e_release_hw_control - release control of the h/w to f/w
2276 * @adapter: address of board private structure
2277 *
2278 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
2279 * For ASF and Pass Through versions of f/w this means that the
2280 * driver is no longer loaded. For AMT version (only with 82573) i
2281 * of the f/w this means that the network i/f is closed.
2282 *
2283 **/
2285 {
2287 u32 ctrl_ext;
2288 u32 swsm;
2290 /* Let firmware taken over control of h/w */
2297 }
2298 }
2300 /**
2301 * e1000_alloc_ring_dma - allocate memory for a ring structure
2302 **/
2305 {
2309 GFP_KERNEL);
2314 }
2316 /**
2317 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors)
2318 * @tx_ring: Tx descriptor ring
2319 *
2320 * Return 0 on success, negative on failure
2321 **/
2323 {
2332 /* round up to nearest 4K */
2344 err:
2348 }
2350 /**
2351 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors)
2352 * @rx_ring: Rx descriptor ring
2353 *
2354 * Returns 0 on success, negative on failure
2355 **/
2357 {
2371 GFP_KERNEL);
2374 }
2378 /* Round up to nearest 4K */
2392 err_pages:
2396 }
2397 err:
2401 }
2403 /**
2404 * e1000_clean_tx_ring - Free Tx Buffers
2405 * @tx_ring: Tx descriptor ring
2406 **/
2408 {
2417 }
2427 }
2429 /**
2430 * e1000e_free_tx_resources - Free Tx Resources per Queue
2431 * @tx_ring: Tx descriptor ring
2432 *
2433 * Free all transmit software resources
2434 **/
2436 {
2448 }
2450 /**
2451 * e1000e_free_rx_resources - Free Rx Resources
2452 * @rx_ring: Rx descriptor ring
2453 *
2454 * Free all receive software resources
2455 **/
2457 {
2473 }
2475 /**
2476 * e1000_update_itr - update the dynamic ITR value based on statistics
2477 * @adapter: pointer to adapter
2478 * @itr_setting: current adapter->itr
2479 * @packets: the number of packets during this measurement interval
2480 * @bytes: the number of bytes during this measurement interval
2481 *
2482 * Stores a new ITR value based on packets and byte
2483 * counts during the last interrupt. The advantage of per interrupt
2484 * computation is faster updates and more accurate ITR for the current
2485 * traffic pattern. Constants in this function were computed
2486 * based on theoretical maximum wire speed and thresholds were set based
2487 * on testing data as well as attempting to minimize response time
2488 * while increasing bulk throughput. This functionality is controlled
2489 * by the InterruptThrottleRate module parameter.
2490 **/
2492 {
2500 /* handle TSO and jumbo frames */
2508 /* this if handles the TSO accounting */
2519 }
2527 }
2529 }
2532 }
2535 {
2536 u16 current_itr;
2539 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2544 }
2549 }
2554 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2561 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2567 /* counts and packets in update_itr are dependent on these numbers */
2580 }
2582 set_itr_now:
2584 /* this attempts to bias the interrupt rate towards Bulk
2585 * by adding intermediate steps when interrupt rate is
2586 * increasing
2587 */
2594 else
2596 }
2597 }
2599 /**
2600 * e1000e_write_itr - write the ITR value to the appropriate registers
2601 * @adapter: address of board private structure
2602 * @itr: new ITR value to program
2603 *
2604 * e1000e_write_itr determines if the adapter is in MSI-X mode
2605 * and, if so, writes the EITR registers with the ITR value.
2606 * Otherwise, it writes the ITR value into the ITR register.
2607 **/
2609 {
2620 }
2621 }
2623 /**
2624 * e1000_alloc_queues - Allocate memory for all rings
2625 * @adapter: board private structure to initialize
2626 **/
2628 {
2644 err:
2649 }
2651 /**
2652 * e1000e_poll - NAPI Rx polling callback
2653 * @napi: struct associated with this polling callback
2654 * @budget: number of packets driver is allowed to process this poll
2655 **/
2657 {
2659 napi);
2675 /* Exit the polling mode, but don't re-enable interrupts if stack might
2676 * poll us due to busy-polling
2677 */
2684 else
2686 }
2687 }
2690 }
2694 {
2699 /* don't update vlan cookie if already programmed */
2701 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2705 /* add VID to filter table */
2711 }
2716 }
2720 {
2726 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2728 /* release control to f/w */
2731 }
2733 /* remove VID from filter table */
2739 }
2744 }
2746 /**
2747 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering
2748 * @adapter: board private structure to initialize
2749 **/
2751 {
2754 u32 rctl;
2757 /* disable VLAN receive filtering */
2766 }
2767 }
2768 }
2770 /**
2771 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering
2772 * @adapter: board private structure to initialize
2773 **/
2775 {
2777 u32 rctl;
2780 /* enable VLAN receive filtering */
2785 }
2786 }
2788 /**
2789 * e1000e_vlan_strip_disable - helper to disable HW VLAN stripping
2790 * @adapter: board private structure to initialize
2791 **/
2793 {
2795 u32 ctrl;
2797 /* disable VLAN tag insert/strip */
2801 }
2803 /**
2804 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping
2805 * @adapter: board private structure to initialize
2806 **/
2808 {
2810 u32 ctrl;
2812 /* enable VLAN tag insert/strip */
2816 }
2819 {
2827 }
2831 }
2834 {
2835 u16 vid;
2841 }
2844 {
2853 /* enable receiving management packets to the host. this will probably
2854 * generate destination unreachable messages from the host OS, but
2855 * the packets will be handled on SMBUS
2856 */
2866 /* Check if IPMI pass-through decision filter already exists;
2867 * if so, enable it.
2868 */
2872 /* Ignore filters with anything other than IPMI ports */
2876 /* Enable this decision filter in MANC2H */
2881 }
2886 /* Create new decision filter in an empty filter */
2890 E1000_MDEF_PORT_664));
2892 j++;
2894 }
2899 }
2903 }
2905 /**
2906 * e1000_configure_tx - Configure Transmit Unit after Reset
2907 * @adapter: board private structure
2908 *
2909 * Configure the Tx unit of the MAC after a reset.
2910 **/
2912 {
2915 u64 tdba;
2918 /* Setup the HW Tx Head and Tail descriptor pointers */
2932 else
2935 /* Set the Tx Interrupt Delay register */
2937 /* Tx irq moderation */
2944 E1000_TXDCTL_WTHRESH);
2945 /* set up some performance related parameters to encourage the
2946 * hardware to use the bus more efficiently in bursts, depends
2947 * on the tx_int_delay to be enabled,
2948 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls
2949 * hthresh = 1 ==> prefetch when one or more available
2950 * pthresh = 0x1f ==> prefetch if internal cache 31 or less
2951 * BEWARE: this seems to work but should be considered first if
2952 * there are Tx hangs or other Tx related bugs
2953 */
2956 }
2957 /* erratum work around: set txdctl the same for both queues */
2960 /* Program the Transmit Control Register */
2968 /* set the speed mode bit, we'll clear it if we're not at
2969 * gigabit link later
2970 */
2971 #define SPEED_MODE_BIT BIT(21)
2974 }
2976 /* errata: program both queues to unweighted RR */
2984 }
2986 /* Setup Transmit Descriptor Settings for eop descriptor */
2989 /* only set IDE if we are delaying interrupts using the timers */
2993 /* enable Report Status bit */
3000 /* SPT and KBL Si errata workaround to avoid data corruption */
3002 u32 reg_val;
3009 /* SPT and KBL Si errata workaround to avoid Tx hang.
3010 * Dropping the number of outstanding requests from
3011 * 3 to 2 in order to avoid a buffer overrun.
3012 */
3016 }
3017 }
3019 /**
3020 * e1000_setup_rctl - configure the receive control registers
3021 * @adapter: Board private structure
3022 **/
3023 #define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
3024 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
3026 {
3031 /* Workaround Si errata on PCHx - configure jumbo frame flow.
3032 * If jumbo frames not set, program related MAC/PHY registers
3033 * to h/w defaults
3034 */
3036 s32 ret_val;
3040 else
3045 }
3047 /* Program MC offset vector base */
3054 /* Do not Store bad packets */
3057 /* Enable Long Packet receive */
3060 else
3063 /* Some systems expect that the CRC is included in SMBUS traffic. The
3064 * hardware strips the CRC before sending to both SMBUS (BMC) and to
3065 * host memory when this is enabled
3066 */
3070 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */
3072 u16 phy_data;
3085 }
3087 /* Setup buffer sizes */
3105 }
3107 /* Enable Extended Status in all Receive Descriptors */
3112 /* 82571 and greater support packet-split where the protocol
3113 * header is placed in skb->data and the packet data is
3114 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
3115 * In the case of a non-split, skb->data is linearly filled,
3116 * followed by the page buffers. Therefore, skb->data is
3117 * sized to hold the largest protocol header.
3118 *
3119 * allocations using alloc_page take too long for regular MTU
3120 * so only enable packet split for jumbo frames
3121 *
3122 * Using pages when the page size is greater than 16k wastes
3123 * a lot of memory, since we allocate 3 pages at all times
3124 * per packet.
3125 */
3129 else
3135 /* Enable Packet split descriptors */
3143 /* fall-through */
3146 /* fall-through */
3150 }
3153 }
3155 /* This is useful for sniffing bad packets. */
3157 /* UPE and MPE will be handled by normal PROMISC logic
3158 * in e1000e_set_rx_mode
3159 */
3167 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3168 * and that breaks VLANs.
3169 */
3170 }
3173 /* just started the receive unit, no need to restart */
3175 }
3177 /**
3178 * e1000_configure_rx - Configure Receive Unit after Reset
3179 * @adapter: board private structure
3180 *
3181 * Configure the Rx unit of the MAC after a reset.
3182 **/
3184 {
3187 u64 rdba;
3191 /* this is a 32 byte descriptor */
3204 }
3206 /* disable receives while setting up the descriptors */
3214 /* set the writeback threshold (only takes effect if the RDTR
3215 * is set). set GRAN=1 and write back up to 0x4 worth, and
3216 * enable prefetching of 0x20 Rx descriptors
3217 * granularity = 01
3218 * wthresh = 04,
3219 * hthresh = 04,
3220 * pthresh = 0x20
3221 */
3224 }
3226 /* set the Receive Delay Timer Register */
3229 /* irq moderation */
3235 /* Auto-Mask interrupts upon ICR access */
3241 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3242 * the Base and Length of the Rx Descriptor Ring
3243 */
3256 else
3259 /* Enable Receive Checksum Offload for TCP and UDP */
3263 else
3267 /* With jumbo frames, excessive C-state transition latencies result
3268 * in dropped transactions.
3269 */
3271 u32 lat =
3279 }
3286 PM_QOS_DEFAULT_VALUE);
3287 }
3289 /* Enable Receives */
3291 }
3293 /**
3294 * e1000e_write_mc_addr_list - write multicast addresses to MTA
3295 * @netdev: network interface device structure
3296 *
3297 * Writes multicast address list to the MTA hash table.
3298 * Returns: -ENOMEM on failure
3299 * 0 on no addresses written
3300 * X on writing X addresses to MTA
3301 */
3303 {
3311 /* nothing to program, so clear mc list */
3314 }
3320 /* update_mc_addr_list expects a packed array of only addresses. */
3329 }
3331 /**
3332 * e1000e_write_uc_addr_list - write unicast addresses to RAR table
3333 * @netdev: network interface device structure
3334 *
3335 * Writes unicast address list to the RAR table.
3336 * Returns: -ENOMEM on failure/insufficient address space
3337 * 0 on no addresses written
3338 * X on writing X addresses to the RAR table
3339 **/
3341 {
3349 /* save a rar entry for our hardware address */
3350 rar_entries--;
3352 /* save a rar entry for the LAA workaround */
3354 rar_entries--;
3356 /* return ENOMEM indicating insufficient memory for addresses */
3363 /* write the addresses in reverse order to avoid write
3364 * combining
3365 */
3374 count++;
3375 }
3376 }
3378 /* zero out the remaining RAR entries not used above */
3382 }
3386 }
3388 /**
3389 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set
3390 * @netdev: network interface device structure
3391 *
3392 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast
3393 * address list or the network interface flags are updated. This routine is
3394 * responsible for configuring the hardware for proper unicast, multicast,
3395 * promiscuous mode, and all-multi behavior.
3396 **/
3398 {
3401 u32 rctl;
3406 /* Check for Promiscuous and All Multicast modes */
3409 /* clear the affected bits */
3414 /* Do not hardware filter VLANs in promisc mode */
3422 /* Write addresses to the MTA, if the attempt fails
3423 * then we should just turn on promiscuous mode so
3424 * that we can at least receive multicast traffic
3425 */
3429 }
3431 /* Write addresses to available RAR registers, if there is not
3432 * sufficient space to store all the addresses then enable
3433 * unicast promiscuous mode
3434 */
3438 }
3444 else
3446 }
3449 {
3459 /* Direct all traffic to queue 0 */
3463 /* Disable raw packet checksumming so that RSS hash is placed in
3464 * descriptor on writeback.
3465 */
3472 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3473 E1000_MRQC_RSS_FIELD_IPV6 |
3474 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3475 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
3478 }
3480 /**
3481 * e1000e_get_base_timinca - get default SYSTIM time increment attributes
3482 * @adapter: board private structure
3483 * @timinca: pointer to returned time increment attributes
3484 *
3485 * Get attributes for incrementing the System Time Register SYSTIML/H at
3486 * the default base frequency, and set the cyclecounter shift value.
3487 **/
3489 {
3493 /* Make sure clock is enabled on I217/I218/I219 before checking
3494 * the frequency
3495 */
3504 }
3505 }
3509 /* Stable 96MHz frequency */
3517 /* Stable 96MHz frequency */
3523 /* Stable 25MHz frequency */
3528 }
3531 /* Stable 24MHz frequency */
3541 /* Stable 24MHz frequency */
3547 /* Stable 38400KHz frequency */
3552 }
3556 /* Stable 25MHz frequency */
3564 }
3570 }
3572 /**
3573 * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable
3574 * @adapter: board private structure
3575 *
3576 * Outgoing time stamping can be enabled and disabled. Play nice and
3577 * disable it when requested, although it shouldn't cause any overhead
3578 * when no packet needs it. At most one packet in the queue may be
3579 * marked for time stamping, otherwise it would be impossible to tell
3580 * for sure to which packet the hardware time stamp belongs.
3581 *
3582 * Incoming time stamping has to be configured via the hardware filters.
3583 * Not all combinations are supported, in particular event type has to be
3584 * specified. Matching the kind of event packet is not supported, with the
3585 * exception of "all V2 events regardless of level 2 or 4".
3586 **/
3589 {
3597 u32 regval;
3602 /* flags reserved for future extensions - must be zero */
3614 }
3631 /* Also time stamps V2 L2 Path Delay Request/Response */
3637 /* Also time stamps V2 L2 Path Delay Request/Response. */
3643 /* Hardware cannot filter just V2 L4 Sync messages;
3644 * fall-through to V2 (both L2 and L4) Sync.
3645 */
3647 /* Also time stamps V2 Path Delay Request/Response. */
3654 /* Hardware cannot filter just V2 L4 Delay Request messages;
3655 * fall-through to V2 (both L2 and L4) Delay Request.
3656 */
3658 /* Also time stamps V2 Path Delay Request/Response. */
3666 /* Hardware cannot filter just V2 L4 or L2 Event messages;
3667 * fall-through to all V2 (both L2 and L4) Events.
3668 */
3676 /* For V1, the hardware can only filter Sync messages or
3677 * Delay Request messages but not both so fall-through to
3678 * time stamp all packets.
3679 */
3689 }
3693 /* enable/disable Tx h/w time stamping */
3702 }
3704 /* enable/disable Rx h/w time stamping */
3710 E1000_TSYNCRXCTL_TYPE_MASK)) !=
3712 E1000_TSYNCRXCTL_TYPE_MASK))) {
3715 }
3717 /* L2: define ethertype filter for time stamped packets */
3721 /* define which PTP packets get time stamped */
3724 /* Filter by destination port */
3728 }
3733 /* Clear TSYNCRXCTL_VALID & TSYNCTXCTL_VALID bit */
3738 }
3740 /**
3741 * e1000_configure - configure the hardware for Rx and Tx
3742 * @adapter: private board structure
3743 **/
3745 {
3760 }
3762 /**
3763 * e1000e_power_up_phy - restore link in case the phy was powered down
3764 * @adapter: address of board private structure
3765 *
3766 * The phy may be powered down to save power and turn off link when the
3767 * driver is unloaded and wake on lan is not enabled (among others)
3768 * *** this routine MUST be followed by a call to e1000e_reset ***
3769 **/
3771 {
3776 }
3778 /**
3779 * e1000_power_down_phy - Power down the PHY
3780 *
3781 * Power down the PHY so no link is implied when interface is down.
3782 * The PHY cannot be powered down if management or WoL is active.
3783 */
3785 {
3788 }
3790 /**
3791 * e1000_flush_tx_ring - remove all descriptors from the tx_ring
3792 *
3793 * We want to clear all pending descriptors from the TX ring.
3794 * zeroing happens when the HW reads the regs. We assign the ring itself as
3795 * the data of the next descriptor. We don't care about the data we are about
3796 * to reset the HW.
3797 */
3799 {
3815 /* flush descriptors to memory before notifying the HW */
3822 }
3824 /**
3825 * e1000_flush_rx_ring - remove all descriptors from the rx_ring
3826 *
3827 * Mark all descriptors in the RX ring as consumed and disable the rx ring
3828 */
3830 {
3840 /* zero the lower 14 bits (prefetch and host thresholds) */
3843 /* update thresholds: prefetch threshold to 31, host threshold to 1
3844 * and make sure the granularity is "descriptors" and not "cache lines"
3845 */
3849 /* momentarily enable the RX ring for the changes to take effect */
3854 }
3856 /**
3857 * e1000_flush_desc_rings - remove all descriptors from the descriptor rings
3858 *
3859 * In i219, the descriptor rings must be emptied before resetting the HW
3860 * or before changing the device state to D3 during runtime (runtime PM).
3861 *
3862 * Failure to do this will cause the HW to enter a unit hang state which can
3863 * only be released by PCI reset on the device
3864 *
3865 */
3868 {
3869 u16 hang_state;
3873 /* First, disable MULR fix in FEXTNVM11 */
3877 /* do nothing if we're not in faulty state, or if the queue is empty */
3884 /* recheck, maybe the fault is caused by the rx ring */
3889 }
3891 /**
3892 * e1000e_systim_reset - reset the timesync registers after a hardware reset
3893 * @adapter: board private structure
3894 *
3895 * When the MAC is reset, all hardware bits for timesync will be reset to the
3896 * default values. This function will restore the settings last in place.
3897 * Since the clock SYSTIME registers are reset, we will simply restore the
3898 * cyclecounter to the kernel real clock time.
3899 **/
3901 {
3905 u32 timinca;
3906 s32 ret_val;
3912 /* restore the previous ptp frequency delta */
3915 /* set the default base frequency if no adjustment possible */
3919 }
3924 ret_val);
3926 }
3928 /* reset the systim ns time counter */
3934 /* restore the previous hwtstamp configuration settings */
3936 }
3938 /**
3939 * e1000e_reset - bring the hardware into a known good state
3940 *
3941 * This function boots the hardware and enables some settings that
3942 * require a configuration cycle of the hardware - those cannot be
3943 * set/changed during runtime. After reset the device needs to be
3944 * properly configured for Rx, Tx etc.
3945 */
3947 {
3953 u16 hwm;
3955 /* reset Packet Buffer Allocation to default */
3959 /* To maintain wire speed transmits, the Tx FIFO should be
3960 * large enough to accommodate two full transmit packets,
3961 * rounded up to the next 1KB and expressed in KB. Likewise,
3962 * the Rx FIFO should be large enough to accommodate at least
3963 * one full receive packet and is similarly rounded up and
3964 * expressed in KB.
3965 */
3967 /* upper 16 bits has Tx packet buffer allocation size in KB */
3969 /* lower 16 bits has Rx packet buffer allocation size in KB */
3971 /* the Tx fifo also stores 16 bytes of information about the Tx
3972 * but don't include ethernet FCS because hardware appends it
3973 */
3978 /* software strips receive CRC, so leave room for it */
3983 /* If current Tx allocation is less than the min Tx FIFO size,
3984 * and the min Tx FIFO size is less than the current Rx FIFO
3985 * allocation, take space away from current Rx allocation
3986 */
3991 /* if short on Rx space, Rx wins and must trump Tx
3992 * adjustment
3993 */
3996 }
3999 }
4001 /* flow control settings
4002 *
4003 * The high water mark must be low enough to fit one full frame
4004 * (or the size used for early receive) above it in the Rx FIFO.
4005 * Set it to the lower of:
4006 * - 90% of the Rx FIFO size, and
4007 * - the full Rx FIFO size minus one full frame
4008 */
4011 else
4025 }
4026 /* fall-through */
4035 /* Workaround PCH LOM adapter hangs with certain network
4036 * loads. If hangs persist, try disabling Tx flow control.
4037 */
4044 }
4051 /* fall-through */
4061 }
4068 }
4070 /* Alignment of Tx data is on an arbitrary byte boundary with the
4071 * maximum size per Tx descriptor limited only to the transmit
4072 * allocation of the packet buffer minus 96 bytes with an upper
4073 * limit of 24KB due to receive synchronization limitations.
4074 */
4078 /* Disable Adaptive Interrupt Moderation if 2 full packets cannot
4079 * fit in receive buffer.
4080 */
4088 }
4095 }
4096 }
4100 /* Allow time for pending master requests to run */
4103 /* For parts with AMT enabled, let the firmware know
4104 * that the network interface is in control
4105 */
4116 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
4121 /* restore systim and hwtstamp settings */
4124 /* Set EEE advertisement as appropriate */
4126 s32 ret_val;
4127 u16 adv_addr;
4140 }
4147 }
4154 }
4165 /* speed up time to link by disabling smart power down, ignore
4166 * the return value of this function because there is nothing
4167 * different we would do if it failed
4168 */
4172 }
4174 u32 reg;
4176 /* Fextnvm7 @ 0xe4[2] = 1 */
4180 /* Fextnvm9 @ 0x5bb4[13:12] = 11 */
4183 E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS;
4185 }
4187 }
4189 /**
4190 * e1000e_trigger_lsc - trigger an LSC interrupt
4191 * @adapter:
4192 *
4193 * Fire a link status change interrupt to start the watchdog.
4194 **/
4196 {
4201 else
4203 }
4206 {
4207 /* hardware has been reset, we need to reload some things */
4216 /* Tx queue started by watchdog timer when link is up */
4219 }
4222 {
4228 /* flush pending descriptor writebacks to memory */
4232 /* execute the writes immediately */
4235 /* due to rare timing issues, write to TIDV/RDTR again to ensure the
4236 * write is successful
4237 */
4241 /* execute the writes immediately */
4243 }
4247 /**
4248 * e1000e_down - quiesce the device and optionally reset the hardware
4249 * @adapter: board private structure
4250 * @reset: boolean flag to reset the hardware or not
4251 */
4253 {
4258 /* signal that we're down so the interrupt handler does not
4259 * reschedule our watchdog timer
4260 */
4265 /* disable receives in the hardware */
4269 /* flush and sleep below */
4273 /* disable transmits in the hardware */
4278 /* flush both disables and wait for them to finish */
4298 /* Disable Si errata workaround on PCHx for jumbo frame flow */
4309 }
4312 }
4315 {
4322 }
4324 /**
4325 * e1000e_sanitize_systim - sanitize raw cycle counter reads
4326 * @hw: pointer to the HW structure
4327 * @systim: PHC time value read, sanitized and returned
4328 * @sts: structure to hold system time before and after reading SYSTIML,
4329 * may be NULL
4330 *
4331 * Errata for 82574/82583 possible bad bits read from SYSTIMH/L:
4332 * check to see that the time is incrementing at a reasonable
4333 * rate and is a multiple of incvalue.
4334 **/
4337 {
4339 u64 systim_next;
4340 u32 incvalue;
4345 /* latch SYSTIMH on read of SYSTIML */
4353 /* VMWare users have seen incvalue of zero, don't div / 0 */
4360 }
4363 }
4365 /**
4366 * e1000e_read_systim - read SYSTIM register
4367 * @adapter: board private structure
4368 * @sts: structure which will contain system time before and after reading
4369 * SYSTIML, may be NULL
4370 **/
4373 {
4376 u64 systim;
4377 /* SYSTIMH latching upon SYSTIML read does not work well.
4378 * This means that if SYSTIML overflows after we read it but before
4379 * we read SYSTIMH, the value of SYSTIMH has been incremented and we
4380 * will experience a huge non linear increment in the systime value
4381 * to fix that we test for overflow and if true, we re-read systime.
4382 */
4387 /* Is systimel is so large that overflow is possible? */
4393 /* There was an overflow, read again SYSTIMH, and use
4394 * systimel_2
4395 */
4398 }
4399 }
4407 }
4409 /**
4410 * e1000e_cyclecounter_read - read raw cycle counter (used by time counter)
4411 * @cc: cyclecounter structure
4412 **/
4414 {
4416 cc);
4419 }
4421 /**
4422 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
4423 * @adapter: board private structure to initialize
4424 *
4425 * e1000_sw_init initializes the Adapter private data structure.
4426 * Fields are initialized based on PCI device information and
4427 * OS network device settings (MTU size).
4428 **/
4430 {
4447 /* Setup hardware time stamping cyclecounter */
4452 /* cc.shift set in e1000e_get_base_tininca() */
4456 }
4458 /* Explicitly disable IRQ since the NIC can be in any state. */
4463 }
4465 /**
4466 * e1000_intr_msi_test - Interrupt Handler
4467 * @irq: interrupt number
4468 * @data: pointer to a network interface device structure
4469 **/
4471 {
4480 /* Force memory writes to complete before acknowledging the
4481 * interrupt is handled.
4482 */
4484 }
4487 }
4489 /**
4490 * e1000_test_msi_interrupt - Returns 0 for successful test
4491 * @adapter: board private struct
4492 *
4493 * code flow taken from tg3.c
4494 **/
4496 {
4501 /* poll_enable hasn't been called yet, so don't need disable */
4502 /* clear any pending events */
4505 /* free the real vector and request a test handler */
4509 /* Assume that the test fails, if it succeeds then the test
4510 * MSI irq handler will unset this flag
4511 */
4523 }
4525 /* Force memory writes to complete before enabling and firing an
4526 * interrupt.
4527 */
4532 /* fire an unusual interrupt on the test handler */
4546 }
4551 msi_test_failed:
4554 }
4556 /**
4557 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
4558 * @adapter: board private struct
4559 *
4560 * code flow taken from tg3.c, called with e1000 interrupts disabled.
4561 **/
4563 {
4565 u16 pci_cmd;
4570 /* disable SERR in case the MSI write causes a master abort */
4578 /* re-enable SERR */
4583 }
4586 }
4588 /**
4589 * e1000e_open - Called when a network interface is made active
4590 * @netdev: network interface device structure
4591 *
4592 * Returns 0 on success, negative value on failure
4593 *
4594 * The open entry point is called when a network interface is made
4595 * active by the system (IFF_UP). At this point all resources needed
4596 * for transmit and receive operations are allocated, the interrupt
4597 * handler is registered with the OS, the watchdog timer is started,
4598 * and the stack is notified that the interface is ready.
4599 **/
4601 {
4607 /* disallow open during test */
4616 /* allocate transmit descriptors */
4621 /* allocate receive descriptors */
4626 /* If AMT is enabled, let the firmware know that the network
4627 * interface is now open and reset the part to a known state.
4628 */
4632 }
4640 /* DMA latency requirement to workaround jumbo issue */
4643 /* before we allocate an interrupt, we must be ready to handle it.
4644 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
4645 * as soon as we call pci_request_irq, so we have to setup our
4646 * clean_rx handler before we do so.
4647 */
4654 /* Work around PCIe errata with MSI interrupts causing some chipsets to
4655 * ignore e1000e MSI messages, which means we need to test our MSI
4656 * interrupt now
4657 */
4663 }
4664 }
4666 /* From here on the code is the same as e1000e_up() */
4682 err_req_irq:
4687 err_setup_rx:
4689 err_setup_tx:
4694 }
4696 /**
4697 * e1000e_close - Disables a network interface
4698 * @netdev: network interface device structure
4699 *
4700 * Returns 0, this is not allowed to fail
4701 *
4702 * The close entry point is called when an interface is de-activated
4703 * by the OS. The hardware is still under the drivers control, but
4704 * needs to be disabled. A global MAC reset is issued to stop the
4705 * hardware, and all transmit and receive resources are freed.
4706 **/
4708 {
4724 /* Link status message must follow this format */
4726 }
4733 /* kill manageability vlan ID if supported, but not if a vlan with
4734 * the same ID is registered on the host OS (let 8021q kill it)
4735 */
4740 /* If AMT is enabled, let the firmware know that the network
4741 * interface is now closed
4742 */
4752 }
4754 /**
4755 * e1000_set_mac - Change the Ethernet Address of the NIC
4756 * @netdev: network interface device structure
4757 * @p: pointer to an address structure
4758 *
4759 * Returns 0 on success, negative on failure
4760 **/
4762 {
4776 /* activate the work around */
4779 /* Hold a copy of the LAA in RAR[14] This is done so that
4780 * between the time RAR[0] gets clobbered and the time it
4781 * gets fixed (in e1000_watchdog), the actual LAA is in one
4782 * of the RARs and no incoming packets directed to this port
4783 * are dropped. Eventually the LAA will be in RAR[0] and
4784 * RAR[14]
4785 */
4788 }
4791 }
4793 /**
4794 * e1000e_update_phy_task - work thread to update phy
4795 * @work: pointer to our work struct
4796 *
4797 * this worker thread exists because we must acquire a
4798 * semaphore to read the phy, which we could msleep while
4799 * waiting for it, and we can't msleep in a timer.
4800 **/
4802 {
4805 update_phy_task);
4813 /* Enable EEE on 82579 after link up */
4816 }
4818 /**
4819 * e1000_update_phy_info - timre call-back to update PHY info
4820 * @data: pointer to adapter cast into an unsigned long
4821 *
4822 * Need to wait a few seconds after link up to get diagnostic information from
4823 * the phy
4824 **/
4826 {
4833 }
4835 /**
4836 * e1000e_update_phy_stats - Update the PHY statistics counters
4837 * @adapter: board private structure
4838 *
4839 * Read/clear the upper 16-bit PHY registers and read/accumulate lower
4840 **/
4842 {
4844 s32 ret_val;
4845 u16 phy_data;
4851 /* A page set is expensive so check if already on desired page.
4852 * If not, set to the page with the PHY status registers.
4853 */
4864 }
4866 /* Single Collision Count */
4872 /* Excessive Collision Count */
4878 /* Multiple Collision Count */
4884 /* Late Collision Count */
4890 /* Collision Count - also used for adaptive IFS */
4896 /* Defer Count */
4902 /* Transmit with no CRS */
4908 release:
4910 }
4912 /**
4913 * e1000e_update_stats - Update the board statistics counters
4914 * @adapter: board private structure
4915 **/
4917 {
4922 /* Prevent stats update while adapter is being reset, or if the pci
4923 * connection is down.
4924 */
4940 /* Half-duplex statistics */
4956 }
4958 }
4973 /* used for adaptive IFS */
4984 /* Fill out the OS statistics structure */
4988 /* Rx Errors */
4990 /* RLEC on some newer hardware can be incorrect so build
4991 * our own version based on RUC and ROC
4992 */
5002 /* Tx Errors */
5008 /* Tx Dropped needs to be maintained elsewhere */
5010 /* Management Stats */
5015 /* Correctable ECC Errors */
5023 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
5024 }
5025 }
5027 /**
5028 * e1000_phy_read_status - Update the PHY register status snapshot
5029 * @adapter: board private structure
5030 **/
5032 {
5052 /* Do not read PHY registers if link is not up
5053 * Set values to typical power-on defaults
5054 */
5058 BMSR_ERCAP);
5066 }
5067 }
5070 {
5074 /* Link status message must follow this format for user tools */
5082 }
5085 {
5090 /* get_link_status is set on LSC (link status) interrupt or
5091 * Rx sequence error interrupt. get_link_status will stay
5092 * true until the check_for_link establishes link
5093 * for copper adapters ONLY
5094 */
5102 }
5115 }
5119 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */
5121 }
5124 }
5127 {
5128 /* make sure the receive unit is started */
5136 }
5137 }
5140 {
5143 /* With 82574 controllers, PHY needs to be checked periodically
5144 * for hung state and reset, if two calls return true
5145 */
5148 else
5155 }
5156 }
5158 /**
5159 * e1000_watchdog - Timer Call-back
5160 * @data: pointer to adapter cast into an unsigned long
5161 **/
5163 {
5166 /* Do the rest outside of interrupt context */
5169 /* TODO: make this use queue_delayed_work() */
5170 }
5173 {
5176 watchdog_task);
5190 /* Cancel scheduled suspend requests. */
5195 }
5205 /* Cancel scheduled suspend requests. */
5208 /* Checking if MAC is in DMoff state*/
5214 }
5218 /* Checking if MAC exited DMoff state */
5221 }
5223 /* update snapshot of PHY registers on LSC */
5230 /* check if SmartSpeed worked */
5236 /* On supported PHYs, check for duplex mismatch only
5237 * if link has autonegotiated at 10/100 half
5238 */
5245 u16 autoneg_exp;
5250 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n");
5251 }
5253 /* adjust timeout factor according to speed/duplex */
5264 }
5266 /* workaround: re-program speed mode bit after
5267 * link-up event
5268 */
5271 u32 tarc0;
5276 }
5278 /* disable TSO for pcie and 10/100 speeds, to avoid
5279 * some hardware issues
5280 */
5294 /* oops */
5296 }
5297 }
5299 /* enable transmits in the hardware, need to do this
5300 * after setting TARC(0)
5301 */
5306 /* Perform any post-link-up configuration before
5307 * reporting link up.
5308 */
5318 }
5323 /* Link status message must follow this format */
5331 /* 8000ES2LAN requires a Rx packet buffer work-around
5332 * on link down event; reset the controller to flush
5333 * the Rx packet buffer.
5334 */
5337 else
5339 LINK_TIMEOUT);
5340 }
5341 }
5343 link_up:
5358 /* If the link is lost the controller stops DMA, but
5359 * if there is queued Tx work it cannot be done. So
5360 * reset the controller to flush the Tx packet buffers.
5361 */
5366 /* If reset is necessary, do it outside of interrupt context. */
5369 /* return immediately since reset is imminent */
5371 }
5375 /* Simple mode for Interrupt Throttle Rate (ITR) */
5377 /* Symmetric Tx/Rx gets a reduced ITR=2000;
5378 * Total asymmetrical Tx or Rx gets ITR=8000;
5379 * everyone else is between 2000-8000.
5380 */
5388 }
5390 /* Cause software interrupt to ensure Rx ring is cleaned */
5393 else
5396 /* flush pending descriptors to memory before detecting Tx hang */
5399 /* Force detection of hung controller every watchdog period */
5402 /* With 82571 controllers, LAA may be overwritten due to controller
5403 * reset from the other port. Set the appropriate LAA in RAR[0]
5404 */
5411 /* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */
5419 }
5420 }
5422 /* Reset the timer */
5426 }
5428 #define E1000_TX_FLAGS_CSUM 0x00000001
5429 #define E1000_TX_FLAGS_VLAN 0x00000002
5430 #define E1000_TX_FLAGS_TSO 0x00000004
5431 #define E1000_TX_FLAGS_IPV4 0x00000008
5432 #define E1000_TX_FLAGS_NO_FCS 0x00000010
5433 #define E1000_TX_FLAGS_HWTSTAMP 0x00000020
5434 #define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
5435 #define E1000_TX_FLAGS_VLAN_SHIFT 16
5438 __be16 protocol)
5439 {
5468 }
5494 i++;
5500 }
5503 __be16 protocol)
5504 {
5509 u8 css;
5521 /* XXX not handling all IPV6 headers */
5530 }
5548 i++;
5554 }
5559 {
5585 count++;
5588 i++;
5591 }
5592 }
5601 i++;
5613 DMA_TO_DEVICE);
5620 count++;
5621 }
5622 }
5625 /* multiply data chunks by size of headers */
5635 dma_error:
5639 count--;
5644 i--;
5647 }
5650 }
5653 {
5662 E1000_TXD_CMD_TSE;
5667 }
5672 }
5677 }
5685 }
5697 i++;
5704 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */
5708 /* Force memory writes to complete before letting h/w
5709 * know there are new descriptors to fetch. (Only
5710 * applicable for weak-ordered memory model archs,
5711 * such as IA-64).
5712 */
5716 }
5718 #define MINIMUM_DHCP_PACKET_SIZE 282
5721 {
5728 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
5737 {
5751 }
5754 }
5757 {
5761 /* Herbert's original patch had:
5762 * smp_mb__after_netif_stop_queue();
5763 * but since that doesn't exist yet, just open code it.
5764 */
5767 /* We need to check again in a case another CPU has just
5768 * made room available.
5769 */
5773 /* A reprieve! */
5777 }
5780 {
5786 }
5790 {
5806 }
5811 }
5813 /* The minimum packet size with TCTL.PSP set is 17 bytes so
5814 * pad skb in order to meet this minimum size requirement
5815 */
5821 u8 hdr_len;
5823 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data
5824 * points to just header, pull a few bytes of payload from
5825 * frags into skb->data
5826 */
5828 /* we do this workaround for ES2LAN, but it is un-necessary,
5829 * avoiding it could save a lot of cycles
5830 */
5839 }
5841 }
5842 }
5844 /* reserve a descriptor for the offload context */
5846 count++;
5847 count++;
5859 /* need: count + 2 desc gap to keep tail from touching
5860 * head, otherwise try next time
5861 */
5868 E1000_TX_FLAGS_VLAN_SHIFT);
5869 }
5877 }
5884 /* Old method was to assume IPv4 packet by default if TSO was enabled.
5885 * 82571 hardware supports TSO capabilities for IPv6 as well...
5886 * no longer assume, we must.
5887 */
5894 /* if count is 0 then mapping error has occurred */
5896 nr_frags);
5908 }
5909 }
5915 /* Make sure there is space in the ring for the next send. */
5926 else
5928 }
5933 }
5936 }
5938 /**
5939 * e1000_tx_timeout - Respond to a Tx Hang
5940 * @netdev: network interface device structure
5941 **/
5943 {
5946 /* Do the reset outside of interrupt context */
5949 }
5952 {
5956 /* don't run the task if already down */
5963 }
5965 }
5967 /**
5968 * e1000_get_stats64 - Get System Network Statistics
5969 * @netdev: network interface device structure
5970 * @stats: rtnl_link_stats64 pointer
5971 *
5972 * Returns the address of the device statistics structure.
5973 **/
5976 {
5981 /* Fill out the OS statistics structure */
5989 /* Rx Errors */
5991 /* RLEC on some newer hardware can be incorrect so build
5992 * our own version based on RUC and ROC
5993 */
6002 /* Tx Errors */
6008 /* Tx Dropped needs to be maintained elsewhere */
6011 }
6013 /**
6014 * e1000_change_mtu - Change the Maximum Transfer Unit
6015 * @netdev: network interface device structure
6016 * @new_mtu: new value for maximum frame size
6017 *
6018 * Returns 0 on success, negative on failure
6019 **/
6021 {
6025 /* Jumbo frame support */
6030 }
6032 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
6038 }
6042 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
6053 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
6054 * means we reserve 2 more, this pushes us to allocate from the next
6055 * larger slab size.
6056 * i.e. RXBUFFER_2048 --> size-4096 slab
6057 * However with the new *_jumbo_rx* routines, jumbo receives will use
6058 * fragmented skbs
6059 */
6063 else
6066 /* adjust allocation if LPE protects us, and we aren't using SBP */
6072 else
6080 }
6084 {
6131 }
6136 }
6138 }
6140 /**
6141 * e1000e_hwtstamp_ioctl - control hardware time stamping
6142 * @netdev: network interface device structure
6143 * @ifreq: interface request
6144 *
6145 * Outgoing time stamping can be enabled and disabled. Play nice and
6146 * disable it when requested, although it shouldn't cause any overhead
6147 * when no packet needs it. At most one packet in the queue may be
6148 * marked for time stamping, otherwise it would be impossible to tell
6149 * for sure to which packet the hardware time stamp belongs.
6150 *
6151 * Incoming time stamping has to be configured via the hardware filters.
6152 * Not all combinations are supported, in particular event type has to be
6153 * specified. Matching the kind of event packet is not supported, with the
6154 * exception of "all V2 events regardless of level 2 or 4".
6155 **/
6157 {
6176 /* With V2 type filters which specify a Sync or Delay Request,
6177 * Path Delay Request/Response messages are also time stamped
6178 * by hardware so notify the caller the requested packets plus
6179 * some others are time stamped.
6180 */
6185 }
6189 }
6192 {
6197 }
6200 {
6212 }
6213 }
6216 {
6222 /* copy MAC RARs to PHY RARs */
6229 }
6231 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */
6236 /* copy MAC MTA to PHY MTA - only needed for pchlan */
6243 }
6245 /* configure PHY Rx Control register */
6269 /* enable PHY wakeup in MAC register */
6274 /* configure and enable PHY wakeup in PHY registers */
6278 /* activate PHY wakeup */
6283 release:
6287 }
6290 {
6294 u32 ret_val;
6307 fl_out:
6309 }
6311 #ifdef CONFIG_PM_SLEEP
6312 /* S0ix implementation */
6314 {
6316 u32 mac_data;
6317 u16 phy_data;
6319 /* Disable the periodic inband message,
6320 * don't request PCIe clock in K1 page770_17[10:9] = 10b
6321 */
6327 /* Make sure we don't exit K1 every time a new packet arrives
6328 * 772_29[5] = 1 CS_Mode_Stay_In_K1
6329 */
6334 /* Change the MAC/PHY interface to SMBus
6335 * Force the SMBus in PHY page769_23[0] = 1
6336 * Force the SMBus in MAC CTRL_EXT[11] = 1
6337 */
6345 /* DFT control: PHY bit: page769_20[0] = 1
6346 * Gate PPW via EXTCNF_CTRL - set 0x0F00[7] = 1
6347 */
6356 /* Check MAC Tx/Rx packet buffer pointers.
6357 * Reset MAC Tx/Rx packet buffer pointers to suppress any
6358 * pending traffic indication that would prevent power gating.
6359 */
6391 /* Enable the Dynamic Power Gating in the MAC */
6396 /* Disable the time synchronization clock */
6402 /* Dynamic Power Gating Enable */
6407 /* Enable the Dynamic Clock Gating in the DMA and MAC */
6412 /* No MAC DPG gating SLP_S0 in modern standby
6413 * Switch the logic of the lanphypc to use PMC counter
6414 */
6418 }
6421 {
6423 u32 mac_data;
6424 u16 phy_data;
6426 /* Disable the Dynamic Power Gating in the MAC */
6431 /* Enable the time synchronization clock */
6436 /* Disable Dynamic Power Gating */
6441 /* Disable the Dynamic Clock Gating in the DMA and MAC */
6446 /* Revert the lanphypc logic to use the internal Gbe counter
6447 * and not the PMC counter
6448 */
6453 /* Enable the periodic inband message,
6454 * Request PCIe clock in K1 page770_17[10:9] =01b
6455 */
6461 /* Return back configuration
6462 * 772_29[5] = 0 CS_Mode_Stay_In_K1
6463 */
6468 /* Change the MAC/PHY interface to Kumeran
6469 * Unforce the SMBus in PHY page769_23[0] = 0
6470 * Unforce the SMBus in MAC CTRL_EXT[11] = 0
6471 */
6478 }
6482 {
6500 /* Quiesce the device without resetting the hardware */
6503 }
6508 /* Allow time for pending master requests to run */
6512 }
6515 {
6520 /* Runtime suspend should only enable wakeup for link changes */
6532 /* turn on all-multi mode if wake on multicast is enabled */
6537 }
6547 e1000_media_type_internal_serdes) {
6548 /* keep the laser running in D3 */
6552 }
6561 /* enable wakeup by the PHY */
6566 /* enable wakeup by the MAC */
6569 }
6575 }
6581 /* ULP does not support wake from unicast, multicast
6582 * or broadcast.
6583 */
6588 }
6590 /* Ensure that the appropriate bits are set in LPI_CTRL
6591 * for EEE in Sx
6592 */
6604 I82579_EEE_100_SUPPORTED)
6608 I82579_EEE_1000_SUPPORTED)
6612 lpi_ctrl);
6613 }
6614 }
6616 }
6618 /* Release control of h/w to f/w. If f/w is AMT enabled, this
6619 * would have already happened in close and is redundant.
6620 */
6625 /* The pci-e switch on some quad port adapters will report a
6626 * correctable error when the MAC transitions from D0 to D3. To
6627 * prevent this we need to mask off the correctable errors on the
6628 * downstream port of the pci-e switch.
6629 *
6630 * We don't have the associated upstream bridge while assigning
6631 * the PCI device into guest. For example, the KVM on power is
6632 * one of the cases.
6633 */
6636 u16 devctl;
6649 }
6652 }
6654 /**
6655 * __e1000e_disable_aspm - Disable ASPM states
6656 * @pdev: pointer to PCI device struct
6657 * @state: bit-mask of ASPM states to disable
6658 * @locked: indication if this context holds pci_bus_sem locked.
6659 *
6660 * Some devices *must* have certain ASPM states disabled per hardware errata.
6661 **/
6663 {
6672 /* fall-through - can't have L1 without L0s */
6678 }
6687 }
6689 /* Nothing to do if the ASPM states to be disabled already are */
6700 #ifdef CONFIG_PCIEASPM
6703 else
6706 /* Double-check ASPM control. If not disabled by the above, the
6707 * BIOS is preventing that from happening (or CONFIG_PCIEASPM is
6708 * not enabled); override by writing PCI config space directly.
6709 */
6715 #endif
6717 /* Both device and parent should have the same ASPM setting.
6718 * Disable ASPM in downstream component first and then upstream.
6719 */
6724 aspm_dis_mask);
6725 }
6727 /**
6728 * e1000e_disable_aspm - Disable ASPM states.
6729 * @pdev: pointer to PCI device struct
6730 * @state: bit-mask of ASPM states to disable
6731 *
6732 * This function acquires the pci_bus_sem!
6733 * Some devices *must* have certain ASPM states disabled per hardware errata.
6734 **/
6736 {
6738 }
6740 /**
6741 * e1000e_disable_aspm_locked Disable ASPM states.
6742 * @pdev: pointer to PCI device struct
6743 * @state: bit-mask of ASPM states to disable
6744 *
6745 * This function must be called with pci_bus_sem acquired!
6746 * Some devices *must* have certain ASPM states disabled per hardware errata.
6747 **/
6749 {
6751 }
6754 {
6768 }
6771 err_irq:
6775 }
6777 #ifdef CONFIG_PM
6779 {
6799 /* report the system wakeup cause from S3/S4 */
6801 u16 phy_data;
6812 }
6825 }
6827 }
6833 /* If the controller has AMT, do not set DRV_LOAD until the interface
6834 * is up. For all other cases, let the f/w know that the h/w is now
6835 * under the control of the driver.
6836 */
6841 }
6843 #ifdef CONFIG_PM_SLEEP
6845 {
6860 /* Introduce S0ix implementation */
6865 }
6868 {
6875 /* Introduce S0ix implementation */
6884 }
6888 {
6891 u16 eee_lp;
6898 }
6901 }
6904 {
6918 }
6921 {
6934 /* Down the device without resetting the hardware */
6936 }
6941 }
6944 }
6948 {
6954 }
6956 #ifdef CONFIG_NET_POLL_CONTROLLER
6959 {
6972 vector++;
6978 vector++;
6983 }
6986 }
6988 /**
6989 * e1000_netpoll
6990 * @netdev: network interface device structure
6991 *
6992 * Polling 'interrupt' - used by things like netconsole to send skbs
6993 * without having to re-enable interrupts. It's not called while
6994 * the interrupt routine is executing.
6995 */
6997 {
7014 }
7015 }
7016 #endif
7018 /**
7019 * e1000_io_error_detected - called when PCI error is detected
7020 * @pdev: Pointer to PCI device
7021 * @state: The current pci connection state
7022 *
7023 * This function is called after a PCI bus error affecting
7024 * this device has been detected.
7025 */
7027 pci_channel_state_t state)
7028 {
7036 /* Request a slot slot reset. */
7038 }
7040 /**
7041 * e1000_io_slot_reset - called after the pci bus has been reset.
7042 * @pdev: Pointer to PCI device
7043 *
7044 * Restart the card from scratch, as if from a cold-boot. Implementation
7045 * resembles the first-half of the e1000e_pm_resume routine.
7046 */
7048 {
7054 pci_ers_result_t result;
7079 }
7082 }
7084 /**
7085 * e1000_io_resume - called when traffic can start flowing again.
7086 * @pdev: Pointer to PCI device
7087 *
7088 * This callback is called when the error recovery driver tells us that
7089 * its OK to resume normal operation. Implementation resembles the
7090 * second-half of the e1000e_pm_resume routine.
7091 */
7093 {
7101 /* If the controller has AMT, do not set DRV_LOAD until the interface
7102 * is up. For all other cases, let the f/w know that the h/w is now
7103 * under the control of the driver.
7104 */
7107 }
7110 {
7113 u32 ret_val;
7116 /* print bus type/speed/width info */
7118 /* bus width */
7121 /* MAC address */
7126 E1000_PBANUM_LENGTH);
7131 }
7134 {
7145 /* Deep Smart Power Down (DSPD) */
7148 }
7149 }
7152 netdev_features_t features)
7153 {
7157 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
7161 /* Since there is no support for separate Rx/Tx vlan accel
7162 * enable/disable make sure Tx flag is always in same state as Rx.
7163 */
7166 else
7170 }
7173 netdev_features_t features)
7174 {
7183 NETIF_F_RXALL)))
7190 /* We need to take it back to defaults, which might mean
7191 * stripping is still disabled at the adapter level.
7192 */
7195 else
7197 }
7198 }
7204 else
7208 }
7224 #ifdef CONFIG_NET_POLL_CONTROLLER
7226 #endif
7230 };
7232 /**
7233 * e1000_probe - Device Initialization Routine
7234 * @pdev: PCI device information struct
7235 * @ent: entry in e1000_pci_tbl
7236 *
7237 * Returns 0 on success, negative on failure
7238 *
7239 * e1000_probe initializes an adapter identified by a pci_dev structure.
7240 * The OS initialization, configuring of the adapter private structure,
7241 * and a hardware reset occur.
7242 **/
7244 {
7279 }
7280 }
7284 e1000e_driver_name);
7288 /* AER (Advanced Error Reporting) hooks */
7292 /* PCI config space info */
7336 }
7338 /* Set default EEE advertisement */
7342 /* construct the net_device struct */
7356 /* setup adapter struct */
7378 /* Copper options */
7383 }
7389 /* Set initial default active device features */
7391 NETIF_F_HW_VLAN_CTAG_RX |
7392 NETIF_F_HW_VLAN_CTAG_TX |
7393 NETIF_F_TSO |
7394 NETIF_F_TSO6 |
7395 NETIF_F_RXHASH |
7396 NETIF_F_RXCSUM |
7397 NETIF_F_HW_CSUM);
7399 /* Set user-changeable features (subset of all device features) */
7409 NETIF_F_TSO |
7410 NETIF_F_TSO6 |
7411 NETIF_F_HW_CSUM);
7418 }
7420 /* MTU range: 68 - max_hw_frame_size */
7428 /* before reading the NVM, reset the controller to
7429 * put the device in a known good starting state
7430 */
7433 /* systems with ASPM and others may see the checksum fail on the first
7434 * attempt. Let's give it a few tries
7435 */
7443 }
7444 }
7448 /* copy the MAC address */
7460 }
7471 /* Initialize link parameters. User can change them with ethtool */
7478 /* Initial Wake on LAN setting - If APM wake is enabled in
7479 * the EEPROM, enable the ACPI Magic Packet filter
7480 */
7482 /* APME bit in EEPROM is mapped to WUC.APME */
7492 NVM_INIT_CONTROL3_PORT_B,
7494 else
7496 NVM_INIT_CONTROL3_PORT_A,
7498 }
7500 /* fetch WoL from EEPROM */
7506 /* now that we have the eeprom settings, apply the special cases
7507 * where the eeprom may be wrong or the board simply won't support
7508 * wake on lan on a particular port
7509 */
7513 /* initialize the wol settings based on the eeprom settings */
7516 /* make sure adapter isn't asleep if manageability is enabled */
7521 /* save off EEPROM version number */
7527 }
7529 /* init PTP hardware clock */
7532 /* reset the hardware with the new settings */
7535 /* If the controller has AMT, do not set DRV_LOAD until the interface
7536 * is up. For all other cases, let the f/w know that the h/w is now
7537 * under the control of the driver.
7538 */
7547 /* carrier off reporting is important to ethtool even BEFORE open */
7559 err_register:
7562 err_eeprom:
7565 err_hw_init:
7568 err_sw_init:
7572 err_flashmap:
7574 err_ioremap:
7576 err_alloc_etherdev:
7578 err_pci_reg:
7579 err_dma:
7582 }
7584 /**
7585 * e1000_remove - Device Removal Routine
7586 * @pdev: PCI device information struct
7587 *
7588 * e1000_remove is called by the PCI subsystem to alert the driver
7589 * that it should release a PCI device. The could be caused by a
7590 * Hot-Plug event, or because the driver is going to be removed from
7591 * memory.
7592 **/
7594 {
7600 /* The timers may be rescheduled, so explicitly disable them
7601 * from being rescheduled.
7602 */
7618 }
7619 }
7626 /* Release control of h/w to f/w. If f/w is AMT enabled, this
7627 * would have already happened in close and is redundant.
7628 */
7643 /* AER disable */
7647 }
7649 /* PCI Error Recovery (ERS) */
7654 };
7661 board_82571 },
7682 board_80003es2lan },
7684 board_80003es2lan },
7686 board_80003es2lan },
7688 board_80003es2lan },
7768 };
7772 #ifdef CONFIG_PM_SLEEP
7779 #endif
7781 e1000e_pm_runtime_idle)
7782 };
7784 /* PCI Device API Driver */
7792 },
7795 };
7797 /**
7798 * e1000_init_module - Driver Registration Routine
7799 *
7800 * e1000_init_module is the first routine called when the driver is
7801 * loaded. All it does is register with the PCI subsystem.
7802 **/
7804 {
7806 e1000e_driver_version);
7810 }
7813 /**
7814 * e1000_exit_module - Driver Exit Cleanup Routine
7815 *
7816 * e1000_exit_module is called just before the driver is removed
7817 * from memory.
7818 **/
7820 {
7822 }
7830 /* netdev.c */