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gpio: rcar: Fix runtime PM imbalance on error
[linux/fpc-iii.git] / drivers / scsi / ufs / ufs-qcom.c
blob19aa5c44e0da6f58274183b21cea6f426ff90aac
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2013-2016, Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/acpi.h>
7 #include <linux/time.h>
8 #include <linux/of.h>
9 #include <linux/platform_device.h>
10 #include <linux/phy/phy.h>
11 #include <linux/gpio/consumer.h>
12 #include <linux/reset-controller.h>
13 #include <linux/devfreq.h>
14
15 #include "ufshcd.h"
16 #include "ufshcd-pltfrm.h"
17 #include "unipro.h"
18 #include "ufs-qcom.h"
19 #include "ufshci.h"
20 #include "ufs_quirks.h"
21 #define UFS_QCOM_DEFAULT_DBG_PRINT_EN \
22 (UFS_QCOM_DBG_PRINT_REGS_EN | UFS_QCOM_DBG_PRINT_TEST_BUS_EN)
23
24 enum {
25 TSTBUS_UAWM,
26 TSTBUS_UARM,
27 TSTBUS_TXUC,
28 TSTBUS_RXUC,
29 TSTBUS_DFC,
30 TSTBUS_TRLUT,
31 TSTBUS_TMRLUT,
32 TSTBUS_OCSC,
33 TSTBUS_UTP_HCI,
34 TSTBUS_COMBINED,
35 TSTBUS_WRAPPER,
36 TSTBUS_UNIPRO,
37 TSTBUS_MAX,
38 };
39
40 static struct ufs_qcom_host *ufs_qcom_hosts[MAX_UFS_QCOM_HOSTS];
41
42 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host);
43 static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba,
44 u32 clk_cycles);
45
46 static struct ufs_qcom_host *rcdev_to_ufs_host(struct reset_controller_dev *rcd)
47 {
48 return container_of(rcd, struct ufs_qcom_host, rcdev);
49 }
50
51 static void ufs_qcom_dump_regs_wrapper(struct ufs_hba *hba, int offset, int len,
52 const char *prefix, void *priv)
53 {
54 ufshcd_dump_regs(hba, offset, len * 4, prefix);
55 }
56
57 static int ufs_qcom_get_connected_tx_lanes(struct ufs_hba *hba, u32 *tx_lanes)
58 {
59 int err = 0;
60
61 err = ufshcd_dme_get(hba,
62 UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), tx_lanes);
63 if (err)
64 dev_err(hba->dev, "%s: couldn't read PA_CONNECTEDTXDATALANES %d\n",
65 __func__, err);
66
67 return err;
68 }
69
70 static int ufs_qcom_host_clk_get(struct device *dev,
71 const char *name, struct clk **clk_out, bool optional)
72 {
73 struct clk *clk;
74 int err = 0;
75
76 clk = devm_clk_get(dev, name);
77 if (!IS_ERR(clk)) {
78 *clk_out = clk;
79 return 0;
80 }
81
82 err = PTR_ERR(clk);
83
84 if (optional && err == -ENOENT) {
85 *clk_out = NULL;
86 return 0;
87 }
88
89 if (err != -EPROBE_DEFER)
90 dev_err(dev, "failed to get %s err %d\n", name, err);
91
92 return err;
93 }
94
95 static int ufs_qcom_host_clk_enable(struct device *dev,
96 const char *name, struct clk *clk)
97 {
98 int err = 0;
99
100 err = clk_prepare_enable(clk);
101 if (err)
102 dev_err(dev, "%s: %s enable failed %d\n", __func__, name, err);
103
104 return err;
105 }
106
107 static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host)
108 {
109 if (!host->is_lane_clks_enabled)
110 return;
111
112 clk_disable_unprepare(host->tx_l1_sync_clk);
113 clk_disable_unprepare(host->tx_l0_sync_clk);
114 clk_disable_unprepare(host->rx_l1_sync_clk);
115 clk_disable_unprepare(host->rx_l0_sync_clk);
116
117 host->is_lane_clks_enabled = false;
118 }
119
120 static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host)
121 {
122 int err = 0;
123 struct device *dev = host->hba->dev;
124
125 if (host->is_lane_clks_enabled)
126 return 0;
127
128 err = ufs_qcom_host_clk_enable(dev, "rx_lane0_sync_clk",
129 host->rx_l0_sync_clk);
130 if (err)
131 goto out;
132
133 err = ufs_qcom_host_clk_enable(dev, "tx_lane0_sync_clk",
134 host->tx_l0_sync_clk);
135 if (err)
136 goto disable_rx_l0;
137
138 err = ufs_qcom_host_clk_enable(dev, "rx_lane1_sync_clk",
139 host->rx_l1_sync_clk);
140 if (err)
141 goto disable_tx_l0;
142
143 err = ufs_qcom_host_clk_enable(dev, "tx_lane1_sync_clk",
144 host->tx_l1_sync_clk);
145 if (err)
146 goto disable_rx_l1;
147
148 host->is_lane_clks_enabled = true;
149 goto out;
150
151 disable_rx_l1:
152 clk_disable_unprepare(host->rx_l1_sync_clk);
153 disable_tx_l0:
154 clk_disable_unprepare(host->tx_l0_sync_clk);
155 disable_rx_l0:
156 clk_disable_unprepare(host->rx_l0_sync_clk);
157 out:
158 return err;
159 }
160
161 static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host)
162 {
163 int err = 0;
164 struct device *dev = host->hba->dev;
165
166 if (has_acpi_companion(dev))
167 return 0;
168
169 err = ufs_qcom_host_clk_get(dev, "rx_lane0_sync_clk",
170 &host->rx_l0_sync_clk, false);
171 if (err)
172 goto out;
173
174 err = ufs_qcom_host_clk_get(dev, "tx_lane0_sync_clk",
175 &host->tx_l0_sync_clk, false);
176 if (err)
177 goto out;
178
179 /* In case of single lane per direction, don't read lane1 clocks */
180 if (host->hba->lanes_per_direction > 1) {
181 err = ufs_qcom_host_clk_get(dev, "rx_lane1_sync_clk",
182 &host->rx_l1_sync_clk, false);
183 if (err)
184 goto out;
185
186 err = ufs_qcom_host_clk_get(dev, "tx_lane1_sync_clk",
187 &host->tx_l1_sync_clk, true);
188 }
189 out:
190 return err;
191 }
192
193 static int ufs_qcom_link_startup_post_change(struct ufs_hba *hba)
194 {
195 u32 tx_lanes;
196
197 return ufs_qcom_get_connected_tx_lanes(hba, &tx_lanes);
198 }
199
200 static int ufs_qcom_check_hibern8(struct ufs_hba *hba)
201 {
202 int err;
203 u32 tx_fsm_val = 0;
204 unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS);
205
206 do {
207 err = ufshcd_dme_get(hba,
208 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
209 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
210 &tx_fsm_val);
211 if (err || tx_fsm_val == TX_FSM_HIBERN8)
212 break;
213
214 /* sleep for max. 200us */
215 usleep_range(100, 200);
216 } while (time_before(jiffies, timeout));
217
218 /*
219 * we might have scheduled out for long during polling so
220 * check the state again.
221 */
222 if (time_after(jiffies, timeout))
223 err = ufshcd_dme_get(hba,
224 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
225 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
226 &tx_fsm_val);
227
228 if (err) {
229 dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n",
230 __func__, err);
231 } else if (tx_fsm_val != TX_FSM_HIBERN8) {
232 err = tx_fsm_val;
233 dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n",
234 __func__, err);
235 }
236
237 return err;
238 }
239
240 static void ufs_qcom_select_unipro_mode(struct ufs_qcom_host *host)
241 {
242 ufshcd_rmwl(host->hba, QUNIPRO_SEL,
243 ufs_qcom_cap_qunipro(host) ? QUNIPRO_SEL : 0,
244 REG_UFS_CFG1);
245 /* make sure above configuration is applied before we return */
246 mb();
247 }
248
249 /**
250 * ufs_qcom_host_reset - reset host controller and PHY
251 */
252 static int ufs_qcom_host_reset(struct ufs_hba *hba)
253 {
254 int ret = 0;
255 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
256
257 if (!host->core_reset) {
258 dev_warn(hba->dev, "%s: reset control not set\n", __func__);
259 goto out;
260 }
261
262 ret = reset_control_assert(host->core_reset);
263 if (ret) {
264 dev_err(hba->dev, "%s: core_reset assert failed, err = %d\n",
265 __func__, ret);
266 goto out;
267 }
268
269 /*
270 * The hardware requirement for delay between assert/deassert
271 * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to
272 * ~125us (4/32768). To be on the safe side add 200us delay.
273 */
274 usleep_range(200, 210);
275
276 ret = reset_control_deassert(host->core_reset);
277 if (ret)
278 dev_err(hba->dev, "%s: core_reset deassert failed, err = %d\n",
279 __func__, ret);
280
281 usleep_range(1000, 1100);
282
283 out:
284 return ret;
285 }
286
287 static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
288 {
289 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
290 struct phy *phy = host->generic_phy;
291 int ret = 0;
292 bool is_rate_B = (UFS_QCOM_LIMIT_HS_RATE == PA_HS_MODE_B)
293 ? true : false;
294
295 /* Reset UFS Host Controller and PHY */
296 ret = ufs_qcom_host_reset(hba);
297 if (ret)
298 dev_warn(hba->dev, "%s: host reset returned %d\n",
299 __func__, ret);
300
301 if (is_rate_B)
302 phy_set_mode(phy, PHY_MODE_UFS_HS_B);
303
304 /* phy initialization - calibrate the phy */
305 ret = phy_init(phy);
306 if (ret) {
307 dev_err(hba->dev, "%s: phy init failed, ret = %d\n",
308 __func__, ret);
309 goto out;
310 }
311
312 /* power on phy - start serdes and phy's power and clocks */
313 ret = phy_power_on(phy);
314 if (ret) {
315 dev_err(hba->dev, "%s: phy power on failed, ret = %d\n",
316 __func__, ret);
317 goto out_disable_phy;
318 }
319
320 ufs_qcom_select_unipro_mode(host);
321
322 return 0;
323
324 out_disable_phy:
325 phy_exit(phy);
326 out:
327 return ret;
328 }
329
330 /*
331 * The UTP controller has a number of internal clock gating cells (CGCs).
332 * Internal hardware sub-modules within the UTP controller control the CGCs.
333 * Hardware CGCs disable the clock to inactivate UTP sub-modules not involved
334 * in a specific operation, UTP controller CGCs are by default disabled and
335 * this function enables them (after every UFS link startup) to save some power
336 * leakage.
337 */
338 static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba)
339 {
340 ufshcd_writel(hba,
341 ufshcd_readl(hba, REG_UFS_CFG2) | REG_UFS_CFG2_CGC_EN_ALL,
342 REG_UFS_CFG2);
343
344 /* Ensure that HW clock gating is enabled before next operations */
345 mb();
346 }
347
348 static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba,
349 enum ufs_notify_change_status status)
350 {
351 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
352 int err = 0;
353
354 switch (status) {
355 case PRE_CHANGE:
356 ufs_qcom_power_up_sequence(hba);
357 /*
358 * The PHY PLL output is the source of tx/rx lane symbol
359 * clocks, hence, enable the lane clocks only after PHY
360 * is initialized.
361 */
362 err = ufs_qcom_enable_lane_clks(host);
363 break;
364 case POST_CHANGE:
365 /* check if UFS PHY moved from DISABLED to HIBERN8 */
366 err = ufs_qcom_check_hibern8(hba);
367 ufs_qcom_enable_hw_clk_gating(hba);
368
369 break;
370 default:
371 dev_err(hba->dev, "%s: invalid status %d\n", __func__, status);
372 err = -EINVAL;
373 break;
374 }
375 return err;
376 }
377
378 /**
379 * Returns zero for success and non-zero in case of a failure
380 */
381 static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear,
382 u32 hs, u32 rate, bool update_link_startup_timer)
383 {
384 int ret = 0;
385 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
386 struct ufs_clk_info *clki;
387 u32 core_clk_period_in_ns;
388 u32 tx_clk_cycles_per_us = 0;
389 unsigned long core_clk_rate = 0;
390 u32 core_clk_cycles_per_us = 0;
391
392 static u32 pwm_fr_table[][2] = {
393 {UFS_PWM_G1, 0x1},
394 {UFS_PWM_G2, 0x1},
395 {UFS_PWM_G3, 0x1},
396 {UFS_PWM_G4, 0x1},
397 };
398
399 static u32 hs_fr_table_rA[][2] = {
400 {UFS_HS_G1, 0x1F},
401 {UFS_HS_G2, 0x3e},
402 {UFS_HS_G3, 0x7D},
403 };
404
405 static u32 hs_fr_table_rB[][2] = {
406 {UFS_HS_G1, 0x24},
407 {UFS_HS_G2, 0x49},
408 {UFS_HS_G3, 0x92},
409 };
410
411 /*
412 * The Qunipro controller does not use following registers:
413 * SYS1CLK_1US_REG, TX_SYMBOL_CLK_1US_REG, CLK_NS_REG &
414 * UFS_REG_PA_LINK_STARTUP_TIMER
415 * But UTP controller uses SYS1CLK_1US_REG register for Interrupt
416 * Aggregation logic.
417 */
418 if (ufs_qcom_cap_qunipro(host) && !ufshcd_is_intr_aggr_allowed(hba))
419 goto out;
420
421 if (gear == 0) {
422 dev_err(hba->dev, "%s: invalid gear = %d\n", __func__, gear);
423 goto out_error;
424 }
425
426 list_for_each_entry(clki, &hba->clk_list_head, list) {
427 if (!strcmp(clki->name, "core_clk"))
428 core_clk_rate = clk_get_rate(clki->clk);
429 }
430
431 /* If frequency is smaller than 1MHz, set to 1MHz */
432 if (core_clk_rate < DEFAULT_CLK_RATE_HZ)
433 core_clk_rate = DEFAULT_CLK_RATE_HZ;
434
435 core_clk_cycles_per_us = core_clk_rate / USEC_PER_SEC;
436 if (ufshcd_readl(hba, REG_UFS_SYS1CLK_1US) != core_clk_cycles_per_us) {
437 ufshcd_writel(hba, core_clk_cycles_per_us, REG_UFS_SYS1CLK_1US);
438 /*
439 * make sure above write gets applied before we return from
440 * this function.
441 */
442 mb();
443 }
444
445 if (ufs_qcom_cap_qunipro(host))
446 goto out;
447
448 core_clk_period_in_ns = NSEC_PER_SEC / core_clk_rate;
449 core_clk_period_in_ns <<= OFFSET_CLK_NS_REG;
450 core_clk_period_in_ns &= MASK_CLK_NS_REG;
451
452 switch (hs) {
453 case FASTAUTO_MODE:
454 case FAST_MODE:
455 if (rate == PA_HS_MODE_A) {
456 if (gear > ARRAY_SIZE(hs_fr_table_rA)) {
457 dev_err(hba->dev,
458 "%s: index %d exceeds table size %zu\n",
459 __func__, gear,
460 ARRAY_SIZE(hs_fr_table_rA));
461 goto out_error;
462 }
463 tx_clk_cycles_per_us = hs_fr_table_rA[gear-1][1];
464 } else if (rate == PA_HS_MODE_B) {
465 if (gear > ARRAY_SIZE(hs_fr_table_rB)) {
466 dev_err(hba->dev,
467 "%s: index %d exceeds table size %zu\n",
468 __func__, gear,
469 ARRAY_SIZE(hs_fr_table_rB));
470 goto out_error;
471 }
472 tx_clk_cycles_per_us = hs_fr_table_rB[gear-1][1];
473 } else {
474 dev_err(hba->dev, "%s: invalid rate = %d\n",
475 __func__, rate);
476 goto out_error;
477 }
478 break;
479 case SLOWAUTO_MODE:
480 case SLOW_MODE:
481 if (gear > ARRAY_SIZE(pwm_fr_table)) {
482 dev_err(hba->dev,
483 "%s: index %d exceeds table size %zu\n",
484 __func__, gear,
485 ARRAY_SIZE(pwm_fr_table));
486 goto out_error;
487 }
488 tx_clk_cycles_per_us = pwm_fr_table[gear-1][1];
489 break;
490 case UNCHANGED:
491 default:
492 dev_err(hba->dev, "%s: invalid mode = %d\n", __func__, hs);
493 goto out_error;
494 }
495
496 if (ufshcd_readl(hba, REG_UFS_TX_SYMBOL_CLK_NS_US) !=
497 (core_clk_period_in_ns | tx_clk_cycles_per_us)) {
498 /* this register 2 fields shall be written at once */
499 ufshcd_writel(hba, core_clk_period_in_ns | tx_clk_cycles_per_us,
500 REG_UFS_TX_SYMBOL_CLK_NS_US);
501 /*
502 * make sure above write gets applied before we return from
503 * this function.
504 */
505 mb();
506 }
507
508 if (update_link_startup_timer) {
509 ufshcd_writel(hba, ((core_clk_rate / MSEC_PER_SEC) * 100),
510 REG_UFS_PA_LINK_STARTUP_TIMER);
511 /*
512 * make sure that this configuration is applied before
513 * we return
514 */
515 mb();
516 }
517 goto out;
518
519 out_error:
520 ret = -EINVAL;
521 out:
522 return ret;
523 }
524
525 static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,
526 enum ufs_notify_change_status status)
527 {
528 int err = 0;
529 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
530
531 switch (status) {
532 case PRE_CHANGE:
533 if (ufs_qcom_cfg_timers(hba, UFS_PWM_G1, SLOWAUTO_MODE,
534 0, true)) {
535 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
536 __func__);
537 err = -EINVAL;
538 goto out;
539 }
540
541 if (ufs_qcom_cap_qunipro(host))
542 /*
543 * set unipro core clock cycles to 150 & clear clock
544 * divider
545 */
546 err = ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba,
547 150);
548
549 /*
550 * Some UFS devices (and may be host) have issues if LCC is
551 * enabled. So we are setting PA_Local_TX_LCC_Enable to 0
552 * before link startup which will make sure that both host
553 * and device TX LCC are disabled once link startup is
554 * completed.
555 */
556 if (ufshcd_get_local_unipro_ver(hba) != UFS_UNIPRO_VER_1_41)
557 err = ufshcd_disable_host_tx_lcc(hba);
558
559 break;
560 case POST_CHANGE:
561 ufs_qcom_link_startup_post_change(hba);
562 break;
563 default:
564 break;
565 }
566
567 out:
568 return err;
569 }
570
571 static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
572 {
573 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
574 struct phy *phy = host->generic_phy;
575 int ret = 0;
576
577 if (ufs_qcom_is_link_off(hba)) {
578 /*
579 * Disable the tx/rx lane symbol clocks before PHY is
580 * powered down as the PLL source should be disabled
581 * after downstream clocks are disabled.
582 */
583 ufs_qcom_disable_lane_clks(host);
584 phy_power_off(phy);
585
586 } else if (!ufs_qcom_is_link_active(hba)) {
587 ufs_qcom_disable_lane_clks(host);
588 }
589
590 return ret;
591 }
592
593 static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
594 {
595 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
596 struct phy *phy = host->generic_phy;
597 int err;
598
599 if (ufs_qcom_is_link_off(hba)) {
600 err = phy_power_on(phy);
601 if (err) {
602 dev_err(hba->dev, "%s: failed PHY power on: %d\n",
603 __func__, err);
604 return err;
605 }
606
607 err = ufs_qcom_enable_lane_clks(host);
608 if (err)
609 return err;
610
611 } else if (!ufs_qcom_is_link_active(hba)) {
612 err = ufs_qcom_enable_lane_clks(host);
613 if (err)
614 return err;
615 }
616
617 hba->is_sys_suspended = false;
618 return 0;
619 }
620
621 #ifdef CONFIG_MSM_BUS_SCALING
622 static int ufs_qcom_get_bus_vote(struct ufs_qcom_host *host,
623 const char *speed_mode)
624 {
625 struct device *dev = host->hba->dev;
626 struct device_node *np = dev->of_node;
627 int err;
628 const char *key = "qcom,bus-vector-names";
629
630 if (!speed_mode) {
631 err = -EINVAL;
632 goto out;
633 }
634
635 if (host->bus_vote.is_max_bw_needed && !!strcmp(speed_mode, "MIN"))
636 err = of_property_match_string(np, key, "MAX");
637 else
638 err = of_property_match_string(np, key, speed_mode);
639
640 out:
641 if (err < 0)
642 dev_err(dev, "%s: Invalid %s mode %d\n",
643 __func__, speed_mode, err);
644 return err;
645 }
646
647 static void ufs_qcom_get_speed_mode(struct ufs_pa_layer_attr *p, char *result)
648 {
649 int gear = max_t(u32, p->gear_rx, p->gear_tx);
650 int lanes = max_t(u32, p->lane_rx, p->lane_tx);
651 int pwr;
652
653 /* default to PWM Gear 1, Lane 1 if power mode is not initialized */
654 if (!gear)
655 gear = 1;
656
657 if (!lanes)
658 lanes = 1;
659
660 if (!p->pwr_rx && !p->pwr_tx) {
661 pwr = SLOWAUTO_MODE;
662 snprintf(result, BUS_VECTOR_NAME_LEN, "MIN");
663 } else if (p->pwr_rx == FAST_MODE || p->pwr_rx == FASTAUTO_MODE ||
664 p->pwr_tx == FAST_MODE || p->pwr_tx == FASTAUTO_MODE) {
665 pwr = FAST_MODE;
666 snprintf(result, BUS_VECTOR_NAME_LEN, "%s_R%s_G%d_L%d", "HS",
667 p->hs_rate == PA_HS_MODE_B ? "B" : "A", gear, lanes);
668 } else {
669 pwr = SLOW_MODE;
670 snprintf(result, BUS_VECTOR_NAME_LEN, "%s_G%d_L%d",
671 "PWM", gear, lanes);
672 }
673 }
674
675 static int __ufs_qcom_set_bus_vote(struct ufs_qcom_host *host, int vote)
676 {
677 int err = 0;
678
679 if (vote != host->bus_vote.curr_vote) {
680 err = msm_bus_scale_client_update_request(
681 host->bus_vote.client_handle, vote);
682 if (err) {
683 dev_err(host->hba->dev,
684 "%s: msm_bus_scale_client_update_request() failed: bus_client_handle=0x%x, vote=%d, err=%d\n",
685 __func__, host->bus_vote.client_handle,
686 vote, err);
687 goto out;
688 }
689
690 host->bus_vote.curr_vote = vote;
691 }
692 out:
693 return err;
694 }
695
696 static int ufs_qcom_update_bus_bw_vote(struct ufs_qcom_host *host)
697 {
698 int vote;
699 int err = 0;
700 char mode[BUS_VECTOR_NAME_LEN];
701
702 ufs_qcom_get_speed_mode(&host->dev_req_params, mode);
703
704 vote = ufs_qcom_get_bus_vote(host, mode);
705 if (vote >= 0)
706 err = __ufs_qcom_set_bus_vote(host, vote);
707 else
708 err = vote;
709
710 if (err)
711 dev_err(host->hba->dev, "%s: failed %d\n", __func__, err);
712 else
713 host->bus_vote.saved_vote = vote;
714 return err;
715 }
716
717 static int ufs_qcom_set_bus_vote(struct ufs_hba *hba, bool on)
718 {
719 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
720 int vote, err;
721
722 /*
723 * In case ufs_qcom_init() is not yet done, simply ignore.
724 * This ufs_qcom_set_bus_vote() shall be called from
725 * ufs_qcom_init() after init is done.
726 */
727 if (!host)
728 return 0;
729
730 if (on) {
731 vote = host->bus_vote.saved_vote;
732 if (vote == host->bus_vote.min_bw_vote)
733 ufs_qcom_update_bus_bw_vote(host);
734 } else {
735 vote = host->bus_vote.min_bw_vote;
736 }
737
738 err = __ufs_qcom_set_bus_vote(host, vote);
739 if (err)
740 dev_err(hba->dev, "%s: set bus vote failed %d\n",
741 __func__, err);
742
743 return err;
744 }
745
746 static ssize_t
747 show_ufs_to_mem_max_bus_bw(struct device *dev, struct device_attribute *attr,
748 char *buf)
749 {
750 struct ufs_hba *hba = dev_get_drvdata(dev);
751 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
752
753 return snprintf(buf, PAGE_SIZE, "%u\n",
754 host->bus_vote.is_max_bw_needed);
755 }
756
757 static ssize_t
758 store_ufs_to_mem_max_bus_bw(struct device *dev, struct device_attribute *attr,
759 const char *buf, size_t count)
760 {
761 struct ufs_hba *hba = dev_get_drvdata(dev);
762 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
763 uint32_t value;
764
765 if (!kstrtou32(buf, 0, &value)) {
766 host->bus_vote.is_max_bw_needed = !!value;
767 ufs_qcom_update_bus_bw_vote(host);
768 }
769
770 return count;
771 }
772
773 static int ufs_qcom_bus_register(struct ufs_qcom_host *host)
774 {
775 int err;
776 struct msm_bus_scale_pdata *bus_pdata;
777 struct device *dev = host->hba->dev;
778 struct platform_device *pdev = to_platform_device(dev);
779 struct device_node *np = dev->of_node;
780
781 bus_pdata = msm_bus_cl_get_pdata(pdev);
782 if (!bus_pdata) {
783 dev_err(dev, "%s: failed to get bus vectors\n", __func__);
784 err = -ENODATA;
785 goto out;
786 }
787
788 err = of_property_count_strings(np, "qcom,bus-vector-names");
789 if (err < 0 || err != bus_pdata->num_usecases) {
790 dev_err(dev, "%s: qcom,bus-vector-names not specified correctly %d\n",
791 __func__, err);
792 goto out;
793 }
794
795 host->bus_vote.client_handle = msm_bus_scale_register_client(bus_pdata);
796 if (!host->bus_vote.client_handle) {
797 dev_err(dev, "%s: msm_bus_scale_register_client failed\n",
798 __func__);
799 err = -EFAULT;
800 goto out;
801 }
802
803 /* cache the vote index for minimum and maximum bandwidth */
804 host->bus_vote.min_bw_vote = ufs_qcom_get_bus_vote(host, "MIN");
805 host->bus_vote.max_bw_vote = ufs_qcom_get_bus_vote(host, "MAX");
806
807 host->bus_vote.max_bus_bw.show = show_ufs_to_mem_max_bus_bw;
808 host->bus_vote.max_bus_bw.store = store_ufs_to_mem_max_bus_bw;
809 sysfs_attr_init(&host->bus_vote.max_bus_bw.attr);
810 host->bus_vote.max_bus_bw.attr.name = "max_bus_bw";
811 host->bus_vote.max_bus_bw.attr.mode = S_IRUGO | S_IWUSR;
812 err = device_create_file(dev, &host->bus_vote.max_bus_bw);
813 out:
814 return err;
815 }
816 #else /* CONFIG_MSM_BUS_SCALING */
817 static int ufs_qcom_update_bus_bw_vote(struct ufs_qcom_host *host)
818 {
819 return 0;
820 }
821
822 static int ufs_qcom_set_bus_vote(struct ufs_hba *host, bool on)
823 {
824 return 0;
825 }
826
827 static int ufs_qcom_bus_register(struct ufs_qcom_host *host)
828 {
829 return 0;
830 }
831 #endif /* CONFIG_MSM_BUS_SCALING */
832
833 static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable)
834 {
835 if (host->dev_ref_clk_ctrl_mmio &&
836 (enable ^ host->is_dev_ref_clk_enabled)) {
837 u32 temp = readl_relaxed(host->dev_ref_clk_ctrl_mmio);
838
839 if (enable)
840 temp |= host->dev_ref_clk_en_mask;
841 else
842 temp &= ~host->dev_ref_clk_en_mask;
843
844 /*
845 * If we are here to disable this clock it might be immediately
846 * after entering into hibern8 in which case we need to make
847 * sure that device ref_clk is active for specific time after
848 * hibern8 enter.
849 */
850 if (!enable) {
851 unsigned long gating_wait;
852
853 gating_wait = host->hba->dev_info.clk_gating_wait_us;
854 if (!gating_wait) {
855 udelay(1);
856 } else {
857 /*
858 * bRefClkGatingWaitTime defines the minimum
859 * time for which the reference clock is
860 * required by device during transition from
861 * HS-MODE to LS-MODE or HIBERN8 state. Give it
862 * more delay to be on the safe side.
863 */
864 gating_wait += 10;
865 usleep_range(gating_wait, gating_wait + 10);
866 }
867 }
868
869 writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio);
870
871 /* ensure that ref_clk is enabled/disabled before we return */
872 wmb();
873
874 /*
875 * If we call hibern8 exit after this, we need to make sure that
876 * device ref_clk is stable for at least 1us before the hibern8
877 * exit command.
878 */
879 if (enable)
880 udelay(1);
881
882 host->is_dev_ref_clk_enabled = enable;
883 }
884 }
885
886 static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
887 enum ufs_notify_change_status status,
888 struct ufs_pa_layer_attr *dev_max_params,
889 struct ufs_pa_layer_attr *dev_req_params)
890 {
891 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
892 struct ufs_dev_params ufs_qcom_cap;
893 int ret = 0;
894
895 if (!dev_req_params) {
896 pr_err("%s: incoming dev_req_params is NULL\n", __func__);
897 ret = -EINVAL;
898 goto out;
899 }
900
901 switch (status) {
902 case PRE_CHANGE:
903 ufs_qcom_cap.tx_lanes = UFS_QCOM_LIMIT_NUM_LANES_TX;
904 ufs_qcom_cap.rx_lanes = UFS_QCOM_LIMIT_NUM_LANES_RX;
905 ufs_qcom_cap.hs_rx_gear = UFS_QCOM_LIMIT_HSGEAR_RX;
906 ufs_qcom_cap.hs_tx_gear = UFS_QCOM_LIMIT_HSGEAR_TX;
907 ufs_qcom_cap.pwm_rx_gear = UFS_QCOM_LIMIT_PWMGEAR_RX;
908 ufs_qcom_cap.pwm_tx_gear = UFS_QCOM_LIMIT_PWMGEAR_TX;
909 ufs_qcom_cap.rx_pwr_pwm = UFS_QCOM_LIMIT_RX_PWR_PWM;
910 ufs_qcom_cap.tx_pwr_pwm = UFS_QCOM_LIMIT_TX_PWR_PWM;
911 ufs_qcom_cap.rx_pwr_hs = UFS_QCOM_LIMIT_RX_PWR_HS;
912 ufs_qcom_cap.tx_pwr_hs = UFS_QCOM_LIMIT_TX_PWR_HS;
913 ufs_qcom_cap.hs_rate = UFS_QCOM_LIMIT_HS_RATE;
914 ufs_qcom_cap.desired_working_mode =
915 UFS_QCOM_LIMIT_DESIRED_MODE;
916
917 if (host->hw_ver.major == 0x1) {
918 /*
919 * HS-G3 operations may not reliably work on legacy QCOM
920 * UFS host controller hardware even though capability
921 * exchange during link startup phase may end up
922 * negotiating maximum supported gear as G3.
923 * Hence downgrade the maximum supported gear to HS-G2.
924 */
925 if (ufs_qcom_cap.hs_tx_gear > UFS_HS_G2)
926 ufs_qcom_cap.hs_tx_gear = UFS_HS_G2;
927 if (ufs_qcom_cap.hs_rx_gear > UFS_HS_G2)
928 ufs_qcom_cap.hs_rx_gear = UFS_HS_G2;
929 }
930
931 ret = ufshcd_get_pwr_dev_param(&ufs_qcom_cap,
932 dev_max_params,
933 dev_req_params);
934 if (ret) {
935 pr_err("%s: failed to determine capabilities\n",
936 __func__);
937 goto out;
938 }
939
940 /* enable the device ref clock before changing to HS mode */
941 if (!ufshcd_is_hs_mode(&hba->pwr_info) &&
942 ufshcd_is_hs_mode(dev_req_params))
943 ufs_qcom_dev_ref_clk_ctrl(host, true);
944
945 if (host->hw_ver.major >= 0x4) {
946 if (dev_req_params->gear_tx == UFS_HS_G4) {
947 /* INITIAL ADAPT */
948 ufshcd_dme_set(hba,
949 UIC_ARG_MIB(PA_TXHSADAPTTYPE),
950 PA_INITIAL_ADAPT);
951 } else {
952 /* NO ADAPT */
953 ufshcd_dme_set(hba,
954 UIC_ARG_MIB(PA_TXHSADAPTTYPE),
955 PA_NO_ADAPT);
956 }
957 }
958 break;
959 case POST_CHANGE:
960 if (ufs_qcom_cfg_timers(hba, dev_req_params->gear_rx,
961 dev_req_params->pwr_rx,
962 dev_req_params->hs_rate, false)) {
963 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
964 __func__);
965 /*
966 * we return error code at the end of the routine,
967 * but continue to configure UFS_PHY_TX_LANE_ENABLE
968 * and bus voting as usual
969 */
970 ret = -EINVAL;
971 }
972
973 /* cache the power mode parameters to use internally */
974 memcpy(&host->dev_req_params,
975 dev_req_params, sizeof(*dev_req_params));
976 ufs_qcom_update_bus_bw_vote(host);
977
978 /* disable the device ref clock if entered PWM mode */
979 if (ufshcd_is_hs_mode(&hba->pwr_info) &&
980 !ufshcd_is_hs_mode(dev_req_params))
981 ufs_qcom_dev_ref_clk_ctrl(host, false);
982 break;
983 default:
984 ret = -EINVAL;
985 break;
986 }
987 out:
988 return ret;
989 }
990
991 static int ufs_qcom_quirk_host_pa_saveconfigtime(struct ufs_hba *hba)
992 {
993 int err;
994 u32 pa_vs_config_reg1;
995
996 err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
997 &pa_vs_config_reg1);
998 if (err)
999 goto out;
1000
1001 /* Allow extension of MSB bits of PA_SaveConfigTime attribute */
1002 err = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
1003 (pa_vs_config_reg1 | (1 << 12)));
1004
1005 out:
1006 return err;
1007 }
1008
1009 static int ufs_qcom_apply_dev_quirks(struct ufs_hba *hba)
1010 {
1011 int err = 0;
1012
1013 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME)
1014 err = ufs_qcom_quirk_host_pa_saveconfigtime(hba);
1015
1016 if (hba->dev_info.wmanufacturerid == UFS_VENDOR_WDC)
1017 hba->dev_quirks |= UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE;
1018
1019 return err;
1020 }
1021
1022 static u32 ufs_qcom_get_ufs_hci_version(struct ufs_hba *hba)
1023 {
1024 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1025
1026 if (host->hw_ver.major == 0x1)
1027 return UFSHCI_VERSION_11;
1028 else
1029 return UFSHCI_VERSION_20;
1030 }
1031
1032 /**
1033 * ufs_qcom_advertise_quirks - advertise the known QCOM UFS controller quirks
1034 * @hba: host controller instance
1035 *
1036 * QCOM UFS host controller might have some non standard behaviours (quirks)
1037 * than what is specified by UFSHCI specification. Advertise all such
1038 * quirks to standard UFS host controller driver so standard takes them into
1039 * account.
1040 */
1041 static void ufs_qcom_advertise_quirks(struct ufs_hba *hba)
1042 {
1043 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1044
1045 if (host->hw_ver.major == 0x01) {
1046 hba->quirks |= UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS
1047 | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP
1048 | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE;
1049
1050 if (host->hw_ver.minor == 0x0001 && host->hw_ver.step == 0x0001)
1051 hba->quirks |= UFSHCD_QUIRK_BROKEN_INTR_AGGR;
1052
1053 hba->quirks |= UFSHCD_QUIRK_BROKEN_LCC;
1054 }
1055
1056 if (host->hw_ver.major == 0x2) {
1057 hba->quirks |= UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION;
1058
1059 if (!ufs_qcom_cap_qunipro(host))
1060 /* Legacy UniPro mode still need following quirks */
1061 hba->quirks |= (UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS
1062 | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE
1063 | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP);
1064 }
1065 }
1066
1067 static void ufs_qcom_set_caps(struct ufs_hba *hba)
1068 {
1069 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1070
1071 hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING;
1072 hba->caps |= UFSHCD_CAP_CLK_SCALING;
1073 hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND;
1074
1075 if (host->hw_ver.major >= 0x2) {
1076 host->caps = UFS_QCOM_CAP_QUNIPRO |
1077 UFS_QCOM_CAP_RETAIN_SEC_CFG_AFTER_PWR_COLLAPSE;
1078 }
1079 }
1080
1081 /**
1082 * ufs_qcom_setup_clocks - enables/disable clocks
1083 * @hba: host controller instance
1084 * @on: If true, enable clocks else disable them.
1085 * @status: PRE_CHANGE or POST_CHANGE notify
1086 *
1087 * Returns 0 on success, non-zero on failure.
1088 */
1089 static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
1090 enum ufs_notify_change_status status)
1091 {
1092 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1093 int err = 0;
1094
1095 /*
1096 * In case ufs_qcom_init() is not yet done, simply ignore.
1097 * This ufs_qcom_setup_clocks() shall be called from
1098 * ufs_qcom_init() after init is done.
1099 */
1100 if (!host)
1101 return 0;
1102
1103 switch (status) {
1104 case PRE_CHANGE:
1105 if (on) {
1106 err = ufs_qcom_set_bus_vote(hba, true);
1107 } else {
1108 if (!ufs_qcom_is_link_active(hba)) {
1109 /* disable device ref_clk */
1110 ufs_qcom_dev_ref_clk_ctrl(host, false);
1111 }
1112 }
1113 break;
1114 case POST_CHANGE:
1115 if (on) {
1116 /* enable the device ref clock for HS mode*/
1117 if (ufshcd_is_hs_mode(&hba->pwr_info))
1118 ufs_qcom_dev_ref_clk_ctrl(host, true);
1119 } else {
1120 err = ufs_qcom_set_bus_vote(hba, false);
1121 }
1122 break;
1123 }
1124
1125 return err;
1126 }
1127
1128 static int
1129 ufs_qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
1130 {
1131 struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
1132
1133 /* Currently this code only knows about a single reset. */
1134 WARN_ON(id);
1135 ufs_qcom_assert_reset(host->hba);
1136 /* provide 1ms delay to let the reset pulse propagate. */
1137 usleep_range(1000, 1100);
1138 return 0;
1139 }
1140
1141 static int
1142 ufs_qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
1143 {
1144 struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
1145
1146 /* Currently this code only knows about a single reset. */
1147 WARN_ON(id);
1148 ufs_qcom_deassert_reset(host->hba);
1149
1150 /*
1151 * after reset deassertion, phy will need all ref clocks,
1152 * voltage, current to settle down before starting serdes.
1153 */
1154 usleep_range(1000, 1100);
1155 return 0;
1156 }
1157
1158 static const struct reset_control_ops ufs_qcom_reset_ops = {
1159 .assert = ufs_qcom_reset_assert,
1160 .deassert = ufs_qcom_reset_deassert,
1161 };
1162
1163 #define ANDROID_BOOT_DEV_MAX 30
1164 static char android_boot_dev[ANDROID_BOOT_DEV_MAX];
1165
1166 #ifndef MODULE
1167 static int __init get_android_boot_dev(char *str)
1168 {
1169 strlcpy(android_boot_dev, str, ANDROID_BOOT_DEV_MAX);
1170 return 1;
1171 }
1172 __setup("androidboot.bootdevice=", get_android_boot_dev);
1173 #endif
1174
1175 /**
1176 * ufs_qcom_init - bind phy with controller
1177 * @hba: host controller instance
1178 *
1179 * Binds PHY with controller and powers up PHY enabling clocks
1180 * and regulators.
1181 *
1182 * Returns -EPROBE_DEFER if binding fails, returns negative error
1183 * on phy power up failure and returns zero on success.
1184 */
1185 static int ufs_qcom_init(struct ufs_hba *hba)
1186 {
1187 int err;
1188 struct device *dev = hba->dev;
1189 struct platform_device *pdev = to_platform_device(dev);
1190 struct ufs_qcom_host *host;
1191 struct resource *res;
1192
1193 if (strlen(android_boot_dev) && strcmp(android_boot_dev, dev_name(dev)))
1194 return -ENODEV;
1195
1196 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
1197 if (!host) {
1198 err = -ENOMEM;
1199 dev_err(dev, "%s: no memory for qcom ufs host\n", __func__);
1200 goto out;
1201 }
1202
1203 /* Make a two way bind between the qcom host and the hba */
1204 host->hba = hba;
1205 ufshcd_set_variant(hba, host);
1206
1207 /* Setup the reset control of HCI */
1208 host->core_reset = devm_reset_control_get(hba->dev, "rst");
1209 if (IS_ERR(host->core_reset)) {
1210 err = PTR_ERR(host->core_reset);
1211 dev_warn(dev, "Failed to get reset control %d\n", err);
1212 host->core_reset = NULL;
1213 err = 0;
1214 }
1215
1216 /* Fire up the reset controller. Failure here is non-fatal. */
1217 host->rcdev.of_node = dev->of_node;
1218 host->rcdev.ops = &ufs_qcom_reset_ops;
1219 host->rcdev.owner = dev->driver->owner;
1220 host->rcdev.nr_resets = 1;
1221 err = devm_reset_controller_register(dev, &host->rcdev);
1222 if (err) {
1223 dev_warn(dev, "Failed to register reset controller\n");
1224 err = 0;
1225 }
1226
1227 /*
1228 * voting/devoting device ref_clk source is time consuming hence
1229 * skip devoting it during aggressive clock gating. This clock
1230 * will still be gated off during runtime suspend.
1231 */
1232 host->generic_phy = devm_phy_get(dev, "ufsphy");
1233
1234 if (host->generic_phy == ERR_PTR(-EPROBE_DEFER)) {
1235 /*
1236 * UFS driver might be probed before the phy driver does.
1237 * In that case we would like to return EPROBE_DEFER code.
1238 */
1239 err = -EPROBE_DEFER;
1240 dev_warn(dev, "%s: required phy device. hasn't probed yet. err = %d\n",
1241 __func__, err);
1242 goto out_variant_clear;
1243 } else if (IS_ERR(host->generic_phy)) {
1244 if (has_acpi_companion(dev)) {
1245 host->generic_phy = NULL;
1246 } else {
1247 err = PTR_ERR(host->generic_phy);
1248 dev_err(dev, "%s: PHY get failed %d\n", __func__, err);
1249 goto out_variant_clear;
1250 }
1251 }
1252
1253 host->device_reset = devm_gpiod_get_optional(dev, "reset",
1254 GPIOD_OUT_HIGH);
1255 if (IS_ERR(host->device_reset)) {
1256 err = PTR_ERR(host->device_reset);
1257 if (err != -EPROBE_DEFER)
1258 dev_err(dev, "failed to acquire reset gpio: %d\n", err);
1259 goto out_variant_clear;
1260 }
1261
1262 err = ufs_qcom_bus_register(host);
1263 if (err)
1264 goto out_variant_clear;
1265
1266 ufs_qcom_get_controller_revision(hba, &host->hw_ver.major,
1267 &host->hw_ver.minor, &host->hw_ver.step);
1268
1269 /*
1270 * for newer controllers, device reference clock control bit has
1271 * moved inside UFS controller register address space itself.
1272 */
1273 if (host->hw_ver.major >= 0x02) {
1274 host->dev_ref_clk_ctrl_mmio = hba->mmio_base + REG_UFS_CFG1;
1275 host->dev_ref_clk_en_mask = BIT(26);
1276 } else {
1277 /* "dev_ref_clk_ctrl_mem" is optional resource */
1278 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1279 if (res) {
1280 host->dev_ref_clk_ctrl_mmio =
1281 devm_ioremap_resource(dev, res);
1282 if (IS_ERR(host->dev_ref_clk_ctrl_mmio)) {
1283 dev_warn(dev,
1284 "%s: could not map dev_ref_clk_ctrl_mmio, err %ld\n",
1285 __func__,
1286 PTR_ERR(host->dev_ref_clk_ctrl_mmio));
1287 host->dev_ref_clk_ctrl_mmio = NULL;
1288 }
1289 host->dev_ref_clk_en_mask = BIT(5);
1290 }
1291 }
1292
1293 err = ufs_qcom_init_lane_clks(host);
1294 if (err)
1295 goto out_variant_clear;
1296
1297 ufs_qcom_set_caps(hba);
1298 ufs_qcom_advertise_quirks(hba);
1299
1300 ufs_qcom_set_bus_vote(hba, true);
1301 ufs_qcom_setup_clocks(hba, true, POST_CHANGE);
1302
1303 if (hba->dev->id < MAX_UFS_QCOM_HOSTS)
1304 ufs_qcom_hosts[hba->dev->id] = host;
1305
1306 host->dbg_print_en |= UFS_QCOM_DEFAULT_DBG_PRINT_EN;
1307 ufs_qcom_get_default_testbus_cfg(host);
1308 err = ufs_qcom_testbus_config(host);
1309 if (err) {
1310 dev_warn(dev, "%s: failed to configure the testbus %d\n",
1311 __func__, err);
1312 err = 0;
1313 }
1314
1315 goto out;
1316
1317 out_variant_clear:
1318 ufshcd_set_variant(hba, NULL);
1319 out:
1320 return err;
1321 }
1322
1323 static void ufs_qcom_exit(struct ufs_hba *hba)
1324 {
1325 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1326
1327 ufs_qcom_disable_lane_clks(host);
1328 phy_power_off(host->generic_phy);
1329 phy_exit(host->generic_phy);
1330 }
1331
1332 static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba,
1333 u32 clk_cycles)
1334 {
1335 int err;
1336 u32 core_clk_ctrl_reg;
1337
1338 if (clk_cycles > DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK)
1339 return -EINVAL;
1340
1341 err = ufshcd_dme_get(hba,
1342 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1343 &core_clk_ctrl_reg);
1344 if (err)
1345 goto out;
1346
1347 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK;
1348 core_clk_ctrl_reg |= clk_cycles;
1349
1350 /* Clear CORE_CLK_DIV_EN */
1351 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
1352
1353 err = ufshcd_dme_set(hba,
1354 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1355 core_clk_ctrl_reg);
1356 out:
1357 return err;
1358 }
1359
1360 static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba)
1361 {
1362 /* nothing to do as of now */
1363 return 0;
1364 }
1365
1366 static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba *hba)
1367 {
1368 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1369
1370 if (!ufs_qcom_cap_qunipro(host))
1371 return 0;
1372
1373 /* set unipro core clock cycles to 150 and clear clock divider */
1374 return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 150);
1375 }
1376
1377 static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba)
1378 {
1379 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1380 int err;
1381 u32 core_clk_ctrl_reg;
1382
1383 if (!ufs_qcom_cap_qunipro(host))
1384 return 0;
1385
1386 err = ufshcd_dme_get(hba,
1387 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1388 &core_clk_ctrl_reg);
1389
1390 /* make sure CORE_CLK_DIV_EN is cleared */
1391 if (!err &&
1392 (core_clk_ctrl_reg & DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT)) {
1393 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
1394 err = ufshcd_dme_set(hba,
1395 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1396 core_clk_ctrl_reg);
1397 }
1398
1399 return err;
1400 }
1401
1402 static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba)
1403 {
1404 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1405
1406 if (!ufs_qcom_cap_qunipro(host))
1407 return 0;
1408
1409 /* set unipro core clock cycles to 75 and clear clock divider */
1410 return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 75);
1411 }
1412
1413 static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba,
1414 bool scale_up, enum ufs_notify_change_status status)
1415 {
1416 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1417 struct ufs_pa_layer_attr *dev_req_params = &host->dev_req_params;
1418 int err = 0;
1419
1420 if (status == PRE_CHANGE) {
1421 if (scale_up)
1422 err = ufs_qcom_clk_scale_up_pre_change(hba);
1423 else
1424 err = ufs_qcom_clk_scale_down_pre_change(hba);
1425 } else {
1426 if (scale_up)
1427 err = ufs_qcom_clk_scale_up_post_change(hba);
1428 else
1429 err = ufs_qcom_clk_scale_down_post_change(hba);
1430
1431 if (err || !dev_req_params)
1432 goto out;
1433
1434 ufs_qcom_cfg_timers(hba,
1435 dev_req_params->gear_rx,
1436 dev_req_params->pwr_rx,
1437 dev_req_params->hs_rate,
1438 false);
1439 ufs_qcom_update_bus_bw_vote(host);
1440 }
1441
1442 out:
1443 return err;
1444 }
1445
1446 static void ufs_qcom_print_hw_debug_reg_all(struct ufs_hba *hba,
1447 void *priv, void (*print_fn)(struct ufs_hba *hba,
1448 int offset, int num_regs, const char *str, void *priv))
1449 {
1450 u32 reg;
1451 struct ufs_qcom_host *host;
1452
1453 if (unlikely(!hba)) {
1454 pr_err("%s: hba is NULL\n", __func__);
1455 return;
1456 }
1457 if (unlikely(!print_fn)) {
1458 dev_err(hba->dev, "%s: print_fn is NULL\n", __func__);
1459 return;
1460 }
1461
1462 host = ufshcd_get_variant(hba);
1463 if (!(host->dbg_print_en & UFS_QCOM_DBG_PRINT_REGS_EN))
1464 return;
1465
1466 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_REG_OCSC);
1467 print_fn(hba, reg, 44, "UFS_UFS_DBG_RD_REG_OCSC ", priv);
1468
1469 reg = ufshcd_readl(hba, REG_UFS_CFG1);
1470 reg |= UTP_DBG_RAMS_EN;
1471 ufshcd_writel(hba, reg, REG_UFS_CFG1);
1472
1473 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_EDTL_RAM);
1474 print_fn(hba, reg, 32, "UFS_UFS_DBG_RD_EDTL_RAM ", priv);
1475
1476 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_DESC_RAM);
1477 print_fn(hba, reg, 128, "UFS_UFS_DBG_RD_DESC_RAM ", priv);
1478
1479 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_PRDT_RAM);
1480 print_fn(hba, reg, 64, "UFS_UFS_DBG_RD_PRDT_RAM ", priv);
1481
1482 /* clear bit 17 - UTP_DBG_RAMS_EN */
1483 ufshcd_rmwl(hba, UTP_DBG_RAMS_EN, 0, REG_UFS_CFG1);
1484
1485 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UAWM);
1486 print_fn(hba, reg, 4, "UFS_DBG_RD_REG_UAWM ", priv);
1487
1488 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UARM);
1489 print_fn(hba, reg, 4, "UFS_DBG_RD_REG_UARM ", priv);
1490
1491 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TXUC);
1492 print_fn(hba, reg, 48, "UFS_DBG_RD_REG_TXUC ", priv);
1493
1494 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_RXUC);
1495 print_fn(hba, reg, 27, "UFS_DBG_RD_REG_RXUC ", priv);
1496
1497 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_DFC);
1498 print_fn(hba, reg, 19, "UFS_DBG_RD_REG_DFC ", priv);
1499
1500 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TRLUT);
1501 print_fn(hba, reg, 34, "UFS_DBG_RD_REG_TRLUT ", priv);
1502
1503 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TMRLUT);
1504 print_fn(hba, reg, 9, "UFS_DBG_RD_REG_TMRLUT ", priv);
1505 }
1506
1507 static void ufs_qcom_enable_test_bus(struct ufs_qcom_host *host)
1508 {
1509 if (host->dbg_print_en & UFS_QCOM_DBG_PRINT_TEST_BUS_EN) {
1510 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN,
1511 UFS_REG_TEST_BUS_EN, REG_UFS_CFG1);
1512 ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1);
1513 } else {
1514 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN, 0, REG_UFS_CFG1);
1515 ufshcd_rmwl(host->hba, TEST_BUS_EN, 0, REG_UFS_CFG1);
1516 }
1517 }
1518
1519 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host)
1520 {
1521 /* provide a legal default configuration */
1522 host->testbus.select_major = TSTBUS_UNIPRO;
1523 host->testbus.select_minor = 37;
1524 }
1525
1526 static bool ufs_qcom_testbus_cfg_is_ok(struct ufs_qcom_host *host)
1527 {
1528 if (host->testbus.select_major >= TSTBUS_MAX) {
1529 dev_err(host->hba->dev,
1530 "%s: UFS_CFG1[TEST_BUS_SEL} may not equal 0x%05X\n",
1531 __func__, host->testbus.select_major);
1532 return false;
1533 }
1534
1535 return true;
1536 }
1537
1538 int ufs_qcom_testbus_config(struct ufs_qcom_host *host)
1539 {
1540 int reg;
1541 int offset;
1542 u32 mask = TEST_BUS_SUB_SEL_MASK;
1543
1544 if (!host)
1545 return -EINVAL;
1546
1547 if (!ufs_qcom_testbus_cfg_is_ok(host))
1548 return -EPERM;
1549
1550 switch (host->testbus.select_major) {
1551 case TSTBUS_UAWM:
1552 reg = UFS_TEST_BUS_CTRL_0;
1553 offset = 24;
1554 break;
1555 case TSTBUS_UARM:
1556 reg = UFS_TEST_BUS_CTRL_0;
1557 offset = 16;
1558 break;
1559 case TSTBUS_TXUC:
1560 reg = UFS_TEST_BUS_CTRL_0;
1561 offset = 8;
1562 break;
1563 case TSTBUS_RXUC:
1564 reg = UFS_TEST_BUS_CTRL_0;
1565 offset = 0;
1566 break;
1567 case TSTBUS_DFC:
1568 reg = UFS_TEST_BUS_CTRL_1;
1569 offset = 24;
1570 break;
1571 case TSTBUS_TRLUT:
1572 reg = UFS_TEST_BUS_CTRL_1;
1573 offset = 16;
1574 break;
1575 case TSTBUS_TMRLUT:
1576 reg = UFS_TEST_BUS_CTRL_1;
1577 offset = 8;
1578 break;
1579 case TSTBUS_OCSC:
1580 reg = UFS_TEST_BUS_CTRL_1;
1581 offset = 0;
1582 break;
1583 case TSTBUS_WRAPPER:
1584 reg = UFS_TEST_BUS_CTRL_2;
1585 offset = 16;
1586 break;
1587 case TSTBUS_COMBINED:
1588 reg = UFS_TEST_BUS_CTRL_2;
1589 offset = 8;
1590 break;
1591 case TSTBUS_UTP_HCI:
1592 reg = UFS_TEST_BUS_CTRL_2;
1593 offset = 0;
1594 break;
1595 case TSTBUS_UNIPRO:
1596 reg = UFS_UNIPRO_CFG;
1597 offset = 20;
1598 mask = 0xFFF;
1599 break;
1600 /*
1601 * No need for a default case, since
1602 * ufs_qcom_testbus_cfg_is_ok() checks that the configuration
1603 * is legal
1604 */
1605 }
1606 mask <<= offset;
1607
1608 pm_runtime_get_sync(host->hba->dev);
1609 ufshcd_hold(host->hba, false);
1610 ufshcd_rmwl(host->hba, TEST_BUS_SEL,
1611 (u32)host->testbus.select_major << 19,
1612 REG_UFS_CFG1);
1613 ufshcd_rmwl(host->hba, mask,
1614 (u32)host->testbus.select_minor << offset,
1615 reg);
1616 ufs_qcom_enable_test_bus(host);
1617 /*
1618 * Make sure the test bus configuration is
1619 * committed before returning.
1620 */
1621 mb();
1622 ufshcd_release(host->hba);
1623 pm_runtime_put_sync(host->hba->dev);
1624
1625 return 0;
1626 }
1627
1628 static void ufs_qcom_testbus_read(struct ufs_hba *hba)
1629 {
1630 ufshcd_dump_regs(hba, UFS_TEST_BUS, 4, "UFS_TEST_BUS ");
1631 }
1632
1633 static void ufs_qcom_print_unipro_testbus(struct ufs_hba *hba)
1634 {
1635 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1636 u32 *testbus = NULL;
1637 int i, nminor = 256, testbus_len = nminor * sizeof(u32);
1638
1639 testbus = kmalloc(testbus_len, GFP_KERNEL);
1640 if (!testbus)
1641 return;
1642
1643 host->testbus.select_major = TSTBUS_UNIPRO;
1644 for (i = 0; i < nminor; i++) {
1645 host->testbus.select_minor = i;
1646 ufs_qcom_testbus_config(host);
1647 testbus[i] = ufshcd_readl(hba, UFS_TEST_BUS);
1648 }
1649 print_hex_dump(KERN_ERR, "UNIPRO_TEST_BUS ", DUMP_PREFIX_OFFSET,
1650 16, 4, testbus, testbus_len, false);
1651 kfree(testbus);
1652 }
1653
1654 static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba)
1655 {
1656 ufshcd_dump_regs(hba, REG_UFS_SYS1CLK_1US, 16 * 4,
1657 "HCI Vendor Specific Registers ");
1658
1659 /* sleep a bit intermittently as we are dumping too much data */
1660 ufs_qcom_print_hw_debug_reg_all(hba, NULL, ufs_qcom_dump_regs_wrapper);
1661 usleep_range(1000, 1100);
1662 ufs_qcom_testbus_read(hba);
1663 usleep_range(1000, 1100);
1664 ufs_qcom_print_unipro_testbus(hba);
1665 usleep_range(1000, 1100);
1666 }
1667
1668 /**
1669 * ufs_qcom_device_reset() - toggle the (optional) device reset line
1670 * @hba: per-adapter instance
1671 *
1672 * Toggles the (optional) reset line to reset the attached device.
1673 */
1674 static void ufs_qcom_device_reset(struct ufs_hba *hba)
1675 {
1676 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1677
1678 /* reset gpio is optional */
1679 if (!host->device_reset)
1680 return;
1681
1682 /*
1683 * The UFS device shall detect reset pulses of 1us, sleep for 10us to
1684 * be on the safe side.
1685 */
1686 gpiod_set_value_cansleep(host->device_reset, 1);
1687 usleep_range(10, 15);
1688
1689 gpiod_set_value_cansleep(host->device_reset, 0);
1690 usleep_range(10, 15);
1691 }
1692
1693 #if IS_ENABLED(CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND)
1694 static void ufs_qcom_config_scaling_param(struct ufs_hba *hba,
1695 struct devfreq_dev_profile *p,
1696 void *data)
1697 {
1698 static struct devfreq_simple_ondemand_data *d;
1699
1700 if (!data)
1701 return;
1702
1703 d = (struct devfreq_simple_ondemand_data *)data;
1704 p->polling_ms = 60;
1705 d->upthreshold = 70;
1706 d->downdifferential = 5;
1707 }
1708 #else
1709 static void ufs_qcom_config_scaling_param(struct ufs_hba *hba,
1710 struct devfreq_dev_profile *p,
1711 void *data)
1712 {
1713 }
1714 #endif
1715
1716 /**
1717 * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations
1718 *
1719 * The variant operations configure the necessary controller and PHY
1720 * handshake during initialization.
1721 */
1722 static const struct ufs_hba_variant_ops ufs_hba_qcom_vops = {
1723 .name = "qcom",
1724 .init = ufs_qcom_init,
1725 .exit = ufs_qcom_exit,
1726 .get_ufs_hci_version = ufs_qcom_get_ufs_hci_version,
1727 .clk_scale_notify = ufs_qcom_clk_scale_notify,
1728 .setup_clocks = ufs_qcom_setup_clocks,
1729 .hce_enable_notify = ufs_qcom_hce_enable_notify,
1730 .link_startup_notify = ufs_qcom_link_startup_notify,
1731 .pwr_change_notify = ufs_qcom_pwr_change_notify,
1732 .apply_dev_quirks = ufs_qcom_apply_dev_quirks,
1733 .suspend = ufs_qcom_suspend,
1734 .resume = ufs_qcom_resume,
1735 .dbg_register_dump = ufs_qcom_dump_dbg_regs,
1736 .device_reset = ufs_qcom_device_reset,
1737 .config_scaling_param = ufs_qcom_config_scaling_param,
1738 };
1739
1740 /**
1741 * ufs_qcom_probe - probe routine of the driver
1742 * @pdev: pointer to Platform device handle
1743 *
1744 * Return zero for success and non-zero for failure
1745 */
1746 static int ufs_qcom_probe(struct platform_device *pdev)
1747 {
1748 int err;
1749 struct device *dev = &pdev->dev;
1750
1751 /* Perform generic probe */
1752 err = ufshcd_pltfrm_init(pdev, &ufs_hba_qcom_vops);
1753 if (err)
1754 dev_err(dev, "ufshcd_pltfrm_init() failed %d\n", err);
1755
1756 return err;
1757 }
1758
1759 /**
1760 * ufs_qcom_remove - set driver_data of the device to NULL
1761 * @pdev: pointer to platform device handle
1762 *
1763 * Always returns 0
1764 */
1765 static int ufs_qcom_remove(struct platform_device *pdev)
1766 {
1767 struct ufs_hba *hba = platform_get_drvdata(pdev);
1768
1769 pm_runtime_get_sync(&(pdev)->dev);
1770 ufshcd_remove(hba);
1771 return 0;
1772 }
1773
1774 static const struct of_device_id ufs_qcom_of_match[] = {
1775 { .compatible = "qcom,ufshc"},
1776 {},
1777 };
1778 MODULE_DEVICE_TABLE(of, ufs_qcom_of_match);
1779
1780 #ifdef CONFIG_ACPI
1781 static const struct acpi_device_id ufs_qcom_acpi_match[] = {
1782 { "QCOM24A5" },
1783 { },
1784 };
1785 MODULE_DEVICE_TABLE(acpi, ufs_qcom_acpi_match);
1786 #endif
1787
1788 static const struct dev_pm_ops ufs_qcom_pm_ops = {
1789 .suspend = ufshcd_pltfrm_suspend,
1790 .resume = ufshcd_pltfrm_resume,
1791 .runtime_suspend = ufshcd_pltfrm_runtime_suspend,
1792 .runtime_resume = ufshcd_pltfrm_runtime_resume,
1793 .runtime_idle = ufshcd_pltfrm_runtime_idle,
1794 };
1795
1796 static struct platform_driver ufs_qcom_pltform = {
1797 .probe = ufs_qcom_probe,
1798 .remove = ufs_qcom_remove,
1799 .shutdown = ufshcd_pltfrm_shutdown,
1800 .driver = {
1801 .name = "ufshcd-qcom",
1802 .pm = &ufs_qcom_pm_ops,
1803 .of_match_table = of_match_ptr(ufs_qcom_of_match),
1804 .acpi_match_table = ACPI_PTR(ufs_qcom_acpi_match),
1805 },
1806 };
1807 module_platform_driver(ufs_qcom_pltform);
1808
1809 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support