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usb: dwc3: keystone: drop dma_mask configuration
[linux/fpc-iii.git] / drivers / spi / spi-sh-msiof.c
blob7f0f2ebf3cdca9422caf40de489a50ee8f732f82
1 /*
2 * SuperH MSIOF SPI Master Interface
3 *
4 * Copyright (c) 2009 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12 #include <linux/bitmap.h>
13 #include <linux/clk.h>
14 #include <linux/completion.h>
15 #include <linux/delay.h>
16 #include <linux/err.h>
17 #include <linux/gpio.h>
18 #include <linux/interrupt.h>
19 #include <linux/io.h>
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/of.h>
23 #include <linux/of_device.h>
24 #include <linux/platform_device.h>
25 #include <linux/pm_runtime.h>
26
27 #include <linux/spi/sh_msiof.h>
28 #include <linux/spi/spi.h>
29
30 #include <asm/unaligned.h>
31
32
33 struct sh_msiof_chipdata {
34 u16 tx_fifo_size;
35 u16 rx_fifo_size;
36 u16 master_flags;
37 };
38
39 struct sh_msiof_spi_priv {
40 void __iomem *mapbase;
41 struct clk *clk;
42 struct platform_device *pdev;
43 const struct sh_msiof_chipdata *chipdata;
44 struct sh_msiof_spi_info *info;
45 struct completion done;
46 int tx_fifo_size;
47 int rx_fifo_size;
48 };
49
50 #define TMDR1 0x00 /* Transmit Mode Register 1 */
51 #define TMDR2 0x04 /* Transmit Mode Register 2 */
52 #define TMDR3 0x08 /* Transmit Mode Register 3 */
53 #define RMDR1 0x10 /* Receive Mode Register 1 */
54 #define RMDR2 0x14 /* Receive Mode Register 2 */
55 #define RMDR3 0x18 /* Receive Mode Register 3 */
56 #define TSCR 0x20 /* Transmit Clock Select Register */
57 #define RSCR 0x22 /* Receive Clock Select Register (SH, A1, APE6) */
58 #define CTR 0x28 /* Control Register */
59 #define FCTR 0x30 /* FIFO Control Register */
60 #define STR 0x40 /* Status Register */
61 #define IER 0x44 /* Interrupt Enable Register */
62 #define TDR1 0x48 /* Transmit Control Data Register 1 (SH, A1) */
63 #define TDR2 0x4c /* Transmit Control Data Register 2 (SH, A1) */
64 #define TFDR 0x50 /* Transmit FIFO Data Register */
65 #define RDR1 0x58 /* Receive Control Data Register 1 (SH, A1) */
66 #define RDR2 0x5c /* Receive Control Data Register 2 (SH, A1) */
67 #define RFDR 0x60 /* Receive FIFO Data Register */
68
69 /* TMDR1 and RMDR1 */
70 #define MDR1_TRMD 0x80000000 /* Transfer Mode (1 = Master mode) */
71 #define MDR1_SYNCMD_MASK 0x30000000 /* SYNC Mode */
72 #define MDR1_SYNCMD_SPI 0x20000000 /* Level mode/SPI */
73 #define MDR1_SYNCMD_LR 0x30000000 /* L/R mode */
74 #define MDR1_SYNCAC_SHIFT 25 /* Sync Polarity (1 = Active-low) */
75 #define MDR1_BITLSB_SHIFT 24 /* MSB/LSB First (1 = LSB first) */
76 #define MDR1_FLD_MASK 0x000000c0 /* Frame Sync Signal Interval (0-3) */
77 #define MDR1_FLD_SHIFT 2
78 #define MDR1_XXSTP 0x00000001 /* Transmission/Reception Stop on FIFO */
79 /* TMDR1 */
80 #define TMDR1_PCON 0x40000000 /* Transfer Signal Connection */
81
82 /* TMDR2 and RMDR2 */
83 #define MDR2_BITLEN1(i) (((i) - 1) << 24) /* Data Size (8-32 bits) */
84 #define MDR2_WDLEN1(i) (((i) - 1) << 16) /* Word Count (1-64/256 (SH, A1))) */
85 #define MDR2_GRPMASK1 0x00000001 /* Group Output Mask 1 (SH, A1) */
86
87 /* TSCR and RSCR */
88 #define SCR_BRPS_MASK 0x1f00 /* Prescaler Setting (1-32) */
89 #define SCR_BRPS(i) (((i) - 1) << 8)
90 #define SCR_BRDV_MASK 0x0007 /* Baud Rate Generator's Division Ratio */
91 #define SCR_BRDV_DIV_2 0x0000
92 #define SCR_BRDV_DIV_4 0x0001
93 #define SCR_BRDV_DIV_8 0x0002
94 #define SCR_BRDV_DIV_16 0x0003
95 #define SCR_BRDV_DIV_32 0x0004
96 #define SCR_BRDV_DIV_1 0x0007
97
98 /* CTR */
99 #define CTR_TSCKIZ_MASK 0xc0000000 /* Transmit Clock I/O Polarity Select */
100 #define CTR_TSCKIZ_SCK 0x80000000 /* Disable SCK when TX disabled */
101 #define CTR_TSCKIZ_POL_SHIFT 30 /* Transmit Clock Polarity */
102 #define CTR_RSCKIZ_MASK 0x30000000 /* Receive Clock Polarity Select */
103 #define CTR_RSCKIZ_SCK 0x20000000 /* Must match CTR_TSCKIZ_SCK */
104 #define CTR_RSCKIZ_POL_SHIFT 28 /* Receive Clock Polarity */
105 #define CTR_TEDG_SHIFT 27 /* Transmit Timing (1 = falling edge) */
106 #define CTR_REDG_SHIFT 26 /* Receive Timing (1 = falling edge) */
107 #define CTR_TXDIZ_MASK 0x00c00000 /* Pin Output When TX is Disabled */
108 #define CTR_TXDIZ_LOW 0x00000000 /* 0 */
109 #define CTR_TXDIZ_HIGH 0x00400000 /* 1 */
110 #define CTR_TXDIZ_HIZ 0x00800000 /* High-impedance */
111 #define CTR_TSCKE 0x00008000 /* Transmit Serial Clock Output Enable */
112 #define CTR_TFSE 0x00004000 /* Transmit Frame Sync Signal Output Enable */
113 #define CTR_TXE 0x00000200 /* Transmit Enable */
114 #define CTR_RXE 0x00000100 /* Receive Enable */
115
116 /* STR and IER */
117 #define STR_TEOF 0x00800000 /* Frame Transmission End */
118 #define STR_REOF 0x00000080 /* Frame Reception End */
119
120
121 static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs)
122 {
123 switch (reg_offs) {
124 case TSCR:
125 case RSCR:
126 return ioread16(p->mapbase + reg_offs);
127 default:
128 return ioread32(p->mapbase + reg_offs);
129 }
130 }
131
132 static void sh_msiof_write(struct sh_msiof_spi_priv *p, int reg_offs,
133 u32 value)
134 {
135 switch (reg_offs) {
136 case TSCR:
137 case RSCR:
138 iowrite16(value, p->mapbase + reg_offs);
139 break;
140 default:
141 iowrite32(value, p->mapbase + reg_offs);
142 break;
143 }
144 }
145
146 static int sh_msiof_modify_ctr_wait(struct sh_msiof_spi_priv *p,
147 u32 clr, u32 set)
148 {
149 u32 mask = clr | set;
150 u32 data;
151 int k;
152
153 data = sh_msiof_read(p, CTR);
154 data &= ~clr;
155 data |= set;
156 sh_msiof_write(p, CTR, data);
157
158 for (k = 100; k > 0; k--) {
159 if ((sh_msiof_read(p, CTR) & mask) == set)
160 break;
161
162 udelay(10);
163 }
164
165 return k > 0 ? 0 : -ETIMEDOUT;
166 }
167
168 static irqreturn_t sh_msiof_spi_irq(int irq, void *data)
169 {
170 struct sh_msiof_spi_priv *p = data;
171
172 /* just disable the interrupt and wake up */
173 sh_msiof_write(p, IER, 0);
174 complete(&p->done);
175
176 return IRQ_HANDLED;
177 }
178
179 static struct {
180 unsigned short div;
181 unsigned short scr;
182 } const sh_msiof_spi_clk_table[] = {
183 { 1, SCR_BRPS( 1) | SCR_BRDV_DIV_1 },
184 { 2, SCR_BRPS( 1) | SCR_BRDV_DIV_2 },
185 { 4, SCR_BRPS( 1) | SCR_BRDV_DIV_4 },
186 { 8, SCR_BRPS( 1) | SCR_BRDV_DIV_8 },
187 { 16, SCR_BRPS( 1) | SCR_BRDV_DIV_16 },
188 { 32, SCR_BRPS( 1) | SCR_BRDV_DIV_32 },
189 { 64, SCR_BRPS(32) | SCR_BRDV_DIV_2 },
190 { 128, SCR_BRPS(32) | SCR_BRDV_DIV_4 },
191 { 256, SCR_BRPS(32) | SCR_BRDV_DIV_8 },
192 { 512, SCR_BRPS(32) | SCR_BRDV_DIV_16 },
193 { 1024, SCR_BRPS(32) | SCR_BRDV_DIV_32 },
194 };
195
196 static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
197 unsigned long parent_rate, u32 spi_hz)
198 {
199 unsigned long div = 1024;
200 size_t k;
201
202 if (!WARN_ON(!spi_hz || !parent_rate))
203 div = DIV_ROUND_UP(parent_rate, spi_hz);
204
205 /* TODO: make more fine grained */
206
207 for (k = 0; k < ARRAY_SIZE(sh_msiof_spi_clk_table); k++) {
208 if (sh_msiof_spi_clk_table[k].div >= div)
209 break;
210 }
211
212 k = min_t(int, k, ARRAY_SIZE(sh_msiof_spi_clk_table) - 1);
213
214 sh_msiof_write(p, TSCR, sh_msiof_spi_clk_table[k].scr);
215 if (!(p->chipdata->master_flags & SPI_MASTER_MUST_TX))
216 sh_msiof_write(p, RSCR, sh_msiof_spi_clk_table[k].scr);
217 }
218
219 static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p,
220 u32 cpol, u32 cpha,
221 u32 tx_hi_z, u32 lsb_first, u32 cs_high)
222 {
223 u32 tmp;
224 int edge;
225
226 /*
227 * CPOL CPHA TSCKIZ RSCKIZ TEDG REDG
228 * 0 0 10 10 1 1
229 * 0 1 10 10 0 0
230 * 1 0 11 11 0 0
231 * 1 1 11 11 1 1
232 */
233 sh_msiof_write(p, FCTR, 0);
234
235 tmp = MDR1_SYNCMD_SPI | 1 << MDR1_FLD_SHIFT | MDR1_XXSTP;
236 tmp |= !cs_high << MDR1_SYNCAC_SHIFT;
237 tmp |= lsb_first << MDR1_BITLSB_SHIFT;
238 sh_msiof_write(p, TMDR1, tmp | MDR1_TRMD | TMDR1_PCON);
239 if (p->chipdata->master_flags & SPI_MASTER_MUST_TX) {
240 /* These bits are reserved if RX needs TX */
241 tmp &= ~0x0000ffff;
242 }
243 sh_msiof_write(p, RMDR1, tmp);
244
245 tmp = 0;
246 tmp |= CTR_TSCKIZ_SCK | cpol << CTR_TSCKIZ_POL_SHIFT;
247 tmp |= CTR_RSCKIZ_SCK | cpol << CTR_RSCKIZ_POL_SHIFT;
248
249 edge = cpol ^ !cpha;
250
251 tmp |= edge << CTR_TEDG_SHIFT;
252 tmp |= edge << CTR_REDG_SHIFT;
253 tmp |= tx_hi_z ? CTR_TXDIZ_HIZ : CTR_TXDIZ_LOW;
254 sh_msiof_write(p, CTR, tmp);
255 }
256
257 static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p,
258 const void *tx_buf, void *rx_buf,
259 u32 bits, u32 words)
260 {
261 u32 dr2 = MDR2_BITLEN1(bits) | MDR2_WDLEN1(words);
262
263 if (tx_buf || (p->chipdata->master_flags & SPI_MASTER_MUST_TX))
264 sh_msiof_write(p, TMDR2, dr2);
265 else
266 sh_msiof_write(p, TMDR2, dr2 | MDR2_GRPMASK1);
267
268 if (rx_buf)
269 sh_msiof_write(p, RMDR2, dr2);
270
271 sh_msiof_write(p, IER, STR_TEOF | STR_REOF);
272 }
273
274 static void sh_msiof_reset_str(struct sh_msiof_spi_priv *p)
275 {
276 sh_msiof_write(p, STR, sh_msiof_read(p, STR));
277 }
278
279 static void sh_msiof_spi_write_fifo_8(struct sh_msiof_spi_priv *p,
280 const void *tx_buf, int words, int fs)
281 {
282 const u8 *buf_8 = tx_buf;
283 int k;
284
285 for (k = 0; k < words; k++)
286 sh_msiof_write(p, TFDR, buf_8[k] << fs);
287 }
288
289 static void sh_msiof_spi_write_fifo_16(struct sh_msiof_spi_priv *p,
290 const void *tx_buf, int words, int fs)
291 {
292 const u16 *buf_16 = tx_buf;
293 int k;
294
295 for (k = 0; k < words; k++)
296 sh_msiof_write(p, TFDR, buf_16[k] << fs);
297 }
298
299 static void sh_msiof_spi_write_fifo_16u(struct sh_msiof_spi_priv *p,
300 const void *tx_buf, int words, int fs)
301 {
302 const u16 *buf_16 = tx_buf;
303 int k;
304
305 for (k = 0; k < words; k++)
306 sh_msiof_write(p, TFDR, get_unaligned(&buf_16[k]) << fs);
307 }
308
309 static void sh_msiof_spi_write_fifo_32(struct sh_msiof_spi_priv *p,
310 const void *tx_buf, int words, int fs)
311 {
312 const u32 *buf_32 = tx_buf;
313 int k;
314
315 for (k = 0; k < words; k++)
316 sh_msiof_write(p, TFDR, buf_32[k] << fs);
317 }
318
319 static void sh_msiof_spi_write_fifo_32u(struct sh_msiof_spi_priv *p,
320 const void *tx_buf, int words, int fs)
321 {
322 const u32 *buf_32 = tx_buf;
323 int k;
324
325 for (k = 0; k < words; k++)
326 sh_msiof_write(p, TFDR, get_unaligned(&buf_32[k]) << fs);
327 }
328
329 static void sh_msiof_spi_write_fifo_s32(struct sh_msiof_spi_priv *p,
330 const void *tx_buf, int words, int fs)
331 {
332 const u32 *buf_32 = tx_buf;
333 int k;
334
335 for (k = 0; k < words; k++)
336 sh_msiof_write(p, TFDR, swab32(buf_32[k] << fs));
337 }
338
339 static void sh_msiof_spi_write_fifo_s32u(struct sh_msiof_spi_priv *p,
340 const void *tx_buf, int words, int fs)
341 {
342 const u32 *buf_32 = tx_buf;
343 int k;
344
345 for (k = 0; k < words; k++)
346 sh_msiof_write(p, TFDR, swab32(get_unaligned(&buf_32[k]) << fs));
347 }
348
349 static void sh_msiof_spi_read_fifo_8(struct sh_msiof_spi_priv *p,
350 void *rx_buf, int words, int fs)
351 {
352 u8 *buf_8 = rx_buf;
353 int k;
354
355 for (k = 0; k < words; k++)
356 buf_8[k] = sh_msiof_read(p, RFDR) >> fs;
357 }
358
359 static void sh_msiof_spi_read_fifo_16(struct sh_msiof_spi_priv *p,
360 void *rx_buf, int words, int fs)
361 {
362 u16 *buf_16 = rx_buf;
363 int k;
364
365 for (k = 0; k < words; k++)
366 buf_16[k] = sh_msiof_read(p, RFDR) >> fs;
367 }
368
369 static void sh_msiof_spi_read_fifo_16u(struct sh_msiof_spi_priv *p,
370 void *rx_buf, int words, int fs)
371 {
372 u16 *buf_16 = rx_buf;
373 int k;
374
375 for (k = 0; k < words; k++)
376 put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_16[k]);
377 }
378
379 static void sh_msiof_spi_read_fifo_32(struct sh_msiof_spi_priv *p,
380 void *rx_buf, int words, int fs)
381 {
382 u32 *buf_32 = rx_buf;
383 int k;
384
385 for (k = 0; k < words; k++)
386 buf_32[k] = sh_msiof_read(p, RFDR) >> fs;
387 }
388
389 static void sh_msiof_spi_read_fifo_32u(struct sh_msiof_spi_priv *p,
390 void *rx_buf, int words, int fs)
391 {
392 u32 *buf_32 = rx_buf;
393 int k;
394
395 for (k = 0; k < words; k++)
396 put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_32[k]);
397 }
398
399 static void sh_msiof_spi_read_fifo_s32(struct sh_msiof_spi_priv *p,
400 void *rx_buf, int words, int fs)
401 {
402 u32 *buf_32 = rx_buf;
403 int k;
404
405 for (k = 0; k < words; k++)
406 buf_32[k] = swab32(sh_msiof_read(p, RFDR) >> fs);
407 }
408
409 static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv *p,
410 void *rx_buf, int words, int fs)
411 {
412 u32 *buf_32 = rx_buf;
413 int k;
414
415 for (k = 0; k < words; k++)
416 put_unaligned(swab32(sh_msiof_read(p, RFDR) >> fs), &buf_32[k]);
417 }
418
419 static int sh_msiof_spi_setup(struct spi_device *spi)
420 {
421 struct device_node *np = spi->master->dev.of_node;
422 struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master);
423
424 pm_runtime_get_sync(&p->pdev->dev);
425
426 if (!np) {
427 /*
428 * Use spi->controller_data for CS (same strategy as spi_gpio),
429 * if any. otherwise let HW control CS
430 */
431 spi->cs_gpio = (uintptr_t)spi->controller_data;
432 }
433
434 /* Configure pins before deasserting CS */
435 sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL),
436 !!(spi->mode & SPI_CPHA),
437 !!(spi->mode & SPI_3WIRE),
438 !!(spi->mode & SPI_LSB_FIRST),
439 !!(spi->mode & SPI_CS_HIGH));
440
441 if (spi->cs_gpio >= 0)
442 gpio_set_value(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
443
444
445 pm_runtime_put_sync(&p->pdev->dev);
446
447 return 0;
448 }
449
450 static int sh_msiof_prepare_message(struct spi_master *master,
451 struct spi_message *msg)
452 {
453 struct sh_msiof_spi_priv *p = spi_master_get_devdata(master);
454 const struct spi_device *spi = msg->spi;
455
456 /* Configure pins before asserting CS */
457 sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL),
458 !!(spi->mode & SPI_CPHA),
459 !!(spi->mode & SPI_3WIRE),
460 !!(spi->mode & SPI_LSB_FIRST),
461 !!(spi->mode & SPI_CS_HIGH));
462 return 0;
463 }
464
465 static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p,
466 void (*tx_fifo)(struct sh_msiof_spi_priv *,
467 const void *, int, int),
468 void (*rx_fifo)(struct sh_msiof_spi_priv *,
469 void *, int, int),
470 const void *tx_buf, void *rx_buf,
471 int words, int bits)
472 {
473 int fifo_shift;
474 int ret;
475
476 /* limit maximum word transfer to rx/tx fifo size */
477 if (tx_buf)
478 words = min_t(int, words, p->tx_fifo_size);
479 if (rx_buf)
480 words = min_t(int, words, p->rx_fifo_size);
481
482 /* the fifo contents need shifting */
483 fifo_shift = 32 - bits;
484
485 /* setup msiof transfer mode registers */
486 sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words);
487
488 /* write tx fifo */
489 if (tx_buf)
490 tx_fifo(p, tx_buf, words, fifo_shift);
491
492 /* setup clock and rx/tx signals */
493 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TSCKE);
494 if (rx_buf)
495 ret = ret ? ret : sh_msiof_modify_ctr_wait(p, 0, CTR_RXE);
496 ret = ret ? ret : sh_msiof_modify_ctr_wait(p, 0, CTR_TXE);
497
498 /* start by setting frame bit */
499 reinit_completion(&p->done);
500 ret = ret ? ret : sh_msiof_modify_ctr_wait(p, 0, CTR_TFSE);
501 if (ret) {
502 dev_err(&p->pdev->dev, "failed to start hardware\n");
503 goto err;
504 }
505
506 /* wait for tx fifo to be emptied / rx fifo to be filled */
507 wait_for_completion(&p->done);
508
509 /* read rx fifo */
510 if (rx_buf)
511 rx_fifo(p, rx_buf, words, fifo_shift);
512
513 /* clear status bits */
514 sh_msiof_reset_str(p);
515
516 /* shut down frame, rx/tx and clock signals */
517 ret = sh_msiof_modify_ctr_wait(p, CTR_TFSE, 0);
518 ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_TXE, 0);
519 if (rx_buf)
520 ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_RXE, 0);
521 ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_TSCKE, 0);
522 if (ret) {
523 dev_err(&p->pdev->dev, "failed to shut down hardware\n");
524 goto err;
525 }
526
527 return words;
528
529 err:
530 sh_msiof_write(p, IER, 0);
531 return ret;
532 }
533
534 static int sh_msiof_transfer_one(struct spi_master *master,
535 struct spi_device *spi,
536 struct spi_transfer *t)
537 {
538 struct sh_msiof_spi_priv *p = spi_master_get_devdata(master);
539 void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int);
540 void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int);
541 int bits;
542 int bytes_per_word;
543 int bytes_done;
544 int words;
545 int n;
546 bool swab;
547
548 bits = t->bits_per_word;
549
550 if (bits <= 8 && t->len > 15 && !(t->len & 3)) {
551 bits = 32;
552 swab = true;
553 } else {
554 swab = false;
555 }
556
557 /* setup bytes per word and fifo read/write functions */
558 if (bits <= 8) {
559 bytes_per_word = 1;
560 tx_fifo = sh_msiof_spi_write_fifo_8;
561 rx_fifo = sh_msiof_spi_read_fifo_8;
562 } else if (bits <= 16) {
563 bytes_per_word = 2;
564 if ((unsigned long)t->tx_buf & 0x01)
565 tx_fifo = sh_msiof_spi_write_fifo_16u;
566 else
567 tx_fifo = sh_msiof_spi_write_fifo_16;
568
569 if ((unsigned long)t->rx_buf & 0x01)
570 rx_fifo = sh_msiof_spi_read_fifo_16u;
571 else
572 rx_fifo = sh_msiof_spi_read_fifo_16;
573 } else if (swab) {
574 bytes_per_word = 4;
575 if ((unsigned long)t->tx_buf & 0x03)
576 tx_fifo = sh_msiof_spi_write_fifo_s32u;
577 else
578 tx_fifo = sh_msiof_spi_write_fifo_s32;
579
580 if ((unsigned long)t->rx_buf & 0x03)
581 rx_fifo = sh_msiof_spi_read_fifo_s32u;
582 else
583 rx_fifo = sh_msiof_spi_read_fifo_s32;
584 } else {
585 bytes_per_word = 4;
586 if ((unsigned long)t->tx_buf & 0x03)
587 tx_fifo = sh_msiof_spi_write_fifo_32u;
588 else
589 tx_fifo = sh_msiof_spi_write_fifo_32;
590
591 if ((unsigned long)t->rx_buf & 0x03)
592 rx_fifo = sh_msiof_spi_read_fifo_32u;
593 else
594 rx_fifo = sh_msiof_spi_read_fifo_32;
595 }
596
597 /* setup clocks (clock already enabled in chipselect()) */
598 sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk), t->speed_hz);
599
600 /* transfer in fifo sized chunks */
601 words = t->len / bytes_per_word;
602 bytes_done = 0;
603
604 while (bytes_done < t->len) {
605 void *rx_buf = t->rx_buf ? t->rx_buf + bytes_done : NULL;
606 const void *tx_buf = t->tx_buf ? t->tx_buf + bytes_done : NULL;
607 n = sh_msiof_spi_txrx_once(p, tx_fifo, rx_fifo,
608 tx_buf,
609 rx_buf,
610 words, bits);
611 if (n < 0)
612 break;
613
614 bytes_done += n * bytes_per_word;
615 words -= n;
616 }
617
618 return 0;
619 }
620
621 static const struct sh_msiof_chipdata sh_data = {
622 .tx_fifo_size = 64,
623 .rx_fifo_size = 64,
624 .master_flags = 0,
625 };
626
627 static const struct sh_msiof_chipdata r8a779x_data = {
628 .tx_fifo_size = 64,
629 .rx_fifo_size = 256,
630 .master_flags = SPI_MASTER_MUST_TX,
631 };
632
633 static const struct of_device_id sh_msiof_match[] = {
634 { .compatible = "renesas,sh-msiof", .data = &sh_data },
635 { .compatible = "renesas,sh-mobile-msiof", .data = &sh_data },
636 { .compatible = "renesas,msiof-r8a7790", .data = &r8a779x_data },
637 { .compatible = "renesas,msiof-r8a7791", .data = &r8a779x_data },
638 {},
639 };
640 MODULE_DEVICE_TABLE(of, sh_msiof_match);
641
642 #ifdef CONFIG_OF
643 static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev)
644 {
645 struct sh_msiof_spi_info *info;
646 struct device_node *np = dev->of_node;
647 u32 num_cs = 1;
648
649 info = devm_kzalloc(dev, sizeof(struct sh_msiof_spi_info), GFP_KERNEL);
650 if (!info)
651 return NULL;
652
653 /* Parse the MSIOF properties */
654 of_property_read_u32(np, "num-cs", &num_cs);
655 of_property_read_u32(np, "renesas,tx-fifo-size",
656 &info->tx_fifo_override);
657 of_property_read_u32(np, "renesas,rx-fifo-size",
658 &info->rx_fifo_override);
659
660 info->num_chipselect = num_cs;
661
662 return info;
663 }
664 #else
665 static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev)
666 {
667 return NULL;
668 }
669 #endif
670
671 static int sh_msiof_spi_probe(struct platform_device *pdev)
672 {
673 struct resource *r;
674 struct spi_master *master;
675 const struct of_device_id *of_id;
676 struct sh_msiof_spi_priv *p;
677 int i;
678 int ret;
679
680 master = spi_alloc_master(&pdev->dev, sizeof(struct sh_msiof_spi_priv));
681 if (master == NULL) {
682 dev_err(&pdev->dev, "failed to allocate spi master\n");
683 return -ENOMEM;
684 }
685
686 p = spi_master_get_devdata(master);
687
688 platform_set_drvdata(pdev, p);
689
690 of_id = of_match_device(sh_msiof_match, &pdev->dev);
691 if (of_id) {
692 p->chipdata = of_id->data;
693 p->info = sh_msiof_spi_parse_dt(&pdev->dev);
694 } else {
695 p->chipdata = (const void *)pdev->id_entry->driver_data;
696 p->info = dev_get_platdata(&pdev->dev);
697 }
698
699 if (!p->info) {
700 dev_err(&pdev->dev, "failed to obtain device info\n");
701 ret = -ENXIO;
702 goto err1;
703 }
704
705 init_completion(&p->done);
706
707 p->clk = devm_clk_get(&pdev->dev, NULL);
708 if (IS_ERR(p->clk)) {
709 dev_err(&pdev->dev, "cannot get clock\n");
710 ret = PTR_ERR(p->clk);
711 goto err1;
712 }
713
714 i = platform_get_irq(pdev, 0);
715 if (i < 0) {
716 dev_err(&pdev->dev, "cannot get platform IRQ\n");
717 ret = -ENOENT;
718 goto err1;
719 }
720
721 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
722 p->mapbase = devm_ioremap_resource(&pdev->dev, r);
723 if (IS_ERR(p->mapbase)) {
724 ret = PTR_ERR(p->mapbase);
725 goto err1;
726 }
727
728 ret = devm_request_irq(&pdev->dev, i, sh_msiof_spi_irq, 0,
729 dev_name(&pdev->dev), p);
730 if (ret) {
731 dev_err(&pdev->dev, "unable to request irq\n");
732 goto err1;
733 }
734
735 p->pdev = pdev;
736 pm_runtime_enable(&pdev->dev);
737
738 /* Platform data may override FIFO sizes */
739 p->tx_fifo_size = p->chipdata->tx_fifo_size;
740 p->rx_fifo_size = p->chipdata->rx_fifo_size;
741 if (p->info->tx_fifo_override)
742 p->tx_fifo_size = p->info->tx_fifo_override;
743 if (p->info->rx_fifo_override)
744 p->rx_fifo_size = p->info->rx_fifo_override;
745
746 /* init master code */
747 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
748 master->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE;
749 master->flags = p->chipdata->master_flags;
750 master->bus_num = pdev->id;
751 master->dev.of_node = pdev->dev.of_node;
752 master->num_chipselect = p->info->num_chipselect;
753 master->setup = sh_msiof_spi_setup;
754 master->prepare_message = sh_msiof_prepare_message;
755 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32);
756 master->auto_runtime_pm = true;
757 master->transfer_one = sh_msiof_transfer_one;
758
759 ret = devm_spi_register_master(&pdev->dev, master);
760 if (ret < 0) {
761 dev_err(&pdev->dev, "spi_register_master error.\n");
762 goto err2;
763 }
764
765 return 0;
766
767 err2:
768 pm_runtime_disable(&pdev->dev);
769 err1:
770 spi_master_put(master);
771 return ret;
772 }
773
774 static int sh_msiof_spi_remove(struct platform_device *pdev)
775 {
776 pm_runtime_disable(&pdev->dev);
777 return 0;
778 }
779
780 static struct platform_device_id spi_driver_ids[] = {
781 { "spi_sh_msiof", (kernel_ulong_t)&sh_data },
782 { "spi_r8a7790_msiof", (kernel_ulong_t)&r8a779x_data },
783 { "spi_r8a7791_msiof", (kernel_ulong_t)&r8a779x_data },
784 {},
785 };
786 MODULE_DEVICE_TABLE(platform, spi_driver_ids);
787
788 static struct platform_driver sh_msiof_spi_drv = {
789 .probe = sh_msiof_spi_probe,
790 .remove = sh_msiof_spi_remove,
791 .id_table = spi_driver_ids,
792 .driver = {
793 .name = "spi_sh_msiof",
794 .owner = THIS_MODULE,
795 .of_match_table = of_match_ptr(sh_msiof_match),
796 },
797 };
798 module_platform_driver(sh_msiof_spi_drv);
799
800 MODULE_DESCRIPTION("SuperH MSIOF SPI Master Interface Driver");
801 MODULE_AUTHOR("Magnus Damm");
802 MODULE_LICENSE("GPL v2");
803 MODULE_ALIAS("platform:spi_sh_msiof");
Linux with added FPC-III support