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powerpc: Fix personality handling in ppc64_personality()
[linux/fpc-iii.git] / arch / powerpc / kernel / head_booke.h
blob5f051eeb93a278cb33c823c722582fb4652566f5
1 #ifndef __HEAD_BOOKE_H__
2 #define __HEAD_BOOKE_H__
3
4 #include <asm/ptrace.h> /* for STACK_FRAME_REGS_MARKER */
5 #include <asm/kvm_asm.h>
6 #include <asm/kvm_booke_hv_asm.h>
7
8 /*
9 * Macros used for common Book-e exception handling
10 */
11
12 #define SET_IVOR(vector_number, vector_label) \
13 li r26,vector_label@l; \
14 mtspr SPRN_IVOR##vector_number,r26; \
15 sync
16
17 #if (THREAD_SHIFT < 15)
18 #define ALLOC_STACK_FRAME(reg, val) \
19 addi reg,reg,val
20 #else
21 #define ALLOC_STACK_FRAME(reg, val) \
22 addis reg,reg,val@ha; \
23 addi reg,reg,val@l
24 #endif
25
26 /*
27 * Macro used to get to thread save registers.
28 * Note that entries 0-3 are used for the prolog code, and the remaining
29 * entries are available for specific exception use in the event a handler
30 * requires more than 4 scratch registers.
31 */
32 #define THREAD_NORMSAVE(offset) (THREAD_NORMSAVES + (offset * 4))
33
34 #define NORMAL_EXCEPTION_PROLOG(intno) \
35 mtspr SPRN_SPRG_WSCRATCH0, r10; /* save one register */ \
36 mfspr r10, SPRN_SPRG_THREAD; \
37 stw r11, THREAD_NORMSAVE(0)(r10); \
38 stw r13, THREAD_NORMSAVE(2)(r10); \
39 mfcr r13; /* save CR in r13 for now */\
40 mfspr r11, SPRN_SRR1; \
41 DO_KVM BOOKE_INTERRUPT_##intno SPRN_SRR1; \
42 andi. r11, r11, MSR_PR; /* check whether user or kernel */\
43 mr r11, r1; \
44 beq 1f; \
45 /* if from user, start at top of this thread's kernel stack */ \
46 lwz r11, THREAD_INFO-THREAD(r10); \
47 ALLOC_STACK_FRAME(r11, THREAD_SIZE); \
48 1 : subi r11, r11, INT_FRAME_SIZE; /* Allocate exception frame */ \
49 stw r13, _CCR(r11); /* save various registers */ \
50 stw r12,GPR12(r11); \
51 stw r9,GPR9(r11); \
52 mfspr r13, SPRN_SPRG_RSCRATCH0; \
53 stw r13, GPR10(r11); \
54 lwz r12, THREAD_NORMSAVE(0)(r10); \
55 stw r12,GPR11(r11); \
56 lwz r13, THREAD_NORMSAVE(2)(r10); /* restore r13 */ \
57 mflr r10; \
58 stw r10,_LINK(r11); \
59 mfspr r12,SPRN_SRR0; \
60 stw r1, GPR1(r11); \
61 mfspr r9,SPRN_SRR1; \
62 stw r1, 0(r11); \
63 mr r1, r11; \
64 rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\
65 stw r0,GPR0(r11); \
66 lis r10, STACK_FRAME_REGS_MARKER@ha;/* exception frame marker */ \
67 addi r10, r10, STACK_FRAME_REGS_MARKER@l; \
68 stw r10, 8(r11); \
69 SAVE_4GPRS(3, r11); \
70 SAVE_2GPRS(7, r11)
71
72 /* To handle the additional exception priority levels on 40x and Book-E
73 * processors we allocate a stack per additional priority level.
74 *
75 * On 40x critical is the only additional level
76 * On 44x/e500 we have critical and machine check
77 * On e200 we have critical and debug (machine check occurs via critical)
78 *
79 * Additionally we reserve a SPRG for each priority level so we can free up a
80 * GPR to use as the base for indirect access to the exception stacks. This
81 * is necessary since the MMU is always on, for Book-E parts, and the stacks
82 * are offset from KERNELBASE.
83 *
84 * There is some space optimization to be had here if desired. However
85 * to allow for a common kernel with support for debug exceptions either
86 * going to critical or their own debug level we aren't currently
87 * providing configurations that micro-optimize space usage.
88 */
89
90 #define MC_STACK_BASE mcheckirq_ctx
91 #define CRIT_STACK_BASE critirq_ctx
92
93 /* only on e500mc/e200 */
94 #define DBG_STACK_BASE dbgirq_ctx
95
96 #define EXC_LVL_FRAME_OVERHEAD (THREAD_SIZE - INT_FRAME_SIZE - EXC_LVL_SIZE)
97
98 #ifdef CONFIG_SMP
99 #define BOOKE_LOAD_EXC_LEVEL_STACK(level) \
100 mfspr r8,SPRN_PIR; \
101 slwi r8,r8,2; \
102 addis r8,r8,level##_STACK_BASE@ha; \
103 lwz r8,level##_STACK_BASE@l(r8); \
104 addi r8,r8,EXC_LVL_FRAME_OVERHEAD;
105 #else
106 #define BOOKE_LOAD_EXC_LEVEL_STACK(level) \
107 lis r8,level##_STACK_BASE@ha; \
108 lwz r8,level##_STACK_BASE@l(r8); \
109 addi r8,r8,EXC_LVL_FRAME_OVERHEAD;
110 #endif
111
112 /*
113 * Exception prolog for critical/machine check exceptions. This is a
114 * little different from the normal exception prolog above since a
115 * critical/machine check exception can potentially occur at any point
116 * during normal exception processing. Thus we cannot use the same SPRG
117 * registers as the normal prolog above. Instead we use a portion of the
118 * critical/machine check exception stack at low physical addresses.
119 */
120 #define EXC_LEVEL_EXCEPTION_PROLOG(exc_level, intno, exc_level_srr0, exc_level_srr1) \
121 mtspr SPRN_SPRG_WSCRATCH_##exc_level,r8; \
122 BOOKE_LOAD_EXC_LEVEL_STACK(exc_level);/* r8 points to the exc_level stack*/ \
123 stw r9,GPR9(r8); /* save various registers */\
124 mfcr r9; /* save CR in r9 for now */\
125 stw r10,GPR10(r8); \
126 stw r11,GPR11(r8); \
127 stw r9,_CCR(r8); /* save CR on stack */\
128 mfspr r11,exc_level_srr1; /* check whether user or kernel */\
129 DO_KVM BOOKE_INTERRUPT_##intno exc_level_srr1; \
130 andi. r11,r11,MSR_PR; \
131 mfspr r11,SPRN_SPRG_THREAD; /* if from user, start at top of */\
132 lwz r11,THREAD_INFO-THREAD(r11); /* this thread's kernel stack */\
133 addi r11,r11,EXC_LVL_FRAME_OVERHEAD; /* allocate stack frame */\
134 beq 1f; \
135 /* COMING FROM USER MODE */ \
136 stw r9,_CCR(r11); /* save CR */\
137 lwz r10,GPR10(r8); /* copy regs from exception stack */\
138 lwz r9,GPR9(r8); \
139 stw r10,GPR10(r11); \
140 lwz r10,GPR11(r8); \
141 stw r9,GPR9(r11); \
142 stw r10,GPR11(r11); \
143 b 2f; \
144 /* COMING FROM PRIV MODE */ \
145 1: lwz r9,TI_FLAGS-EXC_LVL_FRAME_OVERHEAD(r11); \
146 lwz r10,TI_PREEMPT-EXC_LVL_FRAME_OVERHEAD(r11); \
147 stw r9,TI_FLAGS-EXC_LVL_FRAME_OVERHEAD(r8); \
148 stw r10,TI_PREEMPT-EXC_LVL_FRAME_OVERHEAD(r8); \
149 lwz r9,TI_TASK-EXC_LVL_FRAME_OVERHEAD(r11); \
150 stw r9,TI_TASK-EXC_LVL_FRAME_OVERHEAD(r8); \
151 mr r11,r8; \
152 2: mfspr r8,SPRN_SPRG_RSCRATCH_##exc_level; \
153 stw r12,GPR12(r11); /* save various registers */\
154 mflr r10; \
155 stw r10,_LINK(r11); \
156 mfspr r12,SPRN_DEAR; /* save DEAR and ESR in the frame */\
157 stw r12,_DEAR(r11); /* since they may have had stuff */\
158 mfspr r9,SPRN_ESR; /* in them at the point where the */\
159 stw r9,_ESR(r11); /* exception was taken */\
160 mfspr r12,exc_level_srr0; \
161 stw r1,GPR1(r11); \
162 mfspr r9,exc_level_srr1; \
163 stw r1,0(r11); \
164 mr r1,r11; \
165 rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\
166 stw r0,GPR0(r11); \
167 SAVE_4GPRS(3, r11); \
168 SAVE_2GPRS(7, r11)
169
170 #define CRITICAL_EXCEPTION_PROLOG(intno) \
171 EXC_LEVEL_EXCEPTION_PROLOG(CRIT, intno, SPRN_CSRR0, SPRN_CSRR1)
172 #define DEBUG_EXCEPTION_PROLOG \
173 EXC_LEVEL_EXCEPTION_PROLOG(DBG, DEBUG, SPRN_DSRR0, SPRN_DSRR1)
174 #define MCHECK_EXCEPTION_PROLOG \
175 EXC_LEVEL_EXCEPTION_PROLOG(MC, MACHINE_CHECK, \
176 SPRN_MCSRR0, SPRN_MCSRR1)
177
178 /*
179 * Guest Doorbell -- this is a bit odd in that uses GSRR0/1 despite
180 * being delivered to the host. This exception can only happen
181 * inside a KVM guest -- so we just handle up to the DO_KVM rather
182 * than try to fit this into one of the existing prolog macros.
183 */
184 #define GUEST_DOORBELL_EXCEPTION \
185 START_EXCEPTION(GuestDoorbell); \
186 mtspr SPRN_SPRG_WSCRATCH0, r10; /* save one register */ \
187 mfspr r10, SPRN_SPRG_THREAD; \
188 stw r11, THREAD_NORMSAVE(0)(r10); \
189 mfspr r11, SPRN_SRR1; \
190 stw r13, THREAD_NORMSAVE(2)(r10); \
191 mfcr r13; /* save CR in r13 for now */\
192 DO_KVM BOOKE_INTERRUPT_GUEST_DBELL SPRN_GSRR1; \
193 trap
194
195 /*
196 * Exception vectors.
197 */
198 #define START_EXCEPTION(label) \
199 .align 5; \
200 label:
201
202 #define FINISH_EXCEPTION(func) \
203 bl transfer_to_handler_full; \
204 .long func; \
205 .long ret_from_except_full
206
207 #define EXCEPTION(n, intno, label, hdlr, xfer) \
208 START_EXCEPTION(label); \
209 NORMAL_EXCEPTION_PROLOG(intno); \
210 addi r3,r1,STACK_FRAME_OVERHEAD; \
211 xfer(n, hdlr)
212
213 #define CRITICAL_EXCEPTION(n, intno, label, hdlr) \
214 START_EXCEPTION(label); \
215 CRITICAL_EXCEPTION_PROLOG(intno); \
216 addi r3,r1,STACK_FRAME_OVERHEAD; \
217 EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
218 NOCOPY, crit_transfer_to_handler, \
219 ret_from_crit_exc)
220
221 #define MCHECK_EXCEPTION(n, label, hdlr) \
222 START_EXCEPTION(label); \
223 MCHECK_EXCEPTION_PROLOG; \
224 mfspr r5,SPRN_ESR; \
225 stw r5,_ESR(r11); \
226 addi r3,r1,STACK_FRAME_OVERHEAD; \
227 EXC_XFER_TEMPLATE(hdlr, n+4, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
228 NOCOPY, mcheck_transfer_to_handler, \
229 ret_from_mcheck_exc)
230
231 #define EXC_XFER_TEMPLATE(hdlr, trap, msr, copyee, tfer, ret) \
232 li r10,trap; \
233 stw r10,_TRAP(r11); \
234 lis r10,msr@h; \
235 ori r10,r10,msr@l; \
236 copyee(r10, r9); \
237 bl tfer; \
238 .long hdlr; \
239 .long ret
240
241 #define COPY_EE(d, s) rlwimi d,s,0,16,16
242 #define NOCOPY(d, s)
243
244 #define EXC_XFER_STD(n, hdlr) \
245 EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, NOCOPY, transfer_to_handler_full, \
246 ret_from_except_full)
247
248 #define EXC_XFER_LITE(n, hdlr) \
249 EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, NOCOPY, transfer_to_handler, \
250 ret_from_except)
251
252 #define EXC_XFER_EE(n, hdlr) \
253 EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, COPY_EE, transfer_to_handler_full, \
254 ret_from_except_full)
255
256 #define EXC_XFER_EE_LITE(n, hdlr) \
257 EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, COPY_EE, transfer_to_handler, \
258 ret_from_except)
259
260 /* Check for a single step debug exception while in an exception
261 * handler before state has been saved. This is to catch the case
262 * where an instruction that we are trying to single step causes
263 * an exception (eg ITLB/DTLB miss) and thus the first instruction of
264 * the exception handler generates a single step debug exception.
265 *
266 * If we get a debug trap on the first instruction of an exception handler,
267 * we reset the MSR_DE in the _exception handler's_ MSR (the debug trap is
268 * a critical exception, so we are using SPRN_CSRR1 to manipulate the MSR).
269 * The exception handler was handling a non-critical interrupt, so it will
270 * save (and later restore) the MSR via SPRN_CSRR1, which will still have
271 * the MSR_DE bit set.
272 */
273 #define DEBUG_DEBUG_EXCEPTION \
274 START_EXCEPTION(DebugDebug); \
275 DEBUG_EXCEPTION_PROLOG; \
276 \
277 /* \
278 * If there is a single step or branch-taken exception in an \
279 * exception entry sequence, it was probably meant to apply to \
280 * the code where the exception occurred (since exception entry \
281 * doesn't turn off DE automatically). We simulate the effect \
282 * of turning off DE on entry to an exception handler by turning \
283 * off DE in the DSRR1 value and clearing the debug status. \
284 */ \
285 mfspr r10,SPRN_DBSR; /* check single-step/branch taken */ \
286 andis. r10,r10,(DBSR_IC|DBSR_BT)@h; \
287 beq+ 2f; \
288 \
289 lis r10,KERNELBASE@h; /* check if exception in vectors */ \
290 ori r10,r10,KERNELBASE@l; \
291 cmplw r12,r10; \
292 blt+ 2f; /* addr below exception vectors */ \
293 \
294 lis r10,DebugDebug@h; \
295 ori r10,r10,DebugDebug@l; \
296 cmplw r12,r10; \
297 bgt+ 2f; /* addr above exception vectors */ \
298 \
299 /* here it looks like we got an inappropriate debug exception. */ \
300 1: rlwinm r9,r9,0,~MSR_DE; /* clear DE in the CDRR1 value */ \
301 lis r10,(DBSR_IC|DBSR_BT)@h; /* clear the IC event */ \
302 mtspr SPRN_DBSR,r10; \
303 /* restore state and get out */ \
304 lwz r10,_CCR(r11); \
305 lwz r0,GPR0(r11); \
306 lwz r1,GPR1(r11); \
307 mtcrf 0x80,r10; \
308 mtspr SPRN_DSRR0,r12; \
309 mtspr SPRN_DSRR1,r9; \
310 lwz r9,GPR9(r11); \
311 lwz r12,GPR12(r11); \
312 mtspr SPRN_SPRG_WSCRATCH_DBG,r8; \
313 BOOKE_LOAD_EXC_LEVEL_STACK(DBG); /* r8 points to the debug stack */ \
314 lwz r10,GPR10(r8); \
315 lwz r11,GPR11(r8); \
316 mfspr r8,SPRN_SPRG_RSCRATCH_DBG; \
317 \
318 PPC_RFDI; \
319 b .; \
320 \
321 /* continue normal handling for a debug exception... */ \
322 2: mfspr r4,SPRN_DBSR; \
323 addi r3,r1,STACK_FRAME_OVERHEAD; \
324 EXC_XFER_TEMPLATE(DebugException, 0x2008, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), NOCOPY, debug_transfer_to_handler, ret_from_debug_exc)
325
326 #define DEBUG_CRIT_EXCEPTION \
327 START_EXCEPTION(DebugCrit); \
328 CRITICAL_EXCEPTION_PROLOG(DEBUG); \
329 \
330 /* \
331 * If there is a single step or branch-taken exception in an \
332 * exception entry sequence, it was probably meant to apply to \
333 * the code where the exception occurred (since exception entry \
334 * doesn't turn off DE automatically). We simulate the effect \
335 * of turning off DE on entry to an exception handler by turning \
336 * off DE in the CSRR1 value and clearing the debug status. \
337 */ \
338 mfspr r10,SPRN_DBSR; /* check single-step/branch taken */ \
339 andis. r10,r10,(DBSR_IC|DBSR_BT)@h; \
340 beq+ 2f; \
341 \
342 lis r10,KERNELBASE@h; /* check if exception in vectors */ \
343 ori r10,r10,KERNELBASE@l; \
344 cmplw r12,r10; \
345 blt+ 2f; /* addr below exception vectors */ \
346 \
347 lis r10,DebugCrit@h; \
348 ori r10,r10,DebugCrit@l; \
349 cmplw r12,r10; \
350 bgt+ 2f; /* addr above exception vectors */ \
351 \
352 /* here it looks like we got an inappropriate debug exception. */ \
353 1: rlwinm r9,r9,0,~MSR_DE; /* clear DE in the CSRR1 value */ \
354 lis r10,(DBSR_IC|DBSR_BT)@h; /* clear the IC event */ \
355 mtspr SPRN_DBSR,r10; \
356 /* restore state and get out */ \
357 lwz r10,_CCR(r11); \
358 lwz r0,GPR0(r11); \
359 lwz r1,GPR1(r11); \
360 mtcrf 0x80,r10; \
361 mtspr SPRN_CSRR0,r12; \
362 mtspr SPRN_CSRR1,r9; \
363 lwz r9,GPR9(r11); \
364 lwz r12,GPR12(r11); \
365 mtspr SPRN_SPRG_WSCRATCH_CRIT,r8; \
366 BOOKE_LOAD_EXC_LEVEL_STACK(CRIT); /* r8 points to the debug stack */ \
367 lwz r10,GPR10(r8); \
368 lwz r11,GPR11(r8); \
369 mfspr r8,SPRN_SPRG_RSCRATCH_CRIT; \
370 \
371 rfci; \
372 b .; \
373 \
374 /* continue normal handling for a critical exception... */ \
375 2: mfspr r4,SPRN_DBSR; \
376 addi r3,r1,STACK_FRAME_OVERHEAD; \
377 EXC_XFER_TEMPLATE(DebugException, 0x2002, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), NOCOPY, crit_transfer_to_handler, ret_from_crit_exc)
378
379 #define DATA_STORAGE_EXCEPTION \
380 START_EXCEPTION(DataStorage) \
381 NORMAL_EXCEPTION_PROLOG(DATA_STORAGE); \
382 mfspr r5,SPRN_ESR; /* Grab the ESR and save it */ \
383 stw r5,_ESR(r11); \
384 mfspr r4,SPRN_DEAR; /* Grab the DEAR */ \
385 EXC_XFER_LITE(0x0300, handle_page_fault)
386
387 #define INSTRUCTION_STORAGE_EXCEPTION \
388 START_EXCEPTION(InstructionStorage) \
389 NORMAL_EXCEPTION_PROLOG(INST_STORAGE); \
390 mfspr r5,SPRN_ESR; /* Grab the ESR and save it */ \
391 stw r5,_ESR(r11); \
392 mr r4,r12; /* Pass SRR0 as arg2 */ \
393 li r5,0; /* Pass zero as arg3 */ \
394 EXC_XFER_LITE(0x0400, handle_page_fault)
395
396 #define ALIGNMENT_EXCEPTION \
397 START_EXCEPTION(Alignment) \
398 NORMAL_EXCEPTION_PROLOG(ALIGNMENT); \
399 mfspr r4,SPRN_DEAR; /* Grab the DEAR and save it */ \
400 stw r4,_DEAR(r11); \
401 addi r3,r1,STACK_FRAME_OVERHEAD; \
402 EXC_XFER_EE(0x0600, alignment_exception)
403
404 #define PROGRAM_EXCEPTION \
405 START_EXCEPTION(Program) \
406 NORMAL_EXCEPTION_PROLOG(PROGRAM); \
407 mfspr r4,SPRN_ESR; /* Grab the ESR and save it */ \
408 stw r4,_ESR(r11); \
409 addi r3,r1,STACK_FRAME_OVERHEAD; \
410 EXC_XFER_STD(0x0700, program_check_exception)
411
412 #define DECREMENTER_EXCEPTION \
413 START_EXCEPTION(Decrementer) \
414 NORMAL_EXCEPTION_PROLOG(DECREMENTER); \
415 lis r0,TSR_DIS@h; /* Setup the DEC interrupt mask */ \
416 mtspr SPRN_TSR,r0; /* Clear the DEC interrupt */ \
417 addi r3,r1,STACK_FRAME_OVERHEAD; \
418 EXC_XFER_LITE(0x0900, timer_interrupt)
419
420 #define FP_UNAVAILABLE_EXCEPTION \
421 START_EXCEPTION(FloatingPointUnavailable) \
422 NORMAL_EXCEPTION_PROLOG(FP_UNAVAIL); \
423 beq 1f; \
424 bl load_up_fpu; /* if from user, just load it up */ \
425 b fast_exception_return; \
426 1: addi r3,r1,STACK_FRAME_OVERHEAD; \
427 EXC_XFER_EE_LITE(0x800, kernel_fp_unavailable_exception)
428
429 #ifndef __ASSEMBLY__
430 struct exception_regs {
431 unsigned long mas0;
432 unsigned long mas1;
433 unsigned long mas2;
434 unsigned long mas3;
435 unsigned long mas6;
436 unsigned long mas7;
437 unsigned long srr0;
438 unsigned long srr1;
439 unsigned long csrr0;
440 unsigned long csrr1;
441 unsigned long dsrr0;
442 unsigned long dsrr1;
443 unsigned long saved_ksp_limit;
444 };
445
446 /* ensure this structure is always sized to a multiple of the stack alignment */
447 #define STACK_EXC_LVL_FRAME_SIZE _ALIGN_UP(sizeof (struct exception_regs), 16)
448
449 #endif /* __ASSEMBLY__ */
450 #endif /* __HEAD_BOOKE_H__ */
Linux with added FPC-III support