| blob | 7ba49662b9bcde0fae3e1651b7795f1bd05dd83e |
1 /*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
12 /include/ "skeleton.dtsi"
14 / {
15 interrupt-parent = <&icoll>;
17 aliases {
18 gpio0 = &gpio0;
19 gpio1 = &gpio1;
20 gpio2 = &gpio2;
21 gpio3 = &gpio3;
22 gpio4 = &gpio4;
23 saif0 = &saif0;
24 saif1 = &saif1;
25 serial0 = &auart0;
26 serial1 = &auart1;
27 serial2 = &auart2;
28 serial3 = &auart3;
29 serial4 = &auart4;
30 ethernet0 = &mac0;
31 ethernet1 = &mac1;
32 };
34 cpus {
35 cpu@0 {
36 compatible = "arm,arm926ejs";
37 };
38 };
40 apb@80000000 {
41 compatible = "simple-bus";
42 #address-cells = <1>;
43 #size-cells = <1>;
44 reg = <0x80000000 0x80000>;
45 ranges;
47 apbh@80000000 {
48 compatible = "simple-bus";
49 #address-cells = <1>;
50 #size-cells = <1>;
51 reg = <0x80000000 0x3c900>;
52 ranges;
54 icoll: interrupt-controller@80000000 {
55 compatible = "fsl,imx28-icoll", "fsl,icoll";
56 interrupt-controller;
57 #interrupt-cells = <1>;
58 reg = <0x80000000 0x2000>;
59 };
61 hsadc@80002000 {
62 reg = <0x80002000 0x2000>;
63 interrupts = <13 87>;
64 status = "disabled";
65 };
67 dma-apbh@80004000 {
68 compatible = "fsl,imx28-dma-apbh";
69 reg = <0x80004000 0x2000>;
70 clocks = <&clks 25>;
71 };
73 perfmon@80006000 {
74 reg = <0x80006000 0x800>;
75 interrupts = <27>;
76 status = "disabled";
77 };
79 gpmi-nand@8000c000 {
80 compatible = "fsl,imx28-gpmi-nand";
81 #address-cells = <1>;
82 #size-cells = <1>;
83 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
84 reg-names = "gpmi-nand", "bch";
85 interrupts = <88>, <41>;
86 interrupt-names = "gpmi-dma", "bch";
87 clocks = <&clks 50>;
88 clock-names = "gpmi_io";
89 fsl,gpmi-dma-channel = <4>;
90 status = "disabled";
91 };
93 ssp0: ssp@80010000 {
94 #address-cells = <1>;
95 #size-cells = <0>;
96 reg = <0x80010000 0x2000>;
97 interrupts = <96 82>;
98 clocks = <&clks 46>;
99 fsl,ssp-dma-channel = <0>;
100 status = "disabled";
101 };
103 ssp1: ssp@80012000 {
104 #address-cells = <1>;
105 #size-cells = <0>;
106 reg = <0x80012000 0x2000>;
107 interrupts = <97 83>;
108 clocks = <&clks 47>;
109 fsl,ssp-dma-channel = <1>;
110 status = "disabled";
111 };
113 ssp2: ssp@80014000 {
114 #address-cells = <1>;
115 #size-cells = <0>;
116 reg = <0x80014000 0x2000>;
117 interrupts = <98 84>;
118 clocks = <&clks 48>;
119 fsl,ssp-dma-channel = <2>;
120 status = "disabled";
121 };
123 ssp3: ssp@80016000 {
124 #address-cells = <1>;
125 #size-cells = <0>;
126 reg = <0x80016000 0x2000>;
127 interrupts = <99 85>;
128 clocks = <&clks 49>;
129 fsl,ssp-dma-channel = <3>;
130 status = "disabled";
131 };
133 pinctrl@80018000 {
134 #address-cells = <1>;
135 #size-cells = <0>;
136 compatible = "fsl,imx28-pinctrl", "simple-bus";
137 reg = <0x80018000 0x2000>;
139 gpio0: gpio@0 {
140 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
141 interrupts = <127>;
142 gpio-controller;
143 #gpio-cells = <2>;
144 interrupt-controller;
145 #interrupt-cells = <2>;
146 };
148 gpio1: gpio@1 {
149 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
150 interrupts = <126>;
151 gpio-controller;
152 #gpio-cells = <2>;
153 interrupt-controller;
154 #interrupt-cells = <2>;
155 };
157 gpio2: gpio@2 {
158 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
159 interrupts = <125>;
160 gpio-controller;
161 #gpio-cells = <2>;
162 interrupt-controller;
163 #interrupt-cells = <2>;
164 };
166 gpio3: gpio@3 {
167 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
168 interrupts = <124>;
169 gpio-controller;
170 #gpio-cells = <2>;
171 interrupt-controller;
172 #interrupt-cells = <2>;
173 };
175 gpio4: gpio@4 {
176 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
177 interrupts = <123>;
178 gpio-controller;
179 #gpio-cells = <2>;
180 interrupt-controller;
181 #interrupt-cells = <2>;
182 };
184 duart_pins_a: duart@0 {
185 reg = <0>;
186 fsl,pinmux-ids = <
187 0x3102 /* MX28_PAD_PWM0__DUART_RX */
188 0x3112 /* MX28_PAD_PWM1__DUART_TX */
189 >;
190 fsl,drive-strength = <0>;
191 fsl,voltage = <1>;
192 fsl,pull-up = <0>;
193 };
195 duart_pins_b: duart@1 {
196 reg = <1>;
197 fsl,pinmux-ids = <
198 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */
199 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */
200 >;
201 fsl,drive-strength = <0>;
202 fsl,voltage = <1>;
203 fsl,pull-up = <0>;
204 };
206 duart_4pins_a: duart-4pins@0 {
207 reg = <0>;
208 fsl,pinmux-ids = <
209 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */
210 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */
211 0x3002 /* MX28_PAD_AUART0_RX__DUART_CTS */
212 0x3012 /* MX28_PAD_AUART0_TX__DUART_RTS */
213 >;
214 fsl,drive-strength = <0>;
215 fsl,voltage = <1>;
216 fsl,pull-up = <0>;
217 };
219 gpmi_pins_a: gpmi-nand@0 {
220 reg = <0>;
221 fsl,pinmux-ids = <
222 0x0000 /* MX28_PAD_GPMI_D00__GPMI_D0 */
223 0x0010 /* MX28_PAD_GPMI_D01__GPMI_D1 */
224 0x0020 /* MX28_PAD_GPMI_D02__GPMI_D2 */
225 0x0030 /* MX28_PAD_GPMI_D03__GPMI_D3 */
226 0x0040 /* MX28_PAD_GPMI_D04__GPMI_D4 */
227 0x0050 /* MX28_PAD_GPMI_D05__GPMI_D5 */
228 0x0060 /* MX28_PAD_GPMI_D06__GPMI_D6 */
229 0x0070 /* MX28_PAD_GPMI_D07__GPMI_D7 */
230 0x0100 /* MX28_PAD_GPMI_CE0N__GPMI_CE0N */
231 0x0140 /* MX28_PAD_GPMI_RDY0__GPMI_READY0 */
232 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */
233 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */
234 0x01a0 /* MX28_PAD_GPMI_ALE__GPMI_ALE */
235 0x01b0 /* MX28_PAD_GPMI_CLE__GPMI_CLE */
236 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */
237 >;
238 fsl,drive-strength = <0>;
239 fsl,voltage = <1>;
240 fsl,pull-up = <0>;
241 };
243 gpmi_status_cfg: gpmi-status-cfg {
244 fsl,pinmux-ids = <
245 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */
246 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */
247 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */
248 >;
249 fsl,drive-strength = <2>;
250 };
252 auart0_pins_a: auart0@0 {
253 reg = <0>;
254 fsl,pinmux-ids = <
255 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */
256 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */
257 0x3020 /* MX28_PAD_AUART0_CTS__AUART0_CTS */
258 0x3030 /* MX28_PAD_AUART0_RTS__AUART0_RTS */
259 >;
260 fsl,drive-strength = <0>;
261 fsl,voltage = <1>;
262 fsl,pull-up = <0>;
263 };
265 auart0_2pins_a: auart0-2pins@0 {
266 reg = <0>;
267 fsl,pinmux-ids = <
268 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */
269 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */
270 >;
271 fsl,drive-strength = <0>;
272 fsl,voltage = <1>;
273 fsl,pull-up = <0>;
274 };
276 auart1_pins_a: auart1@0 {
277 reg = <0>;
278 fsl,pinmux-ids = <
279 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */
280 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */
281 0x3060 /* MX28_PAD_AUART1_CTS__AUART1_CTS */
282 0x3070 /* MX28_PAD_AUART1_RTS__AUART1_RTS */
283 >;
284 fsl,drive-strength = <0>;
285 fsl,voltage = <1>;
286 fsl,pull-up = <0>;
287 };
289 auart1_2pins_a: auart1-2pins@0 {
290 reg = <0>;
291 fsl,pinmux-ids = <
292 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */
293 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */
294 >;
295 fsl,drive-strength = <0>;
296 fsl,voltage = <1>;
297 fsl,pull-up = <0>;
298 };
300 auart2_2pins_a: auart2-2pins@0 {
301 reg = <0>;
302 fsl,pinmux-ids = <
303 0x2101 /* MX28_PAD_SSP2_SCK__AUART2_RX */
304 0x2111 /* MX28_PAD_SSP2_MOSI__AUART2_TX */
305 >;
306 fsl,drive-strength = <0>;
307 fsl,voltage = <1>;
308 fsl,pull-up = <0>;
309 };
311 auart3_pins_a: auart3@0 {
312 reg = <0>;
313 fsl,pinmux-ids = <
314 0x30c0 /* MX28_PAD_AUART3_RX__AUART3_RX */
315 0x30d0 /* MX28_PAD_AUART3_TX__AUART3_TX */
316 0x30e0 /* MX28_PAD_AUART3_CTS__AUART3_CTS */
317 0x30f0 /* MX28_PAD_AUART3_RTS__AUART3_RTS */
318 >;
319 fsl,drive-strength = <0>;
320 fsl,voltage = <1>;
321 fsl,pull-up = <0>;
322 };
324 auart3_2pins_a: auart3-2pins@0 {
325 reg = <0>;
326 fsl,pinmux-ids = <
327 0x2121 /* MX28_PAD_SSP2_MISO__AUART3_RX */
328 0x2131 /* MX28_PAD_SSP2_SS0__AUART3_TX */
329 >;
330 fsl,drive-strength = <0>;
331 fsl,voltage = <1>;
332 fsl,pull-up = <0>;
333 };
335 mac0_pins_a: mac0@0 {
336 reg = <0>;
337 fsl,pinmux-ids = <
338 0x4000 /* MX28_PAD_ENET0_MDC__ENET0_MDC */
339 0x4010 /* MX28_PAD_ENET0_MDIO__ENET0_MDIO */
340 0x4020 /* MX28_PAD_ENET0_RX_EN__ENET0_RX_EN */
341 0x4030 /* MX28_PAD_ENET0_RXD0__ENET0_RXD0 */
342 0x4040 /* MX28_PAD_ENET0_RXD1__ENET0_RXD1 */
343 0x4060 /* MX28_PAD_ENET0_TX_EN__ENET0_TX_EN */
344 0x4070 /* MX28_PAD_ENET0_TXD0__ENET0_TXD0 */
345 0x4080 /* MX28_PAD_ENET0_TXD1__ENET0_TXD1 */
346 0x4100 /* MX28_PAD_ENET_CLK__CLKCTRL_ENET */
347 >;
348 fsl,drive-strength = <1>;
349 fsl,voltage = <1>;
350 fsl,pull-up = <1>;
351 };
353 mac1_pins_a: mac1@0 {
354 reg = <0>;
355 fsl,pinmux-ids = <
356 0x40f1 /* MX28_PAD_ENET0_CRS__ENET1_RX_EN */
357 0x4091 /* MX28_PAD_ENET0_RXD2__ENET1_RXD0 */
358 0x40a1 /* MX28_PAD_ENET0_RXD3__ENET1_RXD1 */
359 0x40e1 /* MX28_PAD_ENET0_COL__ENET1_TX_EN */
360 0x40b1 /* MX28_PAD_ENET0_TXD2__ENET1_TXD0 */
361 0x40c1 /* MX28_PAD_ENET0_TXD3__ENET1_TXD1 */
362 >;
363 fsl,drive-strength = <1>;
364 fsl,voltage = <1>;
365 fsl,pull-up = <1>;
366 };
368 mmc0_8bit_pins_a: mmc0-8bit@0 {
369 reg = <0>;
370 fsl,pinmux-ids = <
371 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
372 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
373 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
374 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
375 0x2040 /* MX28_PAD_SSP0_DATA4__SSP0_D4 */
376 0x2050 /* MX28_PAD_SSP0_DATA5__SSP0_D5 */
377 0x2060 /* MX28_PAD_SSP0_DATA6__SSP0_D6 */
378 0x2070 /* MX28_PAD_SSP0_DATA7__SSP0_D7 */
379 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
380 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
381 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
382 >;
383 fsl,drive-strength = <1>;
384 fsl,voltage = <1>;
385 fsl,pull-up = <1>;
386 };
388 mmc0_4bit_pins_a: mmc0-4bit@0 {
389 reg = <0>;
390 fsl,pinmux-ids = <
391 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
392 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
393 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
394 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
395 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
396 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
397 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
398 >;
399 fsl,drive-strength = <1>;
400 fsl,voltage = <1>;
401 fsl,pull-up = <1>;
402 };
404 mmc0_cd_cfg: mmc0-cd-cfg {
405 fsl,pinmux-ids = <
406 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
407 >;
408 fsl,pull-up = <0>;
409 };
411 mmc0_sck_cfg: mmc0-sck-cfg {
412 fsl,pinmux-ids = <
413 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
414 >;
415 fsl,drive-strength = <2>;
416 fsl,pull-up = <0>;
417 };
419 i2c0_pins_a: i2c0@0 {
420 reg = <0>;
421 fsl,pinmux-ids = <
422 0x3180 /* MX28_PAD_I2C0_SCL__I2C0_SCL */
423 0x3190 /* MX28_PAD_I2C0_SDA__I2C0_SDA */
424 >;
425 fsl,drive-strength = <1>;
426 fsl,voltage = <1>;
427 fsl,pull-up = <1>;
428 };
430 i2c0_pins_b: i2c0@1 {
431 reg = <1>;
432 fsl,pinmux-ids = <
433 0x3001 /* MX28_PAD_AUART0_RX__I2C0_SCL */
434 0x3011 /* MX28_PAD_AUART0_TX__I2C0_SDA */
435 >;
436 fsl,drive-strength = <1>;
437 fsl,voltage = <1>;
438 fsl,pull-up = <1>;
439 };
441 i2c1_pins_a: i2c1@0 {
442 reg = <0>;
443 fsl,pinmux-ids = <
444 0x3101 /* MX28_PAD_PWM0__I2C1_SCL */
445 0x3111 /* MX28_PAD_PWM1__I2C1_SDA */
446 >;
447 fsl,drive-strength = <1>;
448 fsl,voltage = <1>;
449 fsl,pull-up = <1>;
450 };
452 saif0_pins_a: saif0@0 {
453 reg = <0>;
454 fsl,pinmux-ids = <
455 0x3140 /* MX28_PAD_SAIF0_MCLK__SAIF0_MCLK */
456 0x3150 /* MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK */
457 0x3160 /* MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK */
458 0x3170 /* MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 */
459 >;
460 fsl,drive-strength = <2>;
461 fsl,voltage = <1>;
462 fsl,pull-up = <1>;
463 };
465 saif1_pins_a: saif1@0 {
466 reg = <0>;
467 fsl,pinmux-ids = <
468 0x31a0 /* MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 */
469 >;
470 fsl,drive-strength = <2>;
471 fsl,voltage = <1>;
472 fsl,pull-up = <1>;
473 };
475 pwm0_pins_a: pwm0@0 {
476 reg = <0>;
477 fsl,pinmux-ids = <
478 0x3100 /* MX28_PAD_PWM0__PWM_0 */
479 >;
480 fsl,drive-strength = <0>;
481 fsl,voltage = <1>;
482 fsl,pull-up = <0>;
483 };
485 pwm2_pins_a: pwm2@0 {
486 reg = <0>;
487 fsl,pinmux-ids = <
488 0x3120 /* MX28_PAD_PWM2__PWM_2 */
489 >;
490 fsl,drive-strength = <0>;
491 fsl,voltage = <1>;
492 fsl,pull-up = <0>;
493 };
495 pwm3_pins_a: pwm3@0 {
496 reg = <0>;
497 fsl,pinmux-ids = <
498 0x31c0 /* MX28_PAD_PWM3__PWM_3 */
499 >;
500 fsl,drive-strength = <0>;
501 fsl,voltage = <1>;
502 fsl,pull-up = <0>;
503 };
505 pwm3_pins_b: pwm3@1 {
506 reg = <1>;
507 fsl,pinmux-ids = <
508 0x3141 /* MX28_PAD_SAIF0_MCLK__PWM3 */
509 >;
510 fsl,drive-strength = <0>;
511 fsl,voltage = <1>;
512 fsl,pull-up = <0>;
513 };
515 pwm4_pins_a: pwm4@0 {
516 reg = <0>;
517 fsl,pinmux-ids = <
518 0x31d0 /* MX28_PAD_PWM4__PWM_4 */
519 >;
520 fsl,drive-strength = <0>;
521 fsl,voltage = <1>;
522 fsl,pull-up = <0>;
523 };
525 lcdif_24bit_pins_a: lcdif-24bit@0 {
526 reg = <0>;
527 fsl,pinmux-ids = <
528 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */
529 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */
530 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */
531 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */
532 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */
533 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */
534 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */
535 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */
536 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */
537 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */
538 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */
539 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */
540 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */
541 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */
542 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */
543 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */
544 0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */
545 0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */
546 0x1120 /* MX28_PAD_LCD_D18__LCD_D18 */
547 0x1130 /* MX28_PAD_LCD_D19__LCD_D19 */
548 0x1140 /* MX28_PAD_LCD_D20__LCD_D20 */
549 0x1150 /* MX28_PAD_LCD_D21__LCD_D21 */
550 0x1160 /* MX28_PAD_LCD_D22__LCD_D22 */
551 0x1170 /* MX28_PAD_LCD_D23__LCD_D23 */
552 >;
553 fsl,drive-strength = <0>;
554 fsl,voltage = <1>;
555 fsl,pull-up = <0>;
556 };
558 lcdif_16bit_pins_a: lcdif-16bit@0 {
559 reg = <0>;
560 fsl,pinmux-ids = <
561 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */
562 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */
563 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */
564 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */
565 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */
566 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */
567 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */
568 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */
569 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */
570 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */
571 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */
572 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */
573 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */
574 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */
575 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */
576 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */
577 >;
578 fsl,drive-strength = <0>;
579 fsl,voltage = <1>;
580 fsl,pull-up = <0>;
581 };
583 can0_pins_a: can0@0 {
584 reg = <0>;
585 fsl,pinmux-ids = <
586 0x0161 /* MX28_PAD_GPMI_RDY2__CAN0_TX */
587 0x0171 /* MX28_PAD_GPMI_RDY3__CAN0_RX */
588 >;
589 fsl,drive-strength = <0>;
590 fsl,voltage = <1>;
591 fsl,pull-up = <0>;
592 };
594 can1_pins_a: can1@0 {
595 reg = <0>;
596 fsl,pinmux-ids = <
597 0x0121 /* MX28_PAD_GPMI_CE2N__CAN1_TX */
598 0x0131 /* MX28_PAD_GPMI_CE3N__CAN1_RX */
599 >;
600 fsl,drive-strength = <0>;
601 fsl,voltage = <1>;
602 fsl,pull-up = <0>;
603 };
605 spi2_pins_a: spi2@0 {
606 reg = <0>;
607 fsl,pinmux-ids = <
608 0x2100 /* MX28_PAD_SSP2_SCK__SSP2_SCK */
609 0x2110 /* MX28_PAD_SSP2_MOSI__SSP2_CMD */
610 0x2120 /* MX28_PAD_SSP2_MISO__SSP2_D0 */
611 0x2130 /* MX28_PAD_SSP2_SS0__SSP2_D3 */
612 >;
613 fsl,drive-strength = <1>;
614 fsl,voltage = <1>;
615 fsl,pull-up = <1>;
616 };
618 usbphy0_pins_a: usbphy0@0 {
619 reg = <0>;
620 fsl,pinmux-ids = <
621 0x2152 /* MX28_PAD_SSP2_SS2__USB0_OVERCURRENT */
622 >;
623 fsl,drive-strength = <2>;
624 fsl,voltage = <1>;
625 fsl,pull-up = <0>;
626 };
628 usbphy0_pins_b: usbphy0@1 {
629 reg = <1>;
630 fsl,pinmux-ids = <
631 0x3061 /* MX28_PAD_AUART1_CTS__USB0_OVERCURRENT */
632 >;
633 fsl,drive-strength = <2>;
634 fsl,voltage = <1>;
635 fsl,pull-up = <0>;
636 };
638 usbphy1_pins_a: usbphy1@0 {
639 reg = <0>;
640 fsl,pinmux-ids = <
641 0x2142 /* MX28_PAD_SSP2_SS1__USB1_OVERCURRENT */
642 >;
643 fsl,drive-strength = <2>;
644 fsl,voltage = <1>;
645 fsl,pull-up = <0>;
646 };
647 };
649 digctl@8001c000 {
650 reg = <0x8001c000 0x2000>;
651 interrupts = <89>;
652 status = "disabled";
653 };
655 etm@80022000 {
656 reg = <0x80022000 0x2000>;
657 status = "disabled";
658 };
660 dma-apbx@80024000 {
661 compatible = "fsl,imx28-dma-apbx";
662 reg = <0x80024000 0x2000>;
663 clocks = <&clks 26>;
664 };
666 dcp@80028000 {
667 reg = <0x80028000 0x2000>;
668 interrupts = <52 53 54>;
669 status = "disabled";
670 };
672 pxp@8002a000 {
673 reg = <0x8002a000 0x2000>;
674 interrupts = <39>;
675 status = "disabled";
676 };
678 ocotp@8002c000 {
679 reg = <0x8002c000 0x2000>;
680 status = "disabled";
681 };
683 axi-ahb@8002e000 {
684 reg = <0x8002e000 0x2000>;
685 status = "disabled";
686 };
688 lcdif@80030000 {
689 compatible = "fsl,imx28-lcdif";
690 reg = <0x80030000 0x2000>;
691 interrupts = <38 86>;
692 clocks = <&clks 55>;
693 status = "disabled";
694 };
696 can0: can@80032000 {
697 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
698 reg = <0x80032000 0x2000>;
699 interrupts = <8>;
700 clocks = <&clks 58>, <&clks 58>;
701 clock-names = "ipg", "per";
702 status = "disabled";
703 };
705 can1: can@80034000 {
706 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
707 reg = <0x80034000 0x2000>;
708 interrupts = <9>;
709 clocks = <&clks 59>, <&clks 59>;
710 clock-names = "ipg", "per";
711 status = "disabled";
712 };
714 simdbg@8003c000 {
715 reg = <0x8003c000 0x200>;
716 status = "disabled";
717 };
719 simgpmisel@8003c200 {
720 reg = <0x8003c200 0x100>;
721 status = "disabled";
722 };
724 simsspsel@8003c300 {
725 reg = <0x8003c300 0x100>;
726 status = "disabled";
727 };
729 simmemsel@8003c400 {
730 reg = <0x8003c400 0x100>;
731 status = "disabled";
732 };
734 gpiomon@8003c500 {
735 reg = <0x8003c500 0x100>;
736 status = "disabled";
737 };
739 simenet@8003c700 {
740 reg = <0x8003c700 0x100>;
741 status = "disabled";
742 };
744 armjtag@8003c800 {
745 reg = <0x8003c800 0x100>;
746 status = "disabled";
747 };
748 };
750 apbx@80040000 {
751 compatible = "simple-bus";
752 #address-cells = <1>;
753 #size-cells = <1>;
754 reg = <0x80040000 0x40000>;
755 ranges;
757 clks: clkctrl@80040000 {
758 compatible = "fsl,imx28-clkctrl";
759 reg = <0x80040000 0x2000>;
760 #clock-cells = <1>;
761 };
763 saif0: saif@80042000 {
764 compatible = "fsl,imx28-saif";
765 reg = <0x80042000 0x2000>;
766 interrupts = <59 80>;
767 clocks = <&clks 53>;
768 fsl,saif-dma-channel = <4>;
769 status = "disabled";
770 };
772 power@80044000 {
773 reg = <0x80044000 0x2000>;
774 status = "disabled";
775 };
777 saif1: saif@80046000 {
778 compatible = "fsl,imx28-saif";
779 reg = <0x80046000 0x2000>;
780 interrupts = <58 81>;
781 clocks = <&clks 54>;
782 fsl,saif-dma-channel = <5>;
783 status = "disabled";
784 };
786 lradc@80050000 {
787 compatible = "fsl,imx28-lradc";
788 reg = <0x80050000 0x2000>;
789 interrupts = <10 14 15 16 17 18 19
790 20 21 22 23 24 25>;
791 status = "disabled";
792 };
794 spdif@80054000 {
795 reg = <0x80054000 0x2000>;
796 interrupts = <45 66>;
797 status = "disabled";
798 };
800 rtc@80056000 {
801 compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
802 reg = <0x80056000 0x2000>;
803 interrupts = <29>;
804 };
806 i2c0: i2c@80058000 {
807 #address-cells = <1>;
808 #size-cells = <0>;
809 compatible = "fsl,imx28-i2c";
810 reg = <0x80058000 0x2000>;
811 interrupts = <111 68>;
812 clock-frequency = <100000>;
813 fsl,i2c-dma-channel = <6>;
814 status = "disabled";
815 };
817 i2c1: i2c@8005a000 {
818 #address-cells = <1>;
819 #size-cells = <0>;
820 compatible = "fsl,imx28-i2c";
821 reg = <0x8005a000 0x2000>;
822 interrupts = <110 69>;
823 clock-frequency = <100000>;
824 fsl,i2c-dma-channel = <7>;
825 status = "disabled";
826 };
828 pwm: pwm@80064000 {
829 compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
830 reg = <0x80064000 0x2000>;
831 clocks = <&clks 44>;
832 #pwm-cells = <2>;
833 fsl,pwm-number = <8>;
834 status = "disabled";
835 };
837 timrot@80068000 {
838 compatible = "fsl,imx28-timrot", "fsl,timrot";
839 reg = <0x80068000 0x2000>;
840 interrupts = <48 49 50 51>;
841 };
843 auart0: serial@8006a000 {
844 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
845 reg = <0x8006a000 0x2000>;
846 interrupts = <112 70 71>;
847 fsl,auart-dma-channel = <8 9>;
848 clocks = <&clks 45>;
849 status = "disabled";
850 };
852 auart1: serial@8006c000 {
853 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
854 reg = <0x8006c000 0x2000>;
855 interrupts = <113 72 73>;
856 clocks = <&clks 45>;
857 status = "disabled";
858 };
860 auart2: serial@8006e000 {
861 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
862 reg = <0x8006e000 0x2000>;
863 interrupts = <114 74 75>;
864 clocks = <&clks 45>;
865 status = "disabled";
866 };
868 auart3: serial@80070000 {
869 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
870 reg = <0x80070000 0x2000>;
871 interrupts = <115 76 77>;
872 clocks = <&clks 45>;
873 status = "disabled";
874 };
876 auart4: serial@80072000 {
877 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
878 reg = <0x80072000 0x2000>;
879 interrupts = <116 78 79>;
880 clocks = <&clks 45>;
881 status = "disabled";
882 };
884 duart: serial@80074000 {
885 compatible = "arm,pl011", "arm,primecell";
886 reg = <0x80074000 0x1000>;
887 interrupts = <47>;
888 clocks = <&clks 45>, <&clks 26>;
889 clock-names = "uart", "apb_pclk";
890 status = "disabled";
891 };
893 usbphy0: usbphy@8007c000 {
894 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
895 reg = <0x8007c000 0x2000>;
896 clocks = <&clks 62>;
897 status = "disabled";
898 };
900 usbphy1: usbphy@8007e000 {
901 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
902 reg = <0x8007e000 0x2000>;
903 clocks = <&clks 63>;
904 status = "disabled";
905 };
906 };
907 };
909 ahb@80080000 {
910 compatible = "simple-bus";
911 #address-cells = <1>;
912 #size-cells = <1>;
913 reg = <0x80080000 0x80000>;
914 ranges;
916 usb0: usb@80080000 {
917 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
918 reg = <0x80080000 0x10000>;
919 interrupts = <93>;
920 clocks = <&clks 60>;
921 fsl,usbphy = <&usbphy0>;
922 status = "disabled";
923 };
925 usb1: usb@80090000 {
926 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
927 reg = <0x80090000 0x10000>;
928 interrupts = <92>;
929 clocks = <&clks 61>;
930 fsl,usbphy = <&usbphy1>;
931 status = "disabled";
932 };
934 dflpt@800c0000 {
935 reg = <0x800c0000 0x10000>;
936 status = "disabled";
937 };
939 mac0: ethernet@800f0000 {
940 compatible = "fsl,imx28-fec";
941 reg = <0x800f0000 0x4000>;
942 interrupts = <101>;
943 clocks = <&clks 57>, <&clks 57>;
944 clock-names = "ipg", "ahb";
945 status = "disabled";
946 };
948 mac1: ethernet@800f4000 {
949 compatible = "fsl,imx28-fec";
950 reg = <0x800f4000 0x4000>;
951 interrupts = <102>;
952 clocks = <&clks 57>, <&clks 57>;
953 clock-names = "ipg", "ahb";
954 status = "disabled";
955 };
957 switch@800f8000 {
958 reg = <0x800f8000 0x8000>;
959 status = "disabled";
960 };
962 };
963 };