| blob | 790bb2a4b3434d47a500005da78ec20d385afd48 |
1 /*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
8 */
10 /*
11 * Carveout for multimedia usecases
12 * It should be the last 48MB of the first 512MB memory part
13 * In theory, it should not even exist. That zone should be reserved
14 * dynamically during the .reserve callback.
15 */
16 /memreserve/ 0x9d000000 0x03000000;
18 /include/ "skeleton.dtsi"
20 / {
21 compatible = "ti,omap5";
22 interrupt-parent = <&gic>;
24 aliases {
25 serial0 = &uart1;
26 serial1 = &uart2;
27 serial2 = &uart3;
28 serial3 = &uart4;
29 serial4 = &uart5;
30 serial5 = &uart6;
31 };
33 cpus {
34 cpu@0 {
35 compatible = "arm,cortex-a15";
36 timer {
37 compatible = "arm,armv7-timer";
38 /* 14th PPI IRQ, active low level-sensitive */
39 interrupts = <1 14 0x308>;
40 clock-frequency = <6144000>;
41 };
42 };
43 cpu@1 {
44 compatible = "arm,cortex-a15";
45 timer {
46 compatible = "arm,armv7-timer";
47 /* 14th PPI IRQ, active low level-sensitive */
48 interrupts = <1 14 0x308>;
49 clock-frequency = <6144000>;
50 };
51 };
52 };
54 /*
55 * The soc node represents the soc top level view. It is uses for IPs
56 * that are not memory mapped in the MPU view or for the MPU itself.
57 */
58 soc {
59 compatible = "ti,omap-infra";
60 mpu {
61 compatible = "ti,omap5-mpu";
62 ti,hwmods = "mpu";
63 };
64 };
66 /*
67 * XXX: Use a flat representation of the OMAP3 interconnect.
68 * The real OMAP interconnect network is quite complex.
69 * Since that will not bring real advantage to represent that in DT for
70 * the moment, just use a fake OCP bus entry to represent the whole bus
71 * hierarchy.
72 */
73 ocp {
74 compatible = "ti,omap4-l3-noc", "simple-bus";
75 #address-cells = <1>;
76 #size-cells = <1>;
77 ranges;
78 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
80 counter32k: counter@4ae04000 {
81 compatible = "ti,omap-counter32k";
82 reg = <0x4ae04000 0x40>;
83 ti,hwmods = "counter_32k";
84 };
86 omap5_pmx_core: pinmux@4a002840 {
87 compatible = "ti,omap4-padconf", "pinctrl-single";
88 reg = <0x4a002840 0x01b6>;
89 #address-cells = <1>;
90 #size-cells = <0>;
91 pinctrl-single,register-width = <16>;
92 pinctrl-single,function-mask = <0x7fff>;
93 };
94 omap5_pmx_wkup: pinmux@4ae0c840 {
95 compatible = "ti,omap4-padconf", "pinctrl-single";
96 reg = <0x4ae0c840 0x0038>;
97 #address-cells = <1>;
98 #size-cells = <0>;
99 pinctrl-single,register-width = <16>;
100 pinctrl-single,function-mask = <0x7fff>;
101 };
103 gic: interrupt-controller@48211000 {
104 compatible = "arm,cortex-a15-gic";
105 interrupt-controller;
106 #interrupt-cells = <3>;
107 reg = <0x48211000 0x1000>,
108 <0x48212000 0x1000>;
109 };
111 gpio1: gpio@4ae10000 {
112 compatible = "ti,omap4-gpio";
113 reg = <0x4ae10000 0x200>;
114 interrupts = <0 29 0x4>;
115 ti,hwmods = "gpio1";
116 gpio-controller;
117 #gpio-cells = <2>;
118 interrupt-controller;
119 #interrupt-cells = <1>;
120 };
122 gpio2: gpio@48055000 {
123 compatible = "ti,omap4-gpio";
124 reg = <0x48055000 0x200>;
125 interrupts = <0 30 0x4>;
126 ti,hwmods = "gpio2";
127 gpio-controller;
128 #gpio-cells = <2>;
129 interrupt-controller;
130 #interrupt-cells = <1>;
131 };
133 gpio3: gpio@48057000 {
134 compatible = "ti,omap4-gpio";
135 reg = <0x48057000 0x200>;
136 interrupts = <0 31 0x4>;
137 ti,hwmods = "gpio3";
138 gpio-controller;
139 #gpio-cells = <2>;
140 interrupt-controller;
141 #interrupt-cells = <1>;
142 };
144 gpio4: gpio@48059000 {
145 compatible = "ti,omap4-gpio";
146 reg = <0x48059000 0x200>;
147 interrupts = <0 32 0x4>;
148 ti,hwmods = "gpio4";
149 gpio-controller;
150 #gpio-cells = <2>;
151 interrupt-controller;
152 #interrupt-cells = <1>;
153 };
155 gpio5: gpio@4805b000 {
156 compatible = "ti,omap4-gpio";
157 reg = <0x4805b000 0x200>;
158 interrupts = <0 33 0x4>;
159 ti,hwmods = "gpio5";
160 gpio-controller;
161 #gpio-cells = <2>;
162 interrupt-controller;
163 #interrupt-cells = <1>;
164 };
166 gpio6: gpio@4805d000 {
167 compatible = "ti,omap4-gpio";
168 reg = <0x4805d000 0x200>;
169 interrupts = <0 34 0x4>;
170 ti,hwmods = "gpio6";
171 gpio-controller;
172 #gpio-cells = <2>;
173 interrupt-controller;
174 #interrupt-cells = <1>;
175 };
177 gpio7: gpio@48051000 {
178 compatible = "ti,omap4-gpio";
179 reg = <0x48051000 0x200>;
180 interrupts = <0 35 0x4>;
181 ti,hwmods = "gpio7";
182 gpio-controller;
183 #gpio-cells = <2>;
184 interrupt-controller;
185 #interrupt-cells = <1>;
186 };
188 gpio8: gpio@48053000 {
189 compatible = "ti,omap4-gpio";
190 reg = <0x48053000 0x200>;
191 interrupts = <0 121 0x4>;
192 ti,hwmods = "gpio8";
193 gpio-controller;
194 #gpio-cells = <2>;
195 interrupt-controller;
196 #interrupt-cells = <1>;
197 };
199 i2c1: i2c@48070000 {
200 compatible = "ti,omap4-i2c";
201 reg = <0x48070000 0x100>;
202 interrupts = <0 56 0x4>;
203 #address-cells = <1>;
204 #size-cells = <0>;
205 ti,hwmods = "i2c1";
206 };
208 i2c2: i2c@48072000 {
209 compatible = "ti,omap4-i2c";
210 reg = <0x48072000 0x100>;
211 interrupts = <0 57 0x4>;
212 #address-cells = <1>;
213 #size-cells = <0>;
214 ti,hwmods = "i2c2";
215 };
217 i2c3: i2c@48060000 {
218 compatible = "ti,omap4-i2c";
219 reg = <0x48060000 0x100>;
220 interrupts = <0 61 0x4>;
221 #address-cells = <1>;
222 #size-cells = <0>;
223 ti,hwmods = "i2c3";
224 };
226 i2c4: i2c@4807a000 {
227 compatible = "ti,omap4-i2c";
228 reg = <0x4807a000 0x100>;
229 interrupts = <0 62 0x4>;
230 #address-cells = <1>;
231 #size-cells = <0>;
232 ti,hwmods = "i2c4";
233 };
235 i2c5: i2c@4807c000 {
236 compatible = "ti,omap4-i2c";
237 reg = <0x4807c000 0x100>;
238 interrupts = <0 60 0x4>;
239 #address-cells = <1>;
240 #size-cells = <0>;
241 ti,hwmods = "i2c5";
242 };
244 uart1: serial@4806a000 {
245 compatible = "ti,omap4-uart";
246 reg = <0x4806a000 0x100>;
247 interrupts = <0 72 0x4>;
248 ti,hwmods = "uart1";
249 clock-frequency = <48000000>;
250 };
252 uart2: serial@4806c000 {
253 compatible = "ti,omap4-uart";
254 reg = <0x4806c000 0x100>;
255 interrupts = <0 73 0x4>;
256 ti,hwmods = "uart2";
257 clock-frequency = <48000000>;
258 };
260 uart3: serial@48020000 {
261 compatible = "ti,omap4-uart";
262 reg = <0x48020000 0x100>;
263 interrupts = <0 74 0x4>;
264 ti,hwmods = "uart3";
265 clock-frequency = <48000000>;
266 };
268 uart4: serial@4806e000 {
269 compatible = "ti,omap4-uart";
270 reg = <0x4806e000 0x100>;
271 interrupts = <0 70 0x4>;
272 ti,hwmods = "uart4";
273 clock-frequency = <48000000>;
274 };
276 uart5: serial@48066000 {
277 compatible = "ti,omap4-uart";
278 reg = <0x48066000 0x100>;
279 interrupts = <0 105 0x4>;
280 ti,hwmods = "uart5";
281 clock-frequency = <48000000>;
282 };
284 uart6: serial@48068000 {
285 compatible = "ti,omap4-uart";
286 reg = <0x48068000 0x100>;
287 interrupts = <0 106 0x4>;
288 ti,hwmods = "uart6";
289 clock-frequency = <48000000>;
290 };
292 mmc1: mmc@4809c000 {
293 compatible = "ti,omap4-hsmmc";
294 reg = <0x4809c000 0x400>;
295 interrupts = <0 83 0x4>;
296 ti,hwmods = "mmc1";
297 ti,dual-volt;
298 ti,needs-special-reset;
299 };
301 mmc2: mmc@480b4000 {
302 compatible = "ti,omap4-hsmmc";
303 reg = <0x480b4000 0x400>;
304 interrupts = <0 86 0x4>;
305 ti,hwmods = "mmc2";
306 ti,needs-special-reset;
307 };
309 mmc3: mmc@480ad000 {
310 compatible = "ti,omap4-hsmmc";
311 reg = <0x480ad000 0x400>;
312 interrupts = <0 94 0x4>;
313 ti,hwmods = "mmc3";
314 ti,needs-special-reset;
315 };
317 mmc4: mmc@480d1000 {
318 compatible = "ti,omap4-hsmmc";
319 reg = <0x480d1000 0x400>;
320 interrupts = <0 96 0x4>;
321 ti,hwmods = "mmc4";
322 ti,needs-special-reset;
323 };
325 mmc5: mmc@480d5000 {
326 compatible = "ti,omap4-hsmmc";
327 reg = <0x480d5000 0x400>;
328 interrupts = <0 59 0x4>;
329 ti,hwmods = "mmc5";
330 ti,needs-special-reset;
331 };
333 keypad: keypad@4ae1c000 {
334 compatible = "ti,omap4-keypad";
335 ti,hwmods = "kbd";
336 };
338 mcpdm: mcpdm@40132000 {
339 compatible = "ti,omap4-mcpdm";
340 reg = <0x40132000 0x7f>, /* MPU private access */
341 <0x49032000 0x7f>; /* L3 Interconnect */
342 reg-names = "mpu", "dma";
343 interrupts = <0 112 0x4>;
344 ti,hwmods = "mcpdm";
345 };
347 dmic: dmic@4012e000 {
348 compatible = "ti,omap4-dmic";
349 reg = <0x4012e000 0x7f>, /* MPU private access */
350 <0x4902e000 0x7f>; /* L3 Interconnect */
351 reg-names = "mpu", "dma";
352 interrupts = <0 114 0x4>;
353 ti,hwmods = "dmic";
354 };
356 mcbsp1: mcbsp@40122000 {
357 compatible = "ti,omap4-mcbsp";
358 reg = <0x40122000 0xff>, /* MPU private access */
359 <0x49022000 0xff>; /* L3 Interconnect */
360 reg-names = "mpu", "dma";
361 interrupts = <0 17 0x4>;
362 interrupt-names = "common";
363 ti,buffer-size = <128>;
364 ti,hwmods = "mcbsp1";
365 };
367 mcbsp2: mcbsp@40124000 {
368 compatible = "ti,omap4-mcbsp";
369 reg = <0x40124000 0xff>, /* MPU private access */
370 <0x49024000 0xff>; /* L3 Interconnect */
371 reg-names = "mpu", "dma";
372 interrupts = <0 22 0x4>;
373 interrupt-names = "common";
374 ti,buffer-size = <128>;
375 ti,hwmods = "mcbsp2";
376 };
378 mcbsp3: mcbsp@40126000 {
379 compatible = "ti,omap4-mcbsp";
380 reg = <0x40126000 0xff>, /* MPU private access */
381 <0x49026000 0xff>; /* L3 Interconnect */
382 reg-names = "mpu", "dma";
383 interrupts = <0 23 0x4>;
384 interrupt-names = "common";
385 ti,buffer-size = <128>;
386 ti,hwmods = "mcbsp3";
387 };
389 timer1: timer@4ae18000 {
390 compatible = "ti,omap2-timer";
391 reg = <0x4ae18000 0x80>;
392 interrupts = <0 37 0x4>;
393 ti,hwmods = "timer1";
394 ti,timer-alwon;
395 };
397 timer2: timer@48032000 {
398 compatible = "ti,omap2-timer";
399 reg = <0x48032000 0x80>;
400 interrupts = <0 38 0x4>;
401 ti,hwmods = "timer2";
402 };
404 timer3: timer@48034000 {
405 compatible = "ti,omap2-timer";
406 reg = <0x48034000 0x80>;
407 interrupts = <0 39 0x4>;
408 ti,hwmods = "timer3";
409 };
411 timer4: timer@48036000 {
412 compatible = "ti,omap2-timer";
413 reg = <0x48036000 0x80>;
414 interrupts = <0 40 0x4>;
415 ti,hwmods = "timer4";
416 };
418 timer5: timer@40138000 {
419 compatible = "ti,omap2-timer";
420 reg = <0x40138000 0x80>,
421 <0x49038000 0x80>;
422 interrupts = <0 41 0x4>;
423 ti,hwmods = "timer5";
424 ti,timer-dsp;
425 };
427 timer6: timer@4013a000 {
428 compatible = "ti,omap2-timer";
429 reg = <0x4013a000 0x80>,
430 <0x4903a000 0x80>;
431 interrupts = <0 42 0x4>;
432 ti,hwmods = "timer6";
433 ti,timer-dsp;
434 ti,timer-pwm;
435 };
437 timer7: timer@4013c000 {
438 compatible = "ti,omap2-timer";
439 reg = <0x4013c000 0x80>,
440 <0x4903c000 0x80>;
441 interrupts = <0 43 0x4>;
442 ti,hwmods = "timer7";
443 ti,timer-dsp;
444 };
446 timer8: timer@4013e000 {
447 compatible = "ti,omap2-timer";
448 reg = <0x4013e000 0x80>,
449 <0x4903e000 0x80>;
450 interrupts = <0 44 0x4>;
451 ti,hwmods = "timer8";
452 ti,timer-dsp;
453 ti,timer-pwm;
454 };
456 timer9: timer@4803e000 {
457 compatible = "ti,omap2-timer";
458 reg = <0x4803e000 0x80>;
459 interrupts = <0 45 0x4>;
460 ti,hwmods = "timer9";
461 };
463 timer10: timer@48086000 {
464 compatible = "ti,omap2-timer";
465 reg = <0x48086000 0x80>;
466 interrupts = <0 46 0x4>;
467 ti,hwmods = "timer10";
468 };
470 timer11: timer@48088000 {
471 compatible = "ti,omap2-timer";
472 reg = <0x48088000 0x80>;
473 interrupts = <0 47 0x4>;
474 ti,hwmods = "timer11";
475 ti,timer-pwm;
476 };
478 emif1: emif@0x4c000000 {
479 compatible = "ti,emif-4d5";
480 ti,hwmods = "emif1";
481 phy-type = <2>; /* DDR PHY type: Intelli PHY */
482 reg = <0x4c000000 0x400>;
483 interrupts = <0 110 0x4>;
484 hw-caps-read-idle-ctrl;
485 hw-caps-ll-interface;
486 hw-caps-temp-alert;
487 };
489 emif2: emif@0x4d000000 {
490 compatible = "ti,emif-4d5";
491 ti,hwmods = "emif2";
492 phy-type = <2>; /* DDR PHY type: Intelli PHY */
493 reg = <0x4d000000 0x400>;
494 interrupts = <0 111 0x4>;
495 hw-caps-read-idle-ctrl;
496 hw-caps-ll-interface;
497 hw-caps-temp-alert;
498 };
499 };
500 };