arch/x86/power/cpu.c

   1 /*
   2  * Suspend support specific for i386/x86-64.
   3  *
   4  * Distribute under GPLv2
   5  *
   6  * Copyright (c) 2007 Rafael J. Wysocki <rjw@sisk.pl>
   7  * Copyright (c) 2002 Pavel Machek <pavel@suse.cz>
   8  * Copyright (c) 2001 Patrick Mochel <mochel@osdl.org>
   9  */
  10
  11 #include <linux/suspend.h>
  12 #include <linux/smp.h>
  13
  14 #include <asm/pgtable.h>
  15 #include <asm/proto.h>
  16 #include <asm/mtrr.h>
  17 #include <asm/page.h>
  18 #include <asm/mce.h>
  19 #include <asm/xcr.h>
  20 #include <asm/suspend.h>
  21
  22 #ifdef CONFIG_X86_32
  23 static struct saved_context saved_context;
  24
  25 unsigned long saved_context_ebx;
  26 unsigned long saved_context_esp, saved_context_ebp;
  27 unsigned long saved_context_esi, saved_context_edi;
  28 unsigned long saved_context_eflags;
  29 #else
  30 /* CONFIG_X86_64 */
  31 struct saved_context saved_context;
  32 #endif
  33
  34 /**
  35  *      __save_processor_state - save CPU registers before creating a
  36  *              hibernation image and before restoring the memory state from it
  37  *      @ctxt - structure to store the registers contents in
  38  *
  39  *      NOTE: If there is a CPU register the modification of which by the
  40  *      boot kernel (ie. the kernel used for loading the hibernation image)
  41  *      might affect the operations of the restored target kernel (ie. the one
  42  *      saved in the hibernation image), then its contents must be saved by this
  43  *      function.  In other words, if kernel A is hibernated and different
  44  *      kernel B is used for loading the hibernation image into memory, the
  45  *      kernel A's __save_processor_state() function must save all registers
  46  *      needed by kernel A, so that it can operate correctly after the resume
  47  *      regardless of what kernel B does in the meantime.
  48  */
  49 static void __save_processor_state(struct saved_context *ctxt)
  50 {
  51 #ifdef CONFIG_X86_32
  52         mtrr_save_fixed_ranges(NULL);
  53 #endif
  54         kernel_fpu_begin();
  55
  56         /*
  57          * descriptor tables
  58          */
  59 #ifdef CONFIG_X86_32
  60         store_gdt(&ctxt->gdt);
  61         store_idt(&ctxt->idt);
  62 #else
  63 /* CONFIG_X86_64 */
  64         store_gdt((struct desc_ptr *)&ctxt->gdt_limit);
  65         store_idt((struct desc_ptr *)&ctxt->idt_limit);
  66 #endif
  67         store_tr(ctxt->tr);
  68
  69         /* XMM0..XMM15 should be handled by kernel_fpu_begin(). */
  70         /*
  71          * segment registers
  72          */
  73 #ifdef CONFIG_X86_32
  74         savesegment(es, ctxt->es);
  75         savesegment(fs, ctxt->fs);
  76         savesegment(gs, ctxt->gs);
  77         savesegment(ss, ctxt->ss);
  78 #else
  79 /* CONFIG_X86_64 */
  80         asm volatile ("movw %%ds, %0" : "=m" (ctxt->ds));
  81         asm volatile ("movw %%es, %0" : "=m" (ctxt->es));
  82         asm volatile ("movw %%fs, %0" : "=m" (ctxt->fs));
  83         asm volatile ("movw %%gs, %0" : "=m" (ctxt->gs));
  84         asm volatile ("movw %%ss, %0" : "=m" (ctxt->ss));
  85
  86         rdmsrl(MSR_FS_BASE, ctxt->fs_base);
  87         rdmsrl(MSR_GS_BASE, ctxt->gs_base);
  88         rdmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
  89         mtrr_save_fixed_ranges(NULL);
  90
  91         rdmsrl(MSR_EFER, ctxt->efer);
  92 #endif
  93
  94         /*
  95          * control registers
  96          */
  97         ctxt->cr0 = read_cr0();
  98         ctxt->cr2 = read_cr2();
  99         ctxt->cr3 = read_cr3();
 100 #ifdef CONFIG_X86_32
 101         ctxt->cr4 = read_cr4_safe();
 102 #else
 103 /* CONFIG_X86_64 */
 104         ctxt->cr4 = read_cr4();
 105         ctxt->cr8 = read_cr8();
 106 #endif
 107         ctxt->misc_enable_saved = !rdmsrl_safe(MSR_IA32_MISC_ENABLE,
 108                                                &ctxt->misc_enable);
 109 }
 110
 111 /* Needed by apm.c */
 112 void save_processor_state(void)
 113 {
 114         __save_processor_state(&saved_context);
 115         save_sched_clock_state();
 116 }
 117 #ifdef CONFIG_X86_32
 118 EXPORT_SYMBOL(save_processor_state);
 119 #endif
 120
 121 static void do_fpu_end(void)
 122 {
 123         /*
 124          * Restore FPU regs if necessary.
 125          */
 126         kernel_fpu_end();
 127 }
 128
 129 static void fix_processor_context(void)
 130 {
 131         int cpu = smp_processor_id();
 132         struct tss_struct *t = &per_cpu(init_tss, cpu);
 133
 134         set_tss_desc(cpu, t);   /*
 135                                  * This just modifies memory; should not be
 136                                  * necessary. But... This is necessary, because
 137                                  * 386 hardware has concept of busy TSS or some
 138                                  * similar stupidity.
 139                                  */
 140
 141 #ifdef CONFIG_X86_64
 142         get_cpu_gdt_table(cpu)[GDT_ENTRY_TSS].type = 9;
 143
 144         syscall_init();                         /* This sets MSR_*STAR and related */
 145 #endif
 146         load_TR_desc();                         /* This does ltr */
 147         load_LDT(&current->active_mm->context); /* This does lldt */
 148
 149         /*
 150          * Now maybe reload the debug registers
 151          */
 152         if (current->thread.debugreg7) {
 153 #ifdef CONFIG_X86_32
 154                 set_debugreg(current->thread.debugreg0, 0);
 155                 set_debugreg(current->thread.debugreg1, 1);
 156                 set_debugreg(current->thread.debugreg2, 2);
 157                 set_debugreg(current->thread.debugreg3, 3);
 158                 /* no 4 and 5 */
 159                 set_debugreg(current->thread.debugreg6, 6);
 160                 set_debugreg(current->thread.debugreg7, 7);
 161 #else
 162                 /* CONFIG_X86_64 */
 163                 loaddebug(&current->thread, 0);
 164                 loaddebug(&current->thread, 1);
 165                 loaddebug(&current->thread, 2);
 166                 loaddebug(&current->thread, 3);
 167                 /* no 4 and 5 */
 168                 loaddebug(&current->thread, 6);
 169                 loaddebug(&current->thread, 7);
 170 #endif
 171         }
 172
 173 }
 174
 175 /**
 176  *      __restore_processor_state - restore the contents of CPU registers saved
 177  *              by __save_processor_state()
 178  *      @ctxt - structure to load the registers contents from
 179  */
 180 static void __restore_processor_state(struct saved_context *ctxt)
 181 {
 182         if (ctxt->misc_enable_saved)
 183                 wrmsrl(MSR_IA32_MISC_ENABLE, ctxt->misc_enable);
 184         /*
 185          * control registers
 186          */
 187         /* cr4 was introduced in the Pentium CPU */
 188 #ifdef CONFIG_X86_32
 189         if (ctxt->cr4)
 190                 write_cr4(ctxt->cr4);
 191 #else
 192 /* CONFIG X86_64 */
 193         wrmsrl(MSR_EFER, ctxt->efer);
 194         write_cr8(ctxt->cr8);
 195         write_cr4(ctxt->cr4);
 196 #endif
 197         write_cr3(ctxt->cr3);
 198         write_cr2(ctxt->cr2);
 199         write_cr0(ctxt->cr0);
 200
 201         /*
 202          * now restore the descriptor tables to their proper values
 203          * ltr is done i fix_processor_context().
 204          */
 205 #ifdef CONFIG_X86_32
 206         load_gdt(&ctxt->gdt);
 207         load_idt(&ctxt->idt);
 208 #else
 209 /* CONFIG_X86_64 */
 210         load_gdt((const struct desc_ptr *)&ctxt->gdt_limit);
 211         load_idt((const struct desc_ptr *)&ctxt->idt_limit);
 212 #endif
 213
 214         /*
 215          * segment registers
 216          */
 217 #ifdef CONFIG_X86_32
 218         loadsegment(es, ctxt->es);
 219         loadsegment(fs, ctxt->fs);
 220         loadsegment(gs, ctxt->gs);
 221         loadsegment(ss, ctxt->ss);
 222
 223         /*
 224          * sysenter MSRs
 225          */
 226         if (boot_cpu_has(X86_FEATURE_SEP))
 227                 enable_sep_cpu();
 228 #else
 229 /* CONFIG_X86_64 */
 230         asm volatile ("movw %0, %%ds" :: "r" (ctxt->ds));
 231         asm volatile ("movw %0, %%es" :: "r" (ctxt->es));
 232         asm volatile ("movw %0, %%fs" :: "r" (ctxt->fs));
 233         load_gs_index(ctxt->gs);
 234         asm volatile ("movw %0, %%ss" :: "r" (ctxt->ss));
 235
 236         wrmsrl(MSR_FS_BASE, ctxt->fs_base);
 237         wrmsrl(MSR_GS_BASE, ctxt->gs_base);
 238         wrmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
 239 #endif
 240
 241         /*
 242          * restore XCR0 for xsave capable cpu's.
 243          */
 244         if (cpu_has_xsave)
 245                 xsetbv(XCR_XFEATURE_ENABLED_MASK, pcntxt_mask);
 246
 247         fix_processor_context();
 248
 249         do_fpu_end();
 250         mtrr_bp_restore();
 251 }
 252
 253 /* Needed by apm.c */
 254 void restore_processor_state(void)
 255 {
 256         __restore_processor_state(&saved_context);
 257         restore_sched_clock_state();
 258 }
 259 #ifdef CONFIG_X86_32
 260 EXPORT_SYMBOL(restore_processor_state);
 261 #endif