drivers/gpu/drm/msm/msm_gpu.h

   1 /*
   2  * Copyright (C) 2013 Red Hat
   3  * Author: Rob Clark <robdclark@gmail.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #ifndef __MSM_GPU_H__
  19 #define __MSM_GPU_H__
  20
  21 #include <linux/clk.h>
  22 #include <linux/regulator/consumer.h>
  23
  24 #include "msm_drv.h"
  25 #include "msm_fence.h"
  26 #include "msm_ringbuffer.h"
  27
  28 struct msm_gem_submit;
  29 struct msm_gpu_perfcntr;
  30
  31 struct msm_gpu_config {
  32         const char *ioname;
  33         const char *irqname;
  34         uint64_t va_start;
  35         uint64_t va_end;
  36         unsigned int nr_rings;
  37 };
  38
  39 /* So far, with hardware that I've seen to date, we can have:
  40  *  + zero, one, or two z180 2d cores
  41  *  + a3xx or a2xx 3d core, which share a common CP (the firmware
  42  *    for the CP seems to implement some different PM4 packet types
  43  *    but the basics of cmdstream submission are the same)
  44  *
  45  * Which means that the eventual complete "class" hierarchy, once
  46  * support for all past and present hw is in place, becomes:
  47  *  + msm_gpu
  48  *    + adreno_gpu
  49  *      + a3xx_gpu
  50  *      + a2xx_gpu
  51  *    + z180_gpu
  52  */
  53 struct msm_gpu_funcs {
  54         int (*get_param)(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
  55         int (*hw_init)(struct msm_gpu *gpu);
  56         int (*pm_suspend)(struct msm_gpu *gpu);
  57         int (*pm_resume)(struct msm_gpu *gpu);
  58         void (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit,
  59                         struct msm_file_private *ctx);
  60         void (*flush)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
  61         irqreturn_t (*irq)(struct msm_gpu *irq);
  62         struct msm_ringbuffer *(*active_ring)(struct msm_gpu *gpu);
  63         void (*recover)(struct msm_gpu *gpu);
  64         void (*destroy)(struct msm_gpu *gpu);
  65 #ifdef CONFIG_DEBUG_FS
  66         /* show GPU status in debugfs: */
  67         void (*show)(struct msm_gpu *gpu, struct seq_file *m);
  68 #endif
  69         int (*gpu_busy)(struct msm_gpu *gpu, uint64_t *value);
  70 };
  71
  72 struct msm_gpu {
  73         const char *name;
  74         struct drm_device *dev;
  75         struct platform_device *pdev;
  76         const struct msm_gpu_funcs *funcs;
  77
  78         /* performance counters (hw & sw): */
  79         spinlock_t perf_lock;
  80         bool perfcntr_active;
  81         struct {
  82                 bool active;
  83                 ktime_t time;
  84         } last_sample;
  85         uint32_t totaltime, activetime;    /* sw counters */
  86         uint32_t last_cntrs[5];            /* hw counters */
  87         const struct msm_gpu_perfcntr *perfcntrs;
  88         uint32_t num_perfcntrs;
  89
  90         struct msm_ringbuffer *rb[MSM_GPU_MAX_RINGS];
  91         int nr_rings;
  92
  93         /* list of GEM active objects: */
  94         struct list_head active_list;
  95
  96         /* does gpu need hw_init? */
  97         bool needs_hw_init;
  98
  99         /* worker for handling active-list retiring: */
 100         struct work_struct retire_work;
 101
 102         void __iomem *mmio;
 103         int irq;
 104
 105         struct msm_gem_address_space *aspace;
 106
 107         /* Power Control: */
 108         struct regulator *gpu_reg, *gpu_cx;
 109         struct clk **grp_clks;
 110         int nr_clocks;
 111         struct clk *ebi1_clk, *core_clk, *rbbmtimer_clk;
 112         uint32_t fast_rate;
 113
 114         /* Hang and Inactivity Detection:
 115          */
 116 #define DRM_MSM_INACTIVE_PERIOD   66 /* in ms (roughly four frames) */
 117
 118 #define DRM_MSM_HANGCHECK_PERIOD 500 /* in ms */
 119 #define DRM_MSM_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_MSM_HANGCHECK_PERIOD)
 120         struct timer_list hangcheck_timer;
 121         struct work_struct recover_work;
 122
 123         struct drm_gem_object *memptrs_bo;
 124
 125         struct {
 126                 struct devfreq *devfreq;
 127                 u64 busy_cycles;
 128                 ktime_t time;
 129         } devfreq;
 130 };
 131
 132 /* It turns out that all targets use the same ringbuffer size */
 133 #define MSM_GPU_RINGBUFFER_SZ SZ_32K
 134 #define MSM_GPU_RINGBUFFER_BLKSIZE 32
 135
 136 #define MSM_GPU_RB_CNTL_DEFAULT \
 137                 (AXXX_CP_RB_CNTL_BUFSZ(ilog2(MSM_GPU_RINGBUFFER_SZ / 8)) | \
 138                 AXXX_CP_RB_CNTL_BLKSZ(ilog2(MSM_GPU_RINGBUFFER_BLKSIZE / 8)))
 139
 140 static inline bool msm_gpu_active(struct msm_gpu *gpu)
 141 {
 142         int i;
 143
 144         for (i = 0; i < gpu->nr_rings; i++) {
 145                 struct msm_ringbuffer *ring = gpu->rb[i];
 146
 147                 if (ring->seqno > ring->memptrs->fence)
 148                         return true;
 149         }
 150
 151         return false;
 152 }
 153
 154 /* Perf-Counters:
 155  * The select_reg and select_val are just there for the benefit of the child
 156  * class that actually enables the perf counter..  but msm_gpu base class
 157  * will handle sampling/displaying the counters.
 158  */
 159
 160 struct msm_gpu_perfcntr {
 161         uint32_t select_reg;
 162         uint32_t sample_reg;
 163         uint32_t select_val;
 164         const char *name;
 165 };
 166
 167 struct msm_gpu_submitqueue {
 168         int id;
 169         u32 flags;
 170         u32 prio;
 171         int faults;
 172         struct list_head node;
 173         struct kref ref;
 174 };
 175
 176 static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data)
 177 {
 178         msm_writel(data, gpu->mmio + (reg << 2));
 179 }
 180
 181 static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg)
 182 {
 183         return msm_readl(gpu->mmio + (reg << 2));
 184 }
 185
 186 static inline void gpu_rmw(struct msm_gpu *gpu, u32 reg, u32 mask, u32 or)
 187 {
 188         uint32_t val = gpu_read(gpu, reg);
 189
 190         val &= ~mask;
 191         gpu_write(gpu, reg, val | or);
 192 }
 193
 194 static inline u64 gpu_read64(struct msm_gpu *gpu, u32 lo, u32 hi)
 195 {
 196         u64 val;
 197
 198         /*
 199          * Why not a readq here? Two reasons: 1) many of the LO registers are
 200          * not quad word aligned and 2) the GPU hardware designers have a bit
 201          * of a history of putting registers where they fit, especially in
 202          * spins. The longer a GPU family goes the higher the chance that
 203          * we'll get burned.  We could do a series of validity checks if we
 204          * wanted to, but really is a readq() that much better? Nah.
 205          */
 206
 207         /*
 208          * For some lo/hi registers (like perfcounters), the hi value is latched
 209          * when the lo is read, so make sure to read the lo first to trigger
 210          * that
 211          */
 212         val = (u64) msm_readl(gpu->mmio + (lo << 2));
 213         val |= ((u64) msm_readl(gpu->mmio + (hi << 2)) << 32);
 214
 215         return val;
 216 }
 217
 218 static inline void gpu_write64(struct msm_gpu *gpu, u32 lo, u32 hi, u64 val)
 219 {
 220         /* Why not a writeq here? Read the screed above */
 221         msm_writel(lower_32_bits(val), gpu->mmio + (lo << 2));
 222         msm_writel(upper_32_bits(val), gpu->mmio + (hi << 2));
 223 }
 224
 225 int msm_gpu_pm_suspend(struct msm_gpu *gpu);
 226 int msm_gpu_pm_resume(struct msm_gpu *gpu);
 227
 228 int msm_gpu_hw_init(struct msm_gpu *gpu);
 229
 230 void msm_gpu_perfcntr_start(struct msm_gpu *gpu);
 231 void msm_gpu_perfcntr_stop(struct msm_gpu *gpu);
 232 int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime,
 233                 uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs);
 234
 235 void msm_gpu_retire(struct msm_gpu *gpu);
 236 void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
 237                 struct msm_file_private *ctx);
 238
 239 int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
 240                 struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
 241                 const char *name, struct msm_gpu_config *config);
 242
 243 void msm_gpu_cleanup(struct msm_gpu *gpu);
 244
 245 struct msm_gpu *adreno_load_gpu(struct drm_device *dev);
 246 void __init adreno_register(void);
 247 void __exit adreno_unregister(void);
 248
 249 static inline void msm_submitqueue_put(struct msm_gpu_submitqueue *queue)
 250 {
 251         if (queue)
 252                 kref_put(&queue->ref, msm_submitqueue_destroy);
 253 }
 254
 255 #endif /* __MSM_GPU_H__ */