| blob | 7cb3ef466cc7799eea7a9e7cb85465d40b5619e8 |
1 /*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
35 #include <linux/delay.h>
42 /**
43 * t4_wait_op_done_val - wait until an operation is completed
44 * @adapter: the adapter performing the operation
45 * @reg: the register to check for completion
46 * @mask: a single-bit field within @reg that indicates completion
47 * @polarity: the value of the field when the operation is completed
48 * @attempts: number of check iterations
49 * @delay: delay in usecs between iterations
50 * @valp: where to store the value of the register at completion time
51 *
52 * Wait until an operation is completed by checking a bit in a register
53 * up to @attempts times. If @valp is not NULL the value of the register
54 * at the time it indicated completion is stored there. Returns 0 if the
55 * operation completes and -EAGAIN otherwise.
56 */
59 {
67 }
72 }
73 }
77 {
80 }
82 /**
83 * t4_set_reg_field - set a register field to a value
84 * @adapter: the adapter to program
85 * @addr: the register address
86 * @mask: specifies the portion of the register to modify
87 * @val: the new value for the register field
88 *
89 * Sets a register field specified by the supplied mask to the
90 * given value.
91 */
93 u32 val)
94 {
99 }
101 /**
102 * t4_read_indirect - read indirectly addressed registers
103 * @adap: the adapter
104 * @addr_reg: register holding the indirect address
105 * @data_reg: register holding the value of the indirect register
106 * @vals: where the read register values are stored
107 * @nregs: how many indirect registers to read
108 * @start_idx: index of first indirect register to read
109 *
110 * Reads registers that are accessed indirectly through an address/data
111 * register pair.
112 */
116 {
120 start_idx++;
121 }
122 }
124 /**
125 * t4_write_indirect - write indirectly addressed registers
126 * @adap: the adapter
127 * @addr_reg: register holding the indirect addresses
128 * @data_reg: register holding the value for the indirect registers
129 * @vals: values to write
130 * @nregs: how many indirect registers to write
131 * @start_idx: address of first indirect register to write
132 *
133 * Writes a sequential block of registers that are accessed indirectly
134 * through an address/data register pair.
135 */
139 {
143 }
144 }
146 /*
147 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
148 * mechanism. This guarantees that we get the real value even if we're
149 * operating within a Virtual Machine and the Hypervisor is trapping our
150 * Configuration Space accesses.
151 */
153 {
158 else
167 /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
168 * Configuration Space read. (None of the other fields matter when
169 * ENABLE is 0 so a simple register write is easier than a
170 * read-modify-write via t4_set_reg_field().)
171 */
173 }
175 /*
176 * t4_report_fw_error - report firmware error
177 * @adap: the adapter
178 *
179 * The adapter firmware can indicate error conditions to the host.
180 * If the firmware has indicated an error, print out the reason for
181 * the firmware error.
182 */
184 {
194 };
195 u32 pcie_fw;
202 }
203 }
205 /*
206 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
207 */
209 u32 mbox_addr)
210 {
213 }
215 /*
216 * Handle a FW assertion reported in a mailbox.
217 */
219 {
227 }
229 /**
230 * t4_record_mbox - record a Firmware Mailbox Command/Reply in the log
231 * @adapter: the adapter
232 * @cmd: the Firmware Mailbox Command or Reply
233 * @size: command length in bytes
234 * @access: the time (ms) needed to access the Firmware Mailbox
235 * @execute: the time (ms) the command spent being executed
236 */
240 {
257 }
259 /**
260 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
261 * @adap: the adapter
262 * @mbox: index of the mailbox to use
263 * @cmd: the command to write
264 * @size: command length in bytes
265 * @rpl: where to optionally store the reply
266 * @sleep_ok: if true we may sleep while awaiting command completion
267 * @timeout: time to wait for command to finish before timing out
268 *
269 * Sends the given command to FW through the selected mailbox and waits
270 * for the FW to execute the command. If @rpl is not %NULL it is used to
271 * store the FW's reply to the command. The command and its optional
272 * reply are of the same length. FW can take up to %FW_CMD_MAX_TIMEOUT ms
273 * to respond. @sleep_ok determines whether we may sleep while awaiting
274 * the response. If sleeping is allowed we use progressive backoff
275 * otherwise we spin.
276 *
277 * The return value is 0 on success or a negative errno on failure. A
278 * failure can happen either because we are not able to execute the
279 * command or FW executes it but signals an error. In the latter case
280 * the return value is the error code indicated by FW (negated).
281 */
284 {
287 };
292 u32 v;
293 u64 res;
299 u32 pcie_fw;
304 /*
305 * If the device is off-line, as in EEH, commands will time out.
306 * Fail them early so we don't waste time waiting.
307 */
311 /* If we have a negative timeout, that implies that we can't sleep. */
315 }
317 /* Queue ourselves onto the mailbox access list. When our entry is at
318 * the front of the list, we have rights to access the mailbox. So we
319 * wait [for a while] till we're at the front [or bail out with an
320 * EBUSY] ...
321 */
330 /* If we've waited too long, return a busy indication. This
331 * really ought to be based on our initial position in the
332 * mailbox access list but this is a start. We very rearely
333 * contend on access to the mailbox ...
334 */
343 }
345 /* If we're at the head, break out and start the mailbox
346 * protocol.
347 */
352 /* Delay for a bit before checking again ... */
356 delay_idx++;
360 }
361 }
363 /* Loop trying to get ownership of the mailbox. Return an error
364 * if we can't gain ownership.
365 */
376 }
378 /* Copy in the new mailbox command and send it on its way ... */
396 delay_idx++;
406 }
416 }
427 }
428 }
440 }
444 {
446 FW_CMD_MAX_TIMEOUT);
447 }
450 {
451 u32 edc_ecc_err_addr_reg;
452 u32 rdata_reg;
457 }
461 }
472 rdata_reg,
484 }
486 /**
487 * t4_memory_rw_init - Get memory window relative offset, base, and size.
488 * @adap: the adapter
489 * @win: PCI-E Memory Window to use
490 * @mtype: memory type: MEM_EDC0, MEM_EDC1, MEM_HMA or MEM_MC
491 * @mem_off: memory relative offset with respect to @mtype.
492 * @mem_base: configured memory base address.
493 * @mem_aperture: configured memory window aperture.
494 *
495 * Get the configured memory window's relative offset, base, and size.
496 */
499 {
502 /* Offset into the region of memory which is being accessed
503 * MEM_EDC0 = 0
504 * MEM_EDC1 = 1
505 * MEM_MC = 2 -- MEM_MC for chips with only 1 memory controller
506 * MEM_MC1 = 3 -- for chips with 2 memory controllers (e.g. T5)
507 * MEM_HMA = 4
508 */
516 MA_EXT_MEMORY0_BAR_A));
518 }
520 /* Each PCI-E Memory Window is programmed with a window size -- or
521 * "aperture" -- which controls the granularity of its mapping onto
522 * adapter memory. We need to grab that aperture in order to know
523 * how to use the specified window. The window is also programmed
524 * with the base address of the Memory Window in BAR0's address
525 * space. For T4 this is an absolute PCI-E Bus Address. For T5
526 * the address is relative to BAR0.
527 */
530 win));
531 /* a dead adapter will return 0xffffffff for PIO reads */
541 }
543 /**
544 * t4_memory_update_win - Move memory window to specified address.
545 * @adap: the adapter
546 * @win: PCI-E Memory Window to use
547 * @addr: location to move.
548 *
549 * Move memory window to specified address.
550 */
552 {
555 addr);
556 /* Read it back to ensure that changes propagate before we
557 * attempt to use the new value.
558 */
561 }
563 /**
564 * t4_memory_rw_residual - Read/Write residual data.
565 * @adap: the adapter
566 * @off: relative offset within residual to start read/write.
567 * @addr: address within indicated memory type.
568 * @buf: host memory buffer
569 * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
570 *
571 * Read/Write residual data less than 32-bits.
572 */
575 {
577 u32 word;
594 }
595 }
597 /**
598 * t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
599 * @adap: the adapter
600 * @win: PCI-E Memory Window to use
601 * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
602 * @addr: address within indicated memory type
603 * @len: amount of memory to transfer
604 * @hbuf: host memory buffer
605 * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
606 *
607 * Reads/writes an [almost] arbitrary memory region in the firmware: the
608 * firmware memory address and host buffer must be aligned on 32-bit
609 * boudaries; the length may be arbitrary. The memory is transferred as
610 * a raw byte sequence from/to the firmware's memory. If this memory
611 * contains data structures which contain multi-byte integers, it's the
612 * caller's responsibility to perform appropriate byte order conversions.
613 */
616 {
622 /* Argument sanity checks ...
623 */
628 /* It's convenient to be able to handle lengths which aren't a
629 * multiple of 32-bits because we often end up transferring files to
630 * the firmware. So we'll handle that by normalizing the length here
631 * and then handling any residual transfer at the end.
632 */
641 /* Determine the PCIE_MEM_ACCESS_OFFSET */
646 /* Calculate our initial PCI-E Memory Window Position and Offset into
647 * that Window.
648 */
652 /* Set up initial PCI-E Memory Window to cover the start of our
653 * transfer.
654 */
657 /* Transfer data to/from the adapter as long as there's an integral
658 * number of 32-bit transfers to complete.
659 *
660 * A note on Endianness issues:
661 *
662 * The "register" reads and writes below from/to the PCI-E Memory
663 * Window invoke the standard adapter Big-Endian to PCI-E Link
664 * Little-Endian "swizzel." As a result, if we have the following
665 * data in adapter memory:
666 *
667 * Memory: ... | b0 | b1 | b2 | b3 | ...
668 * Address: i+0 i+1 i+2 i+3
669 *
670 * Then a read of the adapter memory via the PCI-E Memory Window
671 * will yield:
672 *
673 * x = readl(i)
674 * 31 0
675 * [ b3 | b2 | b1 | b0 ]
676 *
677 * If this value is stored into local memory on a Little-Endian system
678 * it will show up correctly in local memory as:
679 *
680 * ( ..., b0, b1, b2, b3, ... )
681 *
682 * But on a Big-Endian system, the store will show up in memory
683 * incorrectly swizzled as:
684 *
685 * ( ..., b3, b2, b1, b0, ... )
686 *
687 * So we need to account for this in the reads and writes to the
688 * PCI-E Memory Window below by undoing the register read/write
689 * swizzels.
690 */
695 else
701 /* If we've reached the end of our current window aperture,
702 * move the PCI-E Memory Window on to the next. Note that
703 * doing this here after "len" may be 0 allows us to set up
704 * the PCI-E Memory Window for a possible final residual
705 * transfer below ...
706 */
711 }
712 }
714 /* If the original transfer had a length which wasn't a multiple of
715 * 32-bits, now's where we need to finish off the transfer of the
716 * residual amount. The PCI-E Memory Window has already been moved
717 * above (if necessary) to cover this final transfer.
718 */
724 }
726 /* Return the specified PCI-E Configuration Space register from our Physical
727 * Function. We try first via a Firmware LDST Command since we prefer to let
728 * the firmware own all of these registers, but if that fails we go for it
729 * directly ourselves.
730 */
732 {
735 /* If fw_attach != 0, construct and send the Firmware LDST Command to
736 * retrieve the specified PCI-E Configuration Space register.
737 */
744 FW_CMD_REQUEST_F |
745 FW_CMD_READ_F |
746 ldst_addrspace);
753 /* If the LDST Command succeeds, return the result, otherwise
754 * fall through to reading it directly ourselves ...
755 */
760 else
761 /* Read the desired Configuration Space register via the PCI-E
762 * Backdoor mechanism.
763 */
766 }
768 /* Get the window based on base passed to it.
769 * Window aperture is currently unhandled, but there is no use case for it
770 * right now
771 */
773 u32 memwin_base)
774 {
775 u32 ret;
778 u32 bar0;
780 /* Truncation intentional: we only read the bottom 32-bits of
781 * the 64-bit BAR0/BAR1 ... We use the hardware backdoor
782 * mechanism to read BAR0 instead of using
783 * pci_resource_start() because we could be operating from
784 * within a Virtual Machine which is trapping our accesses to
785 * our Configuration Space and we need to set up the PCI-E
786 * Memory Window decoders with the actual addresses which will
787 * be coming across the PCI-E link.
788 */
795 /* For T5, only relative offset inside the PCIe BAR is passed */
797 }
799 }
801 /* Get the default utility window (win0) used by everyone */
803 {
806 }
808 /* Set up memory window for accessing adapter memory ranges. (Read
809 * back MA register to ensure that changes propagate before we attempt
810 * to use the new values.)
811 */
813 {
820 }
822 /**
823 * t4_get_regs_len - return the size of the chips register set
824 * @adapter: the adapter
825 *
826 * Returns the size of the chip's BAR0 register space.
827 */
829 {
839 }
844 }
846 /**
847 * t4_get_regs - read chip registers into provided buffer
848 * @adap: the adapter
849 * @buf: register buffer
850 * @buf_size: size (in bytes) of register buffer
851 *
852 * If the provided register buffer isn't large enough for the chip's
853 * full register range, the register dump will be truncated to the
854 * register buffer's size.
855 */
857 {
1315 };
2082 };
2643 };
2650 /* Select the right set of register ranges to dump depending on the
2651 * adapter chip type.
2652 */
2673 }
2675 /* Clear the register buffer and insert the appropriate register
2676 * values selected by the above register ranges.
2677 */
2684 /* Iterate across the register range filling in the register
2685 * buffer but don't write past the end of the register buffer.
2686 */
2690 }
2691 }
2692 }
2694 #define EEPROM_STAT_ADDR 0x7bfc
2695 #define VPD_BASE 0x400
2696 #define VPD_BASE_OLD 0
2697 #define VPD_LEN 1024
2698 #define CHELSIO_VPD_UNIQUE_ID 0x82
2700 /**
2701 * t4_eeprom_ptov - translate a physical EEPROM address to virtual
2702 * @phys_addr: the physical EEPROM address
2703 * @fn: the PCI function number
2704 * @sz: size of function-specific area
2705 *
2706 * Translate a physical EEPROM address to virtual. The first 1K is
2707 * accessed through virtual addresses starting at 31K, the rest is
2708 * accessed through virtual addresses starting at 0.
2709 *
2710 * The mapping is as follows:
2711 * [0..1K) -> [31K..32K)
2712 * [1K..1K+A) -> [31K-A..31K)
2713 * [1K+A..ES) -> [0..ES-A-1K)
2714 *
2715 * where A = @fn * @sz, and ES = EEPROM size.
2716 */
2718 {
2727 }
2729 /**
2730 * t4_seeprom_wp - enable/disable EEPROM write protection
2731 * @adapter: the adapter
2732 * @enable: whether to enable or disable write protection
2733 *
2734 * Enables or disables write protection on the serial EEPROM.
2735 */
2737 {
2741 }
2743 /**
2744 * t4_get_raw_vpd_params - read VPD parameters from VPD EEPROM
2745 * @adapter: adapter to read
2746 * @p: where to store the parameters
2747 *
2748 * Reads card parameters stored in VPD EEPROM.
2749 */
2751 {
2761 /* Card information normally starts at VPD_BASE but early cards had
2762 * it at 0.
2763 */
2768 /* The VPD shall have a unique identifier specified by the PCI SIG.
2769 * For chelsio adapters, the identifier is 0x82. The first byte of a VPD
2770 * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software
2771 * is expected to automatically put this entry at the
2772 * beginning of the VPD.
2773 */
2784 }
2795 }
2803 }
2805 #define FIND_VPD_KW(var, name) do { \
2806 var = pci_vpd_find_info_keyword(vpd, kw_offset, vpdr_len, name); \
2807 if (var < 0) { \
2809 ret = -EINVAL; \
2810 goto out; \
2811 } \
2812 var += PCI_VPD_INFO_FLD_HDR_SIZE; \
2813 } while (0)
2824 }
2830 #undef FIND_VPD_KW
2845 out:
2848 }
2850 /**
2851 * t4_get_vpd_params - read VPD parameters & retrieve Core Clock
2852 * @adapter: adapter to read
2853 * @p: where to store the parameters
2854 *
2855 * Reads card parameters stored in VPD EEPROM and retrieves the Core
2856 * Clock. This can only be called after a connection to the firmware
2857 * is established.
2858 */
2860 {
2864 /* Grab the raw VPD parameters.
2865 */
2870 /* Ask firmware for the Core Clock since it knows how to translate the
2871 * Reference Clock ('V2') VPD field into a Core Clock value ...
2872 */
2883 }
2885 /* serial flash and firmware constants */
2889 /* flash command opcodes */
2897 };
2899 /**
2900 * sf1_read - read data from the serial flash
2901 * @adapter: the adapter
2902 * @byte_cnt: number of bytes to read
2903 * @cont: whether another operation will be chained
2904 * @lock: whether to lock SF for PL access only
2905 * @valp: where to store the read data
2906 *
2907 * Reads up to 4 bytes of data from the serial flash. The location of
2908 * the read needs to be specified prior to calling this by issuing the
2909 * appropriate commands to the serial flash.
2910 */
2913 {
2926 }
2928 /**
2929 * sf1_write - write data to the serial flash
2930 * @adapter: the adapter
2931 * @byte_cnt: number of bytes to write
2932 * @cont: whether another operation will be chained
2933 * @lock: whether to lock SF for PL access only
2934 * @val: value to write
2935 *
2936 * Writes up to 4 bytes of data to the serial flash. The location of
2937 * the write needs to be specified prior to calling this by issuing the
2938 * appropriate commands to the serial flash.
2939 */
2942 {
2951 }
2953 /**
2954 * flash_wait_op - wait for a flash operation to complete
2955 * @adapter: the adapter
2956 * @attempts: max number of polls of the status register
2957 * @delay: delay between polls in ms
2958 *
2959 * Wait for a flash operation to complete by polling the status register.
2960 */
2962 {
2964 u32 status;
2976 }
2977 }
2979 /**
2980 * t4_read_flash - read words from serial flash
2981 * @adapter: the adapter
2982 * @addr: the start address for the read
2983 * @nwords: how many 32-bit words to read
2984 * @data: where to store the read data
2985 * @byte_oriented: whether to store data as bytes or as words
2986 *
2987 * Read the specified number of 32-bit words from the serial flash.
2988 * If @byte_oriented is set the read data is stored as a byte array
2989 * (i.e., big-endian), otherwise as 32-bit words in the platform's
2990 * natural endianness.
2991 */
2994 {
3014 }
3016 }
3018 /**
3019 * t4_write_flash - write up to a page of data to the serial flash
3020 * @adapter: the adapter
3021 * @addr: the start address to write
3022 * @n: length of data to write in bytes
3023 * @data: the data to write
3024 *
3025 * Writes up to a page of data (256 bytes) to the serial flash starting
3026 * at the given address. All the data must be written to the same page.
3027 */
3030 {
3052 }
3059 /* Read the page to verify the write succeeded */
3067 addr);
3069 }
3072 unlock:
3075 }
3077 /**
3078 * t4_get_fw_version - read the firmware version
3079 * @adapter: the adapter
3080 * @vers: where to place the version
3081 *
3082 * Reads the FW version from flash.
3083 */
3085 {
3089 }
3091 /**
3092 * t4_get_bs_version - read the firmware bootstrap version
3093 * @adapter: the adapter
3094 * @vers: where to place the version
3095 *
3096 * Reads the FW Bootstrap version from flash.
3097 */
3099 {
3103 }
3105 /**
3106 * t4_get_tp_version - read the TP microcode version
3107 * @adapter: the adapter
3108 * @vers: where to place the version
3109 *
3110 * Reads the TP microcode version from flash.
3111 */
3113 {
3117 }
3119 /**
3120 * t4_get_exprom_version - return the Expansion ROM version (if any)
3121 * @adapter: the adapter
3122 * @vers: where to place the version
3123 *
3124 * Reads the Expansion ROM header from FLASH and returns the version
3125 * number (if present) through the @vers return value pointer. We return
3126 * this in the Firmware Version Format since it's convenient. Return
3127 * 0 on success, -ENOENT if no Expansion ROM is present.
3128 */
3130 {
3154 }
3156 /**
3157 * t4_get_vpd_version - return the VPD version
3158 * @adapter: the adapter
3159 * @vers: where to place the version
3160 *
3161 * Reads the VPD via the Firmware interface (thus this can only be called
3162 * once we're ready to issue Firmware commands). The format of the
3163 * VPD version is adapter specific. Returns 0 on success, an error on
3164 * failure.
3165 *
3166 * Note that early versions of the Firmware didn't include the ability
3167 * to retrieve the VPD version, so we zero-out the return-value parameter
3168 * in that case to avoid leaving it with garbage in it.
3169 *
3170 * Also note that the Firmware will return its cached copy of the VPD
3171 * Revision ID, not the actual Revision ID as written in the Serial
3172 * EEPROM. This is only an issue if a new VPD has been written and the
3173 * Firmware/Chip haven't yet gone through a RESET sequence. So it's best
3174 * to defer calling this routine till after a FW_RESET_CMD has been issued
3175 * if the Host Driver will be performing a full adapter initialization.
3176 */
3178 {
3179 u32 vpdrev_param;
3189 }
3191 /**
3192 * t4_get_scfg_version - return the Serial Configuration version
3193 * @adapter: the adapter
3194 * @vers: where to place the version
3195 *
3196 * Reads the Serial Configuration Version via the Firmware interface
3197 * (thus this can only be called once we're ready to issue Firmware
3198 * commands). The format of the Serial Configuration version is
3199 * adapter specific. Returns 0 on success, an error on failure.
3200 *
3201 * Note that early versions of the Firmware didn't include the ability
3202 * to retrieve the Serial Configuration version, so we zero-out the
3203 * return-value parameter in that case to avoid leaving it with
3204 * garbage in it.
3205 *
3206 * Also note that the Firmware will return its cached copy of the Serial
3207 * Initialization Revision ID, not the actual Revision ID as written in
3208 * the Serial EEPROM. This is only an issue if a new VPD has been written
3209 * and the Firmware/Chip haven't yet gone through a RESET sequence. So
3210 * it's best to defer calling this routine till after a FW_RESET_CMD has
3211 * been issued if the Host Driver will be performing a full adapter
3212 * initialization.
3213 */
3215 {
3216 u32 scfgrev_param;
3226 }
3228 /**
3229 * t4_get_version_info - extract various chip/firmware version information
3230 * @adapter: the adapter
3231 *
3232 * Reads various chip/firmware version numbers and stores them into the
3233 * adapter Adapter Parameters structure. If any of the efforts fails
3234 * the first failure will be returned, but all of the version numbers
3235 * will be read.
3236 */
3238 {
3241 #define FIRST_RET(__getvinfo) \
3242 do { \
3243 int __ret = __getvinfo; \
3244 if (__ret && !ret) \
3245 ret = __ret; \
3246 } while (0)
3255 #undef FIRST_RET
3257 }
3259 /**
3260 * t4_dump_version_info - dump all of the adapter configuration IDs
3261 * @adapter: the adapter
3262 *
3263 * Dumps all of the various bits of adapter configuration version/revision
3264 * IDs information. This is typically called at some point after
3265 * t4_get_version_info() has been called.
3266 */
3268 {
3269 /* Device information */
3276 /* Firmware Version */
3279 else
3286 /* Bootstrap Firmware Version. (Some adapters don't have Bootstrap
3287 * Firmware, so dev_info() is more appropriate here.)
3288 */
3291 else
3298 /* TP Microcode Version */
3301 else
3309 /* Expansion ROM version */
3312 else
3320 /* Serial Configuration version */
3324 /* VPD Version */
3327 }
3329 /**
3330 * t4_check_fw_version - check if the FW is supported with this driver
3331 * @adap: the adapter
3332 *
3333 * Checks if an adapter's FW is compatible with the driver. Returns 0
3334 * if there's exact match, a negative error if the version could not be
3335 * read or there's a major version mismatch
3336 */
3338 {
3344 /* Try multiple times before returning error */
3375 }
3380 "Card has firmware version %u.%u.%u, minimum "
3384 }
3386 }
3388 /* Is the given firmware API compatible with the one the driver was compiled
3389 * with?
3390 */
3392 {
3394 /* short circuit if it's the exact same firmware version */
3398 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
3402 #undef SAME_INTF
3405 }
3407 /* The firmware in the filesystem is usable, but should it be installed?
3408 * This routine explains itself in detail if it indicates the filesystem
3409 * firmware should be installed.
3410 */
3413 {
3419 }
3424 }
3428 install:
3437 }
3443 {
3450 /* Read the header of the firmware on the card */
3460 }
3468 }
3472 /* Common case: the firmware on the card is an exact match and
3473 * the filesystem one is an exact match too, or the filesystem
3474 * one is absent/incompatible.
3475 */
3486 }
3488 /* Installed successfully, update the cached header too. */
3492 }
3502 "chip state %d, "
3503 "driver compiled with %d.%d.%d.%d, "
3505 state,
3514 }
3516 /* We're using whatever's on the card and it's known to be good. */
3520 bye:
3522 }
3524 /**
3525 * t4_flash_erase_sectors - erase a range of flash sectors
3526 * @adapter: the adapter
3527 * @start: the first sector to erase
3528 * @end: the last sector to erase
3529 *
3530 * Erases the sectors in the given inclusive range.
3531 */
3533 {
3548 }
3549 start++;
3550 }
3553 }
3555 /**
3556 * t4_flash_cfg_addr - return the address of the flash configuration file
3557 * @adapter: the adapter
3558 *
3559 * Return the address within the flash where the Firmware Configuration
3560 * File is stored.
3561 */
3563 {
3566 else
3568 }
3570 /* Return TRUE if the specified firmware matches the adapter. I.e. T4
3571 * firmware for T4 adapters, T5 firmware for T5 adapters, etc. We go ahead
3572 * and emit an error message for mismatched firmware to save our caller the
3573 * effort ...
3574 */
3577 {
3578 /* The expression below will return FALSE for any unsupported adapter
3579 * which will keep us "honest" in the future ...
3580 */
3590 }
3592 /**
3593 * t4_load_fw - download firmware
3594 * @adap: the adapter
3595 * @fw_data: the firmware image to write
3596 * @size: image size
3597 *
3598 * Write the supplied firmware image to the card's serial flash.
3599 */
3601 {
3602 u32 csum;
3616 }
3621 }
3626 }
3629 fw_size);
3631 }
3642 }
3649 /*
3650 * We write the correct version at the end so the driver can see a bad
3651 * version if the FW write fails. Start by writing a copy of the
3652 * first page with a bad version.
3653 */
3667 }
3672 out:
3675 ret);
3676 else
3679 }
3681 /**
3682 * t4_phy_fw_ver - return current PHY firmware version
3683 * @adap: the adapter
3684 * @phy_fw_ver: return value buffer for PHY firmware version
3685 *
3686 * Returns the current version of external PHY firmware on the
3687 * adapter.
3688 */
3690 {
3704 }
3706 /**
3707 * t4_load_phy_fw - download port PHY firmware
3708 * @adap: the adapter
3709 * @win: the PCI-E Memory Window index to use for t4_memory_rw()
3710 * @win_lock: the lock to use to guard the memory copy
3711 * @phy_fw_version: function to check PHY firmware versions
3712 * @phy_fw_data: the PHY firmware image to write
3713 * @phy_fw_size: image size
3714 *
3715 * Transfer the specified PHY firmware to the adapter. If a non-NULL
3716 * @phy_fw_version is supplied, then it will be used to determine if
3717 * it's necessary to perform the transfer by comparing the version
3718 * of any existing adapter PHY firmware with that of the passed in
3719 * PHY firmware image. If @win_lock is non-NULL then it will be used
3720 * around the call to t4_memory_rw() which transfers the PHY firmware
3721 * to the adapter.
3722 *
3723 * A negative error number will be returned if an error occurs. If
3724 * version number support is available and there's no need to upgrade
3725 * the firmware, 0 will be returned. If firmware is successfully
3726 * transferred to the adapter, 1 will be retured.
3727 *
3728 * NOTE: some adapters only have local RAM to store the PHY firmware. As
3729 * a result, a RESET of the adapter would cause that RAM to lose its
3730 * contents. Thus, loading PHY firmware on such adapters must happen
3731 * after any FW_RESET_CMDs ...
3732 */
3737 {
3743 /* If we have version number support, then check to see if the adapter
3744 * already has up-to-date PHY firmware loaded.
3745 */
3756 }
3757 }
3759 /* Ask the firmware where it wants us to copy the PHY firmware image.
3760 * The size of the file requires a special version of the READ coommand
3761 * which will pass the file size via the values field in PARAMS_CMD and
3762 * retrieve the return value from firmware and place it in the same
3763 * buffer values
3764 */
3777 /* Copy the supplied PHY Firmware image to the adapter memory location
3778 * allocated by the adapter firmware.
3779 */
3784 T4_MEMORY_WRITE);
3790 /* Tell the firmware that the PHY firmware image has been written to
3791 * RAM and it can now start copying it over to the PHYs. The chip
3792 * firmware will RESET the affected PHYs as part of this operation
3793 * leaving them running the new PHY firmware image.
3794 */
3802 /* If we have version number support, then check to see that the new
3803 * firmware got loaded properly.
3804 */
3812 "version on adapter %#x, "
3816 }
3817 }
3820 }
3822 /**
3823 * t4_fwcache - firmware cache operation
3824 * @adap: the adapter
3825 * @op : the operation (flush or flush and invalidate)
3826 */
3828 {
3844 }
3849 {
3871 req++;
3872 rsp++;
3873 }
3876 }
3878 }
3881 {
3882 u32 cfg;
3896 }
3897 }
3899 }
3902 {
3913 }
3914 }
3916 #define ADVERT_MASK (FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_M) | \
3917 FW_PORT_CAP32_ANEG)
3919 /**
3920 * fwcaps16_to_caps32 - convert 16-bit Port Capabilities to 32-bits
3921 * @caps16: a 16-bit Port Capabilities value
3922 *
3923 * Returns the equivalent 32-bit Port Capabilities value.
3924 */
3926 {
3929 #define CAP16_TO_CAP32(__cap) \
3930 do { \
3931 if (caps16 & FW_PORT_CAP_##__cap) \
3932 caps32 |= FW_PORT_CAP32_##__cap; \
3933 } while (0)
3951 #undef CAP16_TO_CAP32
3954 }
3956 /**
3957 * fwcaps32_to_caps16 - convert 32-bit Port Capabilities to 16-bits
3958 * @caps32: a 32-bit Port Capabilities value
3959 *
3960 * Returns the equivalent 16-bit Port Capabilities value. Note that
3961 * not all 32-bit Port Capabilities can be represented in the 16-bit
3962 * Port Capabilities and some fields/values may not make it.
3963 */
3965 {
3968 #define CAP32_TO_CAP16(__cap) \
3969 do { \
3970 if (caps32 & FW_PORT_CAP32_##__cap) \
3971 caps16 |= FW_PORT_CAP_##__cap; \
3972 } while (0)
3990 #undef CAP32_TO_CAP16
3993 }
3995 /* Translate Firmware Port Capabilities Pause specification to Common Code */
3997 {
4006 }
4008 /* Translate Common Code Pause specification into Firmware Port Capabilities */
4010 {
4019 }
4021 /* Translate Firmware Forward Error Correction specification to Common Code */
4023 {
4032 }
4034 /* Translate Common Code Forward Error Correction specification to Firmware */
4036 {
4045 }
4047 /**
4048 * t4_link_l1cfg - apply link configuration to MAC/PHY
4049 * @adapter: the adapter
4050 * @mbox: the Firmware Mailbox to use
4051 * @port: the Port ID
4052 * @lc: the Port's Link Configuration
4053 *
4054 * Set up a port's MAC and PHY according to a desired link configuration.
4055 * - If the PHY can auto-negotiate first decide what to advertise, then
4056 * enable/disable auto-negotiation as desired, and reset.
4057 * - If the PHY does not auto-negotiate just reset it.
4058 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
4059 * otherwise do it later based on the outcome of auto-negotiation.
4060 */
4063 {
4069 /* Convert driver coding of Pause Frame Flow Control settings into the
4070 * Firmware's API.
4071 */
4074 /* Convert Common Code Forward Error Control settings into the
4075 * Firmware's API. If the current Requested FEC has "Automatic"
4076 * (IEEE 802.3) specified, then we use whatever the Firmware
4077 * sent us as part of it's IEEE 802.3-based interpratation of
4078 * the Transceiver Module EPROM FEC parameters. Otherwise we
4079 * use whatever is in the current Requested FEC settings.
4080 */
4083 else
4087 /* Figure out what our Requested Port Capabilities are going to be.
4088 */
4099 }
4101 /* And send that on to the Firmware ...
4102 */
4109 ? FW_PORT_ACTION_L1_CFG
4114 else
4117 }
4119 /**
4120 * t4_restart_aneg - restart autonegotiation
4121 * @adap: the adapter
4122 * @mbox: mbox to use for the FW command
4123 * @port: the port id
4124 *
4125 * Restarts autonegotiation for the selected port.
4126 */
4128 {
4140 }
4150 };
4152 /**
4153 * t4_handle_intr_status - table driven interrupt handler
4154 * @adapter: the adapter that generated the interrupt
4155 * @reg: the interrupt status register to process
4156 * @acts: table of interrupt actions
4157 *
4158 * A table driven interrupt handler that applies a set of masks to an
4159 * interrupt status word and performs the corresponding actions if the
4160 * interrupts described by the mask have occurred. The actions include
4161 * optionally emitting a warning or alert message. The table is terminated
4162 * by an entry specifying mask 0. Returns the number of fatal interrupt
4163 * conditions.
4164 */
4167 {
4176 fatal++;
4185 }
4190 }
4192 /*
4193 * Interrupt handler for the PCIE module.
4194 */
4196 {
4204 };
4216 };
4250 };
4290 };
4296 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A,
4297 sysbus_intr_info) +
4299 PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A,
4300 pcie_port_intr_info) +
4302 pcie_intr_info);
4303 else
4305 t5_pcie_intr_info);
4309 }
4311 /*
4312 * TP interrupt handler.
4313 */
4315 {
4320 };
4324 }
4326 /*
4327 * SGE interrupt handler.
4328 */
4330 {
4331 u64 v;
4332 u32 err;
4356 };
4364 };
4373 }
4378 t4t5_sge_intr_info);
4388 UNCAPTURED_ERROR_F);
4389 }
4393 }
4395 #define CIM_OBQ_INTR (OBQULP0PARERR_F | OBQULP1PARERR_F | OBQULP2PARERR_F |\
4396 OBQULP3PARERR_F | OBQSGEPARERR_F | OBQNCSIPARERR_F)
4397 #define CIM_IBQ_INTR (IBQTP0PARERR_F | IBQTP1PARERR_F | IBQULPPARERR_F |\
4398 IBQSGEHIPARERR_F | IBQSGELOPARERR_F | IBQNCSIPARERR_F)
4400 /*
4401 * CIM interrupt handler.
4402 */
4404 {
4415 };
4446 };
4455 /* When the Firmware detects an internal error which normally
4456 * wouldn't raise a Host Interrupt, it forces a CIM Timer0 interrupt
4457 * in order to make sure the Host sees the Firmware Crash. So
4458 * if we have a Timer0 interrupt and don't see a Firmware Crash,
4459 * ignore the Timer0 interrupt.
4460 */
4467 TIMER0INT_F);
4470 cim_intr_info) +
4472 cim_upintr_info);
4475 }
4477 /*
4478 * ULP RX interrupt handler.
4479 */
4481 {
4486 };
4490 }
4492 /*
4493 * ULP TX interrupt handler.
4494 */
4496 {
4508 };
4512 }
4514 /*
4515 * PM TX interrupt handler.
4516 */
4518 {
4531 };
4535 }
4537 /*
4538 * PM RX interrupt handler.
4539 */
4541 {
4551 };
4555 }
4557 /*
4558 * CPL switch interrupt handler.
4559 */
4561 {
4570 };
4574 }
4576 /*
4577 * LE interrupt handler.
4578 */
4580 {
4589 };
4598 };
4604 }
4606 /*
4607 * MPS interrupt handler.
4608 */
4610 {
4614 };
4626 };
4634 /* MPS Tx Bubble is normal for T6 */
4638 };
4645 };
4649 };
4653 };
4657 };
4663 };
4668 mps_rx_intr_info) +
4671 ? t6_mps_tx_intr_info
4674 mps_trc_intr_info) +
4676 mps_stat_sram_intr_info) +
4678 mps_stat_tx_intr_info) +
4680 mps_stat_rx_intr_info) +
4682 mps_cls_intr_info);
4688 }
4690 #define MEM_INT_MASK (PERR_INT_CAUSE_F | ECC_CE_INT_CAUSE_F | \
4691 ECC_UE_INT_CAUSE_F)
4693 /*
4694 * EDC/MC interrupt handler.
4695 */
4697 {
4712 }
4716 }
4732 }
4740 }
4742 /*
4743 * MA interrupt handler.
4744 */
4746 {
4757 MA_PARITY_ERROR_STATUS2_A));
4758 }
4765 }
4768 }
4770 /*
4771 * SMB interrupt handler.
4772 */
4774 {
4780 };
4784 }
4786 /*
4787 * NC-SI interrupt handler.
4788 */
4790 {
4797 };
4801 }
4803 /*
4804 * XGMAC interrupt handler.
4805 */
4807 {
4812 else
4823 port);
4826 port);
4829 }
4831 /*
4832 * PL interrupt handler.
4833 */
4835 {
4840 };
4844 }
4846 #define PF_INTR_MASK (PFSW_F)
4847 #define GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | EDC0_F | \
4848 EDC1_F | LE_F | TP_F | MA_F | PM_TX_F | PM_RX_F | ULP_RX_F | \
4849 CPL_SWITCH_F | SGE_F | ULP_TX_F | SF_F)
4851 /**
4852 * t4_slow_intr_handler - control path interrupt handler
4853 * @adapter: the adapter
4854 *
4855 * T4 interrupt handler for non-data global interrupt events, e.g., errors.
4856 * The designation 'slow' is because it involves register reads, while
4857 * data interrupts typically don't involve any MMIOs.
4858 */
4860 {
4912 /* Clear the interrupts just processed for which we are the master. */
4916 }
4918 /**
4919 * t4_intr_enable - enable interrupts
4920 * @adapter: the adapter whose interrupts should be enabled
4921 *
4922 * Enable PF-specific interrupts for the calling function and the top-level
4923 * interrupt concentrator for global interrupts. Interrupts are already
4924 * enabled at each module, here we just enable the roots of the interrupt
4925 * hierarchies.
4926 *
4927 * Note: this function should be called only when the driver manages
4928 * non PF-specific interrupts from the various HW modules. Only one PCI
4929 * function at a time should be doing this.
4930 */
4932 {
4949 }
4951 /**
4952 * t4_intr_disable - disable interrupts
4953 * @adapter: the adapter whose interrupts should be disabled
4954 *
4955 * Disable interrupts. We only disable the top-level interrupt
4956 * concentrators. The caller must be a PCI function managing global
4957 * interrupts.
4958 */
4960 {
4972 }
4975 {
4978 else
4980 }
4982 /**
4983 * t4_config_rss_range - configure a portion of the RSS mapping table
4984 * @adapter: the adapter
4985 * @mbox: mbox to use for the FW command
4986 * @viid: virtual interface whose RSS subtable is to be written
4987 * @start: start entry in the table to write
4988 * @n: how many table entries to write
4989 * @rspq: values for the response queue lookup table
4990 * @nrspq: number of values in @rspq
4991 *
4992 * Programs the selected part of the VI's RSS mapping table with the
4993 * provided values. If @nrspq < @n the supplied values are used repeatedly
4994 * until the full table range is populated.
4995 *
4996 * The caller must ensure the values in @rspq are in the range allowed for
4997 * @viid.
4998 */
5001 {
5013 /* each fw_rss_ind_tbl_cmd takes up to 32 entries */
5039 }
5044 }
5046 }
5048 /**
5049 * t4_config_glbl_rss - configure the global RSS mode
5050 * @adapter: the adapter
5051 * @mbox: mbox to use for the FW command
5052 * @mode: global RSS mode
5053 * @flags: mode-specific flags
5054 *
5055 * Sets the global RSS mode.
5056 */
5059 {
5076 }
5078 /**
5079 * t4_config_vi_rss - configure per VI RSS settings
5080 * @adapter: the adapter
5081 * @mbox: mbox to use for the FW command
5082 * @viid: the VI id
5083 * @flags: RSS flags
5084 * @defq: id of the default RSS queue for the VI.
5085 *
5086 * Configures VI-specific RSS properties.
5087 */
5090 {
5101 }
5103 /* Read an RSS table row */
5105 {
5109 }
5111 /**
5112 * t4_read_rss - read the contents of the RSS mapping table
5113 * @adapter: the adapter
5114 * @map: holds the contents of the RSS mapping table
5115 *
5116 * Reads the contents of the RSS hash->queue mapping table.
5117 */
5119 {
5121 u32 val;
5130 }
5132 }
5135 {
5137 }
5139 /**
5140 * t4_tp_fw_ldst_rw - Access TP indirect register through LDST
5141 * @adap: the adapter
5142 * @cmd: TP fw ldst address space type
5143 * @vals: where the indirect register values are stored/written
5144 * @nregs: how many indirect registers to read/write
5145 * @start_idx: index of first indirect register to read/write
5146 * @rw: Read (1) or Write (0)
5147 * @sleep_ok: if true we may sleep while awaiting command completion
5148 *
5149 * Access TP indirect registers through LDST
5150 */
5154 {
5162 FW_CMD_REQUEST_F |
5164 FW_CMD_WRITE_F) |
5171 sleep_ok);
5177 }
5179 }
5181 /**
5182 * t4_tp_indirect_rw - Read/Write TP indirect register through LDST or backdoor
5183 * @adap: the adapter
5184 * @reg_addr: Address Register
5185 * @reg_data: Data register
5186 * @buff: where the indirect register values are stored/written
5187 * @nregs: how many indirect registers to read/write
5188 * @start_index: index of first indirect register to read/write
5189 * @rw: READ(1) or WRITE(0)
5190 * @sleep_ok: if true we may sleep while awaiting command completion
5191 *
5192 * Read/Write TP indirect registers through LDST if possible.
5193 * Else, use backdoor access
5194 **/
5198 {
5214 }
5218 sleep_ok);
5220 indirect_access:
5225 start_index);
5226 else
5228 start_index);
5229 }
5230 }
5232 /**
5233 * t4_tp_pio_read - Read TP PIO registers
5234 * @adap: the adapter
5235 * @buff: where the indirect register values are written
5236 * @nregs: how many indirect registers to read
5237 * @start_index: index of first indirect register to read
5238 * @sleep_ok: if true we may sleep while awaiting command completion
5239 *
5240 * Read TP PIO Registers
5241 **/
5244 {
5247 }
5249 /**
5250 * t4_tp_pio_write - Write TP PIO registers
5251 * @adap: the adapter
5252 * @buff: where the indirect register values are stored
5253 * @nregs: how many indirect registers to write
5254 * @start_index: index of first indirect register to write
5255 * @sleep_ok: if true we may sleep while awaiting command completion
5256 *
5257 * Write TP PIO Registers
5258 **/
5261 {
5264 }
5266 /**
5267 * t4_tp_tm_pio_read - Read TP TM PIO registers
5268 * @adap: the adapter
5269 * @buff: where the indirect register values are written
5270 * @nregs: how many indirect registers to read
5271 * @start_index: index of first indirect register to read
5272 * @sleep_ok: if true we may sleep while awaiting command completion
5273 *
5274 * Read TP TM PIO Registers
5275 **/
5278 {
5281 }
5283 /**
5284 * t4_tp_mib_read - Read TP MIB registers
5285 * @adap: the adapter
5286 * @buff: where the indirect register values are written
5287 * @nregs: how many indirect registers to read
5288 * @start_index: index of first indirect register to read
5289 * @sleep_ok: if true we may sleep while awaiting command completion
5290 *
5291 * Read TP MIB Registers
5292 **/
5295 {
5298 }
5300 /**
5301 * t4_read_rss_key - read the global RSS key
5302 * @adap: the adapter
5303 * @key: 10-entry array holding the 320-bit RSS key
5304 * @sleep_ok: if true we may sleep while awaiting command completion
5305 *
5306 * Reads the global 320-bit RSS key.
5307 */
5309 {
5311 }
5313 /**
5314 * t4_write_rss_key - program one of the RSS keys
5315 * @adap: the adapter
5316 * @key: 10-entry array holding the 320-bit RSS key
5317 * @idx: which RSS key to write
5318 * @sleep_ok: if true we may sleep while awaiting command completion
5319 *
5320 * Writes one of the RSS keys with the given 320-bit value. If @idx is
5321 * 0..15 the corresponding entry in the RSS key table is written,
5322 * otherwise the global RSS key is written.
5323 */
5326 {
5330 /* T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
5331 * allows access to key addresses 16-63 by using KeyWrAddrX
5332 * as index[5:4](upper 2) into key table
5333 */
5345 else
5348 }
5349 }
5351 /**
5352 * t4_read_rss_pf_config - read PF RSS Configuration Table
5353 * @adapter: the adapter
5354 * @index: the entry in the PF RSS table to read
5355 * @valp: where to store the returned value
5356 * @sleep_ok: if true we may sleep while awaiting command completion
5357 *
5358 * Reads the PF RSS Configuration Table at the specified index and returns
5359 * the value found there.
5360 */
5363 {
5365 }
5367 /**
5368 * t4_read_rss_vf_config - read VF RSS Configuration Table
5369 * @adapter: the adapter
5370 * @index: the entry in the VF RSS table to read
5371 * @vfl: where to store the returned VFL
5372 * @vfh: where to store the returned VFH
5373 * @sleep_ok: if true we may sleep while awaiting command completion
5374 *
5375 * Reads the VF RSS Configuration Table at the specified index and returns
5376 * the (VFL, VFH) values found there.
5377 */
5380 {
5389 }
5391 /* Request that the index'th VF Table values be read into VFL/VFH.
5392 */
5398 /* Grab the VFL/VFH values ...
5399 */
5402 }
5404 /**
5405 * t4_read_rss_pf_map - read PF RSS Map
5406 * @adapter: the adapter
5407 * @sleep_ok: if true we may sleep while awaiting command completion
5408 *
5409 * Reads the PF RSS Map register and returns its value.
5410 */
5412 {
5413 u32 pfmap;
5417 }
5419 /**
5420 * t4_read_rss_pf_mask - read PF RSS Mask
5421 * @adapter: the adapter
5422 * @sleep_ok: if true we may sleep while awaiting command completion
5423 *
5424 * Reads the PF RSS Mask register and returns its value.
5425 */
5427 {
5428 u32 pfmask;
5432 }
5434 /**
5435 * t4_tp_get_tcp_stats - read TP's TCP MIB counters
5436 * @adap: the adapter
5437 * @v4: holds the TCP/IP counter values
5438 * @v6: holds the TCP/IPv6 counter values
5439 * @sleep_ok: if true we may sleep while awaiting command completion
5440 *
5441 * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
5442 * Either @v4 or @v6 may be %NULL to skip the corresponding stats.
5443 */
5446 {
5449 #define STAT_IDX(x) ((TP_MIB_TCP_##x##_A) - TP_MIB_TCP_OUT_RST_A)
5450 #define STAT(x) val[STAT_IDX(x)]
5451 #define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
5460 }
5468 }
5469 #undef STAT64
5470 #undef STAT
5471 #undef STAT_IDX
5472 }
5474 /**
5475 * t4_tp_get_err_stats - read TP's error MIB counters
5476 * @adap: the adapter
5477 * @st: holds the counter values
5478 * @sleep_ok: if true we may sleep while awaiting command completion
5479 *
5480 * Returns the values of TP's error counters.
5481 */
5484 {
5488 sleep_ok);
5490 sleep_ok);
5492 sleep_ok);
5498 sleep_ok);
5504 sleep_ok);
5505 }
5507 /**
5508 * t4_tp_get_cpl_stats - read TP's CPL MIB counters
5509 * @adap: the adapter
5510 * @st: holds the counter values
5511 * @sleep_ok: if true we may sleep while awaiting command completion
5512 *
5513 * Returns the values of TP's CPL counters.
5514 */
5517 {
5523 }
5525 /**
5526 * t4_tp_get_rdma_stats - read TP's RDMA MIB counters
5527 * @adap: the adapter
5528 * @st: holds the counter values
5529 * @sleep_ok: if true we may sleep while awaiting command completion
5530 *
5531 * Returns the values of TP's RDMA counters.
5532 */
5535 {
5537 sleep_ok);
5538 }
5540 /**
5541 * t4_get_fcoe_stats - read TP's FCoE MIB counters for a port
5542 * @adap: the adapter
5543 * @idx: the port index
5544 * @st: holds the counter values
5545 * @sleep_ok: if true we may sleep while awaiting command completion
5546 *
5547 * Returns the values of TP's FCoE counters for the selected port.
5548 */
5551 {
5555 sleep_ok);
5561 sleep_ok);
5564 }
5566 /**
5567 * t4_get_usm_stats - read TP's non-TCP DDP MIB counters
5568 * @adap: the adapter
5569 * @st: holds the counter values
5570 * @sleep_ok: if true we may sleep while awaiting command completion
5571 *
5572 * Returns the values of TP's counters for non-TCP directly-placed packets.
5573 */
5576 {
5583 }
5585 /**
5586 * t4_read_mtu_tbl - returns the values in the HW path MTU table
5587 * @adap: the adapter
5588 * @mtus: where to store the MTU values
5589 * @mtu_log: where to store the MTU base-2 log (may be %NULL)
5590 *
5591 * Reads the HW path MTU table.
5592 */
5594 {
5595 u32 v;
5605 }
5606 }
5608 /**
5609 * t4_read_cong_tbl - reads the congestion control table
5610 * @adap: the adapter
5611 * @incr: where to store the alpha values
5612 *
5613 * Reads the additive increments programmed into the HW congestion
5614 * control table.
5615 */
5617 {
5626 }
5627 }
5629 /**
5630 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
5631 * @adap: the adapter
5632 * @addr: the indirect TP register address
5633 * @mask: specifies the field within the register to modify
5634 * @val: new value for the field
5635 *
5636 * Sets a field of an indirect TP register to the given value.
5637 */
5640 {
5644 }
5646 /**
5647 * init_cong_ctrl - initialize congestion control parameters
5648 * @a: the alpha values for congestion control
5649 * @b: the beta values for congestion control
5650 *
5651 * Initialize the congestion control parameters.
5652 */
5654 {
5688 }
5690 /* The minimum additive increment value for the congestion control table */
5691 #define CC_MIN_INCR 2U
5693 /**
5694 * t4_load_mtus - write the MTU and congestion control HW tables
5695 * @adap: the adapter
5696 * @mtus: the values for the MTU table
5697 * @alpha: the values for the congestion control alpha parameter
5698 * @beta: the values for the congestion control beta parameter
5699 *
5700 * Write the HW MTU table with the supplied MTUs and the high-speed
5701 * congestion control table with the supplied alpha, beta, and MTUs.
5702 * We write the two tables together because the additive increments
5703 * depend on the MTUs.
5704 */
5707 {
5712 };
5721 log2--;
5729 CC_MIN_INCR);
5733 }
5734 }
5735 }
5737 /* Calculates a rate in bytes/s given the number of 256-byte units per 4K core
5738 * clocks. The formula is
5739 *
5740 * bytes/s = bytes256 * 256 * ClkFreq / 4096
5741 *
5742 * which is equivalent to
5743 *
5744 * bytes/s = 62.5 * bytes256 * ClkFreq_ms
5745 */
5747 {
5751 }
5753 /**
5754 * t4_get_chan_txrate - get the current per channel Tx rates
5755 * @adap: the adapter
5756 * @nic_rate: rates for NIC traffic
5757 * @ofld_rate: rates for offloaded traffic
5758 *
5759 * Return the current Tx rates in bytes/s for NIC and offloaded traffic
5760 * for each channel.
5761 */
5763 {
5764 u32 v;
5772 }
5780 }
5781 }
5783 /**
5784 * t4_set_trace_filter - configure one of the tracing filters
5785 * @adap: the adapter
5786 * @tp: the desired trace filter parameters
5787 * @idx: which filter to configure
5788 * @enable: whether to enable or disable the filter
5789 *
5790 * Configures one of the tracing filters available in HW. If @enable is
5791 * %0 @tp is not examined and may be %NULL. The user is responsible to
5792 * set the single/multiple trace mode by writing to MPS_TRC_CFG_A register
5793 */
5796 {
5804 }
5808 /* If multiple tracers are enabled, then maximum
5809 * capture size is 2.5KB (FIFO size of a single channel)
5810 * minus 2 flits for CPL_TRACE_PKT header.
5811 */
5815 /* If multiple tracers are disabled, to avoid deadlocks
5816 * maximum packet capture size of 9600 bytes is recommended.
5817 * Also in this mode, only trace0 can be enabled and running.
5818 */
5822 }
5829 /* stop the tracer we'll be changing */
5839 }
5851 }
5853 /**
5854 * t4_get_trace_filter - query one of the tracing filters
5855 * @adap: the adapter
5856 * @tp: the current trace filter parameters
5857 * @idx: which trace filter to query
5858 * @enabled: non-zero if the filter is enabled
5859 *
5860 * Returns the current settings of one of the HW tracing filters.
5861 */
5864 {
5880 }
5893 }
5894 }
5896 /**
5897 * t4_pmtx_get_stats - returns the HW stats from PMTX
5898 * @adap: the adapter
5899 * @cnt: where to store the count statistics
5900 * @cycles: where to store the cycle statistics
5901 *
5902 * Returns performance statistics from PMTX.
5903 */
5905 {
5917 PM_TX_DBG_STAT_MSB_A);
5919 }
5920 }
5921 }
5923 /**
5924 * t4_pmrx_get_stats - returns the HW stats from PMRX
5925 * @adap: the adapter
5926 * @cnt: where to store the count statistics
5927 * @cycles: where to store the cycle statistics
5928 *
5929 * Returns performance statistics from PMRX.
5930 */
5932 {
5944 PM_RX_DBG_STAT_MSB_A);
5946 }
5947 }
5948 }
5950 /**
5951 * compute_mps_bg_map - compute the MPS Buffer Group Map for a Port
5952 * @adap: the adapter
5953 * @pidx: the port index
5954 *
5955 * Computes and returns a bitmap indicating which MPS buffer groups are
5956 * associated with the given Port. Bit i is set if buffer group i is
5957 * used by the Port.
5958 */
5961 {
5974 }
5980 }
5982 }
5988 }
5990 /**
5991 * t4_get_mps_bg_map - return the buffer groups associated with a port
5992 * @adapter: the adapter
5993 * @pidx: the port index
5994 *
5995 * Returns a bitmap indicating which MPS buffer groups are associated
5996 * with the given Port. Bit i is set if buffer group i is used by the
5997 * Port.
5998 */
6000 {
6009 }
6011 /* If we've already retrieved/computed this, just return the result.
6012 */
6017 /* Newer Firmware can tell us what the MPS Buffer Group Map is.
6018 * If we're talking to such Firmware, let it tell us. If the new
6019 * API isn't supported, revert back to old hardcoded way. The value
6020 * obtained from Firmware is encoded in below format:
6021 *
6022 * val = (( MPSBGMAP[Port 3] << 24 ) |
6023 * ( MPSBGMAP[Port 2] << 16 ) |
6024 * ( MPSBGMAP[Port 1] << 8 ) |
6025 * ( MPSBGMAP[Port 0] << 0 ))
6026 */
6038 /* Store the BG Map for all of the Ports in order to
6039 * avoid more calls to the Firmware in the future.
6040 */
6045 }
6046 }
6048 /* Either we're not talking to the Firmware or we're dealing with
6049 * older Firmware which doesn't support the new API to get the MPS
6050 * Buffer Group Map. Fall back to computing it ourselves.
6051 */
6054 }
6056 /**
6057 * t4_get_tp_ch_map - return TP ingress channels associated with a port
6058 * @adapter: the adapter
6059 * @pidx: the port index
6060 *
6061 * Returns a bitmap indicating which TP Ingress Channels are associated
6062 * with a given Port. Bit i is set if TP Ingress Channel i is used by
6063 * the Port.
6064 */
6066 {
6074 }
6079 /* Note that this happens to be the same values as the MPS
6080 * Buffer Group Map for these Chips. But we replicate the code
6081 * here because they're really separate concepts.
6082 */
6087 }
6094 }
6096 }
6101 }
6103 /**
6104 * t4_get_port_type_description - return Port Type string description
6105 * @port_type: firmware Port Type enumeration
6106 */
6108 {
6132 "KR_XLAUI"
6133 };
6138 }
6140 /**
6141 * t4_get_port_stats_offset - collect port stats relative to a previous
6142 * snapshot
6143 * @adap: The adapter
6144 * @idx: The port
6145 * @stats: Current stats to fill
6146 * @offset: Previous stats snapshot
6147 */
6151 {
6160 }
6162 /**
6163 * t4_get_port_stats - collect port statistics
6164 * @adap: the adapter
6165 * @idx: the port index
6166 * @p: the stats structure to fill
6167 *
6168 * Collect statistics related to the given port from HW.
6169 */
6171 {
6175 #define GET_STAT(name) \
6176 t4_read_reg64(adap, \
6177 (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \
6178 T5_PORT_REG(idx, MPS_PORT_STAT_##name##_L)))
6179 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
6210 }
6244 }
6255 #undef GET_STAT
6256 #undef GET_STAT_COM
6257 }
6259 /**
6260 * t4_get_lb_stats - collect loopback port statistics
6261 * @adap: the adapter
6262 * @idx: the loopback port index
6263 * @p: the stats structure to fill
6264 *
6265 * Return HW statistics for the given loopback port.
6266 */
6268 {
6271 #define GET_STAT(name) \
6272 t4_read_reg64(adap, \
6273 (is_t4(adap->params.chip) ? \
6274 PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L) : \
6275 T5_PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L)))
6276 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
6303 #undef GET_STAT
6304 #undef GET_STAT_COM
6305 }
6307 /* t4_mk_filtdelwr - create a delete filter WR
6308 * @ftid: the filter ID
6309 * @wr: the filter work request to populate
6310 * @qid: ingress queue to receive the delete notification
6311 *
6312 * Creates a filter work request to delete the supplied filter. If @qid is
6313 * negative the delete notification is suppressed.
6314 */
6316 {
6326 }
6328 #define INIT_CMD(var, cmd, rd_wr) do { \
6329 (var).op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_##cmd##_CMD) | \
6330 FW_CMD_REQUEST_F | \
6331 FW_CMD_##rd_wr##_F); \
6332 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
6333 } while (0)
6337 {
6338 u32 ldst_addrspace;
6344 FW_CMD_REQUEST_F |
6345 FW_CMD_WRITE_F |
6346 ldst_addrspace);
6352 }
6354 /**
6355 * t4_mdio_rd - read a PHY register through MDIO
6356 * @adap: the adapter
6357 * @mbox: mailbox to use for the FW command
6358 * @phy_addr: the PHY address
6359 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
6360 * @reg: the register to read
6361 * @valp: where to store the value
6362 *
6363 * Issues a FW command through the given mailbox to read a PHY register.
6364 */
6367 {
6369 u32 ldst_addrspace;
6376 ldst_addrspace);
6386 }
6388 /**
6389 * t4_mdio_wr - write a PHY register through MDIO
6390 * @adap: the adapter
6391 * @mbox: mailbox to use for the FW command
6392 * @phy_addr: the PHY address
6393 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
6394 * @reg: the register to write
6395 * @valp: value to write
6396 *
6397 * Issues a FW command through the given mailbox to write a PHY register.
6398 */
6401 {
6402 u32 ldst_addrspace;
6409 ldst_addrspace);
6417 }
6419 /**
6420 * t4_sge_decode_idma_state - decode the idma state
6421 * @adap: the adapter
6422 * @state: the state idma is stuck in
6423 */
6425 {
6462 };
6497 };
6530 };
6532 SGE_DEBUG_DATA_LOW_INDEX_2_A,
6533 SGE_DEBUG_DATA_LOW_INDEX_3_A,
6534 SGE_DEBUG_DATA_HIGH_INDEX_10_A,
6535 };
6541 /* Select the right set of decode strings to dump depending on the
6542 * adapter chip type.
6543 */
6564 }
6572 }
6576 else
6582 }
6584 /**
6585 * t4_sge_ctxt_flush - flush the SGE context cache
6586 * @adap: the adapter
6587 * @mbox: mailbox to use for the FW command
6588 * @ctx_type: Egress or Ingress
6589 *
6590 * Issues a FW command through the given mailbox to flush the
6591 * SGE context cache.
6592 */
6594 {
6596 u32 ldst_addrspace;
6601 FW_LDST_ADDRSPC_SGE_EGRC :
6602 FW_LDST_ADDRSPC_SGE_INGC);
6605 ldst_addrspace);
6611 }
6613 /**
6614 * t4_fw_hello - establish communication with FW
6615 * @adap: the adapter
6616 * @mbox: mailbox to use for the FW command
6617 * @evt_mbox: mailbox to receive async FW events
6618 * @master: specifies the caller's willingness to be the device master
6619 * @state: returns the current device state (if non-NULL)
6620 *
6621 * Issues a command to establish communication with FW. Returns either
6622 * an error (negative integer) or the mailbox of the Master PF.
6623 */
6626 {
6629 u32 v;
6633 retry:
6643 FW_HELLO_CMD_CLEARINIT_F);
6645 /*
6646 * Issue the HELLO command to the firmware. If it's not successful
6647 * but indicates that we got a "busy" or "timeout" condition, retry
6648 * the HELLO until we exhaust our retry limit. If we do exceed our
6649 * retry limit, check to see if the firmware left us any error
6650 * information and report that if so.
6651 */
6659 }
6668 else
6670 }
6672 /*
6673 * If we're not the Master PF then we need to wait around for the
6674 * Master PF Driver to finish setting up the adapter.
6675 *
6676 * Note that we also do this wait if we're a non-Master-capable PF and
6677 * there is no current Master PF; a Master PF may show up momentarily
6678 * and we wouldn't want to fail pointlessly. (This can happen when an
6679 * OS loads lots of different drivers rapidly at the same time). In
6680 * this case, the Master PF returned by the firmware will be
6681 * PCIE_FW_MASTER_M so the test below will work ...
6682 */
6687 /*
6688 * Wait for the firmware to either indicate an error or
6689 * initialized state. If we see either of these we bail out
6690 * and report the issue to the caller. If we exhaust the
6691 * "hello timeout" and we haven't exhausted our retries, try
6692 * again. Otherwise bail with a timeout error.
6693 */
6695 u32 pcie_fw;
6700 /*
6701 * If neither Error nor Initialialized are indicated
6702 * by the firmware keep waiting till we exaust our
6703 * timeout ... and then retry if we haven't exhausted
6704 * our retries ...
6705 */
6713 }
6715 }
6717 /*
6718 * We either have an Error or Initialized condition
6719 * report errors preferentially.
6720 */
6726 }
6728 /*
6729 * If we arrived before a Master PF was selected and
6730 * there's not a valid Master PF, grab its identity
6731 * for our caller.
6732 */
6737 }
6738 }
6741 }
6743 /**
6744 * t4_fw_bye - end communication with FW
6745 * @adap: the adapter
6746 * @mbox: mailbox to use for the FW command
6747 *
6748 * Issues a command to terminate communication with FW.
6749 */
6751 {
6757 }
6759 /**
6760 * t4_init_cmd - ask FW to initialize the device
6761 * @adap: the adapter
6762 * @mbox: mailbox to use for the FW command
6763 *
6764 * Issues a command to FW to partially initialize the device. This
6765 * performs initialization that generally doesn't depend on user input.
6766 */
6768 {
6774 }
6776 /**
6777 * t4_fw_reset - issue a reset to FW
6778 * @adap: the adapter
6779 * @mbox: mailbox to use for the FW command
6780 * @reset: specifies the type of reset to perform
6781 *
6782 * Issues a reset command of the specified type to FW.
6783 */
6785 {
6792 }
6794 /**
6795 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
6796 * @adap: the adapter
6797 * @mbox: mailbox to use for the FW RESET command (if desired)
6798 * @force: force uP into RESET even if FW RESET command fails
6799 *
6800 * Issues a RESET command to firmware (if desired) with a HALT indication
6801 * and then puts the microprocessor into RESET state. The RESET command
6802 * will only be issued if a legitimate mailbox is provided (mbox <=
6803 * PCIE_FW_MASTER_M).
6804 *
6805 * This is generally used in order for the host to safely manipulate the
6806 * adapter without fear of conflicting with whatever the firmware might
6807 * be doing. The only way out of this state is to RESTART the firmware
6808 * ...
6809 */
6811 {
6814 /*
6815 * If a legitimate mailbox is provided, issue a RESET command
6816 * with a HALT indication.
6817 */
6826 }
6828 /*
6829 * Normally we won't complete the operation if the firmware RESET
6830 * command fails but if our caller insists we'll go ahead and put the
6831 * uP into RESET. This can be useful if the firmware is hung or even
6832 * missing ... We'll have to take the risk of putting the uP into
6833 * RESET without the cooperation of firmware in that case.
6834 *
6835 * We also force the firmware's HALT flag to be on in case we bypassed
6836 * the firmware RESET command above or we're dealing with old firmware
6837 * which doesn't have the HALT capability. This will serve as a flag
6838 * for the incoming firmware to know that it's coming out of a HALT
6839 * rather than a RESET ... if it's new enough to understand that ...
6840 */
6844 PCIE_FW_HALT_F);
6845 }
6847 /*
6848 * And we always return the result of the firmware RESET command
6849 * even when we force the uP into RESET ...
6850 */
6852 }
6854 /**
6855 * t4_fw_restart - restart the firmware by taking the uP out of RESET
6856 * @adap: the adapter
6857 * @reset: if we want to do a RESET to restart things
6858 *
6859 * Restart firmware previously halted by t4_fw_halt(). On successful
6860 * return the previous PF Master remains as the new PF Master and there
6861 * is no need to issue a new HELLO command, etc.
6862 *
6863 * We do this in two ways:
6864 *
6865 * 1. If we're dealing with newer firmware we'll simply want to take
6866 * the chip's microprocessor out of RESET. This will cause the
6867 * firmware to start up from its start vector. And then we'll loop
6868 * until the firmware indicates it's started again (PCIE_FW.HALT
6869 * reset to 0) or we timeout.
6870 *
6871 * 2. If we're dealing with older firmware then we'll need to RESET
6872 * the chip since older firmware won't recognize the PCIE_FW.HALT
6873 * flag and automatically RESET itself on startup.
6874 */
6876 {
6878 /*
6879 * Since we're directing the RESET instead of the firmware
6880 * doing it automatically, we need to clear the PCIE_FW.HALT
6881 * bit.
6882 */
6885 /*
6886 * If we've been given a valid mailbox, first try to get the
6887 * firmware to do the RESET. If that works, great and we can
6888 * return success. Otherwise, if we haven't been given a
6889 * valid mailbox or the RESET command failed, fall back to
6890 * hitting the chip with a hammer.
6891 */
6898 }
6911 }
6913 }
6915 }
6917 /**
6918 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW
6919 * @adap: the adapter
6920 * @mbox: mailbox to use for the FW RESET command (if desired)
6921 * @fw_data: the firmware image to write
6922 * @size: image size
6923 * @force: force upgrade even if firmware doesn't cooperate
6924 *
6925 * Perform all of the steps necessary for upgrading an adapter's
6926 * firmware image. Normally this requires the cooperation of the
6927 * existing firmware in order to halt all existing activities
6928 * but if an invalid mailbox token is passed in we skip that step
6929 * (though we'll still put the adapter microprocessor into RESET in
6930 * that case).
6931 *
6932 * On successful return the new firmware will have been loaded and
6933 * the adapter will have been fully RESET losing all previous setup
6934 * state. On unsuccessful return the adapter may be completely hosed ...
6935 * positive errno indicates that the adapter is ~probably~ intact, a
6936 * negative errno indicates that things are looking bad ...
6937 */
6940 {
6947 /* Disable FW_OK flag so that mbox commands with FW_OK flag set
6948 * wont be sent when we are flashing FW.
6949 */
6960 /*
6961 * If there was a Firmware Configuration File stored in FLASH,
6962 * there's a good chance that it won't be compatible with the new
6963 * Firmware. In order to prevent difficult to diagnose adapter
6964 * initialization issues, we clear out the Firmware Configuration File
6965 * portion of the FLASH . The user will need to re-FLASH a new
6966 * Firmware Configuration File which is compatible with the new
6967 * Firmware if that's desired.
6968 */
6971 /*
6972 * Older versions of the firmware don't understand the new
6973 * PCIE_FW.HALT flag and so won't know to perform a RESET when they
6974 * restart. So for newly loaded older firmware we'll have to do the
6975 * RESET for it so it starts up on a clean slate. We can tell if
6976 * the newly loaded firmware will handle this right by checking
6977 * its header flags to see if it advertises the capability.
6978 */
6982 /* Grab potentially new Firmware Device Log parameters so we can see
6983 * how healthy the new Firmware is. It's okay to contact the new
6984 * Firmware for these parameters even though, as far as it's
6985 * concerned, we've never said "HELLO" to it ...
6986 */
6988 out:
6991 }
6993 /**
6994 * t4_fl_pkt_align - return the fl packet alignment
6995 * @adap: the adapter
6996 *
6997 * T4 has a single field to specify the packing and padding boundary.
6998 * T5 onwards has separate fields for this and hence the alignment for
6999 * next packet offset is maximum of these two.
7000 *
7001 */
7003 {
7009 /* T4 uses a single control field to specify both the PCIe Padding and
7010 * Packing Boundary. T5 introduced the ability to specify these
7011 * separately. The actual Ingress Packet Data alignment boundary
7012 * within Packed Buffer Mode is the maximum of these two
7013 * specifications. (Note that it makes no real practical sense to
7014 * have the Pading Boudary be larger than the Packing Boundary but you
7015 * could set the chip up that way and, in fact, legacy T4 code would
7016 * end doing this because it would initialize the Padding Boundary and
7017 * leave the Packing Boundary initialized to 0 (16 bytes).)
7018 * Padding Boundary values in T6 starts from 8B,
7019 * where as it is 32B for T4 and T5.
7020 */
7023 else
7030 /* T5 has a weird interpretation of one of the PCIe Packing
7031 * Boundary values. No idea why ...
7032 */
7037 else
7039 INGPACKBOUNDARY_SHIFT_X);
7042 }
7044 }
7046 /**
7047 * t4_fixup_host_params - fix up host-dependent parameters
7048 * @adap: the adapter
7049 * @page_size: the host's Base Page Size
7050 * @cache_line_size: the host's Cache Line Size
7051 *
7052 * Various registers in T4 contain values which are dependent on the
7053 * host's Base Page and Cache Line Sizes. This function will fix all of
7054 * those registers with the appropriate values as passed in ...
7055 */
7058 {
7078 EGRSTATUSPAGESIZE_F,
7080 INGPADBOUNDARY_SHIFT_X) |
7087 /* T5 introduced the separation of the Free List Padding and
7088 * Packing Boundaries. Thus, we can select a smaller Padding
7089 * Boundary to avoid uselessly chewing up PCIe Link and Memory
7090 * Bandwidth, and use a Packing Boundary which is large enough
7091 * to avoid false sharing between CPUs, etc.
7092 *
7093 * For the PCI Link, the smaller the Padding Boundary the
7094 * better. For the Memory Controller, a smaller Padding
7095 * Boundary is better until we cross under the Memory Line
7096 * Size (the minimum unit of transfer to/from Memory). If we
7097 * have a Padding Boundary which is smaller than the Memory
7098 * Line Size, that'll involve a Read-Modify-Write cycle on the
7099 * Memory Controller which is never good.
7100 */
7102 /* We want the Packing Boundary to be based on the Cache Line
7103 * Size in order to help avoid False Sharing performance
7104 * issues between CPUs, etc. We also want the Packing
7105 * Boundary to incorporate the PCI-E Maximum Payload Size. We
7106 * get best performance when the Packing Boundary is a
7107 * multiple of the Maximum Payload Size.
7108 */
7113 u16 devctl;
7115 /* The PCIe Device Control Maximum Payload Size field
7116 * [bits 7:5] encodes sizes as powers of 2 starting at
7117 * 128 bytes.
7118 */
7126 }
7128 /* N.B. T5/T6 have a crazy special interpretation of the "0"
7129 * value for the Packing Boundary. This corresponds to 16
7130 * bytes instead of the expected 32 bytes. So if we want 32
7131 * bytes, the best we can really do is 64 bytes ...
7132 */
7144 }
7146 /* Use the smallest Ingress Padding which isn't smaller than
7147 * the Memory Controller Read/Write Size. We'll take that as
7148 * being 8 bytes since we don't know of any system with a
7149 * wider Memory Controller Bus Width.
7150 */
7153 else
7158 EGRSTATUSPAGESIZE_F,
7164 }
7165 /*
7166 * Adjust various SGE Free List Host Buffer Sizes.
7167 *
7168 * This is something of a crock since we're using fixed indices into
7169 * the array which are also known by the sge.c code and the T4
7170 * Firmware Configuration File. We need to come up with a much better
7171 * approach to managing this array. For now, the first four entries
7172 * are:
7173 *
7174 * 0: Host Page Size
7175 * 1: 64KB
7176 * 2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
7177 * 3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
7178 *
7179 * For the single-MTU buffers in unpacked mode we need to include
7180 * space for the SGE Control Packet Shift, 14 byte Ethernet header,
7181 * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
7182 * Padding boundary. All of these are accommodated in the Factory
7183 * Default Firmware Configuration File but we need to adjust it for
7184 * this host's cache line size.
7185 */
7197 }
7199 /**
7200 * t4_fw_initialize - ask FW to initialize the device
7201 * @adap: the adapter
7202 * @mbox: mailbox to use for the FW command
7203 *
7204 * Issues a command to FW to partially initialize the device. This
7205 * performs initialization that generally doesn't depend on user input.
7206 */
7208 {
7214 }
7216 /**
7217 * t4_query_params_rw - query FW or device parameters
7218 * @adap: the adapter
7219 * @mbox: mailbox to use for the FW command
7220 * @pf: the PF
7221 * @vf: the VF
7222 * @nparams: the number of parameters
7223 * @params: the parameter names
7224 * @val: the parameter values
7225 * @rw: Write and read flag
7226 * @sleep_ok: if true, we may sleep awaiting mbox cmd completion
7227 *
7228 * Reads the value of FW or device parameters. Up to 7 parameters can be
7229 * queried at once.
7230 */
7234 {
7253 p++;
7254 }
7261 }
7266 {
7269 }
7274 {
7277 }
7279 /**
7280 * t4_set_params_timeout - sets FW or device parameters
7281 * @adap: the adapter
7282 * @mbox: mailbox to use for the FW command
7283 * @pf: the PF
7284 * @vf: the VF
7285 * @nparams: the number of parameters
7286 * @params: the parameter names
7287 * @val: the parameter values
7288 * @timeout: the timeout time
7289 *
7290 * Sets the value of FW or device parameters. Up to 7 parameters can be
7291 * specified at once.
7292 */
7297 {
7314 }
7317 }
7319 /**
7320 * t4_set_params - sets FW or device parameters
7321 * @adap: the adapter
7322 * @mbox: mailbox to use for the FW command
7323 * @pf: the PF
7324 * @vf: the VF
7325 * @nparams: the number of parameters
7326 * @params: the parameter names
7327 * @val: the parameter values
7328 *
7329 * Sets the value of FW or device parameters. Up to 7 parameters can be
7330 * specified at once.
7331 */
7335 {
7337 FW_CMD_MAX_TIMEOUT);
7338 }
7340 /**
7341 * t4_cfg_pfvf - configure PF/VF resource limits
7342 * @adap: the adapter
7343 * @mbox: mailbox to use for the FW command
7344 * @pf: the PF being configured
7345 * @vf: the VF being configured
7346 * @txq: the max number of egress queues
7347 * @txq_eth_ctrl: the max number of egress Ethernet or control queues
7348 * @rxqi: the max number of interrupt-capable ingress queues
7349 * @rxq: the max number of interruptless ingress queues
7350 * @tc: the PCI traffic class
7351 * @vi: the max number of virtual interfaces
7352 * @cmask: the channel access rights mask for the PF/VF
7353 * @pmask: the port access rights mask for the PF/VF
7354 * @nexact: the maximum number of exact MPS filters
7355 * @rcaps: read capabilities
7356 * @wxcaps: write/execute capabilities
7357 *
7358 * Configures resource limits and capabilities for a physical or virtual
7359 * function.
7360 */
7366 {
7386 }
7388 /**
7389 * t4_alloc_vi - allocate a virtual interface
7390 * @adap: the adapter
7391 * @mbox: mailbox to use for the FW command
7392 * @port: physical port associated with the VI
7393 * @pf: the PF owning the VI
7394 * @vf: the VF owning the VI
7395 * @nmac: number of MAC addresses needed (1 to 5)
7396 * @mac: the MAC addresses of the VI
7397 * @rss_size: size of RSS table slice associated with this VI
7398 *
7399 * Allocates a virtual interface for the given physical port. If @mac is
7400 * not %NULL it contains the MAC addresses of the VI as assigned by FW.
7401 * @mac should be large enough to hold @nmac Ethernet addresses, they are
7402 * stored consecutively so the space needed is @nmac * 6 bytes.
7403 * Returns a negative error number or the non-negative VI id.
7404 */
7408 {
7435 }
7436 }
7440 }
7442 /**
7443 * t4_free_vi - free a virtual interface
7444 * @adap: the adapter
7445 * @mbox: mailbox to use for the FW command
7446 * @pf: the PF owning the VI
7447 * @vf: the VF owning the VI
7448 * @viid: virtual interface identifiler
7449 *
7450 * Free a previously allocated virtual interface.
7451 */
7454 {
7459 FW_CMD_REQUEST_F |
7460 FW_CMD_EXEC_F |
7467 }
7469 /**
7470 * t4_set_rxmode - set Rx properties of a virtual interface
7471 * @adap: the adapter
7472 * @mbox: mailbox to use for the FW command
7473 * @viid: the VI id
7474 * @mtu: the new MTU or -1
7475 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
7476 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
7477 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
7478 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
7479 * @sleep_ok: if true we may sleep while awaiting command completion
7480 *
7481 * Sets Rx properties of a virtual interface.
7482 */
7486 {
7489 /* convert to FW values */
7513 }
7515 /**
7516 * t4_free_raw_mac_filt - Frees a raw mac entry in mps tcam
7517 * @adap: the adapter
7518 * @viid: the VI id
7519 * @addr: the MAC address
7520 * @mask: the mask
7521 * @idx: index of the entry in mps tcam
7522 * @lookup_type: MAC address for inner (1) or outer (0) header
7523 * @port_id: the port index
7524 * @sleep_ok: call is allowed to sleep
7525 *
7526 * Removes the mac entry at the specified index using raw mac interface.
7527 *
7528 * Returns a negative error number on failure.
7529 */
7533 {
7536 u32 val;
7549 FW_VI_MAC_ID_BASED_FREE);
7551 /* Lookup Type. Outer header: 0, Inner header: 1 */
7554 /* Lookup mask and port mask */
7558 /* Copy the address and the mask */
7563 }
7565 /**
7566 * t4_alloc_raw_mac_filt - Adds a mac entry in mps tcam
7567 * @adap: the adapter
7568 * @viid: the VI id
7569 * @mac: the MAC address
7570 * @mask: the mask
7571 * @idx: index at which to add this entry
7572 * @port_id: the port index
7573 * @lookup_type: MAC address for inner (1) or outer (0) header
7574 * @sleep_ok: call is allowed to sleep
7575 *
7576 * Adds the mac entry at the specified index using raw mac interface.
7577 *
7578 * Returns a negative error number or the allocated index for this mac.
7579 */
7583 {
7587 u32 val;
7597 /* Specify that this is an inner mac address */
7600 /* Lookup Type. Outer header: 0, Inner header: 1 */
7603 /* Lookup mask and port mask */
7607 /* Copy the address and the mask */
7616 }
7619 }
7621 /**
7622 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
7623 * @adap: the adapter
7624 * @mbox: mailbox to use for the FW command
7625 * @viid: the VI id
7626 * @free: if true any existing filters for this VI id are first removed
7627 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
7628 * @addr: the MAC address(es)
7629 * @idx: where to store the index of each allocated filter
7630 * @hash: pointer to hash address filter bitmap
7631 * @sleep_ok: call is allowed to sleep
7632 *
7633 * Allocates an exact-match filter for each of the supplied addresses and
7634 * sets it to the corresponding address. If @idx is not %NULL it should
7635 * have at least @naddr entries, each of which will be set to the index of
7636 * the filter allocated for the corresponding MAC address. If a filter
7637 * could not be allocated for an address its index is set to 0xffff.
7638 * If @hash is not %NULL addresses that fail to allocate an exact filter
7639 * are hashed and update the hash filter bitmap pointed at by @hash.
7640 *
7641 * Returns a negative error number or the number of filters allocated.
7642 */
7646 {
7666 FW_CMD_REQUEST_F |
7667 FW_CMD_WRITE_F |
7678 FW_VI_MAC_ADD_MAC));
7681 }
7683 /* It's okay if we run out of space in our MAC address arena.
7684 * Some of the addresses we submit may get stored so we need
7685 * to run through the reply to see what the results were ...
7686 */
7699 nfilters++;
7703 }
7708 }
7713 }
7715 /**
7716 * t4_free_mac_filt - frees exact-match filters of given MAC addresses
7717 * @adap: the adapter
7718 * @mbox: mailbox to use for the FW command
7719 * @viid: the VI id
7720 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
7721 * @addr: the MAC address(es)
7722 * @sleep_ok: call is allowed to sleep
7723 *
7724 * Frees the exact-match filter for each of the supplied addresses
7725 *
7726 * Returns a negative error number or the number of filters freed.
7727 */
7731 {
7736 NUM_MPS_CLS_SRAM_L_INSTANCES :
7737 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
7745 ? rem
7754 FW_CMD_REQUEST_F |
7755 FW_CMD_WRITE_F |
7764 FW_VI_MAC_CMD_VALID_F |
7767 }
7778 nfilters++;
7779 }
7783 }
7788 }
7790 /**
7791 * t4_change_mac - modifies the exact-match filter for a MAC address
7792 * @adap: the adapter
7793 * @mbox: mailbox to use for the FW command
7794 * @viid: the VI id
7795 * @idx: index of existing filter for old value of MAC address, or -1
7796 * @addr: the new MAC address value
7797 * @persist: whether a new MAC allocation should be persistent
7798 * @add_smt: if true also add the address to the HW SMT
7799 *
7800 * Modifies an exact-match filter and sets it to the new MAC address.
7801 * Note that in general it is not possible to modify the value of a given
7802 * filter so the generic way to modify an address filter is to free the one
7803 * being used by the old address value and allocate a new filter for the
7804 * new address value. @idx can be -1 if the address is a new addition.
7805 *
7806 * Returns a negative error number or the index of the filter with the new
7807 * MAC value.
7808 */
7811 {
7836 }
7838 }
7840 /**
7841 * t4_set_addr_hash - program the MAC inexact-match hash filter
7842 * @adap: the adapter
7843 * @mbox: mailbox to use for the FW command
7844 * @viid: the VI id
7845 * @ucast: whether the hash filter should also match unicast addresses
7846 * @vec: the value to be written to the hash filter
7847 * @sleep_ok: call is allowed to sleep
7848 *
7849 * Sets the 64-bit inexact-match hash filter for a virtual interface.
7850 */
7853 {
7865 }
7867 /**
7868 * t4_enable_vi_params - enable/disable a virtual interface
7869 * @adap: the adapter
7870 * @mbox: mailbox to use for the FW command
7871 * @viid: the VI id
7872 * @rx_en: 1=enable Rx, 0=disable Rx
7873 * @tx_en: 1=enable Tx, 0=disable Tx
7874 * @dcb_en: 1=enable delivery of Data Center Bridging messages.
7875 *
7876 * Enables/disables a virtual interface. Note that setting DCB Enable
7877 * only makes sense when enabling a Virtual Interface ...
7878 */
7881 {
7893 }
7895 /**
7896 * t4_enable_vi - enable/disable a virtual interface
7897 * @adap: the adapter
7898 * @mbox: mailbox to use for the FW command
7899 * @viid: the VI id
7900 * @rx_en: 1=enable Rx, 0=disable Rx
7901 * @tx_en: 1=enable Tx, 0=disable Tx
7902 *
7903 * Enables/disables a virtual interface.
7904 */
7907 {
7909 }
7911 /**
7912 * t4_identify_port - identify a VI's port by blinking its LED
7913 * @adap: the adapter
7914 * @mbox: mailbox to use for the FW command
7915 * @viid: the VI id
7916 * @nblinks: how many times to blink LED at 2.5 Hz
7917 *
7918 * Identifies a VI's port by blinking its LED.
7919 */
7922 {
7932 }
7934 /**
7935 * t4_iq_stop - stop an ingress queue and its FLs
7936 * @adap: the adapter
7937 * @mbox: mailbox to use for the FW command
7938 * @pf: the PF owning the queues
7939 * @vf: the VF owning the queues
7940 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
7941 * @iqid: ingress queue id
7942 * @fl0id: FL0 queue id or 0xffff if no attached FL0
7943 * @fl1id: FL1 queue id or 0xffff if no attached FL1
7944 *
7945 * Stops an ingress queue and its associated FLs, if any. This causes
7946 * any current or future data/messages destined for these queues to be
7947 * tossed.
7948 */
7952 {
7965 }
7967 /**
7968 * t4_iq_free - free an ingress queue and its FLs
7969 * @adap: the adapter
7970 * @mbox: mailbox to use for the FW command
7971 * @pf: the PF owning the queues
7972 * @vf: the VF owning the queues
7973 * @iqtype: the ingress queue type
7974 * @iqid: ingress queue id
7975 * @fl0id: FL0 queue id or 0xffff if no attached FL0
7976 * @fl1id: FL1 queue id or 0xffff if no attached FL1
7977 *
7978 * Frees an ingress queue and its associated FLs, if any.
7979 */
7983 {
7996 }
7998 /**
7999 * t4_eth_eq_free - free an Ethernet egress queue
8000 * @adap: the adapter
8001 * @mbox: mailbox to use for the FW command
8002 * @pf: the PF owning the queue
8003 * @vf: the VF owning the queue
8004 * @eqid: egress queue id
8005 *
8006 * Frees an Ethernet egress queue.
8007 */
8010 {
8021 }
8023 /**
8024 * t4_ctrl_eq_free - free a control egress queue
8025 * @adap: the adapter
8026 * @mbox: mailbox to use for the FW command
8027 * @pf: the PF owning the queue
8028 * @vf: the VF owning the queue
8029 * @eqid: egress queue id
8030 *
8031 * Frees a control egress queue.
8032 */
8035 {
8046 }
8048 /**
8049 * t4_ofld_eq_free - free an offload egress queue
8050 * @adap: the adapter
8051 * @mbox: mailbox to use for the FW command
8052 * @pf: the PF owning the queue
8053 * @vf: the VF owning the queue
8054 * @eqid: egress queue id
8055 *
8056 * Frees a control egress queue.
8057 */
8060 {
8071 }
8073 /**
8074 * t4_link_down_rc_str - return a string for a Link Down Reason Code
8075 * @adap: the adapter
8076 * @link_down_rc: Link Down Reason Code
8077 *
8078 * Returns a string representation of the Link Down Reason Code.
8079 */
8081 {
8091 };
8097 }
8099 /**
8100 * Return the highest speed set in the port capabilities, in Mb/s.
8101 */
8103 {
8104 #define TEST_SPEED_RETURN(__caps_speed, __speed) \
8105 do { \
8106 if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \
8107 return __speed; \
8108 } while (0)
8120 #undef TEST_SPEED_RETURN
8123 }
8125 /**
8126 * fwcap_to_fwspeed - return highest speed in Port Capabilities
8127 * @acaps: advertised Port Capabilities
8128 *
8129 * Get the highest speed for the port from the advertised Port
8130 * Capabilities. It will be either the highest speed from the list of
8131 * speeds or whatever user has set using ethtool.
8132 */
8134 {
8135 #define TEST_SPEED_RETURN(__caps_speed) \
8136 do { \
8137 if (acaps & FW_PORT_CAP32_SPEED_##__caps_speed) \
8138 return FW_PORT_CAP32_SPEED_##__caps_speed; \
8139 } while (0)
8151 #undef TEST_SPEED_RETURN
8154 }
8156 /**
8157 * lstatus_to_fwcap - translate old lstatus to 32-bit Port Capabilities
8158 * @lstatus: old FW_PORT_ACTION_GET_PORT_INFO lstatus value
8159 *
8160 * Translates old FW_PORT_ACTION_GET_PORT_INFO lstatus field into new
8161 * 32-bit Port Capabilities value.
8162 */
8164 {
8167 /* Unfortunately the format of the Link Status in the old
8168 * 16-bit Port Information message isn't the same as the
8169 * 16-bit Port Capabilities bitfield used everywhere else ...
8170 */
8189 }
8191 /**
8192 * t4_handle_get_port_info - process a FW reply message
8193 * @pi: the port info
8194 * @rpl: start of the FW message
8195 *
8196 * Processes a GET_PORT_INFO FW reply message.
8197 */
8199 {
8210 /* Extract the various fields from the Port Information message.
8211 */
8225 }
8228 u32 lstatus32;
8240 }
8246 }
8253 /* With the newer SFP28 and QSFP28 Transceiver Module Types,
8254 * various fundamental Port Capabilities which used to be
8255 * immutable can now change radically. We can now have
8256 * Speeds, Auto-Negotiation, Forward Error Correction, etc.
8257 * all change based on what Transceiver Module is inserted.
8258 * So we need to record the Physical "Port" Capabilities on
8259 * every Transceiver Module change.
8260 */
8263 /* When a new Transceiver Module is inserted, the Firmware
8264 * will examine its i2c EPROM to determine its type and
8265 * general operating parameters including things like Forward
8266 * Error Control, etc. Various IEEE 802.3 standards dictate
8267 * how to interpret these i2c values to determine default
8268 * "sutomatic" settings. We record these for future use when
8269 * the user explicitly requests these standards-based values.
8270 */
8273 /* Some versions of the early T6 Firmware "cheated" when
8274 * handling different Transceiver Modules by changing the
8275 * underlaying Port Type reported to the Host Drivers. As
8276 * such we need to capture whatever Port Type the Firmware
8277 * sends us and record it in case it's different from what we
8278 * were told earlier. Unfortunately, since Firmware is
8279 * forever, we'll need to keep this code here forever, but in
8280 * later T6 Firmware it should just be an assignment of the
8281 * same value already recorded.
8282 */
8287 }
8295 }
8307 /* When Autoneg is disabled, user needs to set
8308 * single speed.
8309 * Similar to cxgb4_ethtool.c: set_link_ksettings
8310 */
8314 }
8317 }
8318 }
8320 /**
8321 * t4_update_port_info - retrieve and update port information if changed
8322 * @pi: the port_info
8323 *
8324 * We issue a Get Port Information Command to the Firmware and, if
8325 * successful, we check to see if anything is different from what we
8326 * last recorded and update things accordingly.
8327 */
8329 {
8340 ? FW_PORT_ACTION_GET_PORT_INFO
8350 }
8352 /**
8353 * t4_get_link_params - retrieve basic link parameters for given port
8354 * @pi: the port
8355 * @link_okp: value return pointer for link up/down
8356 * @speedp: value return pointer for speed (Mb/s)
8357 * @mtup: value return pointer for mtu
8358 *
8359 * Retrieves basic link parameters for a port: link up/down, speed (Mb/s),
8360 * and MTU for a specified port. A negative error is returned on
8361 * failure; 0 on success.
8362 */
8365 {
8369 fw_port_cap32_t linkattr;
8377 ? FW_PORT_ACTION_GET_PORT_INFO
8394 u32 lstatus32 =
8401 }
8409 }
8411 /**
8412 * t4_handle_fw_rpl - process a FW reply message
8413 * @adap: the adapter
8414 * @rpl: start of the FW message
8415 *
8416 * Processes a FW message, such as link state change messages.
8417 */
8419 {
8422 /* This might be a port command ... this simplifies the following
8423 * conditionals ... We can get away with pre-dereferencing
8424 * action_to_len16 because it's in the first 16 bytes and all messages
8425 * will be at least that long.
8426 */
8442 }
8447 opcode);
8449 }
8451 }
8454 {
8455 u16 val;
8461 }
8462 }
8464 /**
8465 * init_link_config - initialize a link's SW state
8466 * @lc: pointer to structure holding the link state
8467 * @pcaps: link Port Capabilities
8468 * @acaps: link current Advertised Port Capabilities
8469 *
8470 * Initializes the SW state maintained for each link, including the link's
8471 * capabilities and default speed/flow-control/autonegotiation settings.
8472 */
8474 fw_port_cap32_t acaps)
8475 {
8483 /* For Forward Error Control, we default to whatever the Firmware
8484 * tells us the Link is currently advertising.
8485 */
8496 }
8497 }
8499 #define CIM_PF_NOACCESS 0xeeeeeeee
8502 {
8503 u32 whoami;
8512 }
8515 u32 vendor_and_model_id;
8516 u32 size_mb;
8517 };
8520 {
8521 /* Table for non-Numonix supported flash parts. Numonix parts are left
8522 * to the preexisting code. All flash parts have 64KB sectors.
8523 */
8526 };
8533 /* Issue a Read ID Command to the Flash part. We decode supported
8534 * Flash parts and their sizes from this. There's a newer Query
8535 * Command which can retrieve detailed geometry information but many
8536 * Flash parts don't support it.
8537 */
8546 /* Check to see if it's one of our non-standard supported Flash parts.
8547 */
8554 }
8556 /* Decode Flash part size. The code below looks repetative with
8557 * common encodings, but that's not guaranteed in the JEDEC
8558 * specification for the Read JADEC ID command. The only thing that
8559 * we're guaranteed by the JADEC specification is where the
8560 * Manufacturer ID is in the returned result. After that each
8561 * Manufacturer ~could~ encode things completely differently.
8562 * Note, all Flash parts must have 64KB sectors.
8563 */
8567 /* This Density -> Size decoding table is taken from Micron
8568 * Data Sheets.
8569 */
8604 }
8606 }
8608 /* This Density -> Size decoding table is taken from ISSI
8609 * Data Sheets.
8610 */
8623 }
8625 }
8627 /* This Density -> Size decoding table is taken from Macronix
8628 * Data Sheets.
8629 */
8642 }
8644 }
8646 /* This Density -> Size decoding table is taken from Winbond
8647 * Data Sheets.
8648 */
8661 }
8663 }
8666 flashid);
8668 }
8670 /* Store decoded Flash size and fall through into vetting code. */
8674 found:
8679 }
8681 /**
8682 * t4_prep_adapter - prepare SW and HW for operation
8683 * @adapter: the adapter
8684 * @reset: if true perform a HW reset
8685 *
8686 * Initialize adapter SW state for the various HW modules, set initial
8687 * values for some adapter tunables, take PHYs out of reset, and
8688 * initialize the MDIO interface.
8689 */
8691 {
8694 u32 pl_rev;
8703 }
8705 /* Retrieve adapter's device ID
8706 */
8715 NUM_MPS_CLS_SRAM_L_INSTANCES;
8720 /* Congestion map is for 4 channels so that
8721 * MPS can have 4 priority per port.
8722 */
8729 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
8740 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
8745 /* Congestion map will be for 2 channels so that
8746 * MPS can have 8 priority per port.
8747 */
8752 device_id);
8754 }
8759 /*
8760 * Default port for debugging in case we can't reach FW.
8761 */
8766 /* Set PCIe completion timeout to 4 seconds. */
8770 }
8772 /**
8773 * t4_shutdown_adapter - shut down adapter, host & wire
8774 * @adapter: the adapter
8775 *
8776 * Perform an emergency shutdown of the adapter and stop it from
8777 * continuing any further communication on the ports or DMA to the
8778 * host. This is typically used when the adapter and/or firmware
8779 * have crashed and we want to prevent any further accidental
8780 * communication with the rest of the world. This will also force
8781 * the port Link Status to go down -- if register writes work --
8782 * which should help our peers figure out that we're down.
8783 */
8785 {
8798 }
8802 }
8804 /**
8805 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information
8806 * @adapter: the adapter
8807 * @qid: the Queue ID
8808 * @qtype: the Ingress or Egress type for @qid
8809 * @user: true if this request is for a user mode queue
8810 * @pbar2_qoffset: BAR2 Queue Offset
8811 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
8812 *
8813 * Returns the BAR2 SGE Queue Registers information associated with the
8814 * indicated Absolute Queue ID. These are passed back in return value
8815 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
8816 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
8817 *
8818 * This may return an error which indicates that BAR2 SGE Queue
8819 * registers aren't available. If an error is not returned, then the
8820 * following values are returned:
8821 *
8822 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
8823 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
8824 *
8825 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
8826 * require the "Inferred Queue ID" ability may be used. E.g. the
8827 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
8828 * then these "Inferred Queue ID" register may not be used.
8829 */
8836 {
8841 /* T4 doesn't support BAR2 SGE Queue registers for kernel mode queues */
8845 /* Get our SGE Page Size parameters.
8846 */
8850 /* Get the right Queues per Page parameters for our Queue.
8851 */
8857 /* Calculate the basics of the BAR2 SGE Queue register area:
8858 * o The BAR2 page the Queue registers will be in.
8859 * o The BAR2 Queue ID.
8860 * o The BAR2 Queue ID Offset into the BAR2 page.
8861 */
8866 /* If the BAR2 Queue ID Offset is less than the Page Size, then the
8867 * hardware will infer the Absolute Queue ID simply from the writes to
8868 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
8869 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply
8870 * write to the first BAR2 SGE Queue Area within the BAR2 Page with
8871 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
8872 * from the BAR2 Page and BAR2 Queue ID.
8873 *
8874 * One important censequence of this is that some BAR2 SGE registers
8875 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
8876 * there. But other registers synthesize the SGE Queue ID purely
8877 * from the writes to the registers -- the Write Combined Doorbell
8878 * Buffer is a good example. These BAR2 SGE Registers are only
8879 * available for those BAR2 SGE Register areas where the SGE Absolute
8880 * Queue ID can be inferred from simple writes.
8881 */
8887 }
8892 }
8894 /**
8895 * t4_init_devlog_params - initialize adapter->params.devlog
8896 * @adap: the adapter
8897 *
8898 * Initialize various fields of the adapter's Firmware Device Log
8899 * Parameters structure.
8900 */
8902 {
8904 u32 pf_dparams;
8909 /* If we're dealing with newer firmware, the Device Log Paramerters
8910 * are stored in a designated register which allows us to access the
8911 * Device Log even if we can't talk to the firmware.
8912 */
8913 pf_dparams =
8926 }
8928 /* Otherwise, ask the firmware for it's Device Log Parameters.
8929 */
8939 devlog_meminfo =
8946 }
8948 /**
8949 * t4_init_sge_params - initialize adap->params.sge
8950 * @adapter: the adapter
8951 *
8952 * Initialize various fields of the adapter's SGE Parameters structure.
8953 */
8955 {
8960 /* Extract the SGE Page Size for our PF.
8961 */
8967 /* Extract the SGE Egress and Ingess Queues Per Page for our PF.
8968 */
8977 }
8979 /**
8980 * t4_init_tp_params - initialize adap->params.tp
8981 * @adap: the adapter
8982 * @sleep_ok: if true we may sleep while awaiting command completion
8983 *
8984 * Initialize various fields of the adapter's TP Parameters structure.
8985 */
8987 {
8989 u32 v;
8995 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
8999 /* Cache the adapter's Compressed Filter Mode and global Incress
9000 * Configuration.
9001 */
9007 /* For T6, cache the adapter's compressed error vector
9008 * and passing outer header info for encapsulated packets.
9009 */
9013 }
9015 /* Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
9016 * shift positions of several elements of the Compressed Filter Tuple
9017 * for this adapter which we need frequently ...
9018 */
9025 PROTOCOL_F);
9027 ETHERTYPE_F);
9029 MACMATCH_F);
9031 MPSHITTYPE_F);
9033 FRAGMENTATION_F);
9035 /* If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
9036 * represents the presence of an Outer VLAN instead of a VNIC ID.
9037 */
9046 }
9048 /**
9049 * t4_filter_field_shift - calculate filter field shift
9050 * @adap: the adapter
9051 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
9052 *
9053 * Return the shift position of a filter field within the Compressed
9054 * Filter Tuple. The filter field is specified via its selection bit
9055 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN.
9056 */
9058 {
9098 }
9099 }
9101 }
9104 {
9122 }
9124 }
9126 /**
9127 * t4_init_portinfo - allocate a virtual interface and initialize port_info
9128 * @pi: the port_info
9129 * @mbox: mailbox to use for the FW command
9130 * @port: physical port associated with the VI
9131 * @pf: the PF owning the VI
9132 * @vf: the VF owning the VI
9133 * @mac: the MAC address of the VI
9134 *
9135 * Allocates a virtual interface for the given physical port. If @mac is
9136 * not %NULL it contains the MAC address of the VI as assigned by FW.
9137 * @mac should be large enough to hold an Ethernet address.
9138 * Returns < 0 on error.
9139 */
9142 {
9152 /* If we haven't yet determined whether we're talking to Firmware
9153 * which knows the new 32-bit Port Capabilities, it's time to find
9154 * out now. This will also tell new Firmware to send us Port Status
9155 * Updates using the new 32-bit Port Capabilities version of the
9156 * Port Information message.
9157 */
9167 }
9175 ? FW_PORT_ACTION_GET_PORT_INFO
9182 /* Extract the various fields from the Port Information message.
9183 */
9202 }
9219 }
9222 {
9230 j++;
9237 j++;
9238 }
9240 }
9242 /**
9243 * t4_read_cimq_cfg - read CIM queue configuration
9244 * @adap: the adapter
9245 * @base: holds the queue base addresses in bytes
9246 * @size: holds the queue sizes in bytes
9247 * @thres: holds the queue full thresholds in bytes
9248 *
9249 * Returns the current configuration of the CIM queues, starting with
9250 * the IBQs, then the OBQs.
9251 */
9253 {
9262 /* value is in 256-byte units */
9266 }
9271 /* value is in 256-byte units */
9274 }
9275 }
9277 /**
9278 * t4_read_cim_ibq - read the contents of a CIM inbound queue
9279 * @adap: the adapter
9280 * @qid: the queue index
9281 * @data: where to store the queue contents
9282 * @n: capacity of @data in 32-bit words
9283 *
9284 * Reads the contents of the selected CIM queue starting at address 0 up
9285 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
9286 * error and the number of 32-bit words actually read on success.
9287 */
9289 {
9301 /* It might take 3-10ms before the IBQ debug read access is allowed.
9302 * Wait for 1 Sec with a delay of 1 usec.
9303 */
9308 IBQDBGEN_F);
9314 }
9317 }
9319 /**
9320 * t4_read_cim_obq - read the contents of a CIM outbound queue
9321 * @adap: the adapter
9322 * @qid: the queue index
9323 * @data: where to store the queue contents
9324 * @n: capacity of @data in 32-bit words
9325 *
9326 * Reads the contents of the selected CIM queue starting at address 0 up
9327 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
9328 * error and the number of 32-bit words actually read on success.
9329 */
9331 {
9351 OBQDBGEN_F);
9357 }
9360 }
9362 /**
9363 * t4_cim_read - read a block from CIM internal address space
9364 * @adap: the adapter
9365 * @addr: the start address within the CIM address space
9366 * @n: number of words to read
9367 * @valp: where to store the result
9368 *
9369 * Reads a block of 4-byte words from the CIM intenal address space.
9370 */
9373 {
9385 }
9387 }
9389 /**
9390 * t4_cim_write - write a block into CIM internal address space
9391 * @adap: the adapter
9392 * @addr: the start address within the CIM address space
9393 * @n: number of words to write
9394 * @valp: set of values to write
9395 *
9396 * Writes a block of 4-byte words into the CIM intenal address space.
9397 */
9400 {
9411 }
9413 }
9417 {
9419 }
9421 /**
9422 * t4_cim_read_la - read CIM LA capture buffer
9423 * @adap: the adapter
9424 * @la_buf: where to store the LA data
9425 * @wrptr: the HW write pointer within the capture buffer
9426 *
9427 * Reads the contents of the CIM LA buffer with the most recent entry at
9428 * the end of the returned data and with the entry at @wrptr first.
9429 * We try to leave the LA in the running state we find it in.
9430 */
9432 {
9444 }
9465 }
9470 /* Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to
9471 * identify the 32-bit portion of the full 312-bit data
9472 */
9475 else
9476 idx++;
9477 /* address can't exceed 0xfff */
9479 }
9480 restart:
9486 }
9488 }
9490 /**
9491 * t4_tp_read_la - read TP LA capture buffer
9492 * @adap: the adapter
9493 * @la_buf: where to store the LA data
9494 * @wrptr: the HW write pointer within the capture buffer
9495 *
9496 * Reads the contents of the TP LA buffer with the most recent entry at
9497 * the end of the returned data and with the entry at @wrptr first.
9498 * We leave the LA in the running state we find it in.
9499 */
9501 {
9526 }
9528 /* Wipe out last entry if it isn't valid */
9535 }
9537 /* SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in
9538 * seconds). If we find one of the SGE Ingress DMA State Machines in the same
9539 * state for more than the Warning Threshold then we'll issue a warning about
9540 * a potential hang. We'll repeat the warning as the SGE Ingress DMA Channel
9541 * appears to be hung every Warning Repeat second till the situation clears.
9542 * If the situation clears, we'll note that as well.
9543 */
9544 #define SGE_IDMA_WARN_THRESH 1
9545 #define SGE_IDMA_WARN_REPEAT 300
9547 /**
9548 * t4_idma_monitor_init - initialize SGE Ingress DMA Monitor
9549 * @adapter: the adapter
9550 * @idma: the adapter IDMA Monitor state
9551 *
9552 * Initialize the state of an SGE Ingress DMA Monitor.
9553 */
9556 {
9557 /* Initialize the state variables for detecting an SGE Ingress DMA
9558 * hang. The SGE has internal counters which count up on each clock
9559 * tick whenever the SGE finds its Ingress DMA State Engines in the
9560 * same state they were on the previous clock tick. The clock used is
9561 * the Core Clock so we have a limit on the maximum "time" they can
9562 * record; typically a very small number of seconds. For instance,
9563 * with a 600MHz Core Clock, we can only count up to a bit more than
9564 * 7s. So we'll synthesize a larger counter in order to not run the
9565 * risk of having the "timers" overflow and give us the flexibility to
9566 * maintain a Hung SGE State Machine of our own which operates across
9567 * a longer time frame.
9568 */
9572 }
9574 /**
9575 * t4_idma_monitor - monitor SGE Ingress DMA state
9576 * @adapter: the adapter
9577 * @idma: the adapter IDMA Monitor state
9578 * @hz: number of ticks/second
9579 * @ticks: number of ticks since the last IDMA Monitor call
9580 */
9584 {
9587 /* Read the SGE Debug Ingress DMA Same State Count registers. These
9588 * are counters inside the SGE which count up on each clock when the
9589 * SGE finds its Ingress DMA State Engines in the same states they
9590 * were in the previous clock. The counters will peg out at
9591 * 0xffffffff without wrapping around so once they pass the 1s
9592 * threshold they'll stay above that till the IDMA state changes.
9593 */
9601 /* If the Ingress DMA Same State Counter ("timer") is less
9602 * than 1s, then we can reset our synthesized Stall Timer and
9603 * continue. If we have previously emitted warnings about a
9604 * potential stalled Ingress Queue, issue a note indicating
9605 * that the Ingress Queue has resumed forward progress.
9606 */
9615 }
9617 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz
9618 * domain. The first time we get here it'll be because we
9619 * passed the 1s Threshold; each additional time it'll be
9620 * because the RX Timer Callback is being fired on its regular
9621 * schedule.
9622 *
9623 * If the stall is below our Potential Hung Ingress Queue
9624 * Warning Threshold, continue.
9625 */
9632 }
9637 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds.
9638 */
9643 /* Read and save the SGE IDMA State and Queue ID information.
9644 * We do this every time in case it changes across time ...
9645 * can't be too careful ...
9646 */
9661 }
9662 }
9664 /**
9665 * t4_load_cfg - download config file
9666 * @adap: the adapter
9667 * @cfg_data: the cfg text file to write
9668 * @size: text file size
9669 *
9670 * Write the supplied config text file to the card's serial flash.
9671 */
9673 {
9688 FLASH_CFG_MAX_SIZE);
9690 }
9693 sf_sec_size);
9696 /* If size == 0 then we're simply erasing the FLASH sectors associated
9697 * with the on-adapter Firmware Configuration File.
9698 */
9702 /* this will write to the flash up to SF_PAGE_SIZE at a time */
9706 else
9714 }
9716 out:
9721 }
9723 /**
9724 * t4_set_vf_mac - Set MAC address for the specified VF
9725 * @adapter: The adapter
9726 * @vf: one of the VFs instantiated by the specified PF
9727 * @naddr: the number of MAC addresses
9728 * @addr: the MAC address(es) to be set to the specified VF
9729 */
9732 {
9737 FW_CMD_REQUEST_F |
9738 FW_CMD_WRITE_F |
9742 /* Note: Do not enable the ACL */
9759 }
9762 }
9764 /**
9765 * t4_read_pace_tbl - read the pace table
9766 * @adap: the adapter
9767 * @pace_vals: holds the returned values
9768 *
9769 * Returns the values of TP's pace table in microseconds.
9770 */
9772 {
9779 }
9780 }
9782 /**
9783 * t4_get_tx_sched - get the configuration of a Tx HW traffic scheduler
9784 * @adap: the adapter
9785 * @sched: the scheduler index
9786 * @kbps: the byte rate in Kbps
9787 * @ipg: the interpacket delay in tenths of nanoseconds
9788 * @sleep_ok: if true we may sleep while awaiting command completion
9789 *
9790 * Return the current configuration of a HW Tx scheduler.
9791 */
9794 {
9809 }
9810 }
9818 }
9819 }
9821 /* t4_sge_ctxt_rd - read an SGE context through FW
9822 * @adap: the adapter
9823 * @mbox: mailbox to use for the FW command
9824 * @cid: the context id
9825 * @ctype: the context type
9826 * @data: where to store the context data
9827 *
9828 * Issues a FW command through the given mailbox to read an SGE context.
9829 */
9832 {
9838 else
9856 }
9858 }
9860 /**
9861 * t4_sge_ctxt_rd_bd - read an SGE context bypassing FW
9862 * @adap: the adapter
9863 * @cid: the context id
9864 * @ctype: the context type
9865 * @data: where to store the context data
9866 *
9867 * Reads an SGE context directly, bypassing FW. This is only for
9868 * debugging when FW is unavailable.
9869 */
9872 {
9881 }
9886 {
9891 FW_CMD_REQUEST_F |
9892 FW_CMD_WRITE_F);
9910 }
9912 /**
9913 * t4_i2c_rd - read I2C data from adapter
9914 * @adap: the adapter
9915 * @port: Port number if per-port device; <0 if not
9916 * @devid: per-port device ID or absolute device ID
9917 * @offset: byte offset into device I2C space
9918 * @len: byte length of I2C space data
9919 * @buf: buffer in which to return I2C data
9920 *
9921 * Reads the I2C data from the indicated device and location.
9922 */
9926 {
9934 /* Dont allow reads that spans multiple pages */
9941 FW_CMD_REQUEST_F |
9942 FW_CMD_READ_F |
9963 }
9966 }
9968 /**
9969 * t4_set_vlan_acl - Set a VLAN id for the specified VF
9970 * @adapter: the adapter
9971 * @mbox: mailbox to use for the FW command
9972 * @vf: one of the VFs instantiated by the specified PF
9973 * @vlan: The vlanid to be set
9974 */
9976 u16 vlan)
9977 {
9984 FW_CMD_REQUEST_F |
9985 FW_CMD_WRITE_F |
9986 FW_CMD_EXEC_F |
9990 /* Drop all packets that donot match vlan id */
9995 }
9998 }