arch/arm/mach-integrator/integrator_ap.c

   1 /*
   2  *  linux/arch/arm/mach-integrator/integrator_ap.c
   3  *
   4  *  Copyright (C) 2000-2003 Deep Blue Solutions Ltd
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include <linux/types.h>
  21 #include <linux/kernel.h>
  22 #include <linux/init.h>
  23 #include <linux/list.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/slab.h>
  26 #include <linux/string.h>
  27 #include <linux/syscore_ops.h>
  28 #include <linux/amba/bus.h>
  29 #include <linux/amba/kmi.h>
  30 #include <linux/io.h>
  31 #include <linux/irqchip.h>
  32 #include <linux/mtd/physmap.h>
  33 #include <linux/platform_data/clk-integrator.h>
  34 #include <linux/of_irq.h>
  35 #include <linux/of_address.h>
  36 #include <linux/of_platform.h>
  37 #include <linux/stat.h>
  38 #include <linux/termios.h>
  39
  40 #include <asm/setup.h>
  41 #include <asm/param.h>          /* HZ */
  42 #include <asm/mach-types.h>
  43
  44 #include <asm/mach/arch.h>
  45 #include <asm/mach/irq.h>
  46 #include <asm/mach/map.h>
  47 #include <asm/mach/time.h>
  48
  49 #include "hardware.h"
  50 #include "cm.h"
  51 #include "common.h"
  52 #include "pci_v3.h"
  53 #include "lm.h"
  54
  55 /* Base address to the AP system controller */
  56 void __iomem *ap_syscon_base;
  57 /* Base address to the external bus interface */
  58 static void __iomem *ebi_base;
  59
  60
  61 /*
  62  * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
  63  * is the (PA >> 12).
  64  *
  65  * Setup a VA for the Integrator interrupt controller (for header #0,
  66  * just for now).
  67  */
  68 #define VA_IC_BASE      __io_address(INTEGRATOR_IC_BASE)
  69
  70 /*
  71  * Logical      Physical
  72  * ef000000                     Cache flush
  73  * f1100000     11000000        System controller registers
  74  * f1300000     13000000        Counter/Timer
  75  * f1400000     14000000        Interrupt controller
  76  * f1600000     16000000        UART 0
  77  * f1700000     17000000        UART 1
  78  * f1a00000     1a000000        Debug LEDs
  79  * f1b00000     1b000000        GPIO
  80  */
  81
  82 static struct map_desc ap_io_desc[] __initdata __maybe_unused = {
  83         {
  84                 .virtual        = IO_ADDRESS(INTEGRATOR_IC_BASE),
  85                 .pfn            = __phys_to_pfn(INTEGRATOR_IC_BASE),
  86                 .length         = SZ_4K,
  87                 .type           = MT_DEVICE
  88         }, {
  89                 .virtual        = IO_ADDRESS(INTEGRATOR_UART0_BASE),
  90                 .pfn            = __phys_to_pfn(INTEGRATOR_UART0_BASE),
  91                 .length         = SZ_4K,
  92                 .type           = MT_DEVICE
  93         }, {
  94                 .virtual        = IO_ADDRESS(INTEGRATOR_DBG_BASE),
  95                 .pfn            = __phys_to_pfn(INTEGRATOR_DBG_BASE),
  96                 .length         = SZ_4K,
  97                 .type           = MT_DEVICE
  98         }, {
  99                 .virtual        = IO_ADDRESS(INTEGRATOR_AP_GPIO_BASE),
 100                 .pfn            = __phys_to_pfn(INTEGRATOR_AP_GPIO_BASE),
 101                 .length         = SZ_4K,
 102                 .type           = MT_DEVICE
 103         }
 104 };
 105
 106 static void __init ap_map_io(void)
 107 {
 108         iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
 109         pci_v3_early_init();
 110 }
 111
 112 #ifdef CONFIG_PM
 113 static unsigned long ic_irq_enable;
 114
 115 static int irq_suspend(void)
 116 {
 117         ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE);
 118         return 0;
 119 }
 120
 121 static void irq_resume(void)
 122 {
 123         /* disable all irq sources */
 124         cm_clear_irqs();
 125         writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
 126         writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
 127
 128         writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET);
 129 }
 130 #else
 131 #define irq_suspend NULL
 132 #define irq_resume NULL
 133 #endif
 134
 135 static struct syscore_ops irq_syscore_ops = {
 136         .suspend        = irq_suspend,
 137         .resume         = irq_resume,
 138 };
 139
 140 static int __init irq_syscore_init(void)
 141 {
 142         register_syscore_ops(&irq_syscore_ops);
 143
 144         return 0;
 145 }
 146
 147 device_initcall(irq_syscore_init);
 148
 149 /*
 150  * Flash handling.
 151  */
 152 static int ap_flash_init(struct platform_device *dev)
 153 {
 154         u32 tmp;
 155
 156         writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP,
 157                ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
 158
 159         tmp = readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET) |
 160                 INTEGRATOR_EBI_WRITE_ENABLE;
 161         writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET);
 162
 163         if (!(readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET)
 164               & INTEGRATOR_EBI_WRITE_ENABLE)) {
 165                 writel(0xa05f, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);
 166                 writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET);
 167                 writel(0, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);
 168         }
 169         return 0;
 170 }
 171
 172 static void ap_flash_exit(struct platform_device *dev)
 173 {
 174         u32 tmp;
 175
 176         writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP,
 177                ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
 178
 179         tmp = readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET) &
 180                 ~INTEGRATOR_EBI_WRITE_ENABLE;
 181         writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET);
 182
 183         if (readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET) &
 184             INTEGRATOR_EBI_WRITE_ENABLE) {
 185                 writel(0xa05f, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);
 186                 writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET);
 187                 writel(0, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);
 188         }
 189 }
 190
 191 static void ap_flash_set_vpp(struct platform_device *pdev, int on)
 192 {
 193         if (on)
 194                 writel(INTEGRATOR_SC_CTRL_nFLVPPEN,
 195                        ap_syscon_base + INTEGRATOR_SC_CTRLS_OFFSET);
 196         else
 197                 writel(INTEGRATOR_SC_CTRL_nFLVPPEN,
 198                        ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
 199 }
 200
 201 static struct physmap_flash_data ap_flash_data = {
 202         .width          = 4,
 203         .init           = ap_flash_init,
 204         .exit           = ap_flash_exit,
 205         .set_vpp        = ap_flash_set_vpp,
 206 };
 207
 208 /*
 209  * For the PL010 found in the Integrator/AP some of the UART control is
 210  * implemented in the system controller and accessed using a callback
 211  * from the driver.
 212  */
 213 static void integrator_uart_set_mctrl(struct amba_device *dev,
 214                                 void __iomem *base, unsigned int mctrl)
 215 {
 216         unsigned int ctrls = 0, ctrlc = 0, rts_mask, dtr_mask;
 217         u32 phybase = dev->res.start;
 218
 219         if (phybase == INTEGRATOR_UART0_BASE) {
 220                 /* UART0 */
 221                 rts_mask = 1 << 4;
 222                 dtr_mask = 1 << 5;
 223         } else {
 224                 /* UART1 */
 225                 rts_mask = 1 << 6;
 226                 dtr_mask = 1 << 7;
 227         }
 228
 229         if (mctrl & TIOCM_RTS)
 230                 ctrlc |= rts_mask;
 231         else
 232                 ctrls |= rts_mask;
 233
 234         if (mctrl & TIOCM_DTR)
 235                 ctrlc |= dtr_mask;
 236         else
 237                 ctrls |= dtr_mask;
 238
 239         __raw_writel(ctrls, ap_syscon_base + INTEGRATOR_SC_CTRLS_OFFSET);
 240         __raw_writel(ctrlc, ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
 241 }
 242
 243 struct amba_pl010_data ap_uart_data = {
 244         .set_mctrl = integrator_uart_set_mctrl,
 245 };
 246
 247 void __init ap_init_early(void)
 248 {
 249 }
 250
 251 static void __init ap_init_irq_of(void)
 252 {
 253         cm_init();
 254         irqchip_init();
 255 }
 256
 257 /* For the Device Tree, add in the UART callbacks as AUXDATA */
 258 static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = {
 259         OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
 260                 "rtc", NULL),
 261         OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
 262                 "uart0", &ap_uart_data),
 263         OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
 264                 "uart1", &ap_uart_data),
 265         OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
 266                 "kmi0", NULL),
 267         OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
 268                 "kmi1", NULL),
 269         OF_DEV_AUXDATA("cfi-flash", INTEGRATOR_FLASH_BASE,
 270                 "physmap-flash", &ap_flash_data),
 271         { /* sentinel */ },
 272 };
 273
 274 static const struct of_device_id ap_syscon_match[] = {
 275         { .compatible = "arm,integrator-ap-syscon"},
 276         { },
 277 };
 278
 279 static const struct of_device_id ebi_match[] = {
 280         { .compatible = "arm,external-bus-interface"},
 281         { },
 282 };
 283
 284 static void __init ap_init_of(void)
 285 {
 286         unsigned long sc_dec;
 287         struct device_node *syscon;
 288         struct device_node *ebi;
 289         int i;
 290
 291         syscon = of_find_matching_node(NULL, ap_syscon_match);
 292         if (!syscon)
 293                 return;
 294         ebi = of_find_matching_node(NULL, ebi_match);
 295         if (!ebi)
 296                 return;
 297
 298         ap_syscon_base = of_iomap(syscon, 0);
 299         if (!ap_syscon_base)
 300                 return;
 301         ebi_base = of_iomap(ebi, 0);
 302         if (!ebi_base)
 303                 return;
 304
 305         of_platform_populate(NULL, of_default_bus_match_table,
 306                         ap_auxdata_lookup, NULL);
 307
 308         sc_dec = readl(ap_syscon_base + INTEGRATOR_SC_DEC_OFFSET);
 309         for (i = 0; i < 4; i++) {
 310                 struct lm_device *lmdev;
 311
 312                 if ((sc_dec & (16 << i)) == 0)
 313                         continue;
 314
 315                 lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
 316                 if (!lmdev)
 317                         continue;
 318
 319                 lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
 320                 lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
 321                 lmdev->resource.flags = IORESOURCE_MEM;
 322                 lmdev->irq = irq_of_parse_and_map(syscon, i);
 323                 lmdev->id = i;
 324
 325                 lm_device_register(lmdev);
 326         }
 327 }
 328
 329 static const char * ap_dt_board_compat[] = {
 330         "arm,integrator-ap",
 331         NULL,
 332 };
 333
 334 DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)")
 335         .reserve        = integrator_reserve,
 336         .map_io         = ap_map_io,
 337         .init_early     = ap_init_early,
 338         .init_irq       = ap_init_irq_of,
 339         .init_machine   = ap_init_of,
 340         .dt_compat      = ap_dt_board_compat,
 341 MACHINE_END