x86/xen: resume timer irqs early
[linux/fpc-iii.git] / arch / powerpc / kernel / hw_breakpoint.c
blobf0b47d1a6b0ebd92dddd3ed49275e40a361c72ea
1 /*
2 * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
3 * using the CPU's debug registers. Derived from
4 * "arch/x86/kernel/hw_breakpoint.c"
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 * Copyright 2010 IBM Corporation
21 * Author: K.Prasad <prasad@linux.vnet.ibm.com>
25 #include <linux/hw_breakpoint.h>
26 #include <linux/notifier.h>
27 #include <linux/kprobes.h>
28 #include <linux/percpu.h>
29 #include <linux/kernel.h>
30 #include <linux/sched.h>
31 #include <linux/init.h>
32 #include <linux/smp.h>
34 #include <asm/hw_breakpoint.h>
35 #include <asm/processor.h>
36 #include <asm/sstep.h>
37 #include <asm/uaccess.h>
40 * Stores the breakpoints currently in use on each breakpoint address
41 * register for every cpu
43 static DEFINE_PER_CPU(struct perf_event *, bp_per_reg);
46 * Returns total number of data or instruction breakpoints available.
48 int hw_breakpoint_slots(int type)
50 if (type == TYPE_DATA)
51 return HBP_NUM;
52 return 0; /* no instruction breakpoints available */
56 * Install a perf counter breakpoint.
58 * We seek a free debug address register and use it for this
59 * breakpoint.
61 * Atomic: we hold the counter->ctx->lock and we only handle variables
62 * and registers local to this cpu.
64 int arch_install_hw_breakpoint(struct perf_event *bp)
66 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
67 struct perf_event **slot = &__get_cpu_var(bp_per_reg);
69 *slot = bp;
72 * Do not install DABR values if the instruction must be single-stepped.
73 * If so, DABR will be populated in single_step_dabr_instruction().
75 if (current->thread.last_hit_ubp != bp)
76 set_breakpoint(info);
78 return 0;
82 * Uninstall the breakpoint contained in the given counter.
84 * First we search the debug address register it uses and then we disable
85 * it.
87 * Atomic: we hold the counter->ctx->lock and we only handle variables
88 * and registers local to this cpu.
90 void arch_uninstall_hw_breakpoint(struct perf_event *bp)
92 struct perf_event **slot = &__get_cpu_var(bp_per_reg);
94 if (*slot != bp) {
95 WARN_ONCE(1, "Can't find the breakpoint");
96 return;
99 *slot = NULL;
100 hw_breakpoint_disable();
104 * Perform cleanup of arch-specific counters during unregistration
105 * of the perf-event
107 void arch_unregister_hw_breakpoint(struct perf_event *bp)
110 * If the breakpoint is unregistered between a hw_breakpoint_handler()
111 * and the single_step_dabr_instruction(), then cleanup the breakpoint
112 * restoration variables to prevent dangling pointers.
114 if (bp->ctx && bp->ctx->task)
115 bp->ctx->task->thread.last_hit_ubp = NULL;
119 * Check for virtual address in kernel space.
121 int arch_check_bp_in_kernelspace(struct perf_event *bp)
123 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
125 return is_kernel_addr(info->address);
128 int arch_bp_generic_fields(int type, int *gen_bp_type)
130 *gen_bp_type = 0;
131 if (type & HW_BRK_TYPE_READ)
132 *gen_bp_type |= HW_BREAKPOINT_R;
133 if (type & HW_BRK_TYPE_WRITE)
134 *gen_bp_type |= HW_BREAKPOINT_W;
135 if (*gen_bp_type == 0)
136 return -EINVAL;
137 return 0;
141 * Validate the arch-specific HW Breakpoint register settings
143 int arch_validate_hwbkpt_settings(struct perf_event *bp)
145 int ret = -EINVAL, length_max;
146 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
148 if (!bp)
149 return ret;
151 info->type = HW_BRK_TYPE_TRANSLATE;
152 if (bp->attr.bp_type & HW_BREAKPOINT_R)
153 info->type |= HW_BRK_TYPE_READ;
154 if (bp->attr.bp_type & HW_BREAKPOINT_W)
155 info->type |= HW_BRK_TYPE_WRITE;
156 if (info->type == HW_BRK_TYPE_TRANSLATE)
157 /* must set alteast read or write */
158 return ret;
159 if (!(bp->attr.exclude_user))
160 info->type |= HW_BRK_TYPE_USER;
161 if (!(bp->attr.exclude_kernel))
162 info->type |= HW_BRK_TYPE_KERNEL;
163 if (!(bp->attr.exclude_hv))
164 info->type |= HW_BRK_TYPE_HYP;
165 info->address = bp->attr.bp_addr;
166 info->len = bp->attr.bp_len;
169 * Since breakpoint length can be a maximum of HW_BREAKPOINT_LEN(8)
170 * and breakpoint addresses are aligned to nearest double-word
171 * HW_BREAKPOINT_ALIGN by rounding off to the lower address, the
172 * 'symbolsize' should satisfy the check below.
174 length_max = 8; /* DABR */
175 if (cpu_has_feature(CPU_FTR_DAWR)) {
176 length_max = 512 ; /* 64 doublewords */
177 /* DAWR region can't cross 512 boundary */
178 if ((bp->attr.bp_addr >> 10) !=
179 ((bp->attr.bp_addr + bp->attr.bp_len - 1) >> 10))
180 return -EINVAL;
182 if (info->len >
183 (length_max - (info->address & HW_BREAKPOINT_ALIGN)))
184 return -EINVAL;
185 return 0;
189 * Restores the breakpoint on the debug registers.
190 * Invoke this function if it is known that the execution context is
191 * about to change to cause loss of MSR_SE settings.
193 void thread_change_pc(struct task_struct *tsk, struct pt_regs *regs)
195 struct arch_hw_breakpoint *info;
197 if (likely(!tsk->thread.last_hit_ubp))
198 return;
200 info = counter_arch_bp(tsk->thread.last_hit_ubp);
201 regs->msr &= ~MSR_SE;
202 set_breakpoint(info);
203 tsk->thread.last_hit_ubp = NULL;
207 * Handle debug exception notifications.
209 int __kprobes hw_breakpoint_handler(struct die_args *args)
211 int rc = NOTIFY_STOP;
212 struct perf_event *bp;
213 struct pt_regs *regs = args->regs;
214 int stepped = 1;
215 struct arch_hw_breakpoint *info;
216 unsigned int instr;
217 unsigned long dar = regs->dar;
219 /* Disable breakpoints during exception handling */
220 hw_breakpoint_disable();
223 * The counter may be concurrently released but that can only
224 * occur from a call_rcu() path. We can then safely fetch
225 * the breakpoint, use its callback, touch its counter
226 * while we are in an rcu_read_lock() path.
228 rcu_read_lock();
230 bp = __get_cpu_var(bp_per_reg);
231 if (!bp)
232 goto out;
233 info = counter_arch_bp(bp);
236 * Return early after invoking user-callback function without restoring
237 * DABR if the breakpoint is from ptrace which always operates in
238 * one-shot mode. The ptrace-ed process will receive the SIGTRAP signal
239 * generated in do_dabr().
241 if (bp->overflow_handler == ptrace_triggered) {
242 perf_bp_event(bp, regs);
243 rc = NOTIFY_DONE;
244 goto out;
248 * Verify if dar lies within the address range occupied by the symbol
249 * being watched to filter extraneous exceptions. If it doesn't,
250 * we still need to single-step the instruction, but we don't
251 * generate an event.
253 info->type &= ~HW_BRK_TYPE_EXTRANEOUS_IRQ;
254 if (!((bp->attr.bp_addr <= dar) &&
255 (dar - bp->attr.bp_addr < bp->attr.bp_len)))
256 info->type |= HW_BRK_TYPE_EXTRANEOUS_IRQ;
258 /* Do not emulate user-space instructions, instead single-step them */
259 if (user_mode(regs)) {
260 current->thread.last_hit_ubp = bp;
261 regs->msr |= MSR_SE;
262 goto out;
265 stepped = 0;
266 instr = 0;
267 if (!__get_user_inatomic(instr, (unsigned int *) regs->nip))
268 stepped = emulate_step(regs, instr);
271 * emulate_step() could not execute it. We've failed in reliably
272 * handling the hw-breakpoint. Unregister it and throw a warning
273 * message to let the user know about it.
275 if (!stepped) {
276 WARN(1, "Unable to handle hardware breakpoint. Breakpoint at "
277 "0x%lx will be disabled.", info->address);
278 perf_event_disable(bp);
279 goto out;
282 * As a policy, the callback is invoked in a 'trigger-after-execute'
283 * fashion
285 if (!(info->type & HW_BRK_TYPE_EXTRANEOUS_IRQ))
286 perf_bp_event(bp, regs);
288 set_breakpoint(info);
289 out:
290 rcu_read_unlock();
291 return rc;
295 * Handle single-step exceptions following a DABR hit.
297 int __kprobes single_step_dabr_instruction(struct die_args *args)
299 struct pt_regs *regs = args->regs;
300 struct perf_event *bp = NULL;
301 struct arch_hw_breakpoint *info;
303 bp = current->thread.last_hit_ubp;
305 * Check if we are single-stepping as a result of a
306 * previous HW Breakpoint exception
308 if (!bp)
309 return NOTIFY_DONE;
311 info = counter_arch_bp(bp);
314 * We shall invoke the user-defined callback function in the single
315 * stepping handler to confirm to 'trigger-after-execute' semantics
317 if (!(info->type & HW_BRK_TYPE_EXTRANEOUS_IRQ))
318 perf_bp_event(bp, regs);
320 set_breakpoint(info);
321 current->thread.last_hit_ubp = NULL;
324 * If the process was being single-stepped by ptrace, let the
325 * other single-step actions occur (e.g. generate SIGTRAP).
327 if (test_thread_flag(TIF_SINGLESTEP))
328 return NOTIFY_DONE;
330 return NOTIFY_STOP;
334 * Handle debug exception notifications.
336 int __kprobes hw_breakpoint_exceptions_notify(
337 struct notifier_block *unused, unsigned long val, void *data)
339 int ret = NOTIFY_DONE;
341 switch (val) {
342 case DIE_DABR_MATCH:
343 ret = hw_breakpoint_handler(data);
344 break;
345 case DIE_SSTEP:
346 ret = single_step_dabr_instruction(data);
347 break;
350 return ret;
354 * Release the user breakpoints used by ptrace
356 void flush_ptrace_hw_breakpoint(struct task_struct *tsk)
358 struct thread_struct *t = &tsk->thread;
360 unregister_hw_breakpoint(t->ptrace_bps[0]);
361 t->ptrace_bps[0] = NULL;
364 void hw_breakpoint_pmu_read(struct perf_event *bp)
366 /* TODO */