x86/xen: resume timer irqs early
[linux/fpc-iii.git] / arch / powerpc / kernel / process.c
blobf1106103634bbcf4a59365ba66a09619ad91f871
1 /*
2 * Derived from "arch/i386/kernel/process.c"
3 * Copyright (C) 1995 Linus Torvalds
5 * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
6 * Paul Mackerras (paulus@cs.anu.edu.au)
8 * PowerPC version
9 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
17 #include <linux/errno.h>
18 #include <linux/sched.h>
19 #include <linux/kernel.h>
20 #include <linux/mm.h>
21 #include <linux/smp.h>
22 #include <linux/stddef.h>
23 #include <linux/unistd.h>
24 #include <linux/ptrace.h>
25 #include <linux/slab.h>
26 #include <linux/user.h>
27 #include <linux/elf.h>
28 #include <linux/init.h>
29 #include <linux/prctl.h>
30 #include <linux/init_task.h>
31 #include <linux/export.h>
32 #include <linux/kallsyms.h>
33 #include <linux/mqueue.h>
34 #include <linux/hardirq.h>
35 #include <linux/utsname.h>
36 #include <linux/ftrace.h>
37 #include <linux/kernel_stat.h>
38 #include <linux/personality.h>
39 #include <linux/random.h>
40 #include <linux/hw_breakpoint.h>
42 #include <asm/pgtable.h>
43 #include <asm/uaccess.h>
44 #include <asm/io.h>
45 #include <asm/processor.h>
46 #include <asm/mmu.h>
47 #include <asm/prom.h>
48 #include <asm/machdep.h>
49 #include <asm/time.h>
50 #include <asm/runlatch.h>
51 #include <asm/syscalls.h>
52 #include <asm/switch_to.h>
53 #include <asm/tm.h>
54 #include <asm/debug.h>
55 #ifdef CONFIG_PPC64
56 #include <asm/firmware.h>
57 #endif
58 #include <linux/kprobes.h>
59 #include <linux/kdebug.h>
61 /* Transactional Memory debug */
62 #ifdef TM_DEBUG_SW
63 #define TM_DEBUG(x...) printk(KERN_INFO x)
64 #else
65 #define TM_DEBUG(x...) do { } while(0)
66 #endif
68 extern unsigned long _get_SP(void);
70 #ifndef CONFIG_SMP
71 struct task_struct *last_task_used_math = NULL;
72 struct task_struct *last_task_used_altivec = NULL;
73 struct task_struct *last_task_used_vsx = NULL;
74 struct task_struct *last_task_used_spe = NULL;
75 #endif
77 #ifdef CONFIG_PPC_FPU
79 * Make sure the floating-point register state in the
80 * the thread_struct is up to date for task tsk.
82 void flush_fp_to_thread(struct task_struct *tsk)
84 if (tsk->thread.regs) {
86 * We need to disable preemption here because if we didn't,
87 * another process could get scheduled after the regs->msr
88 * test but before we have finished saving the FP registers
89 * to the thread_struct. That process could take over the
90 * FPU, and then when we get scheduled again we would store
91 * bogus values for the remaining FP registers.
93 preempt_disable();
94 if (tsk->thread.regs->msr & MSR_FP) {
95 #ifdef CONFIG_SMP
97 * This should only ever be called for current or
98 * for a stopped child process. Since we save away
99 * the FP register state on context switch on SMP,
100 * there is something wrong if a stopped child appears
101 * to still have its FP state in the CPU registers.
103 BUG_ON(tsk != current);
104 #endif
105 giveup_fpu(tsk);
107 preempt_enable();
110 EXPORT_SYMBOL_GPL(flush_fp_to_thread);
111 #endif
113 void enable_kernel_fp(void)
115 WARN_ON(preemptible());
117 #ifdef CONFIG_SMP
118 if (current->thread.regs && (current->thread.regs->msr & MSR_FP))
119 giveup_fpu(current);
120 else
121 giveup_fpu(NULL); /* just enables FP for kernel */
122 #else
123 giveup_fpu(last_task_used_math);
124 #endif /* CONFIG_SMP */
126 EXPORT_SYMBOL(enable_kernel_fp);
128 #ifdef CONFIG_ALTIVEC
129 void enable_kernel_altivec(void)
131 WARN_ON(preemptible());
133 #ifdef CONFIG_SMP
134 if (current->thread.regs && (current->thread.regs->msr & MSR_VEC))
135 giveup_altivec(current);
136 else
137 giveup_altivec_notask();
138 #else
139 giveup_altivec(last_task_used_altivec);
140 #endif /* CONFIG_SMP */
142 EXPORT_SYMBOL(enable_kernel_altivec);
145 * Make sure the VMX/Altivec register state in the
146 * the thread_struct is up to date for task tsk.
148 void flush_altivec_to_thread(struct task_struct *tsk)
150 if (tsk->thread.regs) {
151 preempt_disable();
152 if (tsk->thread.regs->msr & MSR_VEC) {
153 #ifdef CONFIG_SMP
154 BUG_ON(tsk != current);
155 #endif
156 giveup_altivec(tsk);
158 preempt_enable();
161 EXPORT_SYMBOL_GPL(flush_altivec_to_thread);
162 #endif /* CONFIG_ALTIVEC */
164 #ifdef CONFIG_VSX
165 #if 0
166 /* not currently used, but some crazy RAID module might want to later */
167 void enable_kernel_vsx(void)
169 WARN_ON(preemptible());
171 #ifdef CONFIG_SMP
172 if (current->thread.regs && (current->thread.regs->msr & MSR_VSX))
173 giveup_vsx(current);
174 else
175 giveup_vsx(NULL); /* just enable vsx for kernel - force */
176 #else
177 giveup_vsx(last_task_used_vsx);
178 #endif /* CONFIG_SMP */
180 EXPORT_SYMBOL(enable_kernel_vsx);
181 #endif
183 void giveup_vsx(struct task_struct *tsk)
185 giveup_fpu(tsk);
186 giveup_altivec(tsk);
187 __giveup_vsx(tsk);
190 void flush_vsx_to_thread(struct task_struct *tsk)
192 if (tsk->thread.regs) {
193 preempt_disable();
194 if (tsk->thread.regs->msr & MSR_VSX) {
195 #ifdef CONFIG_SMP
196 BUG_ON(tsk != current);
197 #endif
198 giveup_vsx(tsk);
200 preempt_enable();
203 EXPORT_SYMBOL_GPL(flush_vsx_to_thread);
204 #endif /* CONFIG_VSX */
206 #ifdef CONFIG_SPE
208 void enable_kernel_spe(void)
210 WARN_ON(preemptible());
212 #ifdef CONFIG_SMP
213 if (current->thread.regs && (current->thread.regs->msr & MSR_SPE))
214 giveup_spe(current);
215 else
216 giveup_spe(NULL); /* just enable SPE for kernel - force */
217 #else
218 giveup_spe(last_task_used_spe);
219 #endif /* __SMP __ */
221 EXPORT_SYMBOL(enable_kernel_spe);
223 void flush_spe_to_thread(struct task_struct *tsk)
225 if (tsk->thread.regs) {
226 preempt_disable();
227 if (tsk->thread.regs->msr & MSR_SPE) {
228 #ifdef CONFIG_SMP
229 BUG_ON(tsk != current);
230 #endif
231 tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
232 giveup_spe(tsk);
234 preempt_enable();
237 #endif /* CONFIG_SPE */
239 #ifndef CONFIG_SMP
241 * If we are doing lazy switching of CPU state (FP, altivec or SPE),
242 * and the current task has some state, discard it.
244 void discard_lazy_cpu_state(void)
246 preempt_disable();
247 if (last_task_used_math == current)
248 last_task_used_math = NULL;
249 #ifdef CONFIG_ALTIVEC
250 if (last_task_used_altivec == current)
251 last_task_used_altivec = NULL;
252 #endif /* CONFIG_ALTIVEC */
253 #ifdef CONFIG_VSX
254 if (last_task_used_vsx == current)
255 last_task_used_vsx = NULL;
256 #endif /* CONFIG_VSX */
257 #ifdef CONFIG_SPE
258 if (last_task_used_spe == current)
259 last_task_used_spe = NULL;
260 #endif
261 preempt_enable();
263 #endif /* CONFIG_SMP */
265 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
266 void do_send_trap(struct pt_regs *regs, unsigned long address,
267 unsigned long error_code, int signal_code, int breakpt)
269 siginfo_t info;
271 current->thread.trap_nr = signal_code;
272 if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
273 11, SIGSEGV) == NOTIFY_STOP)
274 return;
276 /* Deliver the signal to userspace */
277 info.si_signo = SIGTRAP;
278 info.si_errno = breakpt; /* breakpoint or watchpoint id */
279 info.si_code = signal_code;
280 info.si_addr = (void __user *)address;
281 force_sig_info(SIGTRAP, &info, current);
283 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
284 void do_break (struct pt_regs *regs, unsigned long address,
285 unsigned long error_code)
287 siginfo_t info;
289 current->thread.trap_nr = TRAP_HWBKPT;
290 if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
291 11, SIGSEGV) == NOTIFY_STOP)
292 return;
294 if (debugger_break_match(regs))
295 return;
297 /* Clear the breakpoint */
298 hw_breakpoint_disable();
300 /* Deliver the signal to userspace */
301 info.si_signo = SIGTRAP;
302 info.si_errno = 0;
303 info.si_code = TRAP_HWBKPT;
304 info.si_addr = (void __user *)address;
305 force_sig_info(SIGTRAP, &info, current);
307 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
309 static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk);
311 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
313 * Set the debug registers back to their default "safe" values.
315 static void set_debug_reg_defaults(struct thread_struct *thread)
317 thread->iac1 = thread->iac2 = 0;
318 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
319 thread->iac3 = thread->iac4 = 0;
320 #endif
321 thread->dac1 = thread->dac2 = 0;
322 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
323 thread->dvc1 = thread->dvc2 = 0;
324 #endif
325 thread->dbcr0 = 0;
326 #ifdef CONFIG_BOOKE
328 * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
330 thread->dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US | \
331 DBCR1_IAC3US | DBCR1_IAC4US;
333 * Force Data Address Compare User/Supervisor bits to be User-only
334 * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
336 thread->dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
337 #else
338 thread->dbcr1 = 0;
339 #endif
342 static void prime_debug_regs(struct thread_struct *thread)
345 * We could have inherited MSR_DE from userspace, since
346 * it doesn't get cleared on exception entry. Make sure
347 * MSR_DE is clear before we enable any debug events.
349 mtmsr(mfmsr() & ~MSR_DE);
351 mtspr(SPRN_IAC1, thread->iac1);
352 mtspr(SPRN_IAC2, thread->iac2);
353 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
354 mtspr(SPRN_IAC3, thread->iac3);
355 mtspr(SPRN_IAC4, thread->iac4);
356 #endif
357 mtspr(SPRN_DAC1, thread->dac1);
358 mtspr(SPRN_DAC2, thread->dac2);
359 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
360 mtspr(SPRN_DVC1, thread->dvc1);
361 mtspr(SPRN_DVC2, thread->dvc2);
362 #endif
363 mtspr(SPRN_DBCR0, thread->dbcr0);
364 mtspr(SPRN_DBCR1, thread->dbcr1);
365 #ifdef CONFIG_BOOKE
366 mtspr(SPRN_DBCR2, thread->dbcr2);
367 #endif
370 * Unless neither the old or new thread are making use of the
371 * debug registers, set the debug registers from the values
372 * stored in the new thread.
374 static void switch_booke_debug_regs(struct thread_struct *new_thread)
376 if ((current->thread.dbcr0 & DBCR0_IDM)
377 || (new_thread->dbcr0 & DBCR0_IDM))
378 prime_debug_regs(new_thread);
380 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
381 #ifndef CONFIG_HAVE_HW_BREAKPOINT
382 static void set_debug_reg_defaults(struct thread_struct *thread)
384 thread->hw_brk.address = 0;
385 thread->hw_brk.type = 0;
386 set_breakpoint(&thread->hw_brk);
388 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */
389 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
391 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
392 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
394 mtspr(SPRN_DAC1, dabr);
395 #ifdef CONFIG_PPC_47x
396 isync();
397 #endif
398 return 0;
400 #elif defined(CONFIG_PPC_BOOK3S)
401 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
403 mtspr(SPRN_DABR, dabr);
404 if (cpu_has_feature(CPU_FTR_DABRX))
405 mtspr(SPRN_DABRX, dabrx);
406 return 0;
408 #else
409 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
411 return -EINVAL;
413 #endif
415 static inline int set_dabr(struct arch_hw_breakpoint *brk)
417 unsigned long dabr, dabrx;
419 dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR);
420 dabrx = ((brk->type >> 3) & 0x7);
422 if (ppc_md.set_dabr)
423 return ppc_md.set_dabr(dabr, dabrx);
425 return __set_dabr(dabr, dabrx);
428 static inline int set_dawr(struct arch_hw_breakpoint *brk)
430 unsigned long dawr, dawrx, mrd;
432 dawr = brk->address;
434 dawrx = (brk->type & (HW_BRK_TYPE_READ | HW_BRK_TYPE_WRITE)) \
435 << (63 - 58); //* read/write bits */
436 dawrx |= ((brk->type & (HW_BRK_TYPE_TRANSLATE)) >> 2) \
437 << (63 - 59); //* translate */
438 dawrx |= (brk->type & (HW_BRK_TYPE_PRIV_ALL)) \
439 >> 3; //* PRIM bits */
440 /* dawr length is stored in field MDR bits 48:53. Matches range in
441 doublewords (64 bits) baised by -1 eg. 0b000000=1DW and
442 0b111111=64DW.
443 brk->len is in bytes.
444 This aligns up to double word size, shifts and does the bias.
446 mrd = ((brk->len + 7) >> 3) - 1;
447 dawrx |= (mrd & 0x3f) << (63 - 53);
449 if (ppc_md.set_dawr)
450 return ppc_md.set_dawr(dawr, dawrx);
451 mtspr(SPRN_DAWR, dawr);
452 mtspr(SPRN_DAWRX, dawrx);
453 return 0;
456 int set_breakpoint(struct arch_hw_breakpoint *brk)
458 __get_cpu_var(current_brk) = *brk;
460 if (cpu_has_feature(CPU_FTR_DAWR))
461 return set_dawr(brk);
463 return set_dabr(brk);
466 #ifdef CONFIG_PPC64
467 DEFINE_PER_CPU(struct cpu_usage, cpu_usage_array);
468 #endif
470 static inline bool hw_brk_match(struct arch_hw_breakpoint *a,
471 struct arch_hw_breakpoint *b)
473 if (a->address != b->address)
474 return false;
475 if (a->type != b->type)
476 return false;
477 if (a->len != b->len)
478 return false;
479 return true;
481 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
482 static inline void tm_reclaim_task(struct task_struct *tsk)
484 /* We have to work out if we're switching from/to a task that's in the
485 * middle of a transaction.
487 * In switching we need to maintain a 2nd register state as
488 * oldtask->thread.ckpt_regs. We tm_reclaim(oldproc); this saves the
489 * checkpointed (tbegin) state in ckpt_regs and saves the transactional
490 * (current) FPRs into oldtask->thread.transact_fpr[].
492 * We also context switch (save) TFHAR/TEXASR/TFIAR in here.
494 struct thread_struct *thr = &tsk->thread;
496 if (!thr->regs)
497 return;
499 if (!MSR_TM_ACTIVE(thr->regs->msr))
500 goto out_and_saveregs;
502 /* Stash the original thread MSR, as giveup_fpu et al will
503 * modify it. We hold onto it to see whether the task used
504 * FP & vector regs.
506 thr->tm_orig_msr = thr->regs->msr;
508 TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
509 "ccr=%lx, msr=%lx, trap=%lx)\n",
510 tsk->pid, thr->regs->nip,
511 thr->regs->ccr, thr->regs->msr,
512 thr->regs->trap);
514 tm_reclaim(thr, thr->regs->msr, TM_CAUSE_RESCHED);
516 TM_DEBUG("--- tm_reclaim on pid %d complete\n",
517 tsk->pid);
519 out_and_saveregs:
520 /* Always save the regs here, even if a transaction's not active.
521 * This context-switches a thread's TM info SPRs. We do it here to
522 * be consistent with the restore path (in recheckpoint) which
523 * cannot happen later in _switch().
525 tm_save_sprs(thr);
528 extern void __tm_recheckpoint(struct thread_struct *thread,
529 unsigned long orig_msr);
531 void tm_recheckpoint(struct thread_struct *thread,
532 unsigned long orig_msr)
534 unsigned long flags;
536 /* We really can't be interrupted here as the TEXASR registers can't
537 * change and later in the trecheckpoint code, we have a userspace R1.
538 * So let's hard disable over this region.
540 local_irq_save(flags);
541 hard_irq_disable();
543 /* The TM SPRs are restored here, so that TEXASR.FS can be set
544 * before the trecheckpoint and no explosion occurs.
546 tm_restore_sprs(thread);
548 __tm_recheckpoint(thread, orig_msr);
550 local_irq_restore(flags);
553 static inline void tm_recheckpoint_new_task(struct task_struct *new)
555 unsigned long msr;
557 if (!cpu_has_feature(CPU_FTR_TM))
558 return;
560 /* Recheckpoint the registers of the thread we're about to switch to.
562 * If the task was using FP, we non-lazily reload both the original and
563 * the speculative FP register states. This is because the kernel
564 * doesn't see if/when a TM rollback occurs, so if we take an FP
565 * unavoidable later, we are unable to determine which set of FP regs
566 * need to be restored.
568 if (!new->thread.regs)
569 return;
571 if (!MSR_TM_ACTIVE(new->thread.regs->msr)){
572 tm_restore_sprs(&new->thread);
573 return;
575 msr = new->thread.tm_orig_msr;
576 /* Recheckpoint to restore original checkpointed register state. */
577 TM_DEBUG("*** tm_recheckpoint of pid %d "
578 "(new->msr 0x%lx, new->origmsr 0x%lx)\n",
579 new->pid, new->thread.regs->msr, msr);
581 /* This loads the checkpointed FP/VEC state, if used */
582 tm_recheckpoint(&new->thread, msr);
584 /* This loads the speculative FP/VEC state, if used */
585 if (msr & MSR_FP) {
586 do_load_up_transact_fpu(&new->thread);
587 new->thread.regs->msr |=
588 (MSR_FP | new->thread.fpexc_mode);
590 #ifdef CONFIG_ALTIVEC
591 if (msr & MSR_VEC) {
592 do_load_up_transact_altivec(&new->thread);
593 new->thread.regs->msr |= MSR_VEC;
595 #endif
596 /* We may as well turn on VSX too since all the state is restored now */
597 if (msr & MSR_VSX)
598 new->thread.regs->msr |= MSR_VSX;
600 TM_DEBUG("*** tm_recheckpoint of pid %d complete "
601 "(kernel msr 0x%lx)\n",
602 new->pid, mfmsr());
605 static inline void __switch_to_tm(struct task_struct *prev)
607 if (cpu_has_feature(CPU_FTR_TM)) {
608 tm_enable();
609 tm_reclaim_task(prev);
612 #else
613 #define tm_recheckpoint_new_task(new)
614 #define __switch_to_tm(prev)
615 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
617 struct task_struct *__switch_to(struct task_struct *prev,
618 struct task_struct *new)
620 struct thread_struct *new_thread, *old_thread;
621 unsigned long flags;
622 struct task_struct *last;
623 #ifdef CONFIG_PPC_BOOK3S_64
624 struct ppc64_tlb_batch *batch;
625 #endif
627 /* Back up the TAR across context switches.
628 * Note that the TAR is not available for use in the kernel. (To
629 * provide this, the TAR should be backed up/restored on exception
630 * entry/exit instead, and be in pt_regs. FIXME, this should be in
631 * pt_regs anyway (for debug).)
632 * Save the TAR here before we do treclaim/trecheckpoint as these
633 * will change the TAR.
635 save_tar(&prev->thread);
637 __switch_to_tm(prev);
639 #ifdef CONFIG_SMP
640 /* avoid complexity of lazy save/restore of fpu
641 * by just saving it every time we switch out if
642 * this task used the fpu during the last quantum.
644 * If it tries to use the fpu again, it'll trap and
645 * reload its fp regs. So we don't have to do a restore
646 * every switch, just a save.
647 * -- Cort
649 if (prev->thread.regs && (prev->thread.regs->msr & MSR_FP))
650 giveup_fpu(prev);
651 #ifdef CONFIG_ALTIVEC
653 * If the previous thread used altivec in the last quantum
654 * (thus changing altivec regs) then save them.
655 * We used to check the VRSAVE register but not all apps
656 * set it, so we don't rely on it now (and in fact we need
657 * to save & restore VSCR even if VRSAVE == 0). -- paulus
659 * On SMP we always save/restore altivec regs just to avoid the
660 * complexity of changing processors.
661 * -- Cort
663 if (prev->thread.regs && (prev->thread.regs->msr & MSR_VEC))
664 giveup_altivec(prev);
665 #endif /* CONFIG_ALTIVEC */
666 #ifdef CONFIG_VSX
667 if (prev->thread.regs && (prev->thread.regs->msr & MSR_VSX))
668 /* VMX and FPU registers are already save here */
669 __giveup_vsx(prev);
670 #endif /* CONFIG_VSX */
671 #ifdef CONFIG_SPE
673 * If the previous thread used spe in the last quantum
674 * (thus changing spe regs) then save them.
676 * On SMP we always save/restore spe regs just to avoid the
677 * complexity of changing processors.
679 if ((prev->thread.regs && (prev->thread.regs->msr & MSR_SPE)))
680 giveup_spe(prev);
681 #endif /* CONFIG_SPE */
683 #else /* CONFIG_SMP */
684 #ifdef CONFIG_ALTIVEC
685 /* Avoid the trap. On smp this this never happens since
686 * we don't set last_task_used_altivec -- Cort
688 if (new->thread.regs && last_task_used_altivec == new)
689 new->thread.regs->msr |= MSR_VEC;
690 #endif /* CONFIG_ALTIVEC */
691 #ifdef CONFIG_VSX
692 if (new->thread.regs && last_task_used_vsx == new)
693 new->thread.regs->msr |= MSR_VSX;
694 #endif /* CONFIG_VSX */
695 #ifdef CONFIG_SPE
696 /* Avoid the trap. On smp this this never happens since
697 * we don't set last_task_used_spe
699 if (new->thread.regs && last_task_used_spe == new)
700 new->thread.regs->msr |= MSR_SPE;
701 #endif /* CONFIG_SPE */
703 #endif /* CONFIG_SMP */
705 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
706 switch_booke_debug_regs(&new->thread);
707 #else
709 * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
710 * schedule DABR
712 #ifndef CONFIG_HAVE_HW_BREAKPOINT
713 if (unlikely(hw_brk_match(&__get_cpu_var(current_brk), &new->thread.hw_brk)))
714 set_breakpoint(&new->thread.hw_brk);
715 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
716 #endif
719 new_thread = &new->thread;
720 old_thread = &current->thread;
722 #ifdef CONFIG_PPC64
724 * Collect processor utilization data per process
726 if (firmware_has_feature(FW_FEATURE_SPLPAR)) {
727 struct cpu_usage *cu = &__get_cpu_var(cpu_usage_array);
728 long unsigned start_tb, current_tb;
729 start_tb = old_thread->start_tb;
730 cu->current_tb = current_tb = mfspr(SPRN_PURR);
731 old_thread->accum_tb += (current_tb - start_tb);
732 new_thread->start_tb = current_tb;
734 #endif /* CONFIG_PPC64 */
736 #ifdef CONFIG_PPC_BOOK3S_64
737 batch = &__get_cpu_var(ppc64_tlb_batch);
738 if (batch->active) {
739 current_thread_info()->local_flags |= _TLF_LAZY_MMU;
740 if (batch->index)
741 __flush_tlb_pending(batch);
742 batch->active = 0;
744 #endif /* CONFIG_PPC_BOOK3S_64 */
746 local_irq_save(flags);
749 * We can't take a PMU exception inside _switch() since there is a
750 * window where the kernel stack SLB and the kernel stack are out
751 * of sync. Hard disable here.
753 hard_irq_disable();
755 tm_recheckpoint_new_task(new);
757 last = _switch(old_thread, new_thread);
759 #ifdef CONFIG_PPC_BOOK3S_64
760 if (current_thread_info()->local_flags & _TLF_LAZY_MMU) {
761 current_thread_info()->local_flags &= ~_TLF_LAZY_MMU;
762 batch = &__get_cpu_var(ppc64_tlb_batch);
763 batch->active = 1;
765 #endif /* CONFIG_PPC_BOOK3S_64 */
767 local_irq_restore(flags);
769 return last;
772 static int instructions_to_print = 16;
774 static void show_instructions(struct pt_regs *regs)
776 int i;
777 unsigned long pc = regs->nip - (instructions_to_print * 3 / 4 *
778 sizeof(int));
780 printk("Instruction dump:");
782 for (i = 0; i < instructions_to_print; i++) {
783 int instr;
785 if (!(i % 8))
786 printk("\n");
788 #if !defined(CONFIG_BOOKE)
789 /* If executing with the IMMU off, adjust pc rather
790 * than print XXXXXXXX.
792 if (!(regs->msr & MSR_IR))
793 pc = (unsigned long)phys_to_virt(pc);
794 #endif
796 /* We use __get_user here *only* to avoid an OOPS on a
797 * bad address because the pc *should* only be a
798 * kernel address.
800 if (!__kernel_text_address(pc) ||
801 __get_user(instr, (unsigned int __user *)pc)) {
802 printk(KERN_CONT "XXXXXXXX ");
803 } else {
804 if (regs->nip == pc)
805 printk(KERN_CONT "<%08x> ", instr);
806 else
807 printk(KERN_CONT "%08x ", instr);
810 pc += sizeof(int);
813 printk("\n");
816 static struct regbit {
817 unsigned long bit;
818 const char *name;
819 } msr_bits[] = {
820 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
821 {MSR_SF, "SF"},
822 {MSR_HV, "HV"},
823 #endif
824 {MSR_VEC, "VEC"},
825 {MSR_VSX, "VSX"},
826 #ifdef CONFIG_BOOKE
827 {MSR_CE, "CE"},
828 #endif
829 {MSR_EE, "EE"},
830 {MSR_PR, "PR"},
831 {MSR_FP, "FP"},
832 {MSR_ME, "ME"},
833 #ifdef CONFIG_BOOKE
834 {MSR_DE, "DE"},
835 #else
836 {MSR_SE, "SE"},
837 {MSR_BE, "BE"},
838 #endif
839 {MSR_IR, "IR"},
840 {MSR_DR, "DR"},
841 {MSR_PMM, "PMM"},
842 #ifndef CONFIG_BOOKE
843 {MSR_RI, "RI"},
844 {MSR_LE, "LE"},
845 #endif
846 {0, NULL}
849 static void printbits(unsigned long val, struct regbit *bits)
851 const char *sep = "";
853 printk("<");
854 for (; bits->bit; ++bits)
855 if (val & bits->bit) {
856 printk("%s%s", sep, bits->name);
857 sep = ",";
859 printk(">");
862 #ifdef CONFIG_PPC64
863 #define REG "%016lx"
864 #define REGS_PER_LINE 4
865 #define LAST_VOLATILE 13
866 #else
867 #define REG "%08lx"
868 #define REGS_PER_LINE 8
869 #define LAST_VOLATILE 12
870 #endif
872 void show_regs(struct pt_regs * regs)
874 int i, trap;
876 show_regs_print_info(KERN_DEFAULT);
878 printk("NIP: "REG" LR: "REG" CTR: "REG"\n",
879 regs->nip, regs->link, regs->ctr);
880 printk("REGS: %p TRAP: %04lx %s (%s)\n",
881 regs, regs->trap, print_tainted(), init_utsname()->release);
882 printk("MSR: "REG" ", regs->msr);
883 printbits(regs->msr, msr_bits);
884 printk(" CR: %08lx XER: %08lx\n", regs->ccr, regs->xer);
885 #ifdef CONFIG_PPC64
886 printk("SOFTE: %ld\n", regs->softe);
887 #endif
888 trap = TRAP(regs);
889 if ((regs->trap != 0xc00) && cpu_has_feature(CPU_FTR_CFAR))
890 printk("CFAR: "REG"\n", regs->orig_gpr3);
891 if (trap == 0x300 || trap == 0x600)
892 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
893 printk("DEAR: "REG", ESR: "REG"\n", regs->dar, regs->dsisr);
894 #else
895 printk("DAR: "REG", DSISR: %08lx\n", regs->dar, regs->dsisr);
896 #endif
898 for (i = 0; i < 32; i++) {
899 if ((i % REGS_PER_LINE) == 0)
900 printk("\nGPR%02d: ", i);
901 printk(REG " ", regs->gpr[i]);
902 if (i == LAST_VOLATILE && !FULL_REGS(regs))
903 break;
905 printk("\n");
906 #ifdef CONFIG_KALLSYMS
908 * Lookup NIP late so we have the best change of getting the
909 * above info out without failing
911 printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip);
912 printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link);
913 #endif
914 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
915 printk("PACATMSCRATCH [%llx]\n", get_paca()->tm_scratch);
916 #endif
917 show_stack(current, (unsigned long *) regs->gpr[1]);
918 if (!user_mode(regs))
919 show_instructions(regs);
922 void exit_thread(void)
924 discard_lazy_cpu_state();
927 void flush_thread(void)
929 discard_lazy_cpu_state();
931 #ifdef CONFIG_HAVE_HW_BREAKPOINT
932 flush_ptrace_hw_breakpoint(current);
933 #else /* CONFIG_HAVE_HW_BREAKPOINT */
934 set_debug_reg_defaults(&current->thread);
935 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
938 void
939 release_thread(struct task_struct *t)
944 * this gets called so that we can store coprocessor state into memory and
945 * copy the current task into the new thread.
947 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
949 flush_fp_to_thread(src);
950 flush_altivec_to_thread(src);
951 flush_vsx_to_thread(src);
952 flush_spe_to_thread(src);
954 * Flush TM state out so we can copy it. __switch_to_tm() does this
955 * flush but it removes the checkpointed state from the current CPU and
956 * transitions the CPU out of TM mode. Hence we need to call
957 * tm_recheckpoint_new_task() (on the same task) to restore the
958 * checkpointed state back and the TM mode.
960 __switch_to_tm(src);
961 tm_recheckpoint_new_task(src);
963 *dst = *src;
965 clear_task_ebb(dst);
967 return 0;
971 * Copy a thread..
973 extern unsigned long dscr_default; /* defined in arch/powerpc/kernel/sysfs.c */
975 int copy_thread(unsigned long clone_flags, unsigned long usp,
976 unsigned long arg, struct task_struct *p)
978 struct pt_regs *childregs, *kregs;
979 extern void ret_from_fork(void);
980 extern void ret_from_kernel_thread(void);
981 void (*f)(void);
982 unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE;
984 /* Copy registers */
985 sp -= sizeof(struct pt_regs);
986 childregs = (struct pt_regs *) sp;
987 if (unlikely(p->flags & PF_KTHREAD)) {
988 struct thread_info *ti = (void *)task_stack_page(p);
989 memset(childregs, 0, sizeof(struct pt_regs));
990 childregs->gpr[1] = sp + sizeof(struct pt_regs);
991 childregs->gpr[14] = usp; /* function */
992 #ifdef CONFIG_PPC64
993 clear_tsk_thread_flag(p, TIF_32BIT);
994 childregs->softe = 1;
995 #endif
996 childregs->gpr[15] = arg;
997 p->thread.regs = NULL; /* no user register state */
998 ti->flags |= _TIF_RESTOREALL;
999 f = ret_from_kernel_thread;
1000 } else {
1001 struct pt_regs *regs = current_pt_regs();
1002 CHECK_FULL_REGS(regs);
1003 *childregs = *regs;
1004 if (usp)
1005 childregs->gpr[1] = usp;
1006 p->thread.regs = childregs;
1007 childregs->gpr[3] = 0; /* Result from fork() */
1008 if (clone_flags & CLONE_SETTLS) {
1009 #ifdef CONFIG_PPC64
1010 if (!is_32bit_task())
1011 childregs->gpr[13] = childregs->gpr[6];
1012 else
1013 #endif
1014 childregs->gpr[2] = childregs->gpr[6];
1017 f = ret_from_fork;
1019 sp -= STACK_FRAME_OVERHEAD;
1022 * The way this works is that at some point in the future
1023 * some task will call _switch to switch to the new task.
1024 * That will pop off the stack frame created below and start
1025 * the new task running at ret_from_fork. The new task will
1026 * do some house keeping and then return from the fork or clone
1027 * system call, using the stack frame created above.
1029 ((unsigned long *)sp)[0] = 0;
1030 sp -= sizeof(struct pt_regs);
1031 kregs = (struct pt_regs *) sp;
1032 sp -= STACK_FRAME_OVERHEAD;
1033 p->thread.ksp = sp;
1034 #ifdef CONFIG_PPC32
1035 p->thread.ksp_limit = (unsigned long)task_stack_page(p) +
1036 _ALIGN_UP(sizeof(struct thread_info), 16);
1037 #endif
1038 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1039 p->thread.ptrace_bps[0] = NULL;
1040 #endif
1042 #ifdef CONFIG_PPC_STD_MMU_64
1043 if (mmu_has_feature(MMU_FTR_SLB)) {
1044 unsigned long sp_vsid;
1045 unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp;
1047 if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
1048 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T)
1049 << SLB_VSID_SHIFT_1T;
1050 else
1051 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M)
1052 << SLB_VSID_SHIFT;
1053 sp_vsid |= SLB_VSID_KERNEL | llp;
1054 p->thread.ksp_vsid = sp_vsid;
1056 #endif /* CONFIG_PPC_STD_MMU_64 */
1057 #ifdef CONFIG_PPC64
1058 if (cpu_has_feature(CPU_FTR_DSCR)) {
1059 p->thread.dscr_inherit = current->thread.dscr_inherit;
1060 p->thread.dscr = current->thread.dscr;
1062 if (cpu_has_feature(CPU_FTR_HAS_PPR))
1063 p->thread.ppr = INIT_PPR;
1064 #endif
1066 * The PPC64 ABI makes use of a TOC to contain function
1067 * pointers. The function (ret_from_except) is actually a pointer
1068 * to the TOC entry. The first entry is a pointer to the actual
1069 * function.
1071 #ifdef CONFIG_PPC64
1072 kregs->nip = *((unsigned long *)f);
1073 #else
1074 kregs->nip = (unsigned long)f;
1075 #endif
1076 return 0;
1080 * Set up a thread for executing a new program
1082 void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp)
1084 #ifdef CONFIG_PPC64
1085 unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */
1086 #endif
1089 * If we exec out of a kernel thread then thread.regs will not be
1090 * set. Do it now.
1092 if (!current->thread.regs) {
1093 struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE;
1094 current->thread.regs = regs - 1;
1097 memset(regs->gpr, 0, sizeof(regs->gpr));
1098 regs->ctr = 0;
1099 regs->link = 0;
1100 regs->xer = 0;
1101 regs->ccr = 0;
1102 regs->gpr[1] = sp;
1105 * We have just cleared all the nonvolatile GPRs, so make
1106 * FULL_REGS(regs) return true. This is necessary to allow
1107 * ptrace to examine the thread immediately after exec.
1109 regs->trap &= ~1UL;
1111 #ifdef CONFIG_PPC32
1112 regs->mq = 0;
1113 regs->nip = start;
1114 regs->msr = MSR_USER;
1115 #else
1116 if (!is_32bit_task()) {
1117 unsigned long entry, toc;
1119 /* start is a relocated pointer to the function descriptor for
1120 * the elf _start routine. The first entry in the function
1121 * descriptor is the entry address of _start and the second
1122 * entry is the TOC value we need to use.
1124 __get_user(entry, (unsigned long __user *)start);
1125 __get_user(toc, (unsigned long __user *)start+1);
1127 /* Check whether the e_entry function descriptor entries
1128 * need to be relocated before we can use them.
1130 if (load_addr != 0) {
1131 entry += load_addr;
1132 toc += load_addr;
1134 regs->nip = entry;
1135 regs->gpr[2] = toc;
1136 regs->msr = MSR_USER64;
1137 } else {
1138 regs->nip = start;
1139 regs->gpr[2] = 0;
1140 regs->msr = MSR_USER32;
1142 #endif
1143 discard_lazy_cpu_state();
1144 #ifdef CONFIG_VSX
1145 current->thread.used_vsr = 0;
1146 #endif
1147 memset(current->thread.fpr, 0, sizeof(current->thread.fpr));
1148 current->thread.fpscr.val = 0;
1149 #ifdef CONFIG_ALTIVEC
1150 memset(current->thread.vr, 0, sizeof(current->thread.vr));
1151 memset(&current->thread.vscr, 0, sizeof(current->thread.vscr));
1152 current->thread.vscr.u[3] = 0x00010000; /* Java mode disabled */
1153 current->thread.vrsave = 0;
1154 current->thread.used_vr = 0;
1155 #endif /* CONFIG_ALTIVEC */
1156 #ifdef CONFIG_SPE
1157 memset(current->thread.evr, 0, sizeof(current->thread.evr));
1158 current->thread.acc = 0;
1159 current->thread.spefscr = 0;
1160 current->thread.used_spe = 0;
1161 #endif /* CONFIG_SPE */
1162 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1163 if (cpu_has_feature(CPU_FTR_TM))
1164 regs->msr |= MSR_TM;
1165 current->thread.tm_tfhar = 0;
1166 current->thread.tm_texasr = 0;
1167 current->thread.tm_tfiar = 0;
1168 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1171 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
1172 | PR_FP_EXC_RES | PR_FP_EXC_INV)
1174 int set_fpexc_mode(struct task_struct *tsk, unsigned int val)
1176 struct pt_regs *regs = tsk->thread.regs;
1178 /* This is a bit hairy. If we are an SPE enabled processor
1179 * (have embedded fp) we store the IEEE exception enable flags in
1180 * fpexc_mode. fpexc_mode is also used for setting FP exception
1181 * mode (asyn, precise, disabled) for 'Classic' FP. */
1182 if (val & PR_FP_EXC_SW_ENABLE) {
1183 #ifdef CONFIG_SPE
1184 if (cpu_has_feature(CPU_FTR_SPE)) {
1185 tsk->thread.fpexc_mode = val &
1186 (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT);
1187 return 0;
1188 } else {
1189 return -EINVAL;
1191 #else
1192 return -EINVAL;
1193 #endif
1196 /* on a CONFIG_SPE this does not hurt us. The bits that
1197 * __pack_fe01 use do not overlap with bits used for
1198 * PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits
1199 * on CONFIG_SPE implementations are reserved so writing to
1200 * them does not change anything */
1201 if (val > PR_FP_EXC_PRECISE)
1202 return -EINVAL;
1203 tsk->thread.fpexc_mode = __pack_fe01(val);
1204 if (regs != NULL && (regs->msr & MSR_FP) != 0)
1205 regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1))
1206 | tsk->thread.fpexc_mode;
1207 return 0;
1210 int get_fpexc_mode(struct task_struct *tsk, unsigned long adr)
1212 unsigned int val;
1214 if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE)
1215 #ifdef CONFIG_SPE
1216 if (cpu_has_feature(CPU_FTR_SPE))
1217 val = tsk->thread.fpexc_mode;
1218 else
1219 return -EINVAL;
1220 #else
1221 return -EINVAL;
1222 #endif
1223 else
1224 val = __unpack_fe01(tsk->thread.fpexc_mode);
1225 return put_user(val, (unsigned int __user *) adr);
1228 int set_endian(struct task_struct *tsk, unsigned int val)
1230 struct pt_regs *regs = tsk->thread.regs;
1232 if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) ||
1233 (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE)))
1234 return -EINVAL;
1236 if (regs == NULL)
1237 return -EINVAL;
1239 if (val == PR_ENDIAN_BIG)
1240 regs->msr &= ~MSR_LE;
1241 else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE)
1242 regs->msr |= MSR_LE;
1243 else
1244 return -EINVAL;
1246 return 0;
1249 int get_endian(struct task_struct *tsk, unsigned long adr)
1251 struct pt_regs *regs = tsk->thread.regs;
1252 unsigned int val;
1254 if (!cpu_has_feature(CPU_FTR_PPC_LE) &&
1255 !cpu_has_feature(CPU_FTR_REAL_LE))
1256 return -EINVAL;
1258 if (regs == NULL)
1259 return -EINVAL;
1261 if (regs->msr & MSR_LE) {
1262 if (cpu_has_feature(CPU_FTR_REAL_LE))
1263 val = PR_ENDIAN_LITTLE;
1264 else
1265 val = PR_ENDIAN_PPC_LITTLE;
1266 } else
1267 val = PR_ENDIAN_BIG;
1269 return put_user(val, (unsigned int __user *)adr);
1272 int set_unalign_ctl(struct task_struct *tsk, unsigned int val)
1274 tsk->thread.align_ctl = val;
1275 return 0;
1278 int get_unalign_ctl(struct task_struct *tsk, unsigned long adr)
1280 return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr);
1283 static inline int valid_irq_stack(unsigned long sp, struct task_struct *p,
1284 unsigned long nbytes)
1286 unsigned long stack_page;
1287 unsigned long cpu = task_cpu(p);
1290 * Avoid crashing if the stack has overflowed and corrupted
1291 * task_cpu(p), which is in the thread_info struct.
1293 if (cpu < NR_CPUS && cpu_possible(cpu)) {
1294 stack_page = (unsigned long) hardirq_ctx[cpu];
1295 if (sp >= stack_page + sizeof(struct thread_struct)
1296 && sp <= stack_page + THREAD_SIZE - nbytes)
1297 return 1;
1299 stack_page = (unsigned long) softirq_ctx[cpu];
1300 if (sp >= stack_page + sizeof(struct thread_struct)
1301 && sp <= stack_page + THREAD_SIZE - nbytes)
1302 return 1;
1304 return 0;
1307 int validate_sp(unsigned long sp, struct task_struct *p,
1308 unsigned long nbytes)
1310 unsigned long stack_page = (unsigned long)task_stack_page(p);
1312 if (sp >= stack_page + sizeof(struct thread_struct)
1313 && sp <= stack_page + THREAD_SIZE - nbytes)
1314 return 1;
1316 return valid_irq_stack(sp, p, nbytes);
1319 EXPORT_SYMBOL(validate_sp);
1321 unsigned long get_wchan(struct task_struct *p)
1323 unsigned long ip, sp;
1324 int count = 0;
1326 if (!p || p == current || p->state == TASK_RUNNING)
1327 return 0;
1329 sp = p->thread.ksp;
1330 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
1331 return 0;
1333 do {
1334 sp = *(unsigned long *)sp;
1335 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
1336 return 0;
1337 if (count > 0) {
1338 ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE];
1339 if (!in_sched_functions(ip))
1340 return ip;
1342 } while (count++ < 16);
1343 return 0;
1346 static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH;
1348 void show_stack(struct task_struct *tsk, unsigned long *stack)
1350 unsigned long sp, ip, lr, newsp;
1351 int count = 0;
1352 int firstframe = 1;
1353 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1354 int curr_frame = current->curr_ret_stack;
1355 extern void return_to_handler(void);
1356 unsigned long rth = (unsigned long)return_to_handler;
1357 unsigned long mrth = -1;
1358 #ifdef CONFIG_PPC64
1359 extern void mod_return_to_handler(void);
1360 rth = *(unsigned long *)rth;
1361 mrth = (unsigned long)mod_return_to_handler;
1362 mrth = *(unsigned long *)mrth;
1363 #endif
1364 #endif
1366 sp = (unsigned long) stack;
1367 if (tsk == NULL)
1368 tsk = current;
1369 if (sp == 0) {
1370 if (tsk == current)
1371 asm("mr %0,1" : "=r" (sp));
1372 else
1373 sp = tsk->thread.ksp;
1376 lr = 0;
1377 printk("Call Trace:\n");
1378 do {
1379 if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD))
1380 return;
1382 stack = (unsigned long *) sp;
1383 newsp = stack[0];
1384 ip = stack[STACK_FRAME_LR_SAVE];
1385 if (!firstframe || ip != lr) {
1386 printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip);
1387 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1388 if ((ip == rth || ip == mrth) && curr_frame >= 0) {
1389 printk(" (%pS)",
1390 (void *)current->ret_stack[curr_frame].ret);
1391 curr_frame--;
1393 #endif
1394 if (firstframe)
1395 printk(" (unreliable)");
1396 printk("\n");
1398 firstframe = 0;
1401 * See if this is an exception frame.
1402 * We look for the "regshere" marker in the current frame.
1404 if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE)
1405 && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) {
1406 struct pt_regs *regs = (struct pt_regs *)
1407 (sp + STACK_FRAME_OVERHEAD);
1408 lr = regs->link;
1409 printk("--- Exception: %lx at %pS\n LR = %pS\n",
1410 regs->trap, (void *)regs->nip, (void *)lr);
1411 firstframe = 1;
1414 sp = newsp;
1415 } while (count++ < kstack_depth_to_print);
1418 #ifdef CONFIG_PPC64
1419 /* Called with hard IRQs off */
1420 void notrace __ppc64_runlatch_on(void)
1422 struct thread_info *ti = current_thread_info();
1423 unsigned long ctrl;
1425 ctrl = mfspr(SPRN_CTRLF);
1426 ctrl |= CTRL_RUNLATCH;
1427 mtspr(SPRN_CTRLT, ctrl);
1429 ti->local_flags |= _TLF_RUNLATCH;
1432 /* Called with hard IRQs off */
1433 void notrace __ppc64_runlatch_off(void)
1435 struct thread_info *ti = current_thread_info();
1436 unsigned long ctrl;
1438 ti->local_flags &= ~_TLF_RUNLATCH;
1440 ctrl = mfspr(SPRN_CTRLF);
1441 ctrl &= ~CTRL_RUNLATCH;
1442 mtspr(SPRN_CTRLT, ctrl);
1444 #endif /* CONFIG_PPC64 */
1446 unsigned long arch_align_stack(unsigned long sp)
1448 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
1449 sp -= get_random_int() & ~PAGE_MASK;
1450 return sp & ~0xf;
1453 static inline unsigned long brk_rnd(void)
1455 unsigned long rnd = 0;
1457 /* 8MB for 32bit, 1GB for 64bit */
1458 if (is_32bit_task())
1459 rnd = (long)(get_random_int() % (1<<(23-PAGE_SHIFT)));
1460 else
1461 rnd = (long)(get_random_int() % (1<<(30-PAGE_SHIFT)));
1463 return rnd << PAGE_SHIFT;
1466 unsigned long arch_randomize_brk(struct mm_struct *mm)
1468 unsigned long base = mm->brk;
1469 unsigned long ret;
1471 #ifdef CONFIG_PPC_STD_MMU_64
1473 * If we are using 1TB segments and we are allowed to randomise
1474 * the heap, we can put it above 1TB so it is backed by a 1TB
1475 * segment. Otherwise the heap will be in the bottom 1TB
1476 * which always uses 256MB segments and this may result in a
1477 * performance penalty.
1479 if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T))
1480 base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T);
1481 #endif
1483 ret = PAGE_ALIGN(base + brk_rnd());
1485 if (ret < mm->brk)
1486 return mm->brk;
1488 return ret;
1491 unsigned long randomize_et_dyn(unsigned long base)
1493 unsigned long ret = PAGE_ALIGN(base + brk_rnd());
1495 if (ret < base)
1496 return base;
1498 return ret;