drivers/net/ethernet/sfc/nic.c

   1 /****************************************************************************
   2  * Driver for Solarflare network controllers and boards
   3  * Copyright 2005-2006 Fen Systems Ltd.
   4  * Copyright 2006-2013 Solarflare Communications Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published
   8  * by the Free Software Foundation, incorporated herein by reference.
   9  */
  10
  11 #include <linux/bitops.h>
  12 #include <linux/delay.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/pci.h>
  15 #include <linux/module.h>
  16 #include <linux/seq_file.h>
  17 #include <linux/cpu_rmap.h>
  18 #include "net_driver.h"
  19 #include "bitfield.h"
  20 #include "efx.h"
  21 #include "nic.h"
  22 #include "farch_regs.h"
  23 #include "io.h"
  24 #include "workarounds.h"
  25
  26 /**************************************************************************
  27  *
  28  * Generic buffer handling
  29  * These buffers are used for interrupt status, MAC stats, etc.
  30  *
  31  **************************************************************************/
  32
  33 int efx_nic_alloc_buffer(struct efx_nic *efx, struct efx_buffer *buffer,
  34                          unsigned int len, gfp_t gfp_flags)
  35 {
  36         buffer->addr = dma_zalloc_coherent(&efx->pci_dev->dev, len,
  37                                            &buffer->dma_addr, gfp_flags);
  38         if (!buffer->addr)
  39                 return -ENOMEM;
  40         buffer->len = len;
  41         return 0;
  42 }
  43
  44 void efx_nic_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer)
  45 {
  46         if (buffer->addr) {
  47                 dma_free_coherent(&efx->pci_dev->dev, buffer->len,
  48                                   buffer->addr, buffer->dma_addr);
  49                 buffer->addr = NULL;
  50         }
  51 }
  52
  53 /* Check whether an event is present in the eventq at the current
  54  * read pointer.  Only useful for self-test.
  55  */
  56 bool efx_nic_event_present(struct efx_channel *channel)
  57 {
  58         return efx_event_present(efx_event(channel, channel->eventq_read_ptr));
  59 }
  60
  61 void efx_nic_event_test_start(struct efx_channel *channel)
  62 {
  63         channel->event_test_cpu = -1;
  64         smp_wmb();
  65         channel->efx->type->ev_test_generate(channel);
  66 }
  67
  68 void efx_nic_irq_test_start(struct efx_nic *efx)
  69 {
  70         efx->last_irq_cpu = -1;
  71         smp_wmb();
  72         efx->type->irq_test_generate(efx);
  73 }
  74
  75 /* Hook interrupt handler(s)
  76  * Try MSI and then legacy interrupts.
  77  */
  78 int efx_nic_init_interrupt(struct efx_nic *efx)
  79 {
  80         struct efx_channel *channel;
  81         unsigned int n_irqs;
  82         int rc;
  83
  84         if (!EFX_INT_MODE_USE_MSI(efx)) {
  85                 rc = request_irq(efx->legacy_irq,
  86                                  efx->type->irq_handle_legacy, IRQF_SHARED,
  87                                  efx->name, efx);
  88                 if (rc) {
  89                         netif_err(efx, drv, efx->net_dev,
  90                                   "failed to hook legacy IRQ %d\n",
  91                                   efx->pci_dev->irq);
  92                         goto fail1;
  93                 }
  94                 return 0;
  95         }
  96
  97 #ifdef CONFIG_RFS_ACCEL
  98         if (efx->interrupt_mode == EFX_INT_MODE_MSIX) {
  99                 efx->net_dev->rx_cpu_rmap =
 100                         alloc_irq_cpu_rmap(efx->n_rx_channels);
 101                 if (!efx->net_dev->rx_cpu_rmap) {
 102                         rc = -ENOMEM;
 103                         goto fail1;
 104                 }
 105         }
 106 #endif
 107
 108         /* Hook MSI or MSI-X interrupt */
 109         n_irqs = 0;
 110         efx_for_each_channel(channel, efx) {
 111                 rc = request_irq(channel->irq, efx->type->irq_handle_msi,
 112                                  IRQF_PROBE_SHARED, /* Not shared */
 113                                  efx->msi_context[channel->channel].name,
 114                                  &efx->msi_context[channel->channel]);
 115                 if (rc) {
 116                         netif_err(efx, drv, efx->net_dev,
 117                                   "failed to hook IRQ %d\n", channel->irq);
 118                         goto fail2;
 119                 }
 120                 ++n_irqs;
 121
 122 #ifdef CONFIG_RFS_ACCEL
 123                 if (efx->interrupt_mode == EFX_INT_MODE_MSIX &&
 124                     channel->channel < efx->n_rx_channels) {
 125                         rc = irq_cpu_rmap_add(efx->net_dev->rx_cpu_rmap,
 126                                               channel->irq);
 127                         if (rc)
 128                                 goto fail2;
 129                 }
 130 #endif
 131         }
 132
 133         return 0;
 134
 135  fail2:
 136 #ifdef CONFIG_RFS_ACCEL
 137         free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap);
 138         efx->net_dev->rx_cpu_rmap = NULL;
 139 #endif
 140         efx_for_each_channel(channel, efx) {
 141                 if (n_irqs-- == 0)
 142                         break;
 143                 free_irq(channel->irq, &efx->msi_context[channel->channel]);
 144         }
 145  fail1:
 146         return rc;
 147 }
 148
 149 void efx_nic_fini_interrupt(struct efx_nic *efx)
 150 {
 151         struct efx_channel *channel;
 152
 153 #ifdef CONFIG_RFS_ACCEL
 154         free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap);
 155         efx->net_dev->rx_cpu_rmap = NULL;
 156 #endif
 157
 158         if (EFX_INT_MODE_USE_MSI(efx)) {
 159                 /* Disable MSI/MSI-X interrupts */
 160                 efx_for_each_channel(channel, efx)
 161                         free_irq(channel->irq,
 162                                  &efx->msi_context[channel->channel]);
 163         } else {
 164                 /* Disable legacy interrupt */
 165                 free_irq(efx->legacy_irq, efx);
 166         }
 167 }
 168
 169 /* Register dump */
 170
 171 #define REGISTER_REVISION_A     1
 172 #define REGISTER_REVISION_B     2
 173 #define REGISTER_REVISION_C     3
 174 #define REGISTER_REVISION_Z     3       /* latest revision */
 175
 176 struct efx_nic_reg {
 177         u32 offset:24;
 178         u32 min_revision:2, max_revision:2;
 179 };
 180
 181 #define REGISTER(name, min_rev, max_rev) {                              \
 182         FR_ ## min_rev ## max_rev ## _ ## name,                         \
 183         REGISTER_REVISION_ ## min_rev, REGISTER_REVISION_ ## max_rev    \
 184 }
 185 #define REGISTER_AA(name) REGISTER(name, A, A)
 186 #define REGISTER_AB(name) REGISTER(name, A, B)
 187 #define REGISTER_AZ(name) REGISTER(name, A, Z)
 188 #define REGISTER_BB(name) REGISTER(name, B, B)
 189 #define REGISTER_BZ(name) REGISTER(name, B, Z)
 190 #define REGISTER_CZ(name) REGISTER(name, C, Z)
 191
 192 static const struct efx_nic_reg efx_nic_regs[] = {
 193         REGISTER_AZ(ADR_REGION),
 194         REGISTER_AZ(INT_EN_KER),
 195         REGISTER_BZ(INT_EN_CHAR),
 196         REGISTER_AZ(INT_ADR_KER),
 197         REGISTER_BZ(INT_ADR_CHAR),
 198         /* INT_ACK_KER is WO */
 199         /* INT_ISR0 is RC */
 200         REGISTER_AZ(HW_INIT),
 201         REGISTER_CZ(USR_EV_CFG),
 202         REGISTER_AB(EE_SPI_HCMD),
 203         REGISTER_AB(EE_SPI_HADR),
 204         REGISTER_AB(EE_SPI_HDATA),
 205         REGISTER_AB(EE_BASE_PAGE),
 206         REGISTER_AB(EE_VPD_CFG0),
 207         /* EE_VPD_SW_CNTL and EE_VPD_SW_DATA are not used */
 208         /* PMBX_DBG_IADDR and PBMX_DBG_IDATA are indirect */
 209         /* PCIE_CORE_INDIRECT is indirect */
 210         REGISTER_AB(NIC_STAT),
 211         REGISTER_AB(GPIO_CTL),
 212         REGISTER_AB(GLB_CTL),
 213         /* FATAL_INTR_KER and FATAL_INTR_CHAR are partly RC */
 214         REGISTER_BZ(DP_CTRL),
 215         REGISTER_AZ(MEM_STAT),
 216         REGISTER_AZ(CS_DEBUG),
 217         REGISTER_AZ(ALTERA_BUILD),
 218         REGISTER_AZ(CSR_SPARE),
 219         REGISTER_AB(PCIE_SD_CTL0123),
 220         REGISTER_AB(PCIE_SD_CTL45),
 221         REGISTER_AB(PCIE_PCS_CTL_STAT),
 222         /* DEBUG_DATA_OUT is not used */
 223         /* DRV_EV is WO */
 224         REGISTER_AZ(EVQ_CTL),
 225         REGISTER_AZ(EVQ_CNT1),
 226         REGISTER_AZ(EVQ_CNT2),
 227         REGISTER_AZ(BUF_TBL_CFG),
 228         REGISTER_AZ(SRM_RX_DC_CFG),
 229         REGISTER_AZ(SRM_TX_DC_CFG),
 230         REGISTER_AZ(SRM_CFG),
 231         /* BUF_TBL_UPD is WO */
 232         REGISTER_AZ(SRM_UPD_EVQ),
 233         REGISTER_AZ(SRAM_PARITY),
 234         REGISTER_AZ(RX_CFG),
 235         REGISTER_BZ(RX_FILTER_CTL),
 236         /* RX_FLUSH_DESCQ is WO */
 237         REGISTER_AZ(RX_DC_CFG),
 238         REGISTER_AZ(RX_DC_PF_WM),
 239         REGISTER_BZ(RX_RSS_TKEY),
 240         /* RX_NODESC_DROP is RC */
 241         REGISTER_AA(RX_SELF_RST),
 242         /* RX_DEBUG, RX_PUSH_DROP are not used */
 243         REGISTER_CZ(RX_RSS_IPV6_REG1),
 244         REGISTER_CZ(RX_RSS_IPV6_REG2),
 245         REGISTER_CZ(RX_RSS_IPV6_REG3),
 246         /* TX_FLUSH_DESCQ is WO */
 247         REGISTER_AZ(TX_DC_CFG),
 248         REGISTER_AA(TX_CHKSM_CFG),
 249         REGISTER_AZ(TX_CFG),
 250         /* TX_PUSH_DROP is not used */
 251         REGISTER_AZ(TX_RESERVED),
 252         REGISTER_BZ(TX_PACE),
 253         /* TX_PACE_DROP_QID is RC */
 254         REGISTER_BB(TX_VLAN),
 255         REGISTER_BZ(TX_IPFIL_PORTEN),
 256         REGISTER_AB(MD_TXD),
 257         REGISTER_AB(MD_RXD),
 258         REGISTER_AB(MD_CS),
 259         REGISTER_AB(MD_PHY_ADR),
 260         REGISTER_AB(MD_ID),
 261         /* MD_STAT is RC */
 262         REGISTER_AB(MAC_STAT_DMA),
 263         REGISTER_AB(MAC_CTRL),
 264         REGISTER_BB(GEN_MODE),
 265         REGISTER_AB(MAC_MC_HASH_REG0),
 266         REGISTER_AB(MAC_MC_HASH_REG1),
 267         REGISTER_AB(GM_CFG1),
 268         REGISTER_AB(GM_CFG2),
 269         /* GM_IPG and GM_HD are not used */
 270         REGISTER_AB(GM_MAX_FLEN),
 271         /* GM_TEST is not used */
 272         REGISTER_AB(GM_ADR1),
 273         REGISTER_AB(GM_ADR2),
 274         REGISTER_AB(GMF_CFG0),
 275         REGISTER_AB(GMF_CFG1),
 276         REGISTER_AB(GMF_CFG2),
 277         REGISTER_AB(GMF_CFG3),
 278         REGISTER_AB(GMF_CFG4),
 279         REGISTER_AB(GMF_CFG5),
 280         REGISTER_BB(TX_SRC_MAC_CTL),
 281         REGISTER_AB(XM_ADR_LO),
 282         REGISTER_AB(XM_ADR_HI),
 283         REGISTER_AB(XM_GLB_CFG),
 284         REGISTER_AB(XM_TX_CFG),
 285         REGISTER_AB(XM_RX_CFG),
 286         REGISTER_AB(XM_MGT_INT_MASK),
 287         REGISTER_AB(XM_FC),
 288         REGISTER_AB(XM_PAUSE_TIME),
 289         REGISTER_AB(XM_TX_PARAM),
 290         REGISTER_AB(XM_RX_PARAM),
 291         /* XM_MGT_INT_MSK (note no 'A') is RC */
 292         REGISTER_AB(XX_PWR_RST),
 293         REGISTER_AB(XX_SD_CTL),
 294         REGISTER_AB(XX_TXDRV_CTL),
 295         /* XX_PRBS_CTL, XX_PRBS_CHK and XX_PRBS_ERR are not used */
 296         /* XX_CORE_STAT is partly RC */
 297 };
 298
 299 struct efx_nic_reg_table {
 300         u32 offset:24;
 301         u32 min_revision:2, max_revision:2;
 302         u32 step:6, rows:21;
 303 };
 304
 305 #define REGISTER_TABLE_DIMENSIONS(_, offset, min_rev, max_rev, step, rows) { \
 306         offset,                                                         \
 307         REGISTER_REVISION_ ## min_rev, REGISTER_REVISION_ ## max_rev,   \
 308         step, rows                                                      \
 309 }
 310 #define REGISTER_TABLE(name, min_rev, max_rev)                          \
 311         REGISTER_TABLE_DIMENSIONS(                                      \
 312                 name, FR_ ## min_rev ## max_rev ## _ ## name,           \
 313                 min_rev, max_rev,                                       \
 314                 FR_ ## min_rev ## max_rev ## _ ## name ## _STEP,        \
 315                 FR_ ## min_rev ## max_rev ## _ ## name ## _ROWS)
 316 #define REGISTER_TABLE_AA(name) REGISTER_TABLE(name, A, A)
 317 #define REGISTER_TABLE_AZ(name) REGISTER_TABLE(name, A, Z)
 318 #define REGISTER_TABLE_BB(name) REGISTER_TABLE(name, B, B)
 319 #define REGISTER_TABLE_BZ(name) REGISTER_TABLE(name, B, Z)
 320 #define REGISTER_TABLE_BB_CZ(name)                                      \
 321         REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, B, B,           \
 322                                   FR_BZ_ ## name ## _STEP,              \
 323                                   FR_BB_ ## name ## _ROWS),             \
 324         REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, C, Z,           \
 325                                   FR_BZ_ ## name ## _STEP,              \
 326                                   FR_CZ_ ## name ## _ROWS)
 327 #define REGISTER_TABLE_CZ(name) REGISTER_TABLE(name, C, Z)
 328
 329 static const struct efx_nic_reg_table efx_nic_reg_tables[] = {
 330         /* DRIVER is not used */
 331         /* EVQ_RPTR, TIMER_COMMAND, USR_EV and {RX,TX}_DESC_UPD are WO */
 332         REGISTER_TABLE_BB(TX_IPFIL_TBL),
 333         REGISTER_TABLE_BB(TX_SRC_MAC_TBL),
 334         REGISTER_TABLE_AA(RX_DESC_PTR_TBL_KER),
 335         REGISTER_TABLE_BB_CZ(RX_DESC_PTR_TBL),
 336         REGISTER_TABLE_AA(TX_DESC_PTR_TBL_KER),
 337         REGISTER_TABLE_BB_CZ(TX_DESC_PTR_TBL),
 338         REGISTER_TABLE_AA(EVQ_PTR_TBL_KER),
 339         REGISTER_TABLE_BB_CZ(EVQ_PTR_TBL),
 340         /* We can't reasonably read all of the buffer table (up to 8MB!).
 341          * However this driver will only use a few entries.  Reading
 342          * 1K entries allows for some expansion of queue count and
 343          * size before we need to change the version. */
 344         REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL_KER, FR_AA_BUF_FULL_TBL_KER,
 345                                   A, A, 8, 1024),
 346         REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL, FR_BZ_BUF_FULL_TBL,
 347                                   B, Z, 8, 1024),
 348         REGISTER_TABLE_CZ(RX_MAC_FILTER_TBL0),
 349         REGISTER_TABLE_BB_CZ(TIMER_TBL),
 350         REGISTER_TABLE_BB_CZ(TX_PACE_TBL),
 351         REGISTER_TABLE_BZ(RX_INDIRECTION_TBL),
 352         /* TX_FILTER_TBL0 is huge and not used by this driver */
 353         REGISTER_TABLE_CZ(TX_MAC_FILTER_TBL0),
 354         REGISTER_TABLE_CZ(MC_TREG_SMEM),
 355         /* MSIX_PBA_TABLE is not mapped */
 356         /* SRM_DBG is not mapped (and is redundant with BUF_FLL_TBL) */
 357         REGISTER_TABLE_BZ(RX_FILTER_TBL0),
 358 };
 359
 360 size_t efx_nic_get_regs_len(struct efx_nic *efx)
 361 {
 362         const struct efx_nic_reg *reg;
 363         const struct efx_nic_reg_table *table;
 364         size_t len = 0;
 365
 366         for (reg = efx_nic_regs;
 367              reg < efx_nic_regs + ARRAY_SIZE(efx_nic_regs);
 368              reg++)
 369                 if (efx->type->revision >= reg->min_revision &&
 370                     efx->type->revision <= reg->max_revision)
 371                         len += sizeof(efx_oword_t);
 372
 373         for (table = efx_nic_reg_tables;
 374              table < efx_nic_reg_tables + ARRAY_SIZE(efx_nic_reg_tables);
 375              table++)
 376                 if (efx->type->revision >= table->min_revision &&
 377                     efx->type->revision <= table->max_revision)
 378                         len += table->rows * min_t(size_t, table->step, 16);
 379
 380         return len;
 381 }
 382
 383 void efx_nic_get_regs(struct efx_nic *efx, void *buf)
 384 {
 385         const struct efx_nic_reg *reg;
 386         const struct efx_nic_reg_table *table;
 387
 388         for (reg = efx_nic_regs;
 389              reg < efx_nic_regs + ARRAY_SIZE(efx_nic_regs);
 390              reg++) {
 391                 if (efx->type->revision >= reg->min_revision &&
 392                     efx->type->revision <= reg->max_revision) {
 393                         efx_reado(efx, (efx_oword_t *)buf, reg->offset);
 394                         buf += sizeof(efx_oword_t);
 395                 }
 396         }
 397
 398         for (table = efx_nic_reg_tables;
 399              table < efx_nic_reg_tables + ARRAY_SIZE(efx_nic_reg_tables);
 400              table++) {
 401                 size_t size, i;
 402
 403                 if (!(efx->type->revision >= table->min_revision &&
 404                       efx->type->revision <= table->max_revision))
 405                         continue;
 406
 407                 size = min_t(size_t, table->step, 16);
 408
 409                 for (i = 0; i < table->rows; i++) {
 410                         switch (table->step) {
 411                         case 4: /* 32-bit SRAM */
 412                                 efx_readd(efx, buf, table->offset + 4 * i);
 413                                 break;
 414                         case 8: /* 64-bit SRAM */
 415                                 efx_sram_readq(efx,
 416                                                efx->membase + table->offset,
 417                                                buf, i);
 418                                 break;
 419                         case 16: /* 128-bit-readable register */
 420                                 efx_reado_table(efx, buf, table->offset, i);
 421                                 break;
 422                         case 32: /* 128-bit register, interleaved */
 423                                 efx_reado_table(efx, buf, table->offset, 2 * i);
 424                                 break;
 425                         default:
 426                                 WARN_ON(1);
 427                                 return;
 428                         }
 429                         buf += size;
 430                 }
 431         }
 432 }
 433
 434 /**
 435  * efx_nic_describe_stats - Describe supported statistics for ethtool
 436  * @desc: Array of &struct efx_hw_stat_desc describing the statistics
 437  * @count: Length of the @desc array
 438  * @mask: Bitmask of which elements of @desc are enabled
 439  * @names: Buffer to copy names to, or %NULL.  The names are copied
 440  *      starting at intervals of %ETH_GSTRING_LEN bytes.
 441  *
 442  * Returns the number of visible statistics, i.e. the number of set
 443  * bits in the first @count bits of @mask for which a name is defined.
 444  */
 445 size_t efx_nic_describe_stats(const struct efx_hw_stat_desc *desc, size_t count,
 446                               const unsigned long *mask, u8 *names)
 447 {
 448         size_t visible = 0;
 449         size_t index;
 450
 451         for_each_set_bit(index, mask, count) {
 452                 if (desc[index].name) {
 453                         if (names) {
 454                                 strlcpy(names, desc[index].name,
 455                                         ETH_GSTRING_LEN);
 456                                 names += ETH_GSTRING_LEN;
 457                         }
 458                         ++visible;
 459                 }
 460         }
 461
 462         return visible;
 463 }
 464
 465 /**
 466  * efx_nic_update_stats - Convert statistics DMA buffer to array of u64
 467  * @desc: Array of &struct efx_hw_stat_desc describing the DMA buffer
 468  *      layout.  DMA widths of 0, 16, 32 and 64 are supported; where
 469  *      the width is specified as 0 the corresponding element of
 470  *      @stats is not updated.
 471  * @count: Length of the @desc array
 472  * @mask: Bitmask of which elements of @desc are enabled
 473  * @stats: Buffer to update with the converted statistics.  The length
 474  *      of this array must be at least @count.
 475  * @dma_buf: DMA buffer containing hardware statistics
 476  * @accumulate: If set, the converted values will be added rather than
 477  *      directly stored to the corresponding elements of @stats
 478  */
 479 void efx_nic_update_stats(const struct efx_hw_stat_desc *desc, size_t count,
 480                           const unsigned long *mask,
 481                           u64 *stats, const void *dma_buf, bool accumulate)
 482 {
 483         size_t index;
 484
 485         for_each_set_bit(index, mask, count) {
 486                 if (desc[index].dma_width) {
 487                         const void *addr = dma_buf + desc[index].offset;
 488                         u64 val;
 489
 490                         switch (desc[index].dma_width) {
 491                         case 16:
 492                                 val = le16_to_cpup((__le16 *)addr);
 493                                 break;
 494                         case 32:
 495                                 val = le32_to_cpup((__le32 *)addr);
 496                                 break;
 497                         case 64:
 498                                 val = le64_to_cpup((__le64 *)addr);
 499                                 break;
 500                         default:
 501                                 WARN_ON(1);
 502                                 val = 0;
 503                                 break;
 504                         }
 505
 506                         if (accumulate)
 507                                 stats[index] += val;
 508                         else
 509                                 stats[index] = val;
 510                 }
 511         }
 512 }